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[media] adv7604: improve HDMI audio handling
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
30
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/slab.h>
34#include <linux/i2c.h>
35#include <linux/delay.h>
36#include <linux/videodev2.h>
37#include <linux/workqueue.h>
38#include <linux/v4l2-dv-timings.h>
39#include <media/v4l2-device.h>
40#include <media/v4l2-ctrls.h>
25764158 41#include <media/v4l2-dv-timings.h>
54450f59
HV		 42#include <media/adv7604.h>
43
44static int debug;
45module_param(debug, int, 0644);
46MODULE_PARM_DESC(debug, "debug level (0-2)");
47
48MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
49MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
50MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
51MODULE_LICENSE("GPL");
52
53/* ADV7604 system clock frequency */
54#define ADV7604_fsc (28636360)
55
54450f59
HV		 56/*
57 **********************************************************************
58 *
59 * Arrays with configuration parameters for the ADV7604
60 *
61 **********************************************************************
62 */
63struct adv7604_state {
64 struct adv7604_platform_data pdata;
65 struct v4l2_subdev sd;
66 struct media_pad pad;
67 struct v4l2_ctrl_handler hdl;
4a31a93a 68 enum adv7604_input_port selected_input;
54450f59 69 struct v4l2_dv_timings timings;
4a31a93a
MR		 70 struct {
71 u8 edid[256];
72 u32 present;
73 unsigned blocks;
74 } edid;
dd08beb9 75 u16 spa_port_a[2];
54450f59
HV		 76 struct v4l2_fract aspect_ratio;
77 u32 rgb_quantization_range;
78 struct workqueue_struct *work_queues;
79 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 80 bool restart_stdi_once;
54450f59
HV		 81
82 /* i2c clients */
83 struct i2c_client *i2c_avlink;
84 struct i2c_client *i2c_cec;
85 struct i2c_client *i2c_infoframe;
86 struct i2c_client *i2c_esdp;
87 struct i2c_client *i2c_dpp;
88 struct i2c_client *i2c_afe;
89 struct i2c_client *i2c_repeater;
90 struct i2c_client *i2c_edid;
91 struct i2c_client *i2c_hdmi;
92 struct i2c_client *i2c_test;
93 struct i2c_client *i2c_cp;
94 struct i2c_client *i2c_vdp;
95
96 /* controls */
97 struct v4l2_ctrl *detect_tx_5v_ctrl;
98 struct v4l2_ctrl *analog_sampling_phase_ctrl;
99 struct v4l2_ctrl *free_run_color_manual_ctrl;
100 struct v4l2_ctrl *free_run_color_ctrl;
101 struct v4l2_ctrl *rgb_quantization_range_ctrl;
102};
103
104/* Supported CEA and DMT timings */
105static const struct v4l2_dv_timings adv7604_timings[] = {
106 V4L2_DV_BT_CEA_720X480P59_94,
107 V4L2_DV_BT_CEA_720X576P50,
108 V4L2_DV_BT_CEA_1280X720P24,
109 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 110 V4L2_DV_BT_CEA_1280X720P50,
111 V4L2_DV_BT_CEA_1280X720P60,
112 V4L2_DV_BT_CEA_1920X1080P24,
113 V4L2_DV_BT_CEA_1920X1080P25,
114 V4L2_DV_BT_CEA_1920X1080P30,
115 V4L2_DV_BT_CEA_1920X1080P50,
116 V4L2_DV_BT_CEA_1920X1080P60,
117
ccbd5bc4 118 /* sorted by DMT ID */
54450f59
HV		 119 V4L2_DV_BT_DMT_640X350P85,
120 V4L2_DV_BT_DMT_640X400P85,
121 V4L2_DV_BT_DMT_720X400P85,
122 V4L2_DV_BT_DMT_640X480P60,
123 V4L2_DV_BT_DMT_640X480P72,
124 V4L2_DV_BT_DMT_640X480P75,
125 V4L2_DV_BT_DMT_640X480P85,
126 V4L2_DV_BT_DMT_800X600P56,
127 V4L2_DV_BT_DMT_800X600P60,
128 V4L2_DV_BT_DMT_800X600P72,
129 V4L2_DV_BT_DMT_800X600P75,
130 V4L2_DV_BT_DMT_800X600P85,
131 V4L2_DV_BT_DMT_848X480P60,
132 V4L2_DV_BT_DMT_1024X768P60,
133 V4L2_DV_BT_DMT_1024X768P70,
134 V4L2_DV_BT_DMT_1024X768P75,
135 V4L2_DV_BT_DMT_1024X768P85,
136 V4L2_DV_BT_DMT_1152X864P75,
137 V4L2_DV_BT_DMT_1280X768P60_RB,
138 V4L2_DV_BT_DMT_1280X768P60,
139 V4L2_DV_BT_DMT_1280X768P75,
140 V4L2_DV_BT_DMT_1280X768P85,
141 V4L2_DV_BT_DMT_1280X800P60_RB,
142 V4L2_DV_BT_DMT_1280X800P60,
143 V4L2_DV_BT_DMT_1280X800P75,
144 V4L2_DV_BT_DMT_1280X800P85,
145 V4L2_DV_BT_DMT_1280X960P60,
146 V4L2_DV_BT_DMT_1280X960P85,
147 V4L2_DV_BT_DMT_1280X1024P60,
148 V4L2_DV_BT_DMT_1280X1024P75,
149 V4L2_DV_BT_DMT_1280X1024P85,
150 V4L2_DV_BT_DMT_1360X768P60,
151 V4L2_DV_BT_DMT_1400X1050P60_RB,
152 V4L2_DV_BT_DMT_1400X1050P60,
153 V4L2_DV_BT_DMT_1400X1050P75,
154 V4L2_DV_BT_DMT_1400X1050P85,
155 V4L2_DV_BT_DMT_1440X900P60_RB,
156 V4L2_DV_BT_DMT_1440X900P60,
157 V4L2_DV_BT_DMT_1600X1200P60,
158 V4L2_DV_BT_DMT_1680X1050P60_RB,
159 V4L2_DV_BT_DMT_1680X1050P60,
160 V4L2_DV_BT_DMT_1792X1344P60,
161 V4L2_DV_BT_DMT_1856X1392P60,
162 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 163 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 164 V4L2_DV_BT_DMT_1366X768P60,
165 V4L2_DV_BT_DMT_1920X1080P60,
166 { },
167};
168
ccbd5bc4
HV		 169struct adv7604_video_standards {
170 struct v4l2_dv_timings timings;
171 u8 vid_std;
172 u8 v_freq;
173};
174
175/* sorted by number of lines */
176static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
177 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
178 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
179 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
180 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
181 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
182 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
183 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
184 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
185 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
186 /* TODO add 1920x1080P60_RB (CVT timing) */
187 { },
188};
189
190/* sorted by number of lines */
191static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
192 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
193 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
194 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
195 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
196 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
197 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
198 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
199 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
200 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
201 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
202 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
203 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
204 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
205 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
206 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
207 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
208 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
209 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
210 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
211 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
212 /* TODO add 1600X1200P60_RB (not a DMT timing) */
213 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
214 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
215 { },
216};
217
218/* sorted by number of lines */
219static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
220 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
221 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
222 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
223 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
224 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
225 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
226 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
227 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
228 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
229 { },
230};
231
232/* sorted by number of lines */
233static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
234 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
235 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
236 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
237 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
238 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
239 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
240 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
241 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
242 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
243 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
244 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
245 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
246 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
247 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
248 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
249 { },
250};
251
54450f59
HV		 252/* ----------------------------------------------------------------------- */
253
254static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
255{
256 return container_of(sd, struct adv7604_state, sd);
257}
258
259static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
260{
261 return &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
262}
263
264static inline unsigned hblanking(const struct v4l2_bt_timings *t)
265{
eacf8f9a 266 return V4L2_DV_BT_BLANKING_WIDTH(t);
54450f59
HV		 267}
268
269static inline unsigned htotal(const struct v4l2_bt_timings *t)
270{
eacf8f9a 271 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 272}
273
274static inline unsigned vblanking(const struct v4l2_bt_timings *t)
275{
eacf8f9a 276 return V4L2_DV_BT_BLANKING_HEIGHT(t);
54450f59
HV		 277}
278
279static inline unsigned vtotal(const struct v4l2_bt_timings *t)
280{
eacf8f9a 281 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 282}
283
284/* ----------------------------------------------------------------------- */
285
286static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
287 u8 command, bool check)
288{
289 union i2c_smbus_data data;
290
291 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
292 I2C_SMBUS_READ, command,
293 I2C_SMBUS_BYTE_DATA, &data))
294 return data.byte;
295 if (check)
296 v4l_err(client, "error reading %02x, %02x\n",
297 client->addr, command);
298 return -EIO;
299}
300
301static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)
302{
303 return adv_smbus_read_byte_data_check(client, command, true);
304}
305
306static s32 adv_smbus_write_byte_data(struct i2c_client *client,
307 u8 command, u8 value)
308{
309 union i2c_smbus_data data;
310 int err;
311 int i;
312
313 data.byte = value;
314 for (i = 0; i < 3; i++) {
315 err = i2c_smbus_xfer(client->adapter, client->addr,
316 client->flags,
317 I2C_SMBUS_WRITE, command,
318 I2C_SMBUS_BYTE_DATA, &data);
319 if (!err)
320 break;
321 }
322 if (err < 0)
323 v4l_err(client, "error writing %02x, %02x, %02x\n",
324 client->addr, command, value);
325 return err;
326}
327
328static s32 adv_smbus_write_i2c_block_data(struct i2c_client *client,
329 u8 command, unsigned length, const u8 *values)
330{
331 union i2c_smbus_data data;
332
333 if (length > I2C_SMBUS_BLOCK_MAX)
334 length = I2C_SMBUS_BLOCK_MAX;
335 data.block[0] = length;
336 memcpy(data.block + 1, values, length);
337 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
338 I2C_SMBUS_WRITE, command,
339 I2C_SMBUS_I2C_BLOCK_DATA, &data);
340}
341
342/* ----------------------------------------------------------------------- */
343
344static inline int io_read(struct v4l2_subdev *sd, u8 reg)
345{
346 struct i2c_client *client = v4l2_get_subdevdata(sd);
347
348 return adv_smbus_read_byte_data(client, reg);
349}
350
351static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
352{
353 struct i2c_client *client = v4l2_get_subdevdata(sd);
354
355 return adv_smbus_write_byte_data(client, reg, val);
356}
357
358static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
359{
360 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);
361}
362
363static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
364{
365 struct adv7604_state *state = to_state(sd);
366
367 return adv_smbus_read_byte_data(state->i2c_avlink, reg);
368}
369
370static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
371{
372 struct adv7604_state *state = to_state(sd);
373
374 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);
375}
376
377static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
378{
379 struct adv7604_state *state = to_state(sd);
380
381 return adv_smbus_read_byte_data(state->i2c_cec, reg);
382}
383
384static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
385{
386 struct adv7604_state *state = to_state(sd);
387
388 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);
389}
390
391static inline int cec_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
392{
393 return cec_write(sd, reg, (cec_read(sd, reg) & mask) | val);
394}
395
396static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
397{
398 struct adv7604_state *state = to_state(sd);
399
400 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);
401}
402
403static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
404{
405 struct adv7604_state *state = to_state(sd);
406
407 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);
408}
409
410static inline int esdp_read(struct v4l2_subdev *sd, u8 reg)
411{
412 struct adv7604_state *state = to_state(sd);
413
414 return adv_smbus_read_byte_data(state->i2c_esdp, reg);
415}
416
417static inline int esdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
418{
419 struct adv7604_state *state = to_state(sd);
420
421 return adv_smbus_write_byte_data(state->i2c_esdp, reg, val);
422}
423
424static inline int dpp_read(struct v4l2_subdev *sd, u8 reg)
425{
426 struct adv7604_state *state = to_state(sd);
427
428 return adv_smbus_read_byte_data(state->i2c_dpp, reg);
429}
430
431static inline int dpp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
432{
433 struct adv7604_state *state = to_state(sd);
434
435 return adv_smbus_write_byte_data(state->i2c_dpp, reg, val);
436}
437
438static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
439{
440 struct adv7604_state *state = to_state(sd);
441
442 return adv_smbus_read_byte_data(state->i2c_afe, reg);
443}
444
445static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
446{
447 struct adv7604_state *state = to_state(sd);
448
449 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);
450}
451
452static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
453{
454 struct adv7604_state *state = to_state(sd);
455
456 return adv_smbus_read_byte_data(state->i2c_repeater, reg);
457}
458
459static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
460{
461 struct adv7604_state *state = to_state(sd);
462
463 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);
464}
465
466static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
467{
468 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);
469}
470
471static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
472{
473 struct adv7604_state *state = to_state(sd);
474
475 return adv_smbus_read_byte_data(state->i2c_edid, reg);
476}
477
478static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
479{
480 struct adv7604_state *state = to_state(sd);
481
482 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);
483}
484
485static inline int edid_read_block(struct v4l2_subdev *sd, unsigned len, u8 *val)
486{
487 struct adv7604_state *state = to_state(sd);
488 struct i2c_client *client = state->i2c_edid;
489 u8 msgbuf0[1] = { 0 };
490 u8 msgbuf1[256];
09f29673
S		 491 struct i2c_msg msg[2] = {
492 {
493 .addr = client->addr,
494 .len = 1,
495 .buf = msgbuf0
496 },
497 {
498 .addr = client->addr,
499 .flags = I2C_M_RD,
500 .len = len,
501 .buf = msgbuf1
502 },
503 };
54450f59
HV		 504
505 if (i2c_transfer(client->adapter, msg, 2) < 0)
506 return -EIO;
507 memcpy(val, msgbuf1, len);
508 return 0;
509}
510
54450f59
HV		 511static inline int edid_write_block(struct v4l2_subdev *sd,
512 unsigned len, const u8 *val)
513{
54450f59
HV		 514 struct adv7604_state *state = to_state(sd);
515 int err = 0;
516 int i;
517
518 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
519
54450f59
HV		 520 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
521 err = adv_smbus_write_i2c_block_data(state->i2c_edid, i,
522 I2C_SMBUS_BLOCK_MAX, val + i);
dd08beb9
MR		 523 return err;
524}
54450f59 525
dd08beb9
MR		 526static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
527{
528 struct delayed_work *dwork = to_delayed_work(work);
529 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
530 delayed_work_enable_hotplug);
531 struct v4l2_subdev *sd = &state->sd;
54450f59 532
dd08beb9 533 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 534
dd08beb9 535 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
54450f59
HV		 536}
537
538static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
539{
540 struct adv7604_state *state = to_state(sd);
541
542 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);
543}
544
545static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
546{
547 struct adv7604_state *state = to_state(sd);
548
549 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);
550}
551
4a31a93a
MR		 552static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
553{
554 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);
555}
556
54450f59
HV		 557static inline int test_read(struct v4l2_subdev *sd, u8 reg)
558{
559 struct adv7604_state *state = to_state(sd);
560
561 return adv_smbus_read_byte_data(state->i2c_test, reg);
562}
563
564static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
565{
566 struct adv7604_state *state = to_state(sd);
567
568 return adv_smbus_write_byte_data(state->i2c_test, reg, val);
569}
570
571static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
572{
573 struct adv7604_state *state = to_state(sd);
574
575 return adv_smbus_read_byte_data(state->i2c_cp, reg);
576}
577
578static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
579{
580 struct adv7604_state *state = to_state(sd);
581
582 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);
583}
584
585static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
586{
587 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);
588}
589
590static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
591{
592 struct adv7604_state *state = to_state(sd);
593
594 return adv_smbus_read_byte_data(state->i2c_vdp, reg);
595}
596
597static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
598{
599 struct adv7604_state *state = to_state(sd);
600
601 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);
602}
603
604/* ----------------------------------------------------------------------- */
605
4a31a93a
MR		 606static inline bool is_analog_input(struct v4l2_subdev *sd)
607{
608 struct adv7604_state *state = to_state(sd);
609
610 return state->selected_input == ADV7604_INPUT_VGA_RGB ||
611 state->selected_input == ADV7604_INPUT_VGA_COMP;
612}
613
614static inline bool is_digital_input(struct v4l2_subdev *sd)
615{
616 struct adv7604_state *state = to_state(sd);
617
618 return state->selected_input == ADV7604_INPUT_HDMI_PORT_A ||
619 state->selected_input == ADV7604_INPUT_HDMI_PORT_B ||
620 state->selected_input == ADV7604_INPUT_HDMI_PORT_C ||
621 state->selected_input == ADV7604_INPUT_HDMI_PORT_D;
622}
623
624/* ----------------------------------------------------------------------- */
625
54450f59
HV		 626#ifdef CONFIG_VIDEO_ADV_DEBUG
627static void adv7604_inv_register(struct v4l2_subdev *sd)
628{
629 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
630 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
631 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
632 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
633 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
634 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
635 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
636 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
637 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
638 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
639 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
640 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
641 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
642}
643
644static int adv7604_g_register(struct v4l2_subdev *sd,
645 struct v4l2_dbg_register *reg)
646{
54450f59
HV		 647 reg->size = 1;
648 switch (reg->reg >> 8) {
649 case 0:
650 reg->val = io_read(sd, reg->reg & 0xff);
651 break;
652 case 1:
653 reg->val = avlink_read(sd, reg->reg & 0xff);
654 break;
655 case 2:
656 reg->val = cec_read(sd, reg->reg & 0xff);
657 break;
658 case 3:
659 reg->val = infoframe_read(sd, reg->reg & 0xff);
660 break;
661 case 4:
662 reg->val = esdp_read(sd, reg->reg & 0xff);
663 break;
664 case 5:
665 reg->val = dpp_read(sd, reg->reg & 0xff);
666 break;
667 case 6:
668 reg->val = afe_read(sd, reg->reg & 0xff);
669 break;
670 case 7:
671 reg->val = rep_read(sd, reg->reg & 0xff);
672 break;
673 case 8:
674 reg->val = edid_read(sd, reg->reg & 0xff);
675 break;
676 case 9:
677 reg->val = hdmi_read(sd, reg->reg & 0xff);
678 break;
679 case 0xa:
680 reg->val = test_read(sd, reg->reg & 0xff);
681 break;
682 case 0xb:
683 reg->val = cp_read(sd, reg->reg & 0xff);
684 break;
685 case 0xc:
686 reg->val = vdp_read(sd, reg->reg & 0xff);
687 break;
688 default:
689 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
690 adv7604_inv_register(sd);
691 break;
692 }
693 return 0;
694}
695
696static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 697 const struct v4l2_dbg_register *reg)
54450f59 698{
1577461b
HV		 699 u8 val = reg->val & 0xff;
700
54450f59
HV		 701 switch (reg->reg >> 8) {
702 case 0:
1577461b 703 io_write(sd, reg->reg & 0xff, val);
54450f59
HV		 704 break;
705 case 1:
1577461b 706 avlink_write(sd, reg->reg & 0xff, val);
54450f59
HV		 707 break;
708 case 2:
1577461b 709 cec_write(sd, reg->reg & 0xff, val);
54450f59
HV		 710 break;
711 case 3:
1577461b 712 infoframe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 713 break;
714 case 4:
1577461b 715 esdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 716 break;
717 case 5:
1577461b 718 dpp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 719 break;
720 case 6:
1577461b 721 afe_write(sd, reg->reg & 0xff, val);
54450f59
HV		 722 break;
723 case 7:
1577461b 724 rep_write(sd, reg->reg & 0xff, val);
54450f59
HV		 725 break;
726 case 8:
1577461b 727 edid_write(sd, reg->reg & 0xff, val);
54450f59
HV		 728 break;
729 case 9:
1577461b 730 hdmi_write(sd, reg->reg & 0xff, val);
54450f59
HV		 731 break;
732 case 0xa:
1577461b 733 test_write(sd, reg->reg & 0xff, val);
54450f59
HV		 734 break;
735 case 0xb:
1577461b 736 cp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 737 break;
738 case 0xc:
1577461b 739 vdp_write(sd, reg->reg & 0xff, val);
54450f59
HV		 740 break;
741 default:
742 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
743 adv7604_inv_register(sd);
744 break;
745 }
746 return 0;
747}
748#endif
749
750static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
751{
752 struct adv7604_state *state = to_state(sd);
4a31a93a 753 u8 reg_io_6f = io_read(sd, 0x6f);
54450f59 754
54450f59 755 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
4a31a93a
MR		 756 ((reg_io_6f & 0x10) >> 4) |
757 ((reg_io_6f & 0x08) >> 2) |
758 (reg_io_6f & 0x04) |
759 ((reg_io_6f & 0x02) << 2));
54450f59
HV		 760}
761
ccbd5bc4
HV		 762static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
763 u8 prim_mode,
764 const struct adv7604_video_standards *predef_vid_timings,
765 const struct v4l2_dv_timings *timings)
766{
ccbd5bc4
HV		 767 int i;
768
769 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 770 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 771 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 772 continue;
773 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
774 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
775 prim_mode); /* v_freq and prim mode */
776 return 0;
777 }
778
779 return -1;
780}
781
782static int configure_predefined_video_timings(struct v4l2_subdev *sd,
783 struct v4l2_dv_timings *timings)
54450f59 784{
ccbd5bc4
HV		 785 struct adv7604_state *state = to_state(sd);
786 int err;
787
788 v4l2_dbg(1, debug, sd, "%s", __func__);
789
790 /* reset to default values */
791 io_write(sd, 0x16, 0x43);
792 io_write(sd, 0x17, 0x5a);
793 /* disable embedded syncs for auto graphics mode */
794 cp_write_and_or(sd, 0x81, 0xef, 0x00);
795 cp_write(sd, 0x8f, 0x00);
796 cp_write(sd, 0x90, 0x00);
797 cp_write(sd, 0xa2, 0x00);
798 cp_write(sd, 0xa3, 0x00);
799 cp_write(sd, 0xa4, 0x00);
800 cp_write(sd, 0xa5, 0x00);
801 cp_write(sd, 0xa6, 0x00);
802 cp_write(sd, 0xa7, 0x00);
803 cp_write(sd, 0xab, 0x00);
804 cp_write(sd, 0xac, 0x00);
805
4a31a93a 806 if (is_analog_input(sd)) {
ccbd5bc4
HV		 807 err = find_and_set_predefined_video_timings(sd,
808 0x01, adv7604_prim_mode_comp, timings);
809 if (err)
810 err = find_and_set_predefined_video_timings(sd,
811 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 812 } else if (is_digital_input(sd)) {
ccbd5bc4
HV		 813 err = find_and_set_predefined_video_timings(sd,
814 0x05, adv7604_prim_mode_hdmi_comp, timings);
815 if (err)
816 err = find_and_set_predefined_video_timings(sd,
817 0x06, adv7604_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 818 } else {
819 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
820 __func__, state->selected_input);
ccbd5bc4 821 err = -1;
ccbd5bc4
HV		 822 }
823
824
825 return err;
826}
827
828static void configure_custom_video_timings(struct v4l2_subdev *sd,
829 const struct v4l2_bt_timings *bt)
830{
831 struct adv7604_state *state = to_state(sd);
54450f59 832 struct i2c_client *client = v4l2_get_subdevdata(sd);
ccbd5bc4
HV		 833 u32 width = htotal(bt);
834 u32 height = vtotal(bt);
835 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
836 u16 cp_start_eav = width - bt->hfrontporch;
837 u16 cp_start_vbi = height - bt->vfrontporch;
838 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
839 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
840 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
841 const u8 pll[2] = {
842 0xc0 | ((width >> 8) & 0x1f),
843 width & 0xff
844 };
54450f59
HV		 845
846 v4l2_dbg(2, debug, sd, "%s\n", __func__);
847
4a31a93a 848 if (is_analog_input(sd)) {
ccbd5bc4
HV		 849 /* auto graphics */
850 io_write(sd, 0x00, 0x07); /* video std */
851 io_write(sd, 0x01, 0x02); /* prim mode */
852 /* enable embedded syncs for auto graphics mode */
853 cp_write_and_or(sd, 0x81, 0xef, 0x10);
54450f59 854
ccbd5bc4 855 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 856 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
857 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
4a31a93a 858 if (adv_smbus_write_i2c_block_data(client, 0x16, 2, pll))
54450f59 859 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 860
861 /* active video - horizontal timing */
54450f59 862 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 863 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 864 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 865 cp_write(sd, 0xa4, cp_start_eav & 0xff);
866
867 /* active video - vertical timing */
54450f59 868 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 869 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 870 ((cp_end_vbi >> 8) & 0xf));
54450f59 871 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 872 } else if (is_digital_input(sd)) {
ccbd5bc4 873 /* set default prim_mode/vid_std for HDMI
39c1cb2b 874 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 875 io_write(sd, 0x00, 0x02); /* video std */
876 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 877 } else {
878 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
879 __func__, state->selected_input);
54450f59 880 }
54450f59 881
ccbd5bc4
HV		 882 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
883 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
884 cp_write(sd, 0xab, (height >> 4) & 0xff);
885 cp_write(sd, 0xac, (height & 0x0f) << 4);
886}
54450f59
HV		 887
888static void set_rgb_quantization_range(struct v4l2_subdev *sd)
889{
890 struct adv7604_state *state = to_state(sd);
891
9833239e
MR		 892 v4l2_dbg(2, debug, sd, "%s: rgb_quantization_range = %d\n",
893 __func__, state->rgb_quantization_range);
894
54450f59
HV		 895 switch (state->rgb_quantization_range) {
896 case V4L2_DV_RGB_RANGE_AUTO:
9833239e
MR		 897 if (state->selected_input == ADV7604_INPUT_VGA_RGB) {
898 /* Receiving analog RGB signal
899 * Set RGB full range (0-255) */
900 io_write_and_or(sd, 0x02, 0x0f, 0x10);
901 break;
902 }
903
904 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
905 /* Receiving analog YPbPr signal
906 * Set automode */
907 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
908 break;
909 }
910
911 if (hdmi_read(sd, 0x05) & 0x80) {
912 /* Receiving HDMI signal
913 * Set automode */
6b0d5d34 914 io_write_and_or(sd, 0x02, 0x0f, 0xf0);
9833239e
MR		 915 break;
916 }
917
918 /* Receiving DVI-D signal
919 * ADV7604 selects RGB limited range regardless of
920 * input format (CE/IT) in automatic mode */
921 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
922 /* RGB limited range (16-235) */
923 io_write_and_or(sd, 0x02, 0x0f, 0x00);
924 } else {
925 /* RGB full range (0-255) */
926 io_write_and_or(sd, 0x02, 0x0f, 0x10);
54450f59
HV		 927 }
928 break;
929 case V4L2_DV_RGB_RANGE_LIMITED:
d261e842
MR		 930 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
931 /* YCrCb limited range (16-235) */
932 io_write_and_or(sd, 0x02, 0x0f, 0x20);
933 } else {
934 /* RGB limited range (16-235) */
935 io_write_and_or(sd, 0x02, 0x0f, 0x00);
936 }
54450f59
HV		 937 break;
938 case V4L2_DV_RGB_RANGE_FULL:
d261e842
MR		 939 if (state->selected_input == ADV7604_INPUT_VGA_COMP) {
940 /* YCrCb full range (0-255) */
941 io_write_and_or(sd, 0x02, 0x0f, 0x60);
942 } else {
943 /* RGB full range (0-255) */
944 io_write_and_or(sd, 0x02, 0x0f, 0x10);
945 }
54450f59
HV		 946 break;
947 }
948}
949
54450f59
HV		 950static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
951{
952 struct v4l2_subdev *sd = to_sd(ctrl);
953 struct adv7604_state *state = to_state(sd);
954
955 switch (ctrl->id) {
956 case V4L2_CID_BRIGHTNESS:
957 cp_write(sd, 0x3c, ctrl->val);
958 return 0;
959 case V4L2_CID_CONTRAST:
960 cp_write(sd, 0x3a, ctrl->val);
961 return 0;
962 case V4L2_CID_SATURATION:
963 cp_write(sd, 0x3b, ctrl->val);
964 return 0;
965 case V4L2_CID_HUE:
966 cp_write(sd, 0x3d, ctrl->val);
967 return 0;
968 case V4L2_CID_DV_RX_RGB_RANGE:
969 state->rgb_quantization_range = ctrl->val;
970 set_rgb_quantization_range(sd);
971 return 0;
972 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
973 /* Set the analog sampling phase. This is needed to find the
974 best sampling phase for analog video: an application or
975 driver has to try a number of phases and analyze the picture
976 quality before settling on the best performing phase. */
977 afe_write(sd, 0xc8, ctrl->val);
978 return 0;
979 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
980 /* Use the default blue color for free running mode,
981 or supply your own. */
982 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));
983 return 0;
984 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
985 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
986 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
987 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
988 return 0;
989 }
990 return -EINVAL;
991}
992
54450f59
HV		 993/* ----------------------------------------------------------------------- */
994
995static inline bool no_power(struct v4l2_subdev *sd)
996{
997 /* Entire chip or CP powered off */
998 return io_read(sd, 0x0c) & 0x24;
999}
1000
1001static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1002{
4a31a93a
MR		 1003 struct adv7604_state *state = to_state(sd);
1004
1005 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1006}
1007
1008static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1009{
1010 return (io_read(sd, 0x6a) & 0xe0) != 0xe0;
1011}
1012
bb88f325
MB		 1013static inline bool is_hdmi(struct v4l2_subdev *sd)
1014{
1015 return hdmi_read(sd, 0x05) & 0x80;
1016}
1017
54450f59
HV		 1018static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1019{
1020 /* TODO channel 2 */
1021 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1022}
1023
1024static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1025{
1026 /* TODO channel 2 */
1027 return !(cp_read(sd, 0xb1) & 0x80);
1028}
1029
1030static inline bool no_signal(struct v4l2_subdev *sd)
1031{
54450f59
HV		 1032 bool ret;
1033
1034 ret = no_power(sd);
1035
1036 ret |= no_lock_stdi(sd);
1037 ret |= no_lock_sspd(sd);
1038
4a31a93a 1039 if (is_digital_input(sd)) {
54450f59
HV		 1040 ret |= no_lock_tmds(sd);
1041 ret |= no_signal_tmds(sd);
1042 }
1043
1044 return ret;
1045}
1046
1047static inline bool no_lock_cp(struct v4l2_subdev *sd)
1048{
1049 /* CP has detected a non standard number of lines on the incoming
1050 video compared to what it is configured to receive by s_dv_timings */
1051 return io_read(sd, 0x12) & 0x01;
1052}
1053
1054static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1055{
54450f59
HV		 1056 *status = 0;
1057 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1058 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1059 if (no_lock_cp(sd))
4a31a93a 1060 *status |= is_digital_input(sd) ? V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1061
1062 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1063
1064 return 0;
1065}
1066
1067/* ----------------------------------------------------------------------- */
1068
54450f59
HV		 1069struct stdi_readback {
1070 u16 bl, lcf, lcvs;
1071 u8 hs_pol, vs_pol;
1072 bool interlaced;
1073};
1074
1075static int stdi2dv_timings(struct v4l2_subdev *sd,
1076 struct stdi_readback *stdi,
1077 struct v4l2_dv_timings *timings)
1078{
1079 struct adv7604_state *state = to_state(sd);
1080 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1081 u32 pix_clk;
1082 int i;
1083
1084 for (i = 0; adv7604_timings[i].bt.height; i++) {
1085 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1086 continue;
1087 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1088 continue;
1089
1090 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1091
1092 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1093 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1094 *timings = adv7604_timings[i];
1095 return 0;
1096 }
1097 }
1098
1099 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1100 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1101 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1102 timings))
1103 return 0;
1104 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1105 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1106 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1107 state->aspect_ratio, timings))
1108 return 0;
1109
ccbd5bc4
HV		 1110 v4l2_dbg(2, debug, sd,
1111 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1112 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1113 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1114 return -1;
1115}
1116
1117static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1118{
1119 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1120 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1121 return -1;
1122 }
1123
1124 /* read STDI */
1125 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);
1126 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);
1127 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1128 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1129
1130 /* read SSPD */
1131 if ((cp_read(sd, 0xb5) & 0x03) == 0x01) {
1132 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?
1133 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');
1134 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?
1135 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');
1136 } else {
1137 stdi->hs_pol = 'x';
1138 stdi->vs_pol = 'x';
1139 }
1140
1141 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1142 v4l2_dbg(2, debug, sd,
1143 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1144 return -1;
1145 }
1146
1147 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1148 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1149 memset(stdi, 0, sizeof(struct stdi_readback));
1150 return -1;
1151 }
1152
1153 v4l2_dbg(2, debug, sd,
1154 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1155 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1156 stdi->hs_pol, stdi->vs_pol,
1157 stdi->interlaced ? "interlaced" : "progressive");
1158
1159 return 0;
1160}
1161
1162static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1163 struct v4l2_enum_dv_timings *timings)
1164{
1165 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1166 return -EINVAL;
1167 memset(timings->reserved, 0, sizeof(timings->reserved));
1168 timings->timings = adv7604_timings[timings->index];
1169 return 0;
1170}
1171
1172static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1173 struct v4l2_dv_timings_cap *cap)
1174{
54450f59
HV		 1175 cap->type = V4L2_DV_BT_656_1120;
1176 cap->bt.max_width = 1920;
1177 cap->bt.max_height = 1200;
fe9c2564 1178 cap->bt.min_pixelclock = 25000000;
4a31a93a 1179 if (is_digital_input(sd))
54450f59
HV		 1180 cap->bt.max_pixelclock = 225000000;
1181 else
1182 cap->bt.max_pixelclock = 170000000;
1183 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1184 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1185 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1186 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1187 return 0;
1188}
1189
1190/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1191 if the format is listed in adv7604_timings[] */
1192static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1193 struct v4l2_dv_timings *timings)
1194{
54450f59
HV		 1195 int i;
1196
1197 for (i = 0; adv7604_timings[i].bt.width; i++) {
ef1ed8f5 1198 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
4a31a93a 1199 is_digital_input(sd) ? 250000 : 1000000)) {
54450f59
HV		 1200 *timings = adv7604_timings[i];
1201 break;
1202 }
1203 }
1204}
1205
1206static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1207 struct v4l2_dv_timings *timings)
1208{
1209 struct adv7604_state *state = to_state(sd);
1210 struct v4l2_bt_timings *bt = &timings->bt;
1211 struct stdi_readback stdi;
1212
1213 if (!timings)
1214 return -EINVAL;
1215
1216 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1217
1218 if (no_signal(sd)) {
1219 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1220 return -ENOLINK;
1221 }
1222
1223 /* read STDI */
1224 if (read_stdi(sd, &stdi)) {
1225 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1226 return -ENOLINK;
1227 }
1228 bt->interlaced = stdi.interlaced ?
1229 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1230
4a31a93a 1231 if (is_digital_input(sd)) {
bb88f325
MB		 1232 uint32_t freq;
1233
54450f59
HV		 1234 timings->type = V4L2_DV_BT_656_1120;
1235
1236 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);
1237 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);
bb88f325 1238 freq = (hdmi_read(sd, 0x06) * 1000000) +
54450f59 1239 ((hdmi_read(sd, 0x3b) & 0x30) >> 4) * 250000;
bb88f325
MB		 1240 if (is_hdmi(sd)) {
1241 /* adjust for deep color mode */
1242 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1243
1244 freq = freq * 8 / bits_per_channel;
1245 }
1246 bt->pixelclock = freq;
54450f59
HV		 1247 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +
1248 hdmi_read(sd, 0x21);
1249 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +
1250 hdmi_read(sd, 0x23);
1251 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +
1252 hdmi_read(sd, 0x25);
1253 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +
1254 hdmi_read(sd, 0x2b)) / 2;
1255 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +
1256 hdmi_read(sd, 0x2f)) / 2;
1257 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +
1258 hdmi_read(sd, 0x33)) / 2;
1259 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1260 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1261 if (bt->interlaced == V4L2_DV_INTERLACED) {
1262 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +
1263 hdmi_read(sd, 0x0c);
1264 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +
1265 hdmi_read(sd, 0x2d)) / 2;
1266 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +
1267 hdmi_read(sd, 0x31)) / 2;
1268 bt->vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +
1269 hdmi_read(sd, 0x35)) / 2;
1270 }
1271 adv7604_fill_optional_dv_timings_fields(sd, timings);
1272 } else {
1273 /* find format
80939647 1274 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1275 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1276 */
1277 if (!stdi2dv_timings(sd, &stdi, timings))
1278 goto found;
1279 stdi.lcvs += 1;
1280 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1281 if (!stdi2dv_timings(sd, &stdi, timings))
1282 goto found;
1283 stdi.lcvs -= 2;
1284 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1285 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1286 /*
1287 * The STDI block may measure wrong values, especially
1288 * for lcvs and lcf. If the driver can not find any
1289 * valid timing, the STDI block is restarted to measure
1290 * the video timings again. The function will return an
1291 * error, but the restart of STDI will generate a new
1292 * STDI interrupt and the format detection process will
1293 * restart.
1294 */
1295 if (state->restart_stdi_once) {
1296 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1297 /* TODO restart STDI for Sync Channel 2 */
1298 /* enter one-shot mode */
1299 cp_write_and_or(sd, 0x86, 0xf9, 0x00);
1300 /* trigger STDI restart */
1301 cp_write_and_or(sd, 0x86, 0xf9, 0x04);
1302 /* reset to continuous mode */
1303 cp_write_and_or(sd, 0x86, 0xf9, 0x02);
1304 state->restart_stdi_once = false;
1305 return -ENOLINK;
1306 }
54450f59
HV		 1307 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1308 return -ERANGE;
1309 }
cf9afb1d 1310 state->restart_stdi_once = true;
54450f59
HV		 1311 }
1312found:
1313
1314 if (no_signal(sd)) {
1315 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1316 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1317 return -ENOLINK;
1318 }
1319
4a31a93a
MR		 1320 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1321 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1322 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1323 __func__, (u32)bt->pixelclock);
1324 return -ERANGE;
1325 }
1326
1327 if (debug > 1)
11d034c8
HV		 1328 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1329 timings, true);
54450f59
HV		 1330
1331 return 0;
1332}
1333
1334static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1335 struct v4l2_dv_timings *timings)
1336{
1337 struct adv7604_state *state = to_state(sd);
1338 struct v4l2_bt_timings *bt;
ccbd5bc4 1339 int err;
54450f59
HV		 1340
1341 if (!timings)
1342 return -EINVAL;
1343
1344 bt = &timings->bt;
1345
4a31a93a
MR		 1346 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1347 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1348 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1349 __func__, (u32)bt->pixelclock);
1350 return -ERANGE;
1351 }
ccbd5bc4 1352
54450f59
HV		 1353 adv7604_fill_optional_dv_timings_fields(sd, timings);
1354
1355 state->timings = *timings;
1356
ccbd5bc4
HV		 1357 cp_write(sd, 0x91, bt->interlaced ? 0x50 : 0x10);
1358
1359 /* Use prim_mode and vid_std when available */
1360 err = configure_predefined_video_timings(sd, timings);
1361 if (err) {
1362 /* custom settings when the video format
1363 does not have prim_mode/vid_std */
1364 configure_custom_video_timings(sd, bt);
1365 }
54450f59
HV		 1366
1367 set_rgb_quantization_range(sd);
1368
1369
1370 if (debug > 1)
11d034c8
HV		 1371 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1372 timings, true);
54450f59
HV		 1373 return 0;
1374}
1375
1376static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1377 struct v4l2_dv_timings *timings)
1378{
1379 struct adv7604_state *state = to_state(sd);
1380
1381 *timings = state->timings;
1382 return 0;
1383}
1384
6b0d5d34 1385static void enable_input(struct v4l2_subdev *sd)
54450f59 1386{
6b0d5d34
HV		 1387 struct adv7604_state *state = to_state(sd);
1388
4a31a93a 1389 if (is_analog_input(sd)) {
54450f59 1390 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1391 } else if (is_digital_input(sd)) {
4a31a93a 1392 hdmi_write_and_or(sd, 0x00, 0xfc, state->selected_input);
54450f59
HV		 1393 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */
1394 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
5474b983 1395 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */
4a31a93a
MR		 1396 } else {
1397 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1398 __func__, state->selected_input);
54450f59
HV		 1399 }
1400}
1401
1402static void disable_input(struct v4l2_subdev *sd)
1403{
5474b983
MR		 1404 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio */
1405 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1406 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
54450f59
HV		 1407 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */
1408}
1409
6b0d5d34 1410static void select_input(struct v4l2_subdev *sd)
54450f59 1411{
6b0d5d34 1412 struct adv7604_state *state = to_state(sd);
54450f59 1413
4a31a93a 1414 if (is_analog_input(sd)) {
54450f59
HV		 1415 /* reset ADI recommended settings for HDMI: */
1416 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1417 hdmi_write(sd, 0x0d, 0x04); /* HDMI filter optimization */
1418 hdmi_write(sd, 0x3d, 0x00); /* DDC bus active pull-up control */
1419 hdmi_write(sd, 0x3e, 0x74); /* TMDS PLL optimization */
1420 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1421 hdmi_write(sd, 0x57, 0x74); /* TMDS PLL optimization */
1422 hdmi_write(sd, 0x58, 0x63); /* TMDS PLL optimization */
1423 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1424 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1425 hdmi_write(sd, 0x93, 0x88); /* equaliser */
1426 hdmi_write(sd, 0x94, 0x2e); /* equaliser */
1427 hdmi_write(sd, 0x96, 0x00); /* enable automatic EQ changing */
1428
1429 afe_write(sd, 0x00, 0x08); /* power up ADC */
1430 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1431 afe_write(sd, 0xc8, 0x00); /* phase control */
1432
1433 /* set ADI recommended settings for digitizer */
1434 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1435 afe_write(sd, 0x12, 0x7b); /* ADC noise shaping filter controls */
1436 afe_write(sd, 0x0c, 0x1f); /* CP core gain controls */
1437 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */
1438 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1439 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1440 } else if (is_digital_input(sd)) {
1441 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1442
54450f59
HV		 1443 /* set ADI recommended settings for HDMI: */
1444 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
1445 hdmi_write(sd, 0x0d, 0x84); /* HDMI filter optimization */
1446 hdmi_write(sd, 0x3d, 0x10); /* DDC bus active pull-up control */
1447 hdmi_write(sd, 0x3e, 0x39); /* TMDS PLL optimization */
1448 hdmi_write(sd, 0x4e, 0x3b); /* TMDS PLL optimization */
1449 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */
1450 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */
1451 hdmi_write(sd, 0x8d, 0x18); /* equaliser */
1452 hdmi_write(sd, 0x8e, 0x34); /* equaliser */
1453 hdmi_write(sd, 0x93, 0x8b); /* equaliser */
1454 hdmi_write(sd, 0x94, 0x2d); /* equaliser */
1455 hdmi_write(sd, 0x96, 0x01); /* enable automatic EQ changing */
1456
1457 afe_write(sd, 0x00, 0xff); /* power down ADC */
1458 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1459 afe_write(sd, 0xc8, 0x40); /* phase control */
1460
1461 /* reset ADI recommended settings for digitizer */
1462 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
1463 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */
1464 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */
1465 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1466 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1467 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1468 } else {
1469 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1470 __func__, state->selected_input);
54450f59
HV		 1471 }
1472}
1473
1474static int adv7604_s_routing(struct v4l2_subdev *sd,
1475 u32 input, u32 output, u32 config)
1476{
1477 struct adv7604_state *state = to_state(sd);
1478
ff4f80fd
MR		 1479 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1480 __func__, input, state->selected_input);
1481
1482 if (input == state->selected_input)
1483 return 0;
54450f59 1484
4a31a93a 1485 state->selected_input = input;
54450f59
HV		 1486
1487 disable_input(sd);
1488
6b0d5d34 1489 select_input(sd);
54450f59 1490
6b0d5d34 1491 enable_input(sd);
54450f59
HV		 1492
1493 return 0;
1494}
1495
1496static int adv7604_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned int index,
1497 enum v4l2_mbus_pixelcode *code)
1498{
1499 if (index)
1500 return -EINVAL;
1501 /* Good enough for now */
1502 *code = V4L2_MBUS_FMT_FIXED;
1503 return 0;
1504}
1505
1506static int adv7604_g_mbus_fmt(struct v4l2_subdev *sd,
1507 struct v4l2_mbus_framefmt *fmt)
1508{
1509 struct adv7604_state *state = to_state(sd);
1510
1511 fmt->width = state->timings.bt.width;
1512 fmt->height = state->timings.bt.height;
1513 fmt->code = V4L2_MBUS_FMT_FIXED;
1514 fmt->field = V4L2_FIELD_NONE;
1515 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1516 fmt->colorspace = (state->timings.bt.height <= 576) ?
1517 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1518 }
1519 return 0;
1520}
1521
1522static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1523{
54450f59
HV		 1524 u8 fmt_change, fmt_change_digital, tx_5v;
1525
ff4f80fd
MR		 1526 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1527
54450f59
HV		 1528 /* format change */
1529 fmt_change = io_read(sd, 0x43) & 0x98;
1530 if (fmt_change)
1531 io_write(sd, 0x44, fmt_change);
14d03233 1532
4a31a93a 1533 fmt_change_digital = is_digital_input(sd) ? (io_read(sd, 0x6b) & 0xc0) : 0;
54450f59
HV		 1534 if (fmt_change_digital)
1535 io_write(sd, 0x6c, fmt_change_digital);
14d03233 1536
54450f59
HV		 1537 if (fmt_change || fmt_change_digital) {
1538 v4l2_dbg(1, debug, sd,
25a64ac9 1539 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1540 __func__, fmt_change, fmt_change_digital);
25a64ac9 1541
14d03233 1542 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
25a64ac9 1543
54450f59
HV		 1544 if (handled)
1545 *handled = true;
1546 }
1547 /* tx 5v detect */
4a31a93a 1548 tx_5v = io_read(sd, 0x70) & 0x1e;
54450f59
HV		 1549 if (tx_5v) {
1550 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1551 io_write(sd, 0x71, tx_5v);
1552 adv7604_s_detect_tx_5v_ctrl(sd);
1553 if (handled)
1554 *handled = true;
1555 }
1556 return 0;
1557}
1558
1559static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1560{
1561 struct adv7604_state *state = to_state(sd);
4a31a93a 1562 u8 *data = NULL;
54450f59 1563
4a31a93a 1564 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1565 return -EINVAL;
1566 if (edid->blocks == 0)
1567 return -EINVAL;
4a31a93a 1568 if (edid->blocks > 2)
54450f59 1569 return -EINVAL;
4a31a93a
MR		 1570 if (edid->start_block > 1)
1571 return -EINVAL;
1572 if (edid->start_block == 1)
1573 edid->blocks = 1;
54450f59
HV		 1574 if (!edid->edid)
1575 return -EINVAL;
4a31a93a
MR		 1576
1577 if (edid->blocks > state->edid.blocks)
1578 edid->blocks = state->edid.blocks;
1579
1580 switch (edid->pad) {
1581 case ADV7604_EDID_PORT_A:
1582 case ADV7604_EDID_PORT_B:
1583 case ADV7604_EDID_PORT_C:
1584 case ADV7604_EDID_PORT_D:
1585 if (state->edid.present & (1 << edid->pad))
1586 data = state->edid.edid;
1587 break;
1588 default:
1589 return -EINVAL;
1590 break;
1591 }
1592 if (!data)
1593 return -ENODATA;
1594
1595 memcpy(edid->edid,
1596 data + edid->start_block * 128,
54450f59
HV		 1597 edid->blocks * 128);
1598 return 0;
1599}
1600
dd08beb9 1601static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1602{
1603 u8 d;
1604
1605 if ((edid[0x7e] != 1) ||
1606 (edid[0x80] != 0x02) ||
1607 (edid[0x81] != 0x03)) {
1608 return -1;
1609 }
1610
1611 /* search Vendor Specific Data Block (tag 3) */
1612 d = edid[0x82] & 0x7f;
1613 if (d > 4) {
1614 int i = 0x84;
1615 int end = 0x80 + d;
1616
1617 do {
1618 u8 tag = edid[i] >> 5;
1619 u8 len = edid[i] & 0x1f;
1620
1621 if ((tag == 3) && (len >= 5))
1622 return i + 4;
1623 i += len + 1;
1624 } while (i < end);
1625 }
1626 return -1;
1627}
1628
54450f59
HV		 1629static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_subdev_edid *edid)
1630{
1631 struct adv7604_state *state = to_state(sd);
dd08beb9 1632 int spa_loc;
3e86aa85 1633 int tmp = 0;
54450f59 1634 int err;
dd08beb9 1635 int i;
54450f59 1636
4a31a93a 1637 if (edid->pad > ADV7604_EDID_PORT_D)
54450f59
HV		 1638 return -EINVAL;
1639 if (edid->start_block != 0)
1640 return -EINVAL;
1641 if (edid->blocks == 0) {
3e86aa85 1642 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a
MR		 1643 state->edid.present &= ~(1 << edid->pad);
1644 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&state->edid.present);
3e86aa85
MR		 1645 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1646
54450f59
HV		 1647 /* Fall back to a 16:9 aspect ratio */
1648 state->aspect_ratio.numerator = 16;
1649 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 1650
1651 if (!state->edid.present)
1652 state->edid.blocks = 0;
1653
1654 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
1655 __func__, edid->pad, state->edid.present);
54450f59
HV		 1656 return 0;
1657 }
4a31a93a
MR		 1658 if (edid->blocks > 2) {
1659 edid->blocks = 2;
54450f59 1660 return -E2BIG;
4a31a93a 1661 }
54450f59
HV		 1662 if (!edid->edid)
1663 return -EINVAL;
4a31a93a 1664
dd08beb9
MR		 1665 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
1666 __func__, edid->pad, state->edid.present);
1667
3e86aa85 1668 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 1669 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3e86aa85
MR		 1670 v4l2_subdev_notify(sd, ADV7604_HOTPLUG, (void *)&tmp);
1671 rep_write_and_or(sd, 0x77, 0xf0, 0x00);
1672
dd08beb9
MR		 1673 spa_loc = get_edid_spa_location(edid->edid);
1674 if (spa_loc < 0)
1675 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
1676
3e86aa85
MR		 1677 switch (edid->pad) {
1678 case ADV7604_EDID_PORT_A:
dd08beb9
MR		 1679 state->spa_port_a[0] = edid->edid[spa_loc];
1680 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85
MR		 1681 break;
1682 case ADV7604_EDID_PORT_B:
dd08beb9
MR		 1683 rep_write(sd, 0x70, edid->edid[spa_loc]);
1684 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85
MR		 1685 break;
1686 case ADV7604_EDID_PORT_C:
dd08beb9
MR		 1687 rep_write(sd, 0x72, edid->edid[spa_loc]);
1688 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85
MR		 1689 break;
1690 case ADV7604_EDID_PORT_D:
dd08beb9
MR		 1691 rep_write(sd, 0x74, edid->edid[spa_loc]);
1692 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 1693 break;
dd08beb9
MR		 1694 default:
1695 return -EINVAL;
3e86aa85 1696 }
dd08beb9
MR		 1697 rep_write(sd, 0x76, spa_loc & 0xff);
1698 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);
3e86aa85 1699
dd08beb9
MR		 1700 edid->edid[spa_loc] = state->spa_port_a[0];
1701 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 1702
1703 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
1704 state->edid.blocks = edid->blocks;
54450f59
HV		 1705 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
1706 edid->edid[0x16]);
3e86aa85 1707 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 1708
1709 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
1710 if (err < 0) {
3e86aa85 1711 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 1712 return err;
1713 }
1714
dd08beb9
MR		 1715 /* adv7604 calculates the checksums and enables I2C access to internal
1716 EDID RAM from DDC port. */
1717 rep_write_and_or(sd, 0x77, 0xf0, state->edid.present);
1718
1719 for (i = 0; i < 1000; i++) {
1720 if (rep_read(sd, 0x7d) & state->edid.present)
1721 break;
1722 mdelay(1);
1723 }
1724 if (i == 1000) {
1725 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
1726 return -EIO;
1727 }
1728
1729
4a31a93a
MR		 1730 /* enable hotplug after 100 ms */
1731 queue_delayed_work(state->work_queues,
1732 &state->delayed_work_enable_hotplug, HZ / 10);
1733 return 0;
54450f59
HV		 1734}
1735
1736/*********** avi info frame CEA-861-E **************/
1737
1738static void print_avi_infoframe(struct v4l2_subdev *sd)
1739{
1740 int i;
1741 u8 buf[14];
1742 u8 avi_len;
1743 u8 avi_ver;
1744
bb88f325 1745 if (!is_hdmi(sd)) {
54450f59
HV		 1746 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
1747 return;
1748 }
1749 if (!(io_read(sd, 0x60) & 0x01)) {
1750 v4l2_info(sd, "AVI infoframe not received\n");
1751 return;
1752 }
1753
1754 if (io_read(sd, 0x83) & 0x01) {
1755 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
1756 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1757 if (io_read(sd, 0x83) & 0x01) {
1758 v4l2_info(sd, "AVI infoframe checksum error still present\n");
1759 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
1760 }
1761 }
1762
1763 avi_len = infoframe_read(sd, 0xe2);
1764 avi_ver = infoframe_read(sd, 0xe1);
1765 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
1766 avi_ver, avi_len);
1767
1768 if (avi_ver != 0x02)
1769 return;
1770
1771 for (i = 0; i < 14; i++)
1772 buf[i] = infoframe_read(sd, i);
1773
1774 v4l2_info(sd,
1775 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
1776 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
1777 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
1778}
1779
1780static int adv7604_log_status(struct v4l2_subdev *sd)
1781{
1782 struct adv7604_state *state = to_state(sd);
1783 struct v4l2_dv_timings timings;
1784 struct stdi_readback stdi;
1785 u8 reg_io_0x02 = io_read(sd, 0x02);
1786
1787 char *csc_coeff_sel_rb[16] = {
1788 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
1789 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
1790 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
1791 "reserved", "reserved", "reserved", "reserved", "manual"
1792 };
1793 char *input_color_space_txt[16] = {
1794 "RGB limited range (16-235)", "RGB full range (0-255)",
1795 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 1796 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 1797 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
1798 "invalid", "invalid", "invalid", "invalid", "invalid",
1799 "invalid", "invalid", "automatic"
1800 };
1801 char *rgb_quantization_range_txt[] = {
1802 "Automatic",
1803 "RGB limited range (16-235)",
1804 "RGB full range (0-255)",
1805 };
bb88f325
MB		 1806 char *deep_color_mode_txt[4] = {
1807 "8-bits per channel",
1808 "10-bits per channel",
1809 "12-bits per channel",
1810 "16-bits per channel (not supported)"
1811 };
54450f59
HV		 1812
1813 v4l2_info(sd, "-----Chip status-----\n");
1814 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
4a31a93a
MR		 1815 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
1816 ((rep_read(sd, 0x7d) & 0x01) ? "Yes" : "No"),
1817 ((rep_read(sd, 0x7d) & 0x02) ? "Yes" : "No"),
1818 ((rep_read(sd, 0x7d) & 0x04) ? "Yes" : "No"),
1819 ((rep_read(sd, 0x7d) & 0x08) ? "Yes" : "No"));
54450f59
HV		 1820 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
1821 "enabled" : "disabled");
1822
1823 v4l2_info(sd, "-----Signal status-----\n");
4a31a93a
MR		 1824 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
1825 ((io_read(sd, 0x6f) & 0x10) ? "Yes" : "No"),
1826 ((io_read(sd, 0x6f) & 0x08) ? "Yes" : "No"),
1827 ((io_read(sd, 0x6f) & 0x04) ? "Yes" : "No"),
1828 ((io_read(sd, 0x6f) & 0x02) ? "Yes" : "No"));
54450f59
HV		 1829 v4l2_info(sd, "TMDS signal detected: %s\n",
1830 no_signal_tmds(sd) ? "false" : "true");
1831 v4l2_info(sd, "TMDS signal locked: %s\n",
1832 no_lock_tmds(sd) ? "false" : "true");
1833 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
1834 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
1835 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
1836 v4l2_info(sd, "CP free run: %s\n",
1837 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));
ccbd5bc4
HV		 1838 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
1839 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
1840 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 1841
1842 v4l2_info(sd, "-----Video Timings-----\n");
1843 if (read_stdi(sd, &stdi))
1844 v4l2_info(sd, "STDI: not locked\n");
1845 else
1846 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
1847 stdi.lcf, stdi.bl, stdi.lcvs,
1848 stdi.interlaced ? "interlaced" : "progressive",
1849 stdi.hs_pol, stdi.vs_pol);
1850 if (adv7604_query_dv_timings(sd, &timings))
1851 v4l2_info(sd, "No video detected\n");
1852 else
11d034c8
HV		 1853 v4l2_print_dv_timings(sd->name, "Detected format: ",
1854 &timings, true);
1855 v4l2_print_dv_timings(sd->name, "Configured format: ",
1856 &state->timings, true);
54450f59 1857
76eb2d30
MR		 1858 if (no_signal(sd))
1859 return 0;
1860
54450f59
HV		 1861 v4l2_info(sd, "-----Color space-----\n");
1862 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
1863 rgb_quantization_range_txt[state->rgb_quantization_range]);
1864 v4l2_info(sd, "Input color space: %s\n",
1865 input_color_space_txt[reg_io_0x02 >> 4]);
1866 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
1867 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
1868 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
1869 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 1870 "enabled" : "disabled");
54450f59
HV		 1871 v4l2_info(sd, "Color space conversion: %s\n",
1872 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
1873
4a31a93a 1874 if (!is_digital_input(sd))
76eb2d30
MR		 1875 return 0;
1876
1877 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 1878 v4l2_info(sd, "Digital video port selected: %c\n",
1879 (hdmi_read(sd, 0x00) & 0x03) + 'A');
1880 v4l2_info(sd, "HDCP encrypted content: %s\n",
1881 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 1882 v4l2_info(sd, "HDCP keys read: %s%s\n",
1883 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
1884 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
1885 if (!is_hdmi(sd)) {
1886 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
1887 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
1888 bool audio_mute = io_read(sd, 0x65) & 0x40;
1889
1890 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
1891 audio_pll_locked ? "locked" : "not locked",
1892 audio_sample_packet_detect ? "detected" : "not detected",
1893 audio_mute ? "muted" : "enabled");
1894 if (audio_pll_locked && audio_sample_packet_detect) {
1895 v4l2_info(sd, "Audio format: %s\n",
1896 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
1897 }
1898 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
1899 (hdmi_read(sd, 0x5c) << 8) +
1900 (hdmi_read(sd, 0x5d) & 0xf0));
1901 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
1902 (hdmi_read(sd, 0x5e) << 8) +
1903 hdmi_read(sd, 0x5f));
1904 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
1905
1906 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
1907
54450f59
HV		 1908 print_avi_infoframe(sd);
1909 }
1910
1911 return 0;
1912}
1913
1914/* ----------------------------------------------------------------------- */
1915
1916static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
1917 .s_ctrl = adv7604_s_ctrl,
1918};
1919
1920static const struct v4l2_subdev_core_ops adv7604_core_ops = {
1921 .log_status = adv7604_log_status,
1922 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1923 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1924 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1925 .g_ctrl = v4l2_subdev_g_ctrl,
1926 .s_ctrl = v4l2_subdev_s_ctrl,
1927 .queryctrl = v4l2_subdev_queryctrl,
1928 .querymenu = v4l2_subdev_querymenu,
54450f59
HV		 1929 .interrupt_service_routine = adv7604_isr,
1930#ifdef CONFIG_VIDEO_ADV_DEBUG
1931 .g_register = adv7604_g_register,
1932 .s_register = adv7604_s_register,
1933#endif
1934};
1935
1936static const struct v4l2_subdev_video_ops adv7604_video_ops = {
1937 .s_routing = adv7604_s_routing,
1938 .g_input_status = adv7604_g_input_status,
1939 .s_dv_timings = adv7604_s_dv_timings,
1940 .g_dv_timings = adv7604_g_dv_timings,
1941 .query_dv_timings = adv7604_query_dv_timings,
1942 .enum_dv_timings = adv7604_enum_dv_timings,
1943 .dv_timings_cap = adv7604_dv_timings_cap,
1944 .enum_mbus_fmt = adv7604_enum_mbus_fmt,
1945 .g_mbus_fmt = adv7604_g_mbus_fmt,
1946 .try_mbus_fmt = adv7604_g_mbus_fmt,
1947 .s_mbus_fmt = adv7604_g_mbus_fmt,
1948};
1949
1950static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
1951 .get_edid = adv7604_get_edid,
1952 .set_edid = adv7604_set_edid,
1953};
1954
1955static const struct v4l2_subdev_ops adv7604_ops = {
1956 .core = &adv7604_core_ops,
1957 .video = &adv7604_video_ops,
1958 .pad = &adv7604_pad_ops,
1959};
1960
1961/* -------------------------- custom ctrls ---------------------------------- */
1962
1963static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
1964 .ops = &adv7604_ctrl_ops,
1965 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
1966 .name = "Analog Sampling Phase",
1967 .type = V4L2_CTRL_TYPE_INTEGER,
1968 .min = 0,
1969 .max = 0x1f,
1970 .step = 1,
1971 .def = 0,
1972};
1973
1974static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
1975 .ops = &adv7604_ctrl_ops,
1976 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
1977 .name = "Free Running Color, Manual",
1978 .type = V4L2_CTRL_TYPE_BOOLEAN,
1979 .min = false,
1980 .max = true,
1981 .step = 1,
1982 .def = false,
1983};
1984
1985static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
1986 .ops = &adv7604_ctrl_ops,
1987 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
1988 .name = "Free Running Color",
1989 .type = V4L2_CTRL_TYPE_INTEGER,
1990 .min = 0x0,
1991 .max = 0xffffff,
1992 .step = 0x1,
1993 .def = 0x0,
1994};
1995
1996/* ----------------------------------------------------------------------- */
1997
1998static int adv7604_core_init(struct v4l2_subdev *sd)
1999{
2000 struct adv7604_state *state = to_state(sd);
2001 struct adv7604_platform_data *pdata = &state->pdata;
2002
2003 hdmi_write(sd, 0x48,
2004 (pdata->disable_pwrdnb ? 0x80 : 0) |
2005 (pdata->disable_cable_det_rst ? 0x40 : 0));
2006
2007 disable_input(sd);
2008
2009 /* power */
2010 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2011 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2012 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2013
2014 /* video format */
2015 io_write_and_or(sd, 0x02, 0xf0,
2016 pdata->alt_gamma << 3 |
2017 pdata->op_656_range << 2 |
2018 pdata->rgb_out << 1 |
2019 pdata->alt_data_sat << 0);
2020 io_write(sd, 0x03, pdata->op_format_sel);
2021 io_write_and_or(sd, 0x04, 0x1f, pdata->op_ch_sel << 5);
2022 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |
2023 pdata->insert_av_codes << 2 |
2024 pdata->replicate_av_codes << 1 |
2025 pdata->invert_cbcr << 0);
2026
2027 /* TODO from platform data */
2028 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
2029 io_write(sd, 0x06, 0xa6); /* positive VS and HS */
f31b62e1
MK		 2030
2031 /* Adjust drive strength */
2032 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2033 pdata->dr_str_clk << 2 |
2034 pdata->dr_str_sync);
2035
54450f59
HV		 2036 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2037 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2038 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2039 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2040 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2041 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2042 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2043 for digital formats */
2044
5474b983
MR		 2045 /* HDMI audio */
2046 hdmi_write_and_or(sd, 0x15, 0xfc, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2047 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */
2048 hdmi_write_and_or(sd, 0x68, 0xf9, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
2049
54450f59
HV		 2050 /* TODO from platform data */
2051 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2052
2053 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
2054 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);
2055
54450f59
HV		 2056 /* interrupts */
2057 io_write(sd, 0x40, 0xc2); /* Configure INT1 */
2058 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2059 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
2060 io_write(sd, 0x6e, 0xc0); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
4a31a93a 2061 io_write(sd, 0x73, 0x1e); /* Enable CABLE_DET_A_ST (+5v) interrupts */
54450f59
HV		 2062
2063 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2064}
2065
2066static void adv7604_unregister_clients(struct adv7604_state *state)
2067{
2068 if (state->i2c_avlink)
2069 i2c_unregister_device(state->i2c_avlink);
2070 if (state->i2c_cec)
2071 i2c_unregister_device(state->i2c_cec);
2072 if (state->i2c_infoframe)
2073 i2c_unregister_device(state->i2c_infoframe);
2074 if (state->i2c_esdp)
2075 i2c_unregister_device(state->i2c_esdp);
2076 if (state->i2c_dpp)
2077 i2c_unregister_device(state->i2c_dpp);
2078 if (state->i2c_afe)
2079 i2c_unregister_device(state->i2c_afe);
2080 if (state->i2c_repeater)
2081 i2c_unregister_device(state->i2c_repeater);
2082 if (state->i2c_edid)
2083 i2c_unregister_device(state->i2c_edid);
2084 if (state->i2c_hdmi)
2085 i2c_unregister_device(state->i2c_hdmi);
2086 if (state->i2c_test)
2087 i2c_unregister_device(state->i2c_test);
2088 if (state->i2c_cp)
2089 i2c_unregister_device(state->i2c_cp);
2090 if (state->i2c_vdp)
2091 i2c_unregister_device(state->i2c_vdp);
2092}
2093
2094static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2095 u8 addr, u8 io_reg)
2096{
2097 struct i2c_client *client = v4l2_get_subdevdata(sd);
2098
2099 if (addr)
2100 io_write(sd, io_reg, addr << 1);
2101 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2102}
2103
2104static int adv7604_probe(struct i2c_client *client,
2105 const struct i2c_device_id *id)
2106{
2107 struct adv7604_state *state;
2108 struct adv7604_platform_data *pdata = client->dev.platform_data;
2109 struct v4l2_ctrl_handler *hdl;
2110 struct v4l2_subdev *sd;
2111 int err;
2112
2113 /* Check if the adapter supports the needed features */
2114 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2115 return -EIO;
2116 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2117 client->addr << 1);
2118
c02b211d 2119 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59
HV		 2120 if (!state) {
2121 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2122 return -ENOMEM;
2123 }
2124
25a64ac9
MR		 2125 /* initialize variables */
2126 state->restart_stdi_once = true;
ff4f80fd 2127 state->selected_input = ~0;
25a64ac9 2128
54450f59
HV		 2129 /* platform data */
2130 if (!pdata) {
2131 v4l_err(client, "No platform data!\n");
c02b211d 2132 return -ENODEV;
54450f59
HV		 2133 }
2134 memcpy(&state->pdata, pdata, sizeof(state->pdata));
2135
2136 sd = &state->sd;
2137 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
2138 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59
HV		 2139
2140 /* i2c access to adv7604? */
2141 if (adv_smbus_read_byte_data_check(client, 0xfb, false) != 0x68) {
2142 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2143 client->addr << 1);
c02b211d 2144 return -ENODEV;
54450f59
HV		 2145 }
2146
2147 /* control handlers */
2148 hdl = &state->hdl;
2149 v4l2_ctrl_handler_init(hdl, 9);
2150
2151 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2152 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2153 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2154 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2155 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2156 V4L2_CID_SATURATION, 0, 255, 1, 128);
2157 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2158 V4L2_CID_HUE, 0, 128, 1, 0);
2159
2160 /* private controls */
2161 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
4a31a93a 2162 V4L2_CID_DV_RX_POWER_PRESENT, 0, 0x0f, 0, 0);
54450f59
HV		 2163 state->rgb_quantization_range_ctrl =
2164 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2165 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2166 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2167
2168 /* custom controls */
2169 state->analog_sampling_phase_ctrl =
2170 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59
HV		 2171 state->free_run_color_manual_ctrl =
2172 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
54450f59
HV		 2173 state->free_run_color_ctrl =
2174 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
54450f59
HV		 2175
2176 sd->ctrl_handler = hdl;
2177 if (hdl->error) {
2178 err = hdl->error;
2179 goto err_hdl;
2180 }
8c0eadb8
HV		 2181 state->detect_tx_5v_ctrl->is_private = true;
2182 state->rgb_quantization_range_ctrl->is_private = true;
2183 state->analog_sampling_phase_ctrl->is_private = true;
2184 state->free_run_color_manual_ctrl->is_private = true;
2185 state->free_run_color_ctrl->is_private = true;
2186
54450f59
HV		 2187 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2188 err = -ENODEV;
2189 goto err_hdl;
2190 }
2191
2192 state->i2c_avlink = adv7604_dummy_client(sd, pdata->i2c_avlink, 0xf3);
2193 state->i2c_cec = adv7604_dummy_client(sd, pdata->i2c_cec, 0xf4);
2194 state->i2c_infoframe = adv7604_dummy_client(sd, pdata->i2c_infoframe, 0xf5);
2195 state->i2c_esdp = adv7604_dummy_client(sd, pdata->i2c_esdp, 0xf6);
2196 state->i2c_dpp = adv7604_dummy_client(sd, pdata->i2c_dpp, 0xf7);
2197 state->i2c_afe = adv7604_dummy_client(sd, pdata->i2c_afe, 0xf8);
2198 state->i2c_repeater = adv7604_dummy_client(sd, pdata->i2c_repeater, 0xf9);
2199 state->i2c_edid = adv7604_dummy_client(sd, pdata->i2c_edid, 0xfa);
2200 state->i2c_hdmi = adv7604_dummy_client(sd, pdata->i2c_hdmi, 0xfb);
2201 state->i2c_test = adv7604_dummy_client(sd, pdata->i2c_test, 0xfc);
2202 state->i2c_cp = adv7604_dummy_client(sd, pdata->i2c_cp, 0xfd);
2203 state->i2c_vdp = adv7604_dummy_client(sd, pdata->i2c_vdp, 0xfe);
2204 if (!state->i2c_avlink || !state->i2c_cec || !state->i2c_infoframe ||
2205 !state->i2c_esdp || !state->i2c_dpp || !state->i2c_afe ||
2206 !state->i2c_repeater || !state->i2c_edid || !state->i2c_hdmi ||
2207 !state->i2c_test || !state->i2c_cp || !state->i2c_vdp) {
2208 err = -ENOMEM;
2209 v4l2_err(sd, "failed to create all i2c clients\n");
2210 goto err_i2c;
2211 }
2212
2213 /* work queues */
2214 state->work_queues = create_singlethread_workqueue(client->name);
2215 if (!state->work_queues) {
2216 v4l2_err(sd, "Could not create work queue\n");
2217 err = -ENOMEM;
2218 goto err_i2c;
2219 }
2220
2221 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2222 adv7604_delayed_work_enable_hotplug);
2223
2224 state->pad.flags = MEDIA_PAD_FL_SOURCE;
2225 err = media_entity_init(&sd->entity, 1, &state->pad, 0);
2226 if (err)
2227 goto err_work_queues;
2228
2229 err = adv7604_core_init(sd);
2230 if (err)
2231 goto err_entity;
2232 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2233 client->addr << 1, client->adapter->name);
2234 return 0;
2235
2236err_entity:
2237 media_entity_cleanup(&sd->entity);
2238err_work_queues:
2239 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2240 destroy_workqueue(state->work_queues);
2241err_i2c:
2242 adv7604_unregister_clients(state);
2243err_hdl:
2244 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2245 return err;
2246}
2247
2248/* ----------------------------------------------------------------------- */
2249
2250static int adv7604_remove(struct i2c_client *client)
2251{
2252 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2253 struct adv7604_state *state = to_state(sd);
2254
2255 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2256 destroy_workqueue(state->work_queues);
2257 v4l2_device_unregister_subdev(sd);
2258 media_entity_cleanup(&sd->entity);
2259 adv7604_unregister_clients(to_state(sd));
2260 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2261 return 0;
2262}
2263
2264/* ----------------------------------------------------------------------- */
2265
2266static struct i2c_device_id adv7604_id[] = {
2267 { "adv7604", 0 },
2268 { }
2269};
2270MODULE_DEVICE_TABLE(i2c, adv7604_id);
2271
2272static struct i2c_driver adv7604_driver = {
2273 .driver = {
2274 .owner = THIS_MODULE,
2275 .name = "adv7604",
2276 },
2277 .probe = adv7604_probe,
2278 .remove = adv7604_remove,
2279 .id_table = adv7604_id,
2280};
2281
2282module_i2c_driver(adv7604_driver);
Linux kernel - Deliverables
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