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[media] si470x: fixup wait_for_completion_timeout return handling
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
c72a53ce 32#include <linux/i2c.h>
54450f59
HV		 33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
c72a53ce 36#include <linux/v4l2-dv-timings.h>
54450f59
HV		 37#include <linux/videodev2.h>
38#include <linux/workqueue.h>
c72a53ce
LP		 39
40#include <media/adv7604.h>
54450f59 41#include <media/v4l2-ctrls.h>
c72a53ce 42#include <media/v4l2-device.h>
25764158 43#include <media/v4l2-dv-timings.h>
6fa88045 44#include <media/v4l2-of.h>
54450f59
HV		 45
46static int debug;
47module_param(debug, int, 0644);
48MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
51MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53MODULE_LICENSE("GPL");
54
55/* ADV7604 system clock frequency */
56#define ADV7604_fsc (28636360)
57
539b33b0
LP		 58#define ADV7604_RGB_OUT (1 << 1)
59
60#define ADV7604_OP_FORMAT_SEL_8BIT (0 << 0)
61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
62#define ADV7604_OP_FORMAT_SEL_12BIT (2 << 0)
63
64#define ADV7604_OP_MODE_SEL_SDR_422 (0 << 5)
65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
66#define ADV7604_OP_MODE_SEL_SDR_444 (2 << 5)
67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
68#define ADV7604_OP_MODE_SEL_SDR_422_2X (4 << 5)
69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70
71#define ADV7604_OP_CH_SEL_GBR (0 << 5)
72#define ADV7604_OP_CH_SEL_GRB (1 << 5)
73#define ADV7604_OP_CH_SEL_BGR (2 << 5)
74#define ADV7604_OP_CH_SEL_RGB (3 << 5)
75#define ADV7604_OP_CH_SEL_BRG (4 << 5)
76#define ADV7604_OP_CH_SEL_RBG (5 << 5)
77
78#define ADV7604_OP_SWAP_CB_CR (1 << 0)
79
d42010a1
LPC		 80enum adv7604_type {
81 ADV7604,
82 ADV7611,
83};
84
85struct adv7604_reg_seq {
86 unsigned int reg;
87 u8 val;
88};
89
539b33b0 90struct adv7604_format_info {
f5fe58fd 91 u32 code;
539b33b0
LP		 92 u8 op_ch_sel;
93 bool rgb_out;
94 bool swap_cb_cr;
95 u8 op_format_sel;
96};
97
d42010a1
LPC		 98struct adv7604_chip_info {
99 enum adv7604_type type;
100
101 bool has_afe;
102 unsigned int max_port;
103 unsigned int num_dv_ports;
104
105 unsigned int edid_enable_reg;
106 unsigned int edid_status_reg;
107 unsigned int lcf_reg;
108
109 unsigned int cable_det_mask;
110 unsigned int tdms_lock_mask;
111 unsigned int fmt_change_digital_mask;
112
539b33b0
LP		 113 const struct adv7604_format_info *formats;
114 unsigned int nformats;
115
d42010a1
LPC		 116 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
117 void (*setup_irqs)(struct v4l2_subdev *sd);
118 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
119 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
120
121 /* 0 = AFE, 1 = HDMI */
122 const struct adv7604_reg_seq *recommended_settings[2];
123 unsigned int num_recommended_settings[2];
124
125 unsigned long page_mask;
126};
127
54450f59
HV		 128/*
129 **********************************************************************
130 *
131 * Arrays with configuration parameters for the ADV7604
132 *
133 **********************************************************************
134 */
c784b1e2 135
54450f59 136struct adv7604_state {
d42010a1 137 const struct adv7604_chip_info *info;
54450f59 138 struct adv7604_platform_data pdata;
539b33b0 139
e9d50e9e
LP		 140 struct gpio_desc *hpd_gpio[4];
141
54450f59 142 struct v4l2_subdev sd;
c784b1e2
LP		 143 struct media_pad pads[ADV7604_PAD_MAX];
144 unsigned int source_pad;
539b33b0 145
54450f59 146 struct v4l2_ctrl_handler hdl;
539b33b0 147
c784b1e2 148 enum adv7604_pad selected_input;
539b33b0 149
54450f59 150 struct v4l2_dv_timings timings;
539b33b0
LP		 151 const struct adv7604_format_info *format;
152
4a31a93a
MR		 153 struct {
154 u8 edid[256];
155 u32 present;
156 unsigned blocks;
157 } edid;
dd08beb9 158 u16 spa_port_a[2];
54450f59
HV		 159 struct v4l2_fract aspect_ratio;
160 u32 rgb_quantization_range;
161 struct workqueue_struct *work_queues;
162 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 163 bool restart_stdi_once;
54450f59
HV		 164
165 /* i2c clients */
05cacb17 166 struct i2c_client *i2c_clients[ADV7604_PAGE_MAX];
54450f59
HV		 167
168 /* controls */
169 struct v4l2_ctrl *detect_tx_5v_ctrl;
170 struct v4l2_ctrl *analog_sampling_phase_ctrl;
171 struct v4l2_ctrl *free_run_color_manual_ctrl;
172 struct v4l2_ctrl *free_run_color_ctrl;
173 struct v4l2_ctrl *rgb_quantization_range_ctrl;
174};
175
d42010a1
LPC		 176static bool adv7604_has_afe(struct adv7604_state *state)
177{
178 return state->info->has_afe;
179}
180
54450f59
HV		 181/* Supported CEA and DMT timings */
182static const struct v4l2_dv_timings adv7604_timings[] = {
183 V4L2_DV_BT_CEA_720X480P59_94,
184 V4L2_DV_BT_CEA_720X576P50,
185 V4L2_DV_BT_CEA_1280X720P24,
186 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 187 V4L2_DV_BT_CEA_1280X720P50,
188 V4L2_DV_BT_CEA_1280X720P60,
189 V4L2_DV_BT_CEA_1920X1080P24,
190 V4L2_DV_BT_CEA_1920X1080P25,
191 V4L2_DV_BT_CEA_1920X1080P30,
192 V4L2_DV_BT_CEA_1920X1080P50,
193 V4L2_DV_BT_CEA_1920X1080P60,
194
ccbd5bc4 195 /* sorted by DMT ID */
54450f59
HV		 196 V4L2_DV_BT_DMT_640X350P85,
197 V4L2_DV_BT_DMT_640X400P85,
198 V4L2_DV_BT_DMT_720X400P85,
199 V4L2_DV_BT_DMT_640X480P60,
200 V4L2_DV_BT_DMT_640X480P72,
201 V4L2_DV_BT_DMT_640X480P75,
202 V4L2_DV_BT_DMT_640X480P85,
203 V4L2_DV_BT_DMT_800X600P56,
204 V4L2_DV_BT_DMT_800X600P60,
205 V4L2_DV_BT_DMT_800X600P72,
206 V4L2_DV_BT_DMT_800X600P75,
207 V4L2_DV_BT_DMT_800X600P85,
208 V4L2_DV_BT_DMT_848X480P60,
209 V4L2_DV_BT_DMT_1024X768P60,
210 V4L2_DV_BT_DMT_1024X768P70,
211 V4L2_DV_BT_DMT_1024X768P75,
212 V4L2_DV_BT_DMT_1024X768P85,
213 V4L2_DV_BT_DMT_1152X864P75,
214 V4L2_DV_BT_DMT_1280X768P60_RB,
215 V4L2_DV_BT_DMT_1280X768P60,
216 V4L2_DV_BT_DMT_1280X768P75,
217 V4L2_DV_BT_DMT_1280X768P85,
218 V4L2_DV_BT_DMT_1280X800P60_RB,
219 V4L2_DV_BT_DMT_1280X800P60,
220 V4L2_DV_BT_DMT_1280X800P75,
221 V4L2_DV_BT_DMT_1280X800P85,
222 V4L2_DV_BT_DMT_1280X960P60,
223 V4L2_DV_BT_DMT_1280X960P85,
224 V4L2_DV_BT_DMT_1280X1024P60,
225 V4L2_DV_BT_DMT_1280X1024P75,
226 V4L2_DV_BT_DMT_1280X1024P85,
227 V4L2_DV_BT_DMT_1360X768P60,
228 V4L2_DV_BT_DMT_1400X1050P60_RB,
229 V4L2_DV_BT_DMT_1400X1050P60,
230 V4L2_DV_BT_DMT_1400X1050P75,
231 V4L2_DV_BT_DMT_1400X1050P85,
232 V4L2_DV_BT_DMT_1440X900P60_RB,
233 V4L2_DV_BT_DMT_1440X900P60,
234 V4L2_DV_BT_DMT_1600X1200P60,
235 V4L2_DV_BT_DMT_1680X1050P60_RB,
236 V4L2_DV_BT_DMT_1680X1050P60,
237 V4L2_DV_BT_DMT_1792X1344P60,
238 V4L2_DV_BT_DMT_1856X1392P60,
239 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 240 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 241 V4L2_DV_BT_DMT_1366X768P60,
242 V4L2_DV_BT_DMT_1920X1080P60,
243 { },
244};
245
ccbd5bc4
HV		 246struct adv7604_video_standards {
247 struct v4l2_dv_timings timings;
248 u8 vid_std;
249 u8 v_freq;
250};
251
252/* sorted by number of lines */
253static const struct adv7604_video_standards adv7604_prim_mode_comp[] = {
254 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
255 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
256 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
257 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
258 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
259 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
260 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
261 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
262 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
263 /* TODO add 1920x1080P60_RB (CVT timing) */
264 { },
265};
266
267/* sorted by number of lines */
268static const struct adv7604_video_standards adv7604_prim_mode_gr[] = {
269 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
270 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
272 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
273 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
274 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
275 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
276 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
277 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
278 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
279 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
280 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
281 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
282 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
283 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
284 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
285 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
286 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
287 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
288 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
289 /* TODO add 1600X1200P60_RB (not a DMT timing) */
290 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
291 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
292 { },
293};
294
295/* sorted by number of lines */
296static const struct adv7604_video_standards adv7604_prim_mode_hdmi_comp[] = {
297 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
298 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
299 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
300 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
301 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
302 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
303 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
304 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
305 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
306 { },
307};
308
309/* sorted by number of lines */
310static const struct adv7604_video_standards adv7604_prim_mode_hdmi_gr[] = {
311 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
312 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
314 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
315 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
316 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
317 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
318 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
319 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
320 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
321 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
322 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
323 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
324 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
325 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
326 { },
327};
328
54450f59
HV		 329/* ----------------------------------------------------------------------- */
330
331static inline struct adv7604_state *to_state(struct v4l2_subdev *sd)
332{
333 return container_of(sd, struct adv7604_state, sd);
334}
335
54450f59
HV		 336static inline unsigned htotal(const struct v4l2_bt_timings *t)
337{
eacf8f9a 338 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 339}
340
54450f59
HV		 341static inline unsigned vtotal(const struct v4l2_bt_timings *t)
342{
eacf8f9a 343 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 344}
345
346/* ----------------------------------------------------------------------- */
347
348static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
349 u8 command, bool check)
350{
351 union i2c_smbus_data data;
352
353 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
354 I2C_SMBUS_READ, command,
355 I2C_SMBUS_BYTE_DATA, &data))
356 return data.byte;
357 if (check)
358 v4l_err(client, "error reading %02x, %02x\n",
359 client->addr, command);
360 return -EIO;
361}
362
05cacb17
LP		 363static s32 adv_smbus_read_byte_data(struct adv7604_state *state,
364 enum adv7604_page page, u8 command)
54450f59 365{
05cacb17
LP		 366 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
367 command, true);
54450f59
HV		 368}
369
05cacb17
LP		 370static s32 adv_smbus_write_byte_data(struct adv7604_state *state,
371 enum adv7604_page page, u8 command,
372 u8 value)
54450f59 373{
05cacb17 374 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 375 union i2c_smbus_data data;
376 int err;
377 int i;
378
379 data.byte = value;
380 for (i = 0; i < 3; i++) {
381 err = i2c_smbus_xfer(client->adapter, client->addr,
382 client->flags,
383 I2C_SMBUS_WRITE, command,
384 I2C_SMBUS_BYTE_DATA, &data);
385 if (!err)
386 break;
387 }
388 if (err < 0)
389 v4l_err(client, "error writing %02x, %02x, %02x\n",
390 client->addr, command, value);
391 return err;
392}
393
05cacb17
LP		 394static s32 adv_smbus_write_i2c_block_data(struct adv7604_state *state,
395 enum adv7604_page page, u8 command,
396 unsigned length, const u8 *values)
54450f59 397{
05cacb17 398 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 399 union i2c_smbus_data data;
400
401 if (length > I2C_SMBUS_BLOCK_MAX)
402 length = I2C_SMBUS_BLOCK_MAX;
403 data.block[0] = length;
404 memcpy(data.block + 1, values, length);
405 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
406 I2C_SMBUS_WRITE, command,
407 I2C_SMBUS_I2C_BLOCK_DATA, &data);
408}
409
410/* ----------------------------------------------------------------------- */
411
412static inline int io_read(struct v4l2_subdev *sd, u8 reg)
413{
05cacb17 414 struct adv7604_state *state = to_state(sd);
54450f59 415
05cacb17 416 return adv_smbus_read_byte_data(state, ADV7604_PAGE_IO, reg);
54450f59
HV		 417}
418
419static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
420{
05cacb17 421 struct adv7604_state *state = to_state(sd);
54450f59 422
05cacb17 423 return adv_smbus_write_byte_data(state, ADV7604_PAGE_IO, reg, val);
54450f59
HV		 424}
425
22d97e56 426static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 427{
22d97e56 428 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 429}
430
431static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
432{
433 struct adv7604_state *state = to_state(sd);
434
05cacb17 435 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 436}
437
438static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
439{
440 struct adv7604_state *state = to_state(sd);
441
05cacb17 442 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
54450f59
HV		 443}
444
445static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
446{
447 struct adv7604_state *state = to_state(sd);
448
05cacb17 449 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CEC, reg);
54450f59
HV		 450}
451
452static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
453{
454 struct adv7604_state *state = to_state(sd);
455
05cacb17 456 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CEC, reg, val);
54450f59
HV		 457}
458
54450f59
HV		 459static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
460{
461 struct adv7604_state *state = to_state(sd);
462
05cacb17 463 return adv_smbus_read_byte_data(state, ADV7604_PAGE_INFOFRAME, reg);
54450f59
HV		 464}
465
466static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
467{
468 struct adv7604_state *state = to_state(sd);
469
05cacb17
LP		 470 return adv_smbus_write_byte_data(state, ADV7604_PAGE_INFOFRAME,
471 reg, val);
54450f59
HV		 472}
473
54450f59
HV		 474static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
475{
476 struct adv7604_state *state = to_state(sd);
477
05cacb17 478 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AFE, reg);
54450f59
HV		 479}
480
481static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
482{
483 struct adv7604_state *state = to_state(sd);
484
05cacb17 485 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AFE, reg, val);
54450f59
HV		 486}
487
488static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
489{
490 struct adv7604_state *state = to_state(sd);
491
05cacb17 492 return adv_smbus_read_byte_data(state, ADV7604_PAGE_REP, reg);
54450f59
HV		 493}
494
495static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
496{
497 struct adv7604_state *state = to_state(sd);
498
05cacb17 499 return adv_smbus_write_byte_data(state, ADV7604_PAGE_REP, reg, val);
54450f59
HV		 500}
501
22d97e56 502static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 503{
22d97e56 504 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 505}
506
507static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
508{
509 struct adv7604_state *state = to_state(sd);
510
05cacb17 511 return adv_smbus_read_byte_data(state, ADV7604_PAGE_EDID, reg);
54450f59
HV		 512}
513
514static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
515{
516 struct adv7604_state *state = to_state(sd);
517
05cacb17 518 return adv_smbus_write_byte_data(state, ADV7604_PAGE_EDID, reg, val);
54450f59
HV		 519}
520
54450f59
HV		 521static inline int edid_write_block(struct v4l2_subdev *sd,
522 unsigned len, const u8 *val)
523{
54450f59
HV		 524 struct adv7604_state *state = to_state(sd);
525 int err = 0;
526 int i;
527
528 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
529
54450f59 530 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
05cacb17
LP		 531 err = adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_EDID,
532 i, I2C_SMBUS_BLOCK_MAX, val + i);
dd08beb9
MR		 533 return err;
534}
54450f59 535
e9d50e9e
LP		 536static void adv7604_set_hpd(struct adv7604_state *state, unsigned int hpd)
537{
538 unsigned int i;
539
540 for (i = 0; i < state->info->num_dv_ports; ++i) {
541 if (IS_ERR(state->hpd_gpio[i]))
542 continue;
543
544 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
545 }
546
547 v4l2_subdev_notify(&state->sd, ADV7604_HOTPLUG, &hpd);
548}
549
dd08beb9
MR		 550static void adv7604_delayed_work_enable_hotplug(struct work_struct *work)
551{
552 struct delayed_work *dwork = to_delayed_work(work);
553 struct adv7604_state *state = container_of(dwork, struct adv7604_state,
554 delayed_work_enable_hotplug);
555 struct v4l2_subdev *sd = &state->sd;
54450f59 556
dd08beb9 557 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 558
e9d50e9e 559 adv7604_set_hpd(state, state->edid.present);
54450f59
HV		 560}
561
562static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
563{
564 struct adv7604_state *state = to_state(sd);
565
05cacb17 566 return adv_smbus_read_byte_data(state, ADV7604_PAGE_HDMI, reg);
54450f59
HV		 567}
568
51182a94
LP		 569static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
570{
571 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
572}
573
54450f59
HV		 574static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
575{
576 struct adv7604_state *state = to_state(sd);
577
05cacb17 578 return adv_smbus_write_byte_data(state, ADV7604_PAGE_HDMI, reg, val);
54450f59
HV		 579}
580
22d97e56 581static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 582{
22d97e56 583 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 584}
585
54450f59
HV		 586static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
587{
588 struct adv7604_state *state = to_state(sd);
589
05cacb17 590 return adv_smbus_write_byte_data(state, ADV7604_PAGE_TEST, reg, val);
54450f59
HV		 591}
592
593static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
594{
595 struct adv7604_state *state = to_state(sd);
596
05cacb17 597 return adv_smbus_read_byte_data(state, ADV7604_PAGE_CP, reg);
54450f59
HV		 598}
599
51182a94
LP		 600static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
601{
602 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
603}
604
54450f59
HV		 605static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
606{
607 struct adv7604_state *state = to_state(sd);
608
05cacb17 609 return adv_smbus_write_byte_data(state, ADV7604_PAGE_CP, reg, val);
54450f59
HV		 610}
611
22d97e56 612static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 613{
22d97e56 614 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 615}
616
617static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
618{
619 struct adv7604_state *state = to_state(sd);
620
05cacb17 621 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 622}
623
624static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
625{
626 struct adv7604_state *state = to_state(sd);
627
05cacb17
LP		 628 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
629}
d42010a1
LPC		 630
631#define ADV7604_REG(page, offset) (((page) << 8) | (offset))
632#define ADV7604_REG_SEQ_TERM 0xffff
633
634#ifdef CONFIG_VIDEO_ADV_DEBUG
635static int adv7604_read_reg(struct v4l2_subdev *sd, unsigned int reg)
636{
637 struct adv7604_state *state = to_state(sd);
638 unsigned int page = reg >> 8;
639
640 if (!(BIT(page) & state->info->page_mask))
641 return -EINVAL;
642
643 reg &= 0xff;
644
05cacb17 645 return adv_smbus_read_byte_data(state, page, reg);
d42010a1
LPC		 646}
647#endif
648
649static int adv7604_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
650{
651 struct adv7604_state *state = to_state(sd);
652 unsigned int page = reg >> 8;
653
654 if (!(BIT(page) & state->info->page_mask))
655 return -EINVAL;
656
657 reg &= 0xff;
658
05cacb17 659 return adv_smbus_write_byte_data(state, page, reg, val);
d42010a1
LPC		 660}
661
662static void adv7604_write_reg_seq(struct v4l2_subdev *sd,
663 const struct adv7604_reg_seq *reg_seq)
664{
665 unsigned int i;
666
667 for (i = 0; reg_seq[i].reg != ADV7604_REG_SEQ_TERM; i++)
668 adv7604_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
669}
670
539b33b0
LP		 671/* -----------------------------------------------------------------------------
672 * Format helpers
673 */
674
675static const struct adv7604_format_info adv7604_formats[] = {
f5fe58fd 676 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
539b33b0 677 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 678 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 679 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 680 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 681 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 682 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 683 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 684 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 685 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 686 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 687 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 688 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 689 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 690 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 691 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 692 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 693 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 694 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 695 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 696 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 697 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 698 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 699 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 700 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 701 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 702 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 703 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 704 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 705 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
f5fe58fd 706 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 707 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 708 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 709 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 710 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 711 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 712 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0
LP		 713 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
714};
715
716static const struct adv7604_format_info adv7611_formats[] = {
f5fe58fd 717 { MEDIA_BUS_FMT_RGB888_1X24, ADV7604_OP_CH_SEL_RGB, true, false,
539b33b0 718 ADV7604_OP_MODE_SEL_SDR_444 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 719 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 720 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 721 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 722 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 723 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 724 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 725 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 726 ADV7604_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 727 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 728 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 729 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 730 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 731 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 732 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 733 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0 734 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_8BIT },
f5fe58fd 735 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7604_OP_CH_SEL_RBG, false, false,
539b33b0 736 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 737 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7604_OP_CH_SEL_RBG, false, true,
539b33b0 738 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 739 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7604_OP_CH_SEL_RGB, false, false,
539b33b0 740 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
f5fe58fd 741 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7604_OP_CH_SEL_RGB, false, true,
539b33b0
LP		 742 ADV7604_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_12BIT },
743};
744
745static const struct adv7604_format_info *
f5fe58fd 746adv7604_format_info(struct adv7604_state *state, u32 code)
539b33b0
LP		 747{
748 unsigned int i;
749
750 for (i = 0; i < state->info->nformats; ++i) {
751 if (state->info->formats[i].code == code)
752 return &state->info->formats[i];
753 }
754
755 return NULL;
756}
757
54450f59
HV		 758/* ----------------------------------------------------------------------- */
759
4a31a93a
MR		 760static inline bool is_analog_input(struct v4l2_subdev *sd)
761{
762 struct adv7604_state *state = to_state(sd);
763
c784b1e2
LP		 764 return state->selected_input == ADV7604_PAD_VGA_RGB ||
765 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 766}
767
768static inline bool is_digital_input(struct v4l2_subdev *sd)
769{
770 struct adv7604_state *state = to_state(sd);
771
c784b1e2
LP		 772 return state->selected_input == ADV7604_PAD_HDMI_PORT_A ||
773 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
774 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
775 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 776}
777
778/* ----------------------------------------------------------------------- */
779
54450f59
HV		 780#ifdef CONFIG_VIDEO_ADV_DEBUG
781static void adv7604_inv_register(struct v4l2_subdev *sd)
782{
783 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
784 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
785 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
786 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
787 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
788 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
789 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
790 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
791 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
792 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
793 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
794 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
795 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
796}
797
798static int adv7604_g_register(struct v4l2_subdev *sd,
799 struct v4l2_dbg_register *reg)
800{
d42010a1
LPC		 801 int ret;
802
803 ret = adv7604_read_reg(sd, reg->reg);
804 if (ret < 0) {
54450f59
HV		 805 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
806 adv7604_inv_register(sd);
d42010a1 807 return ret;
54450f59 808 }
d42010a1
LPC		 809
810 reg->size = 1;
811 reg->val = ret;
812
54450f59
HV		 813 return 0;
814}
815
816static int adv7604_s_register(struct v4l2_subdev *sd,
977ba3b1 817 const struct v4l2_dbg_register *reg)
54450f59 818{
d42010a1 819 int ret;
1577461b 820
d42010a1
LPC		 821 ret = adv7604_write_reg(sd, reg->reg, reg->val);
822 if (ret < 0) {
54450f59
HV		 823 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
824 adv7604_inv_register(sd);
d42010a1 825 return ret;
54450f59 826 }
d42010a1 827
54450f59
HV		 828 return 0;
829}
830#endif
831
d42010a1
LPC		 832static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
833{
834 u8 value = io_read(sd, 0x6f);
835
836 return ((value & 0x10) >> 4)
837 | ((value & 0x08) >> 2)
838 | ((value & 0x04) << 0)
839 | ((value & 0x02) << 2);
840}
841
842static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
843{
844 u8 value = io_read(sd, 0x6f);
845
846 return value & 1;
847}
848
54450f59
HV		 849static int adv7604_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
850{
851 struct adv7604_state *state = to_state(sd);
d42010a1 852 const struct adv7604_chip_info *info = state->info;
54450f59 853
54450f59 854 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 855 info->read_cable_det(sd));
54450f59
HV		 856}
857
ccbd5bc4
HV		 858static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
859 u8 prim_mode,
860 const struct adv7604_video_standards *predef_vid_timings,
861 const struct v4l2_dv_timings *timings)
862{
ccbd5bc4
HV		 863 int i;
864
865 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 866 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 867 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 868 continue;
869 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
870 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
871 prim_mode); /* v_freq and prim mode */
872 return 0;
873 }
874
875 return -1;
876}
877
878static int configure_predefined_video_timings(struct v4l2_subdev *sd,
879 struct v4l2_dv_timings *timings)
54450f59 880{
ccbd5bc4
HV		 881 struct adv7604_state *state = to_state(sd);
882 int err;
883
884 v4l2_dbg(1, debug, sd, "%s", __func__);
885
d42010a1
LPC		 886 if (adv7604_has_afe(state)) {
887 /* reset to default values */
888 io_write(sd, 0x16, 0x43);
889 io_write(sd, 0x17, 0x5a);
890 }
ccbd5bc4 891 /* disable embedded syncs for auto graphics mode */
22d97e56 892 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 893 cp_write(sd, 0x8f, 0x00);
894 cp_write(sd, 0x90, 0x00);
895 cp_write(sd, 0xa2, 0x00);
896 cp_write(sd, 0xa3, 0x00);
897 cp_write(sd, 0xa4, 0x00);
898 cp_write(sd, 0xa5, 0x00);
899 cp_write(sd, 0xa6, 0x00);
900 cp_write(sd, 0xa7, 0x00);
901 cp_write(sd, 0xab, 0x00);
902 cp_write(sd, 0xac, 0x00);
903
4a31a93a 904 if (is_analog_input(sd)) {
ccbd5bc4
HV		 905 err = find_and_set_predefined_video_timings(sd,
906 0x01, adv7604_prim_mode_comp, timings);
907 if (err)
908 err = find_and_set_predefined_video_timings(sd,
909 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 910 } else if (is_digital_input(sd)) {
ccbd5bc4
HV		 911 err = find_and_set_predefined_video_timings(sd,
912 0x05, adv7604_prim_mode_hdmi_comp, timings);
913 if (err)
914 err = find_and_set_predefined_video_timings(sd,
915 0x06, adv7604_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 916 } else {
917 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
918 __func__, state->selected_input);
ccbd5bc4 919 err = -1;
ccbd5bc4
HV		 920 }
921
922
923 return err;
924}
925
926static void configure_custom_video_timings(struct v4l2_subdev *sd,
927 const struct v4l2_bt_timings *bt)
928{
929 struct adv7604_state *state = to_state(sd);
ccbd5bc4
HV		 930 u32 width = htotal(bt);
931 u32 height = vtotal(bt);
932 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
933 u16 cp_start_eav = width - bt->hfrontporch;
934 u16 cp_start_vbi = height - bt->vfrontporch;
935 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
936 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
937 ((width * (ADV7604_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;
938 const u8 pll[2] = {
939 0xc0 | ((width >> 8) & 0x1f),
940 width & 0xff
941 };
54450f59
HV		 942
943 v4l2_dbg(2, debug, sd, "%s\n", __func__);
944
4a31a93a 945 if (is_analog_input(sd)) {
ccbd5bc4
HV		 946 /* auto graphics */
947 io_write(sd, 0x00, 0x07); /* video std */
948 io_write(sd, 0x01, 0x02); /* prim mode */
949 /* enable embedded syncs for auto graphics mode */
22d97e56 950 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 951
ccbd5bc4 952 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 953 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
954 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
05cacb17
LP		 955 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_IO,
956 0x16, 2, pll))
54450f59 957 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 958
959 /* active video - horizontal timing */
54450f59 960 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 961 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 962 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 963 cp_write(sd, 0xa4, cp_start_eav & 0xff);
964
965 /* active video - vertical timing */
54450f59 966 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 967 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 968 ((cp_end_vbi >> 8) & 0xf));
54450f59 969 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 970 } else if (is_digital_input(sd)) {
ccbd5bc4 971 /* set default prim_mode/vid_std for HDMI
39c1cb2b 972 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 973 io_write(sd, 0x00, 0x02); /* video std */
974 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 975 } else {
976 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
977 __func__, state->selected_input);
54450f59 978 }
54450f59 979
ccbd5bc4
HV		 980 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
981 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
982 cp_write(sd, 0xab, (height >> 4) & 0xff);
983 cp_write(sd, 0xac, (height & 0x0f) << 4);
984}
54450f59 985
5c6c6349
MR		 986static void adv7604_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
987{
988 struct adv7604_state *state = to_state(sd);
989 u8 offset_buf[4];
990
991 if (auto_offset) {
992 offset_a = 0x3ff;
993 offset_b = 0x3ff;
994 offset_c = 0x3ff;
995 }
996
997 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
998 __func__, auto_offset ? "Auto" : "Manual",
999 offset_a, offset_b, offset_c);
1000
1001 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1002 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1003 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1004 offset_buf[3] = offset_c & 0x0ff;
1005
1006 /* Registers must be written in this order with no i2c access in between */
05cacb17
LP		 1007 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1008 0x77, 4, offset_buf))
5c6c6349
MR		 1009 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1010}
1011
1012static void adv7604_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1013{
1014 struct adv7604_state *state = to_state(sd);
1015 u8 gain_buf[4];
1016 u8 gain_man = 1;
1017 u8 agc_mode_man = 1;
1018
1019 if (auto_gain) {
1020 gain_man = 0;
1021 agc_mode_man = 0;
1022 gain_a = 0x100;
1023 gain_b = 0x100;
1024 gain_c = 0x100;
1025 }
1026
1027 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1028 __func__, auto_gain ? "Auto" : "Manual",
1029 gain_a, gain_b, gain_c);
1030
1031 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1032 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1033 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1034 gain_buf[3] = ((gain_c & 0x0ff));
1035
1036 /* Registers must be written in this order with no i2c access in between */
05cacb17
LP		 1037 if (adv_smbus_write_i2c_block_data(state, ADV7604_PAGE_CP,
1038 0x73, 4, gain_buf))
5c6c6349
MR		 1039 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1040}
1041
54450f59
HV		 1042static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1043{
1044 struct adv7604_state *state = to_state(sd);
5c6c6349
MR		 1045 bool rgb_output = io_read(sd, 0x02) & 0x02;
1046 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1047
1048 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1049 __func__, state->rgb_quantization_range,
1050 rgb_output, hdmi_signal);
54450f59 1051
5c6c6349
MR		 1052 adv7604_set_gain(sd, true, 0x0, 0x0, 0x0);
1053 adv7604_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1054
54450f59
HV		 1055 switch (state->rgb_quantization_range) {
1056 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1057 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1058 /* Receiving analog RGB signal
1059 * Set RGB full range (0-255) */
22d97e56 1060 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1061 break;
1062 }
1063
c784b1e2 1064 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1065 /* Receiving analog YPbPr signal
1066 * Set automode */
22d97e56 1067 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1068 break;
1069 }
1070
5c6c6349 1071 if (hdmi_signal) {
9833239e
MR		 1072 /* Receiving HDMI signal
1073 * Set automode */
22d97e56 1074 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1075 break;
1076 }
1077
1078 /* Receiving DVI-D signal
1079 * ADV7604 selects RGB limited range regardless of
1080 * input format (CE/IT) in automatic mode */
1081 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1082 /* RGB limited range (16-235) */
22d97e56 1083 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1084 } else {
1085 /* RGB full range (0-255) */
22d97e56 1086 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1087
1088 if (is_digital_input(sd) && rgb_output) {
1089 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
1090 } else {
1091 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1092 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
1093 }
54450f59
HV		 1094 }
1095 break;
1096 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1097 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1098 /* YCrCb limited range (16-235) */
22d97e56 1099 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1100 break;
d261e842 1101 }
5c6c6349
MR		 1102
1103 /* RGB limited range (16-235) */
22d97e56 1104 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1105
54450f59
HV		 1106 break;
1107 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1108 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1109 /* YCrCb full range (0-255) */
22d97e56 1110 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1111 break;
1112 }
1113
1114 /* RGB full range (0-255) */
22d97e56 1115 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1116
1117 if (is_analog_input(sd) || hdmi_signal)
1118 break;
1119
1120 /* Adjust gain/offset for DVI-D signals only */
1121 if (rgb_output) {
1122 adv7604_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1123 } else {
5c6c6349
MR		 1124 adv7604_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1125 adv7604_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1126 }
54450f59
HV		 1127 break;
1128 }
1129}
1130
54450f59
HV		 1131static int adv7604_s_ctrl(struct v4l2_ctrl *ctrl)
1132{
c269887c
LP		 1133 struct v4l2_subdev *sd =
1134 &container_of(ctrl->handler, struct adv7604_state, hdl)->sd;
1135
54450f59
HV		 1136 struct adv7604_state *state = to_state(sd);
1137
1138 switch (ctrl->id) {
1139 case V4L2_CID_BRIGHTNESS:
1140 cp_write(sd, 0x3c, ctrl->val);
1141 return 0;
1142 case V4L2_CID_CONTRAST:
1143 cp_write(sd, 0x3a, ctrl->val);
1144 return 0;
1145 case V4L2_CID_SATURATION:
1146 cp_write(sd, 0x3b, ctrl->val);
1147 return 0;
1148 case V4L2_CID_HUE:
1149 cp_write(sd, 0x3d, ctrl->val);
1150 return 0;
1151 case V4L2_CID_DV_RX_RGB_RANGE:
1152 state->rgb_quantization_range = ctrl->val;
1153 set_rgb_quantization_range(sd);
1154 return 0;
1155 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
d42010a1
LPC		 1156 if (!adv7604_has_afe(state))
1157 return -EINVAL;
54450f59
HV		 1158 /* Set the analog sampling phase. This is needed to find the
1159 best sampling phase for analog video: an application or
1160 driver has to try a number of phases and analyze the picture
1161 quality before settling on the best performing phase. */
1162 afe_write(sd, 0xc8, ctrl->val);
1163 return 0;
1164 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1165 /* Use the default blue color for free running mode,
1166 or supply your own. */
22d97e56 1167 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1168 return 0;
1169 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1170 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1171 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1172 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1173 return 0;
1174 }
1175 return -EINVAL;
1176}
1177
54450f59
HV		 1178/* ----------------------------------------------------------------------- */
1179
1180static inline bool no_power(struct v4l2_subdev *sd)
1181{
1182 /* Entire chip or CP powered off */
1183 return io_read(sd, 0x0c) & 0x24;
1184}
1185
1186static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1187{
4a31a93a
MR		 1188 struct adv7604_state *state = to_state(sd);
1189
1190 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1191}
1192
1193static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1194{
d42010a1
LPC		 1195 struct adv7604_state *state = to_state(sd);
1196 const struct adv7604_chip_info *info = state->info;
1197
1198 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1199}
1200
bb88f325
MB		 1201static inline bool is_hdmi(struct v4l2_subdev *sd)
1202{
1203 return hdmi_read(sd, 0x05) & 0x80;
1204}
1205
54450f59
HV		 1206static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1207{
d42010a1
LPC		 1208 struct adv7604_state *state = to_state(sd);
1209
1210 /*
1211 * Chips without a AFE don't expose registers for the SSPD, so just assume
1212 * that we have a lock.
1213 */
1214 if (adv7604_has_afe(state))
1215 return false;
1216
54450f59
HV		 1217 /* TODO channel 2 */
1218 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1219}
1220
1221static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1222{
1223 /* TODO channel 2 */
1224 return !(cp_read(sd, 0xb1) & 0x80);
1225}
1226
1227static inline bool no_signal(struct v4l2_subdev *sd)
1228{
54450f59
HV		 1229 bool ret;
1230
1231 ret = no_power(sd);
1232
1233 ret |= no_lock_stdi(sd);
1234 ret |= no_lock_sspd(sd);
1235
4a31a93a 1236 if (is_digital_input(sd)) {
54450f59
HV		 1237 ret |= no_lock_tmds(sd);
1238 ret |= no_signal_tmds(sd);
1239 }
1240
1241 return ret;
1242}
1243
1244static inline bool no_lock_cp(struct v4l2_subdev *sd)
1245{
d42010a1
LPC		 1246 struct adv7604_state *state = to_state(sd);
1247
1248 if (!adv7604_has_afe(state))
1249 return false;
1250
54450f59
HV		 1251 /* CP has detected a non standard number of lines on the incoming
1252 video compared to what it is configured to receive by s_dv_timings */
1253 return io_read(sd, 0x12) & 0x01;
1254}
1255
58514625 1256static inline bool in_free_run(struct v4l2_subdev *sd)
1257{
1258 return cp_read(sd, 0xff) & 0x10;
1259}
1260
54450f59
HV		 1261static int adv7604_g_input_status(struct v4l2_subdev *sd, u32 *status)
1262{
54450f59
HV		 1263 *status = 0;
1264 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1265 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1266 if (!in_free_run(sd) && no_lock_cp(sd))
1267 *status |= is_digital_input(sd) ?
1268 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1269
1270 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1271
1272 return 0;
1273}
1274
1275/* ----------------------------------------------------------------------- */
1276
54450f59
HV		 1277struct stdi_readback {
1278 u16 bl, lcf, lcvs;
1279 u8 hs_pol, vs_pol;
1280 bool interlaced;
1281};
1282
1283static int stdi2dv_timings(struct v4l2_subdev *sd,
1284 struct stdi_readback *stdi,
1285 struct v4l2_dv_timings *timings)
1286{
1287 struct adv7604_state *state = to_state(sd);
1288 u32 hfreq = (ADV7604_fsc * 8) / stdi->bl;
1289 u32 pix_clk;
1290 int i;
1291
1292 for (i = 0; adv7604_timings[i].bt.height; i++) {
1293 if (vtotal(&adv7604_timings[i].bt) != stdi->lcf + 1)
1294 continue;
1295 if (adv7604_timings[i].bt.vsync != stdi->lcvs)
1296 continue;
1297
1298 pix_clk = hfreq * htotal(&adv7604_timings[i].bt);
1299
1300 if ((pix_clk < adv7604_timings[i].bt.pixelclock + 1000000) &&
1301 (pix_clk > adv7604_timings[i].bt.pixelclock - 1000000)) {
1302 *timings = adv7604_timings[i];
1303 return 0;
1304 }
1305 }
1306
1307 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1308 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1309 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1310 timings))
1311 return 0;
1312 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1313 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1314 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1315 state->aspect_ratio, timings))
1316 return 0;
1317
ccbd5bc4
HV		 1318 v4l2_dbg(2, debug, sd,
1319 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1320 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1321 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1322 return -1;
1323}
1324
d42010a1 1325
54450f59
HV		 1326static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1327{
d42010a1
LPC		 1328 struct adv7604_state *state = to_state(sd);
1329 const struct adv7604_chip_info *info = state->info;
4a2ccdd2
LP		 1330 u8 polarity;
1331
54450f59
HV		 1332 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1333 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1334 return -1;
1335 }
1336
1337 /* read STDI */
51182a94 1338 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1339 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1340 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1341 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1342
d42010a1
LPC		 1343 if (adv7604_has_afe(state)) {
1344 /* read SSPD */
1345 polarity = cp_read(sd, 0xb5);
1346 if ((polarity & 0x03) == 0x01) {
1347 stdi->hs_pol = polarity & 0x10
1348 ? (polarity & 0x08 ? '+' : '-') : 'x';
1349 stdi->vs_pol = polarity & 0x40
1350 ? (polarity & 0x20 ? '+' : '-') : 'x';
1351 } else {
1352 stdi->hs_pol = 'x';
1353 stdi->vs_pol = 'x';
1354 }
54450f59 1355 } else {
d42010a1
LPC		 1356 polarity = hdmi_read(sd, 0x05);
1357 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1358 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1359 }
1360
1361 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1362 v4l2_dbg(2, debug, sd,
1363 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1364 return -1;
1365 }
1366
1367 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1368 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1369 memset(stdi, 0, sizeof(struct stdi_readback));
1370 return -1;
1371 }
1372
1373 v4l2_dbg(2, debug, sd,
1374 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1375 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1376 stdi->hs_pol, stdi->vs_pol,
1377 stdi->interlaced ? "interlaced" : "progressive");
1378
1379 return 0;
1380}
1381
1382static int adv7604_enum_dv_timings(struct v4l2_subdev *sd,
1383 struct v4l2_enum_dv_timings *timings)
1384{
afec5599
LP		 1385 struct adv7604_state *state = to_state(sd);
1386
54450f59
HV		 1387 if (timings->index >= ARRAY_SIZE(adv7604_timings) - 1)
1388 return -EINVAL;
afec5599
LP		 1389
1390 if (timings->pad >= state->source_pad)
1391 return -EINVAL;
1392
54450f59
HV		 1393 memset(timings->reserved, 0, sizeof(timings->reserved));
1394 timings->timings = adv7604_timings[timings->index];
1395 return 0;
1396}
1397
7515e096
LP		 1398static int adv7604_dv_timings_cap(struct v4l2_subdev *sd,
1399 struct v4l2_dv_timings_cap *cap)
54450f59 1400{
7515e096
LP		 1401 struct adv7604_state *state = to_state(sd);
1402
1403 if (cap->pad >= state->source_pad)
1404 return -EINVAL;
1405
54450f59
HV		 1406 cap->type = V4L2_DV_BT_656_1120;
1407 cap->bt.max_width = 1920;
1408 cap->bt.max_height = 1200;
fe9c2564 1409 cap->bt.min_pixelclock = 25000000;
afec5599 1410
7515e096 1411 switch (cap->pad) {
afec5599
LP		 1412 case ADV7604_PAD_HDMI_PORT_A:
1413 case ADV7604_PAD_HDMI_PORT_B:
1414 case ADV7604_PAD_HDMI_PORT_C:
1415 case ADV7604_PAD_HDMI_PORT_D:
54450f59 1416 cap->bt.max_pixelclock = 225000000;
afec5599
LP		 1417 break;
1418 case ADV7604_PAD_VGA_RGB:
1419 case ADV7604_PAD_VGA_COMP:
1420 default:
54450f59 1421 cap->bt.max_pixelclock = 170000000;
afec5599
LP		 1422 break;
1423 }
1424
54450f59
HV		 1425 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1426 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1427 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1428 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1429 return 0;
1430}
1431
1432/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
1433 if the format is listed in adv7604_timings[] */
1434static void adv7604_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1435 struct v4l2_dv_timings *timings)
1436{
54450f59
HV		 1437 int i;
1438
1439 for (i = 0; adv7604_timings[i].bt.width; i++) {
ef1ed8f5 1440 if (v4l2_match_dv_timings(timings, &adv7604_timings[i],
4a31a93a 1441 is_digital_input(sd) ? 250000 : 1000000)) {
54450f59
HV		 1442 *timings = adv7604_timings[i];
1443 break;
1444 }
1445 }
1446}
1447
d42010a1
LPC		 1448static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1449{
1450 unsigned int freq;
1451 int a, b;
1452
1453 a = hdmi_read(sd, 0x06);
1454 b = hdmi_read(sd, 0x3b);
1455 if (a < 0 || b < 0)
1456 return 0;
1457 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1458
1459 if (is_hdmi(sd)) {
1460 /* adjust for deep color mode */
1461 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1462
1463 freq = freq * 8 / bits_per_channel;
1464 }
1465
1466 return freq;
1467}
1468
1469static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1470{
1471 int a, b;
1472
1473 a = hdmi_read(sd, 0x51);
1474 b = hdmi_read(sd, 0x52);
1475 if (a < 0 || b < 0)
1476 return 0;
1477 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1478}
1479
54450f59
HV		 1480static int adv7604_query_dv_timings(struct v4l2_subdev *sd,
1481 struct v4l2_dv_timings *timings)
1482{
1483 struct adv7604_state *state = to_state(sd);
d42010a1 1484 const struct adv7604_chip_info *info = state->info;
54450f59
HV		 1485 struct v4l2_bt_timings *bt = &timings->bt;
1486 struct stdi_readback stdi;
1487
1488 if (!timings)
1489 return -EINVAL;
1490
1491 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1492
1493 if (no_signal(sd)) {
1e0b9156 1494 state->restart_stdi_once = true;
54450f59
HV		 1495 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1496 return -ENOLINK;
1497 }
1498
1499 /* read STDI */
1500 if (read_stdi(sd, &stdi)) {
1501 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1502 return -ENOLINK;
1503 }
1504 bt->interlaced = stdi.interlaced ?
1505 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1506
4a31a93a 1507 if (is_digital_input(sd)) {
54450f59
HV		 1508 timings->type = V4L2_DV_BT_656_1120;
1509
d42010a1 1510 /* FIXME: All masks are incorrect for ADV7611 */
51182a94
LP		 1511 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1512 bt->height = hdmi_read16(sd, 0x09, 0xfff);
d42010a1 1513 bt->pixelclock = info->read_hdmi_pixelclock(sd);
51182a94
LP		 1514 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1515 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1516 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1517 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1518 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1519 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
54450f59
HV		 1520 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1521 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1522 if (bt->interlaced == V4L2_DV_INTERLACED) {
51182a94
LP		 1523 bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1524 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1525 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
f8789e6d 1526 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
54450f59
HV		 1527 }
1528 adv7604_fill_optional_dv_timings_fields(sd, timings);
1529 } else {
1530 /* find format
80939647 1531 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1532 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1533 */
1534 if (!stdi2dv_timings(sd, &stdi, timings))
1535 goto found;
1536 stdi.lcvs += 1;
1537 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1538 if (!stdi2dv_timings(sd, &stdi, timings))
1539 goto found;
1540 stdi.lcvs -= 2;
1541 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1542 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1543 /*
1544 * The STDI block may measure wrong values, especially
1545 * for lcvs and lcf. If the driver can not find any
1546 * valid timing, the STDI block is restarted to measure
1547 * the video timings again. The function will return an
1548 * error, but the restart of STDI will generate a new
1549 * STDI interrupt and the format detection process will
1550 * restart.
1551 */
1552 if (state->restart_stdi_once) {
1553 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1554 /* TODO restart STDI for Sync Channel 2 */
1555 /* enter one-shot mode */
22d97e56 1556 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1557 /* trigger STDI restart */
22d97e56 1558 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1559 /* reset to continuous mode */
22d97e56 1560 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1561 state->restart_stdi_once = false;
1562 return -ENOLINK;
1563 }
54450f59
HV		 1564 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1565 return -ERANGE;
1566 }
cf9afb1d 1567 state->restart_stdi_once = true;
54450f59
HV		 1568 }
1569found:
1570
1571 if (no_signal(sd)) {
1572 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1573 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1574 return -ENOLINK;
1575 }
1576
4a31a93a
MR		 1577 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1578 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1579 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1580 __func__, (u32)bt->pixelclock);
1581 return -ERANGE;
1582 }
1583
1584 if (debug > 1)
11d034c8
HV		 1585 v4l2_print_dv_timings(sd->name, "adv7604_query_dv_timings: ",
1586 timings, true);
54450f59
HV		 1587
1588 return 0;
1589}
1590
1591static int adv7604_s_dv_timings(struct v4l2_subdev *sd,
1592 struct v4l2_dv_timings *timings)
1593{
1594 struct adv7604_state *state = to_state(sd);
1595 struct v4l2_bt_timings *bt;
ccbd5bc4 1596 int err;
54450f59
HV		 1597
1598 if (!timings)
1599 return -EINVAL;
1600
d48eb48c
MR		 1601 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1602 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1603 return 0;
1604 }
1605
54450f59
HV		 1606 bt = &timings->bt;
1607
4a31a93a
MR		 1608 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1609 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1610 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1611 __func__, (u32)bt->pixelclock);
1612 return -ERANGE;
1613 }
ccbd5bc4 1614
54450f59
HV		 1615 adv7604_fill_optional_dv_timings_fields(sd, timings);
1616
1617 state->timings = *timings;
1618
22d97e56 1619 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1620
1621 /* Use prim_mode and vid_std when available */
1622 err = configure_predefined_video_timings(sd, timings);
1623 if (err) {
1624 /* custom settings when the video format
1625 does not have prim_mode/vid_std */
1626 configure_custom_video_timings(sd, bt);
1627 }
54450f59
HV		 1628
1629 set_rgb_quantization_range(sd);
1630
54450f59 1631 if (debug > 1)
11d034c8
HV		 1632 v4l2_print_dv_timings(sd->name, "adv7604_s_dv_timings: ",
1633 timings, true);
54450f59
HV		 1634 return 0;
1635}
1636
1637static int adv7604_g_dv_timings(struct v4l2_subdev *sd,
1638 struct v4l2_dv_timings *timings)
1639{
1640 struct adv7604_state *state = to_state(sd);
1641
1642 *timings = state->timings;
1643 return 0;
1644}
1645
d42010a1
LPC		 1646static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1647{
1648 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1649}
1650
1651static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1652{
1653 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1654}
1655
6b0d5d34 1656static void enable_input(struct v4l2_subdev *sd)
54450f59 1657{
6b0d5d34
HV		 1658 struct adv7604_state *state = to_state(sd);
1659
4a31a93a 1660 if (is_analog_input(sd)) {
54450f59 1661 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1662 } else if (is_digital_input(sd)) {
22d97e56 1663 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1664 state->info->set_termination(sd, true);
54450f59 1665 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1666 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1667 } else {
1668 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1669 __func__, state->selected_input);
54450f59
HV		 1670 }
1671}
1672
1673static void disable_input(struct v4l2_subdev *sd)
1674{
d42010a1
LPC		 1675 struct adv7604_state *state = to_state(sd);
1676
22d97e56 1677 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1678 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1679 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1680 state->info->set_termination(sd, false);
54450f59
HV		 1681}
1682
6b0d5d34 1683static void select_input(struct v4l2_subdev *sd)
54450f59 1684{
6b0d5d34 1685 struct adv7604_state *state = to_state(sd);
d42010a1 1686 const struct adv7604_chip_info *info = state->info;
54450f59 1687
4a31a93a 1688 if (is_analog_input(sd)) {
d42010a1 1689 adv7604_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1690
1691 afe_write(sd, 0x00, 0x08); /* power up ADC */
1692 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1693 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1694 } else if (is_digital_input(sd)) {
1695 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1696
d42010a1
LPC		 1697 adv7604_write_reg_seq(sd, info->recommended_settings[1]);
1698
1699 if (adv7604_has_afe(state)) {
1700 afe_write(sd, 0x00, 0xff); /* power down ADC */
1701 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1702 afe_write(sd, 0xc8, 0x40); /* phase control */
1703 }
1704
54450f59
HV		 1705 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1706 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1707 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1708 } else {
1709 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1710 __func__, state->selected_input);
54450f59
HV		 1711 }
1712}
1713
1714static int adv7604_s_routing(struct v4l2_subdev *sd,
1715 u32 input, u32 output, u32 config)
1716{
1717 struct adv7604_state *state = to_state(sd);
1718
ff4f80fd
MR		 1719 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1720 __func__, input, state->selected_input);
1721
1722 if (input == state->selected_input)
1723 return 0;
54450f59 1724
d42010a1
LPC		 1725 if (input > state->info->max_port)
1726 return -EINVAL;
1727
4a31a93a 1728 state->selected_input = input;
54450f59
HV		 1729
1730 disable_input(sd);
1731
6b0d5d34 1732 select_input(sd);
54450f59 1733
6b0d5d34 1734 enable_input(sd);
54450f59
HV		 1735
1736 return 0;
1737}
1738
539b33b0
LP		 1739static int adv7604_enum_mbus_code(struct v4l2_subdev *sd,
1740 struct v4l2_subdev_fh *fh,
1741 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1742{
539b33b0
LP		 1743 struct adv7604_state *state = to_state(sd);
1744
1745 if (code->index >= state->info->nformats)
54450f59 1746 return -EINVAL;
539b33b0
LP		 1747
1748 code->code = state->info->formats[code->index].code;
1749
54450f59
HV		 1750 return 0;
1751}
1752
539b33b0
LP		 1753static void adv7604_fill_format(struct adv7604_state *state,
1754 struct v4l2_mbus_framefmt *format)
54450f59 1755{
539b33b0 1756 memset(format, 0, sizeof(*format));
54450f59 1757
539b33b0
LP		 1758 format->width = state->timings.bt.width;
1759 format->height = state->timings.bt.height;
1760 format->field = V4L2_FIELD_NONE;
1761
1762 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
1763 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1764 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1765}
1766
1767/*
1768 * Compute the op_ch_sel value required to obtain on the bus the component order
1769 * corresponding to the selected format taking into account bus reordering
1770 * applied by the board at the output of the device.
1771 *
1772 * The following table gives the op_ch_value from the format component order
1773 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
1774 * adv7604_bus_order value in row).
1775 *
1776 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1777 * ----------+-------------------------------------------------
1778 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1779 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1780 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1781 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1782 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1783 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1784 */
1785static unsigned int adv7604_op_ch_sel(struct adv7604_state *state)
1786{
1787#define _SEL(a,b,c,d,e,f) { \
1788 ADV7604_OP_CH_SEL_##a, ADV7604_OP_CH_SEL_##b, ADV7604_OP_CH_SEL_##c, \
1789 ADV7604_OP_CH_SEL_##d, ADV7604_OP_CH_SEL_##e, ADV7604_OP_CH_SEL_##f }
1790#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1791
1792 static const unsigned int op_ch_sel[6][6] = {
1793 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1794 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1795 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1796 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1797 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1798 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1799 };
1800
1801 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1802}
1803
1804static void adv7604_setup_format(struct adv7604_state *state)
1805{
1806 struct v4l2_subdev *sd = &state->sd;
1807
22d97e56 1808 io_write_clr_set(sd, 0x02, 0x02,
539b33b0
LP		 1809 state->format->rgb_out ? ADV7604_RGB_OUT : 0);
1810 io_write(sd, 0x03, state->format->op_format_sel |
1811 state->pdata.op_format_mode_sel);
22d97e56
LP		 1812 io_write_clr_set(sd, 0x04, 0xe0, adv7604_op_ch_sel(state));
1813 io_write_clr_set(sd, 0x05, 0x01,
539b33b0
LP		 1814 state->format->swap_cb_cr ? ADV7604_OP_SWAP_CB_CR : 0);
1815}
1816
1817static int adv7604_get_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1818 struct v4l2_subdev_format *format)
1819{
1820 struct adv7604_state *state = to_state(sd);
1821
1822 if (format->pad != state->source_pad)
1823 return -EINVAL;
1824
1825 adv7604_fill_format(state, &format->format);
1826
1827 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1828 struct v4l2_mbus_framefmt *fmt;
1829
1830 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1831 format->format.code = fmt->code;
1832 } else {
1833 format->format.code = state->format->code;
54450f59 1834 }
539b33b0
LP		 1835
1836 return 0;
1837}
1838
1839static int adv7604_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
1840 struct v4l2_subdev_format *format)
1841{
1842 struct adv7604_state *state = to_state(sd);
1843 const struct adv7604_format_info *info;
1844
1845 if (format->pad != state->source_pad)
1846 return -EINVAL;
1847
1848 info = adv7604_format_info(state, format->format.code);
1849 if (info == NULL)
f5fe58fd 1850 info = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0
LP		 1851
1852 adv7604_fill_format(state, &format->format);
1853 format->format.code = info->code;
1854
1855 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1856 struct v4l2_mbus_framefmt *fmt;
1857
1858 fmt = v4l2_subdev_get_try_format(fh, format->pad);
1859 fmt->code = format->format.code;
1860 } else {
1861 state->format = info;
1862 adv7604_setup_format(state);
1863 }
1864
54450f59
HV		 1865 return 0;
1866}
1867
1868static int adv7604_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
1869{
d42010a1
LPC		 1870 struct adv7604_state *state = to_state(sd);
1871 const struct adv7604_chip_info *info = state->info;
f24d229c
MR		 1872 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1873 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1874 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1875 u8 fmt_change_digital;
1876 u8 fmt_change;
1877 u8 tx_5v;
1878
1879 if (irq_reg_0x43)
1880 io_write(sd, 0x44, irq_reg_0x43);
1881 if (irq_reg_0x70)
1882 io_write(sd, 0x71, irq_reg_0x70);
1883 if (irq_reg_0x6b)
1884 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1885
ff4f80fd
MR		 1886 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1887
54450f59 1888 /* format change */
f24d229c 1889 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1890 fmt_change_digital = is_digital_input(sd)
1891 ? irq_reg_0x6b & info->fmt_change_digital_mask
1892 : 0;
14d03233 1893
54450f59
HV		 1894 if (fmt_change || fmt_change_digital) {
1895 v4l2_dbg(1, debug, sd,
25a64ac9 1896 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1897 __func__, fmt_change, fmt_change_digital);
25a64ac9 1898
14d03233 1899 v4l2_subdev_notify(sd, ADV7604_FMT_CHANGE, NULL);
25a64ac9 1900
54450f59
HV		 1901 if (handled)
1902 *handled = true;
1903 }
f24d229c
MR		 1904 /* HDMI/DVI mode */
1905 if (irq_reg_0x6b & 0x01) {
1906 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1907 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1908 set_rgb_quantization_range(sd);
1909 if (handled)
1910 *handled = true;
1911 }
1912
54450f59 1913 /* tx 5v detect */
d42010a1 1914 tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
54450f59
HV		 1915 if (tx_5v) {
1916 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1917 io_write(sd, 0x71, tx_5v);
1918 adv7604_s_detect_tx_5v_ctrl(sd);
1919 if (handled)
1920 *handled = true;
1921 }
1922 return 0;
1923}
1924
b09dfac8 1925static int adv7604_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59
HV		 1926{
1927 struct adv7604_state *state = to_state(sd);
4a31a93a 1928 u8 *data = NULL;
54450f59 1929
dd9ac11a 1930 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1931
1932 switch (edid->pad) {
c784b1e2
LP		 1933 case ADV7604_PAD_HDMI_PORT_A:
1934 case ADV7604_PAD_HDMI_PORT_B:
1935 case ADV7604_PAD_HDMI_PORT_C:
1936 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1937 if (state->edid.present & (1 << edid->pad))
1938 data = state->edid.edid;
1939 break;
1940 default:
1941 return -EINVAL;
4a31a93a 1942 }
dd9ac11a
HV		 1943
1944 if (edid->start_block == 0 && edid->blocks == 0) {
1945 edid->blocks = data ? state->edid.blocks : 0;
1946 return 0;
1947 }
1948
1949 if (data == NULL)
4a31a93a
MR		 1950 return -ENODATA;
1951
dd9ac11a
HV		 1952 if (edid->start_block >= state->edid.blocks)
1953 return -EINVAL;
1954
1955 if (edid->start_block + edid->blocks > state->edid.blocks)
1956 edid->blocks = state->edid.blocks - edid->start_block;
1957
1958 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1959
54450f59
HV		 1960 return 0;
1961}
1962
dd08beb9 1963static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1964{
1965 u8 d;
1966
1967 if ((edid[0x7e] != 1) ||
1968 (edid[0x80] != 0x02) ||
1969 (edid[0x81] != 0x03)) {
1970 return -1;
1971 }
1972
1973 /* search Vendor Specific Data Block (tag 3) */
1974 d = edid[0x82] & 0x7f;
1975 if (d > 4) {
1976 int i = 0x84;
1977 int end = 0x80 + d;
1978
1979 do {
1980 u8 tag = edid[i] >> 5;
1981 u8 len = edid[i] & 0x1f;
1982
1983 if ((tag == 3) && (len >= 5))
1984 return i + 4;
1985 i += len + 1;
1986 } while (i < end);
1987 }
1988 return -1;
1989}
1990
b09dfac8 1991static int adv7604_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59
HV		 1992{
1993 struct adv7604_state *state = to_state(sd);
d42010a1 1994 const struct adv7604_chip_info *info = state->info;
dd08beb9 1995 int spa_loc;
54450f59 1996 int err;
dd08beb9 1997 int i;
54450f59 1998
dd9ac11a
HV		 1999 memset(edid->reserved, 0, sizeof(edid->reserved));
2000
c784b1e2 2001 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2002 return -EINVAL;
2003 if (edid->start_block != 0)
2004 return -EINVAL;
2005 if (edid->blocks == 0) {
3e86aa85 2006 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2007 state->edid.present &= ~(1 << edid->pad);
e9d50e9e 2008 adv7604_set_hpd(state, state->edid.present);
22d97e56 2009 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2010
54450f59
HV		 2011 /* Fall back to a 16:9 aspect ratio */
2012 state->aspect_ratio.numerator = 16;
2013 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2014
2015 if (!state->edid.present)
2016 state->edid.blocks = 0;
2017
2018 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2019 __func__, edid->pad, state->edid.present);
54450f59
HV		 2020 return 0;
2021 }
4a31a93a
MR		 2022 if (edid->blocks > 2) {
2023 edid->blocks = 2;
54450f59 2024 return -E2BIG;
4a31a93a 2025 }
4a31a93a 2026
dd08beb9
MR		 2027 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2028 __func__, edid->pad, state->edid.present);
2029
3e86aa85 2030 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2031 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
e9d50e9e 2032 adv7604_set_hpd(state, 0);
22d97e56 2033 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2034
dd08beb9
MR		 2035 spa_loc = get_edid_spa_location(edid->edid);
2036 if (spa_loc < 0)
2037 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2038
3e86aa85 2039 switch (edid->pad) {
c784b1e2 2040 case ADV7604_PAD_HDMI_PORT_A:
dd08beb9
MR		 2041 state->spa_port_a[0] = edid->edid[spa_loc];
2042 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2043 break;
c784b1e2 2044 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2045 rep_write(sd, 0x70, edid->edid[spa_loc]);
2046 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2047 break;
c784b1e2 2048 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2049 rep_write(sd, 0x72, edid->edid[spa_loc]);
2050 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2051 break;
c784b1e2 2052 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2053 rep_write(sd, 0x74, edid->edid[spa_loc]);
2054 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2055 break;
dd08beb9
MR		 2056 default:
2057 return -EINVAL;
3e86aa85 2058 }
d42010a1
LPC		 2059
2060 if (info->type == ADV7604) {
2061 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2062 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1
LPC		 2063 } else {
2064 /* FIXME: Where is the SPA location LSB register ? */
22d97e56 2065 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2066 }
3e86aa85 2067
dd08beb9
MR		 2068 edid->edid[spa_loc] = state->spa_port_a[0];
2069 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2070
2071 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2072 state->edid.blocks = edid->blocks;
54450f59
HV		 2073 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2074 edid->edid[0x16]);
3e86aa85 2075 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2076
2077 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2078 if (err < 0) {
3e86aa85 2079 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2080 return err;
2081 }
2082
dd08beb9
MR		 2083 /* adv7604 calculates the checksums and enables I2C access to internal
2084 EDID RAM from DDC port. */
22d97e56 2085 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2086
2087 for (i = 0; i < 1000; i++) {
d42010a1 2088 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2089 break;
2090 mdelay(1);
2091 }
2092 if (i == 1000) {
2093 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2094 return -EIO;
2095 }
2096
4a31a93a
MR		 2097 /* enable hotplug after 100 ms */
2098 queue_delayed_work(state->work_queues,
2099 &state->delayed_work_enable_hotplug, HZ / 10);
2100 return 0;
54450f59
HV		 2101}
2102
2103/*********** avi info frame CEA-861-E **************/
2104
2105static void print_avi_infoframe(struct v4l2_subdev *sd)
2106{
2107 int i;
2108 u8 buf[14];
2109 u8 avi_len;
2110 u8 avi_ver;
2111
bb88f325 2112 if (!is_hdmi(sd)) {
54450f59
HV		 2113 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2114 return;
2115 }
2116 if (!(io_read(sd, 0x60) & 0x01)) {
2117 v4l2_info(sd, "AVI infoframe not received\n");
2118 return;
2119 }
2120
2121 if (io_read(sd, 0x83) & 0x01) {
2122 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2123 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2124 if (io_read(sd, 0x83) & 0x01) {
2125 v4l2_info(sd, "AVI infoframe checksum error still present\n");
2126 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2127 }
2128 }
2129
2130 avi_len = infoframe_read(sd, 0xe2);
2131 avi_ver = infoframe_read(sd, 0xe1);
2132 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2133 avi_ver, avi_len);
2134
2135 if (avi_ver != 0x02)
2136 return;
2137
2138 for (i = 0; i < 14; i++)
2139 buf[i] = infoframe_read(sd, i);
2140
2141 v4l2_info(sd,
2142 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2143 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2144 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2145}
2146
2147static int adv7604_log_status(struct v4l2_subdev *sd)
2148{
2149 struct adv7604_state *state = to_state(sd);
d42010a1 2150 const struct adv7604_chip_info *info = state->info;
54450f59
HV		 2151 struct v4l2_dv_timings timings;
2152 struct stdi_readback stdi;
2153 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2154 u8 edid_enabled;
2155 u8 cable_det;
54450f59 2156
f216ccb3 2157 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2158 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2159 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2160 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2161 "reserved", "reserved", "reserved", "reserved", "manual"
2162 };
f216ccb3 2163 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2164 "RGB limited range (16-235)", "RGB full range (0-255)",
2165 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2166 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2167 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2168 "invalid", "invalid", "invalid", "invalid", "invalid",
2169 "invalid", "invalid", "automatic"
2170 };
f216ccb3 2171 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2172 "Automatic",
2173 "RGB limited range (16-235)",
2174 "RGB full range (0-255)",
2175 };
f216ccb3 2176 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2177 "8-bits per channel",
2178 "10-bits per channel",
2179 "12-bits per channel",
2180 "16-bits per channel (not supported)"
2181 };
54450f59
HV		 2182
2183 v4l2_info(sd, "-----Chip status-----\n");
2184 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2185 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2186 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2187 ((edid_enabled & 0x01) ? "Yes" : "No"),
2188 ((edid_enabled & 0x02) ? "Yes" : "No"),
2189 ((edid_enabled & 0x04) ? "Yes" : "No"),
2190 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2191 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2192 "enabled" : "disabled");
2193
2194 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2195 cable_det = info->read_cable_det(sd);
4a31a93a 2196 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2197 ((cable_det & 0x01) ? "Yes" : "No"),
2198 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2199 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2200 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2201 v4l2_info(sd, "TMDS signal detected: %s\n",
2202 no_signal_tmds(sd) ? "false" : "true");
2203 v4l2_info(sd, "TMDS signal locked: %s\n",
2204 no_lock_tmds(sd) ? "false" : "true");
2205 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2206 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2207 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2208 v4l2_info(sd, "CP free run: %s\n",
58514625 2209 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2210 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2211 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2212 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2213
2214 v4l2_info(sd, "-----Video Timings-----\n");
2215 if (read_stdi(sd, &stdi))
2216 v4l2_info(sd, "STDI: not locked\n");
2217 else
2218 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2219 stdi.lcf, stdi.bl, stdi.lcvs,
2220 stdi.interlaced ? "interlaced" : "progressive",
2221 stdi.hs_pol, stdi.vs_pol);
2222 if (adv7604_query_dv_timings(sd, &timings))
2223 v4l2_info(sd, "No video detected\n");
2224 else
11d034c8
HV		 2225 v4l2_print_dv_timings(sd->name, "Detected format: ",
2226 &timings, true);
2227 v4l2_print_dv_timings(sd->name, "Configured format: ",
2228 &state->timings, true);
54450f59 2229
76eb2d30
MR		 2230 if (no_signal(sd))
2231 return 0;
2232
54450f59
HV		 2233 v4l2_info(sd, "-----Color space-----\n");
2234 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2235 rgb_quantization_range_txt[state->rgb_quantization_range]);
2236 v4l2_info(sd, "Input color space: %s\n",
2237 input_color_space_txt[reg_io_0x02 >> 4]);
2238 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2239 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2240 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2241 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 2242 "enabled" : "disabled");
54450f59
HV		 2243 v4l2_info(sd, "Color space conversion: %s\n",
2244 csc_coeff_sel_rb[cp_read(sd, 0xfc) >> 4]);
2245
4a31a93a 2246 if (!is_digital_input(sd))
76eb2d30
MR		 2247 return 0;
2248
2249 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2250 v4l2_info(sd, "Digital video port selected: %c\n",
2251 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2252 v4l2_info(sd, "HDCP encrypted content: %s\n",
2253 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2254 v4l2_info(sd, "HDCP keys read: %s%s\n",
2255 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2256 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2257 if (is_hdmi(sd)) {
76eb2d30
MR		 2258 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2259 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2260 bool audio_mute = io_read(sd, 0x65) & 0x40;
2261
2262 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2263 audio_pll_locked ? "locked" : "not locked",
2264 audio_sample_packet_detect ? "detected" : "not detected",
2265 audio_mute ? "muted" : "enabled");
2266 if (audio_pll_locked && audio_sample_packet_detect) {
2267 v4l2_info(sd, "Audio format: %s\n",
2268 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2269 }
2270 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2271 (hdmi_read(sd, 0x5c) << 8) +
2272 (hdmi_read(sd, 0x5d) & 0xf0));
2273 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2274 (hdmi_read(sd, 0x5e) << 8) +
2275 hdmi_read(sd, 0x5f));
2276 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2277
2278 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2279
54450f59
HV		 2280 print_avi_infoframe(sd);
2281 }
2282
2283 return 0;
2284}
2285
2286/* ----------------------------------------------------------------------- */
2287
2288static const struct v4l2_ctrl_ops adv7604_ctrl_ops = {
2289 .s_ctrl = adv7604_s_ctrl,
2290};
2291
2292static const struct v4l2_subdev_core_ops adv7604_core_ops = {
2293 .log_status = adv7604_log_status,
54450f59
HV		 2294 .interrupt_service_routine = adv7604_isr,
2295#ifdef CONFIG_VIDEO_ADV_DEBUG
2296 .g_register = adv7604_g_register,
2297 .s_register = adv7604_s_register,
2298#endif
2299};
2300
2301static const struct v4l2_subdev_video_ops adv7604_video_ops = {
2302 .s_routing = adv7604_s_routing,
2303 .g_input_status = adv7604_g_input_status,
2304 .s_dv_timings = adv7604_s_dv_timings,
2305 .g_dv_timings = adv7604_g_dv_timings,
2306 .query_dv_timings = adv7604_query_dv_timings,
54450f59
HV		 2307};
2308
2309static const struct v4l2_subdev_pad_ops adv7604_pad_ops = {
539b33b0
LP		 2310 .enum_mbus_code = adv7604_enum_mbus_code,
2311 .get_fmt = adv7604_get_format,
2312 .set_fmt = adv7604_set_format,
54450f59
HV		 2313 .get_edid = adv7604_get_edid,
2314 .set_edid = adv7604_set_edid,
7515e096 2315 .dv_timings_cap = adv7604_dv_timings_cap,
afec5599 2316 .enum_dv_timings = adv7604_enum_dv_timings,
54450f59
HV		 2317};
2318
2319static const struct v4l2_subdev_ops adv7604_ops = {
2320 .core = &adv7604_core_ops,
2321 .video = &adv7604_video_ops,
2322 .pad = &adv7604_pad_ops,
2323};
2324
2325/* -------------------------- custom ctrls ---------------------------------- */
2326
2327static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2328 .ops = &adv7604_ctrl_ops,
2329 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2330 .name = "Analog Sampling Phase",
2331 .type = V4L2_CTRL_TYPE_INTEGER,
2332 .min = 0,
2333 .max = 0x1f,
2334 .step = 1,
2335 .def = 0,
2336};
2337
2338static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color_manual = {
2339 .ops = &adv7604_ctrl_ops,
2340 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2341 .name = "Free Running Color, Manual",
2342 .type = V4L2_CTRL_TYPE_BOOLEAN,
2343 .min = false,
2344 .max = true,
2345 .step = 1,
2346 .def = false,
2347};
2348
2349static const struct v4l2_ctrl_config adv7604_ctrl_free_run_color = {
2350 .ops = &adv7604_ctrl_ops,
2351 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2352 .name = "Free Running Color",
2353 .type = V4L2_CTRL_TYPE_INTEGER,
2354 .min = 0x0,
2355 .max = 0xffffff,
2356 .step = 0x1,
2357 .def = 0x0,
2358};
2359
2360/* ----------------------------------------------------------------------- */
2361
2362static int adv7604_core_init(struct v4l2_subdev *sd)
2363{
2364 struct adv7604_state *state = to_state(sd);
d42010a1 2365 const struct adv7604_chip_info *info = state->info;
54450f59
HV		 2366 struct adv7604_platform_data *pdata = &state->pdata;
2367
2368 hdmi_write(sd, 0x48,
2369 (pdata->disable_pwrdnb ? 0x80 : 0) |
2370 (pdata->disable_cable_det_rst ? 0x40 : 0));
2371
2372 disable_input(sd);
2373
5ef54b59
LP		 2374 if (pdata->default_input >= 0 &&
2375 pdata->default_input < state->source_pad) {
2376 state->selected_input = pdata->default_input;
2377 select_input(sd);
2378 enable_input(sd);
2379 }
2380
54450f59
HV		 2381 /* power */
2382 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2383 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2384 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2385
2386 /* video format */
22d97e56 2387 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2388 pdata->alt_gamma << 3 |
2389 pdata->op_656_range << 2 |
54450f59 2390 pdata->alt_data_sat << 0);
22d97e56 2391 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2392 pdata->insert_av_codes << 2 |
2393 pdata->replicate_av_codes << 1);
2394 adv7604_setup_format(state);
54450f59 2395
54450f59 2396 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2397
2398 /* VS, HS polarities */
1b5ab875
LP		 2399 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2400 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2401
2402 /* Adjust drive strength */
2403 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2404 pdata->dr_str_clk << 2 |
2405 pdata->dr_str_sync);
2406
54450f59
HV		 2407 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2408 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2409 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2410 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2411 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2412 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2413 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2414 for digital formats */
2415
5474b983 2416 /* HDMI audio */
22d97e56
LP		 2417 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2418 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2419 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2420
54450f59
HV		 2421 /* TODO from platform data */
2422 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2423
d42010a1
LPC		 2424 if (adv7604_has_afe(state)) {
2425 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2426 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2427 }
54450f59 2428
54450f59 2429 /* interrupts */
d42010a1 2430 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2431 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2432 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2433 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2434 info->setup_irqs(sd);
54450f59
HV		 2435
2436 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2437}
2438
d42010a1
LPC		 2439static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2440{
2441 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2442}
2443
2444static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2445{
2446 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2447}
2448
54450f59
HV		 2449static void adv7604_unregister_clients(struct adv7604_state *state)
2450{
05cacb17
LP		 2451 unsigned int i;
2452
2453 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2454 if (state->i2c_clients[i])
2455 i2c_unregister_device(state->i2c_clients[i]);
2456 }
54450f59
HV		 2457}
2458
2459static struct i2c_client *adv7604_dummy_client(struct v4l2_subdev *sd,
2460 u8 addr, u8 io_reg)
2461{
2462 struct i2c_client *client = v4l2_get_subdevdata(sd);
2463
2464 if (addr)
2465 io_write(sd, io_reg, addr << 1);
2466 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2467}
2468
d42010a1
LPC		 2469static const struct adv7604_reg_seq adv7604_recommended_settings_afe[] = {
2470 /* reset ADI recommended settings for HDMI: */
2471 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2472 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2473 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2474 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2475 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2476 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2477 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2478 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2479 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2480 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2481 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2482 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2483 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
2484
2485 /* set ADI recommended settings for digitizer */
2486 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2487 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2488 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2489 { ADV7604_REG(ADV7604_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2490 { ADV7604_REG(ADV7604_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2491 { ADV7604_REG(ADV7604_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
2492
2493 { ADV7604_REG_SEQ_TERM, 0 },
2494};
2495
2496static const struct adv7604_reg_seq adv7604_recommended_settings_hdmi[] = {
2497 /* set ADI recommended settings for HDMI: */
2498 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
2499 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2500 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2501 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2502 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2503 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2504 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2505 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2506 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2507 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2508 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2509 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
2510
2511 /* reset ADI recommended settings for digitizer */
2512 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
2513 { ADV7604_REG(ADV7604_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2514 { ADV7604_REG(ADV7604_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
2515
2516 { ADV7604_REG_SEQ_TERM, 0 },
2517};
2518
2519static const struct adv7604_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2520 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
d42010a1 2521 { ADV7604_REG(ADV7604_PAGE_CP, 0x6c), 0x00 },
c41ad9c3
LPC		 2522 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x9b), 0x03 },
2523 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x6f), 0x08 },
2524 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x85), 0x1f },
d42010a1
LPC		 2525 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x87), 0x70 },
2526 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x57), 0xda },
2527 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x58), 0x01 },
2528 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x03), 0x98 },
2529 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x4c), 0x44 },
2530 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8d), 0x04 },
2531 { ADV7604_REG(ADV7604_PAGE_HDMI, 0x8e), 0x1e },
2532
2533 { ADV7604_REG_SEQ_TERM, 0 },
2534};
2535
2536static const struct adv7604_chip_info adv7604_chip_info[] = {
2537 [ADV7604] = {
2538 .type = ADV7604,
2539 .has_afe = true,
c784b1e2 2540 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2541 .num_dv_ports = 4,
2542 .edid_enable_reg = 0x77,
2543 .edid_status_reg = 0x7d,
2544 .lcf_reg = 0xb3,
2545 .tdms_lock_mask = 0xe0,
2546 .cable_det_mask = 0x1e,
2547 .fmt_change_digital_mask = 0xc1,
539b33b0
LP		 2548 .formats = adv7604_formats,
2549 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2550 .set_termination = adv7604_set_termination,
2551 .setup_irqs = adv7604_setup_irqs,
2552 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2553 .read_cable_det = adv7604_read_cable_det,
2554 .recommended_settings = {
2555 [0] = adv7604_recommended_settings_afe,
2556 [1] = adv7604_recommended_settings_hdmi,
2557 },
2558 .num_recommended_settings = {
2559 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2560 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2561 },
2562 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2563 BIT(ADV7604_PAGE_CEC) | BIT(ADV7604_PAGE_INFOFRAME) |
2564 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
2565 BIT(ADV7604_PAGE_AFE) | BIT(ADV7604_PAGE_REP) |
2566 BIT(ADV7604_PAGE_EDID) | BIT(ADV7604_PAGE_HDMI) |
2567 BIT(ADV7604_PAGE_TEST) | BIT(ADV7604_PAGE_CP) |
2568 BIT(ADV7604_PAGE_VDP),
2569 },
2570 [ADV7611] = {
2571 .type = ADV7611,
2572 .has_afe = false,
c784b1e2 2573 .max_port = ADV7604_PAD_HDMI_PORT_A,
d42010a1
LPC		 2574 .num_dv_ports = 1,
2575 .edid_enable_reg = 0x74,
2576 .edid_status_reg = 0x76,
2577 .lcf_reg = 0xa3,
2578 .tdms_lock_mask = 0x43,
2579 .cable_det_mask = 0x01,
2580 .fmt_change_digital_mask = 0x03,
539b33b0
LP		 2581 .formats = adv7611_formats,
2582 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2583 .set_termination = adv7611_set_termination,
2584 .setup_irqs = adv7611_setup_irqs,
2585 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2586 .read_cable_det = adv7611_read_cable_det,
2587 .recommended_settings = {
2588 [1] = adv7611_recommended_settings_hdmi,
2589 },
2590 .num_recommended_settings = {
2591 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2592 },
2593 .page_mask = BIT(ADV7604_PAGE_IO) | BIT(ADV7604_PAGE_CEC) |
2594 BIT(ADV7604_PAGE_INFOFRAME) | BIT(ADV7604_PAGE_AFE) |
2595 BIT(ADV7604_PAGE_REP) | BIT(ADV7604_PAGE_EDID) |
2596 BIT(ADV7604_PAGE_HDMI) | BIT(ADV7604_PAGE_CP),
2597 },
2598};
2599
f82f313e
LP		 2600static struct i2c_device_id adv7604_i2c_id[] = {
2601 { "adv7604", (kernel_ulong_t)&adv7604_chip_info[ADV7604] },
2602 { "adv7611", (kernel_ulong_t)&adv7604_chip_info[ADV7611] },
2603 { }
2604};
2605MODULE_DEVICE_TABLE(i2c, adv7604_i2c_id);
2606
2607static struct of_device_id adv7604_of_id[] __maybe_unused = {
2608 { .compatible = "adi,adv7611", .data = &adv7604_chip_info[ADV7611] },
2609 { }
2610};
2611MODULE_DEVICE_TABLE(of, adv7604_of_id);
2612
2613static int adv7604_parse_dt(struct adv7604_state *state)
2614{
6fa88045
LP		 2615 struct v4l2_of_endpoint bus_cfg;
2616 struct device_node *endpoint;
2617 struct device_node *np;
2618 unsigned int flags;
2619
2620 np = state->i2c_clients[ADV7604_PAGE_IO]->dev.of_node;
2621
2622 /* Parse the endpoint. */
2623 endpoint = of_graph_get_next_endpoint(np, NULL);
2624 if (!endpoint)
2625 return -EINVAL;
2626
2627 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2628 of_node_put(endpoint);
2629
2630 flags = bus_cfg.bus.parallel.flags;
2631
2632 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2633 state->pdata.inv_hs_pol = 1;
2634
2635 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2636 state->pdata.inv_vs_pol = 1;
2637
2638 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2639 state->pdata.inv_llc_pol = 1;
2640
2641 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2642 state->pdata.insert_av_codes = 1;
2643 state->pdata.op_656_range = 1;
2644 }
2645
f82f313e
LP		 2646 /* Disable the interrupt for now as no DT-based board uses it. */
2647 state->pdata.int1_config = ADV7604_INT1_CONFIG_DISABLED;
2648
2649 /* Use the default I2C addresses. */
2650 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
2651 state->pdata.i2c_addresses[ADV7604_PAGE_CEC] = 0x40;
2652 state->pdata.i2c_addresses[ADV7604_PAGE_INFOFRAME] = 0x3e;
2653 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2654 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
2655 state->pdata.i2c_addresses[ADV7604_PAGE_AFE] = 0x26;
2656 state->pdata.i2c_addresses[ADV7604_PAGE_REP] = 0x32;
2657 state->pdata.i2c_addresses[ADV7604_PAGE_EDID] = 0x36;
2658 state->pdata.i2c_addresses[ADV7604_PAGE_HDMI] = 0x34;
2659 state->pdata.i2c_addresses[ADV7604_PAGE_TEST] = 0x30;
2660 state->pdata.i2c_addresses[ADV7604_PAGE_CP] = 0x22;
2661 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2662
2663 /* Hardcode the remaining platform data fields. */
2664 state->pdata.disable_pwrdnb = 0;
2665 state->pdata.disable_cable_det_rst = 0;
2666 state->pdata.default_input = -1;
2667 state->pdata.blank_data = 1;
f82f313e 2668 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2669 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2670 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2671
2672 return 0;
2673}
2674
54450f59
HV		 2675static int adv7604_probe(struct i2c_client *client,
2676 const struct i2c_device_id *id)
2677{
591b72fe
HV		 2678 static const struct v4l2_dv_timings cea640x480 =
2679 V4L2_DV_BT_CEA_640X480P59_94;
54450f59 2680 struct adv7604_state *state;
54450f59
HV		 2681 struct v4l2_ctrl_handler *hdl;
2682 struct v4l2_subdev *sd;
c784b1e2 2683 unsigned int i;
d42010a1 2684 u16 val;
54450f59
HV		 2685 int err;
2686
2687 /* Check if the adapter supports the needed features */
2688 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2689 return -EIO;
2690 v4l_dbg(1, debug, client, "detecting adv7604 client on address 0x%x\n",
2691 client->addr << 1);
2692
c02b211d 2693 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59
HV		 2694 if (!state) {
2695 v4l_err(client, "Could not allocate adv7604_state memory!\n");
2696 return -ENOMEM;
2697 }
2698
05cacb17 2699 state->i2c_clients[ADV7604_PAGE_IO] = client;
d42010a1 2700
25a64ac9
MR		 2701 /* initialize variables */
2702 state->restart_stdi_once = true;
ff4f80fd 2703 state->selected_input = ~0;
25a64ac9 2704
f82f313e
LP		 2705 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2706 const struct of_device_id *oid;
2707
2708 oid = of_match_node(adv7604_of_id, client->dev.of_node);
2709 state->info = oid->data;
2710
2711 err = adv7604_parse_dt(state);
2712 if (err < 0) {
2713 v4l_err(client, "DT parsing error\n");
2714 return err;
2715 }
2716 } else if (client->dev.platform_data) {
2717 struct adv7604_platform_data *pdata = client->dev.platform_data;
2718
2719 state->info = (const struct adv7604_chip_info *)id->driver_data;
2720 state->pdata = *pdata;
2721 } else {
54450f59 2722 v4l_err(client, "No platform data!\n");
c02b211d 2723 return -ENODEV;
54450f59 2724 }
e9d50e9e
LP		 2725
2726 /* Request GPIOs. */
2727 for (i = 0; i < state->info->num_dv_ports; ++i) {
2728 state->hpd_gpio[i] =
2729 devm_gpiod_get_index(&client->dev, "hpd", i);
2730 if (IS_ERR(state->hpd_gpio[i]))
2731 continue;
2732
9b2c3823 2733 gpiod_direction_output(state->hpd_gpio[i], 0);
e9d50e9e
LP		 2734
2735 v4l_info(client, "Handling HPD %u GPIO\n", i);
2736 }
2737
591b72fe 2738 state->timings = cea640x480;
f5fe58fd 2739 state->format = adv7604_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 2740
2741 sd = &state->sd;
2742 v4l2_i2c_subdev_init(sd, client, &adv7604_ops);
d42010a1
LPC		 2743 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2744 id->name, i2c_adapter_id(client->adapter),
2745 client->addr);
54450f59 2746 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59 2747
d42010a1
LPC		 2748 /*
2749 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2750 * identifies the revision, while on ADV7611 it identifies the model as
2751 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2752 */
2753 if (state->info->type == ADV7604) {
2754 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2755 if (val != 0x68) {
2756 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2757 client->addr << 1);
2758 return -ENODEV;
2759 }
2760 } else {
2761 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2762 | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2763 if (val != 0x2051) {
2764 v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2765 client->addr << 1);
2766 return -ENODEV;
2767 }
54450f59
HV		 2768 }
2769
2770 /* control handlers */
2771 hdl = &state->hdl;
d42010a1 2772 v4l2_ctrl_handler_init(hdl, adv7604_has_afe(state) ? 9 : 8);
54450f59
HV		 2773
2774 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2775 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
2776 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2777 V4L2_CID_CONTRAST, 0, 255, 1, 128);
2778 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2779 V4L2_CID_SATURATION, 0, 255, 1, 128);
2780 v4l2_ctrl_new_std(hdl, &adv7604_ctrl_ops,
2781 V4L2_CID_HUE, 0, 128, 1, 0);
2782
2783 /* private controls */
2784 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 2785 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2786 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59
HV		 2787 state->rgb_quantization_range_ctrl =
2788 v4l2_ctrl_new_std_menu(hdl, &adv7604_ctrl_ops,
2789 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2790 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2791
2792 /* custom controls */
d42010a1
LPC		 2793 if (adv7604_has_afe(state))
2794 state->analog_sampling_phase_ctrl =
2795 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59
HV		 2796 state->free_run_color_manual_ctrl =
2797 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color_manual, NULL);
54450f59
HV		 2798 state->free_run_color_ctrl =
2799 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_free_run_color, NULL);
54450f59
HV		 2800
2801 sd->ctrl_handler = hdl;
2802 if (hdl->error) {
2803 err = hdl->error;
2804 goto err_hdl;
2805 }
8c0eadb8
HV		 2806 state->detect_tx_5v_ctrl->is_private = true;
2807 state->rgb_quantization_range_ctrl->is_private = true;
d42010a1
LPC		 2808 if (adv7604_has_afe(state))
2809 state->analog_sampling_phase_ctrl->is_private = true;
8c0eadb8
HV		 2810 state->free_run_color_manual_ctrl->is_private = true;
2811 state->free_run_color_ctrl->is_private = true;
2812
54450f59
HV		 2813 if (adv7604_s_detect_tx_5v_ctrl(sd)) {
2814 err = -ENODEV;
2815 goto err_hdl;
2816 }
2817
05cacb17
LP		 2818 for (i = 1; i < ADV7604_PAGE_MAX; ++i) {
2819 if (!(BIT(i) & state->info->page_mask))
2820 continue;
54450f59 2821
05cacb17 2822 state->i2c_clients[i] =
f82f313e 2823 adv7604_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 2824 0xf2 + i);
2825 if (state->i2c_clients[i] == NULL) {
d42010a1 2826 err = -ENOMEM;
05cacb17 2827 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 2828 goto err_i2c;
2829 }
2830 }
05cacb17 2831
54450f59
HV		 2832 /* work queues */
2833 state->work_queues = create_singlethread_workqueue(client->name);
2834 if (!state->work_queues) {
2835 v4l2_err(sd, "Could not create work queue\n");
2836 err = -ENOMEM;
2837 goto err_i2c;
2838 }
2839
2840 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
2841 adv7604_delayed_work_enable_hotplug);
2842
c784b1e2
LP		 2843 state->source_pad = state->info->num_dv_ports
2844 + (state->info->has_afe ? 2 : 0);
2845 for (i = 0; i < state->source_pad; ++i)
2846 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2847 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2848
2849 err = media_entity_init(&sd->entity, state->source_pad + 1,
2850 state->pads, 0);
54450f59
HV		 2851 if (err)
2852 goto err_work_queues;
2853
2854 err = adv7604_core_init(sd);
2855 if (err)
2856 goto err_entity;
2857 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2858 client->addr << 1, client->adapter->name);
bedc3939
LPC		 2859
2860 err = v4l2_async_register_subdev(sd);
2861 if (err)
2862 goto err_entity;
2863
54450f59
HV		 2864 return 0;
2865
2866err_entity:
2867 media_entity_cleanup(&sd->entity);
2868err_work_queues:
2869 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2870 destroy_workqueue(state->work_queues);
2871err_i2c:
2872 adv7604_unregister_clients(state);
2873err_hdl:
2874 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2875 return err;
2876}
2877
2878/* ----------------------------------------------------------------------- */
2879
2880static int adv7604_remove(struct i2c_client *client)
2881{
2882 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2883 struct adv7604_state *state = to_state(sd);
2884
2885 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2886 destroy_workqueue(state->work_queues);
bedc3939 2887 v4l2_async_unregister_subdev(sd);
54450f59
HV		 2888 v4l2_device_unregister_subdev(sd);
2889 media_entity_cleanup(&sd->entity);
2890 adv7604_unregister_clients(to_state(sd));
2891 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2892 return 0;
2893}
2894
2895/* ----------------------------------------------------------------------- */
2896
54450f59
HV		 2897static struct i2c_driver adv7604_driver = {
2898 .driver = {
2899 .owner = THIS_MODULE,
2900 .name = "adv7604",
f82f313e 2901 .of_match_table = of_match_ptr(adv7604_of_id),
54450f59
HV		 2902 },
2903 .probe = adv7604_probe,
2904 .remove = adv7604_remove,
f82f313e 2905 .id_table = adv7604_i2c_id,
54450f59
HV		 2906};
2907
2908module_i2c_driver(adv7604_driver);
Linux kernel - Deliverables
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