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[media] Add helper function for subdev event notifications
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
516613c1 32#include <linux/hdmi.h>
c72a53ce 33#include <linux/i2c.h>
54450f59
HV		 34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/slab.h>
c72a53ce 37#include <linux/v4l2-dv-timings.h>
54450f59
HV		 38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
f862f57d 40#include <linux/regmap.h>
c72a53ce
LP		 41
42#include <media/adv7604.h>
54450f59 43#include <media/v4l2-ctrls.h>
c72a53ce 44#include <media/v4l2-device.h>
0975626d 45#include <media/v4l2-event.h>
25764158 46#include <media/v4l2-dv-timings.h>
6fa88045 47#include <media/v4l2-of.h>
54450f59
HV		 48
49static int debug;
50module_param(debug, int, 0644);
51MODULE_PARM_DESC(debug, "debug level (0-2)");
52
53MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
54MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
56MODULE_LICENSE("GPL");
57
58/* ADV7604 system clock frequency */
b44b2e06 59#define ADV76XX_FSC (28636360)
54450f59 60
b44b2e06 61#define ADV76XX_RGB_OUT (1 << 1)
539b33b0 62
b44b2e06 63#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
539b33b0 64#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
b44b2e06 65#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
539b33b0 66
b44b2e06 67#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
539b33b0 68#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
b44b2e06 69#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
539b33b0 70#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
b44b2e06 71#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
539b33b0
LP		 72#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
73
b44b2e06
PA		 74#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
75#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
76#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
77#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
78#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
79#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
539b33b0 80
b44b2e06 81#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
539b33b0 82
b44b2e06 83enum adv76xx_type {
d42010a1
LPC		 84 ADV7604,
85 ADV7611,
8331d30b 86 ADV7612,
d42010a1
LPC		 87};
88
b44b2e06 89struct adv76xx_reg_seq {
d42010a1
LPC		 90 unsigned int reg;
91 u8 val;
92};
93
b44b2e06 94struct adv76xx_format_info {
f5fe58fd 95 u32 code;
539b33b0
LP		 96 u8 op_ch_sel;
97 bool rgb_out;
98 bool swap_cb_cr;
99 u8 op_format_sel;
100};
101
516613c1
HV		 102struct adv76xx_cfg_read_infoframe {
103 const char *desc;
104 u8 present_mask;
105 u8 head_addr;
106 u8 payload_addr;
107};
108
b44b2e06
PA		 109struct adv76xx_chip_info {
110 enum adv76xx_type type;
d42010a1
LPC		 111
112 bool has_afe;
113 unsigned int max_port;
114 unsigned int num_dv_ports;
115
116 unsigned int edid_enable_reg;
117 unsigned int edid_status_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
80f4944e 123 unsigned int cp_csc;
d42010a1 124
b44b2e06 125 const struct adv76xx_format_info *formats;
539b33b0
LP		 126 unsigned int nformats;
127
d42010a1
LPC		 128 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
129 void (*setup_irqs)(struct v4l2_subdev *sd);
130 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
131 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
132
133 /* 0 = AFE, 1 = HDMI */
b44b2e06 134 const struct adv76xx_reg_seq *recommended_settings[2];
d42010a1
LPC		 135 unsigned int num_recommended_settings[2];
136
137 unsigned long page_mask;
5380baaf 138
139 /* Masks for timings */
140 unsigned int linewidth_mask;
141 unsigned int field0_height_mask;
142 unsigned int field1_height_mask;
143 unsigned int hfrontporch_mask;
144 unsigned int hsync_mask;
145 unsigned int hbackporch_mask;
146 unsigned int field0_vfrontporch_mask;
147 unsigned int field1_vfrontporch_mask;
148 unsigned int field0_vsync_mask;
149 unsigned int field1_vsync_mask;
150 unsigned int field0_vbackporch_mask;
151 unsigned int field1_vbackporch_mask;
d42010a1
LPC		 152};
153
54450f59
HV		 154/*
155 **********************************************************************
156 *
157 * Arrays with configuration parameters for the ADV7604
158 *
159 **********************************************************************
160 */
c784b1e2 161
b44b2e06
PA		 162struct adv76xx_state {
163 const struct adv76xx_chip_info *info;
164 struct adv76xx_platform_data pdata;
539b33b0 165
e9d50e9e
LP		 166 struct gpio_desc *hpd_gpio[4];
167
54450f59 168 struct v4l2_subdev sd;
b44b2e06 169 struct media_pad pads[ADV76XX_PAD_MAX];
c784b1e2 170 unsigned int source_pad;
539b33b0 171
54450f59 172 struct v4l2_ctrl_handler hdl;
539b33b0 173
b44b2e06 174 enum adv76xx_pad selected_input;
539b33b0 175
54450f59 176 struct v4l2_dv_timings timings;
b44b2e06 177 const struct adv76xx_format_info *format;
539b33b0 178
4a31a93a
MR		 179 struct {
180 u8 edid[256];
181 u32 present;
182 unsigned blocks;
183 } edid;
dd08beb9 184 u16 spa_port_a[2];
54450f59
HV		 185 struct v4l2_fract aspect_ratio;
186 u32 rgb_quantization_range;
187 struct workqueue_struct *work_queues;
188 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 189 bool restart_stdi_once;
54450f59
HV		 190
191 /* i2c clients */
b44b2e06 192 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
54450f59 193
f862f57d
PA		 194 /* Regmaps */
195 struct regmap *regmap[ADV76XX_PAGE_MAX];
196
54450f59
HV		 197 /* controls */
198 struct v4l2_ctrl *detect_tx_5v_ctrl;
199 struct v4l2_ctrl *analog_sampling_phase_ctrl;
200 struct v4l2_ctrl *free_run_color_manual_ctrl;
201 struct v4l2_ctrl *free_run_color_ctrl;
202 struct v4l2_ctrl *rgb_quantization_range_ctrl;
203};
204
b44b2e06 205static bool adv76xx_has_afe(struct adv76xx_state *state)
d42010a1
LPC		 206{
207 return state->info->has_afe;
208}
209
54450f59 210/* Supported CEA and DMT timings */
b44b2e06 211static const struct v4l2_dv_timings adv76xx_timings[] = {
54450f59
HV		 212 V4L2_DV_BT_CEA_720X480P59_94,
213 V4L2_DV_BT_CEA_720X576P50,
214 V4L2_DV_BT_CEA_1280X720P24,
215 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 216 V4L2_DV_BT_CEA_1280X720P50,
217 V4L2_DV_BT_CEA_1280X720P60,
218 V4L2_DV_BT_CEA_1920X1080P24,
219 V4L2_DV_BT_CEA_1920X1080P25,
220 V4L2_DV_BT_CEA_1920X1080P30,
221 V4L2_DV_BT_CEA_1920X1080P50,
222 V4L2_DV_BT_CEA_1920X1080P60,
223
ccbd5bc4 224 /* sorted by DMT ID */
54450f59
HV		 225 V4L2_DV_BT_DMT_640X350P85,
226 V4L2_DV_BT_DMT_640X400P85,
227 V4L2_DV_BT_DMT_720X400P85,
228 V4L2_DV_BT_DMT_640X480P60,
229 V4L2_DV_BT_DMT_640X480P72,
230 V4L2_DV_BT_DMT_640X480P75,
231 V4L2_DV_BT_DMT_640X480P85,
232 V4L2_DV_BT_DMT_800X600P56,
233 V4L2_DV_BT_DMT_800X600P60,
234 V4L2_DV_BT_DMT_800X600P72,
235 V4L2_DV_BT_DMT_800X600P75,
236 V4L2_DV_BT_DMT_800X600P85,
237 V4L2_DV_BT_DMT_848X480P60,
238 V4L2_DV_BT_DMT_1024X768P60,
239 V4L2_DV_BT_DMT_1024X768P70,
240 V4L2_DV_BT_DMT_1024X768P75,
241 V4L2_DV_BT_DMT_1024X768P85,
242 V4L2_DV_BT_DMT_1152X864P75,
243 V4L2_DV_BT_DMT_1280X768P60_RB,
244 V4L2_DV_BT_DMT_1280X768P60,
245 V4L2_DV_BT_DMT_1280X768P75,
246 V4L2_DV_BT_DMT_1280X768P85,
247 V4L2_DV_BT_DMT_1280X800P60_RB,
248 V4L2_DV_BT_DMT_1280X800P60,
249 V4L2_DV_BT_DMT_1280X800P75,
250 V4L2_DV_BT_DMT_1280X800P85,
251 V4L2_DV_BT_DMT_1280X960P60,
252 V4L2_DV_BT_DMT_1280X960P85,
253 V4L2_DV_BT_DMT_1280X1024P60,
254 V4L2_DV_BT_DMT_1280X1024P75,
255 V4L2_DV_BT_DMT_1280X1024P85,
256 V4L2_DV_BT_DMT_1360X768P60,
257 V4L2_DV_BT_DMT_1400X1050P60_RB,
258 V4L2_DV_BT_DMT_1400X1050P60,
259 V4L2_DV_BT_DMT_1400X1050P75,
260 V4L2_DV_BT_DMT_1400X1050P85,
261 V4L2_DV_BT_DMT_1440X900P60_RB,
262 V4L2_DV_BT_DMT_1440X900P60,
263 V4L2_DV_BT_DMT_1600X1200P60,
264 V4L2_DV_BT_DMT_1680X1050P60_RB,
265 V4L2_DV_BT_DMT_1680X1050P60,
266 V4L2_DV_BT_DMT_1792X1344P60,
267 V4L2_DV_BT_DMT_1856X1392P60,
268 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 269 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 270 V4L2_DV_BT_DMT_1366X768P60,
271 V4L2_DV_BT_DMT_1920X1080P60,
272 { },
273};
274
b44b2e06 275struct adv76xx_video_standards {
ccbd5bc4
HV		 276 struct v4l2_dv_timings timings;
277 u8 vid_std;
278 u8 v_freq;
279};
280
281/* sorted by number of lines */
b44b2e06 282static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
ccbd5bc4
HV		 283 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
284 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
285 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
286 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
287 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
288 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
289 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
290 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
291 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
292 /* TODO add 1920x1080P60_RB (CVT timing) */
293 { },
294};
295
296/* sorted by number of lines */
b44b2e06 297static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
ccbd5bc4
HV		 298 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
299 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
300 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
301 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
302 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
303 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
304 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
305 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
306 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
307 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
308 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
309 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
310 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
311 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
312 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
313 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
314 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
315 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
316 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
317 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
318 /* TODO add 1600X1200P60_RB (not a DMT timing) */
319 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
320 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
321 { },
322};
323
324/* sorted by number of lines */
b44b2e06 325static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
ccbd5bc4
HV		 326 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
327 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
328 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
329 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
330 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
331 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
332 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
333 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
334 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
335 { },
336};
337
338/* sorted by number of lines */
b44b2e06 339static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
ccbd5bc4
HV		 340 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
341 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
342 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
343 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
344 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
345 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
346 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
347 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
348 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
349 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
350 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
351 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
352 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
353 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
354 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
355 { },
356};
357
48519838
HV		 358static const struct v4l2_event adv76xx_ev_fmt = {
359 .type = V4L2_EVENT_SOURCE_CHANGE,
360 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
361};
362
54450f59
HV		 363/* ----------------------------------------------------------------------- */
364
b44b2e06 365static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
54450f59 366{
b44b2e06 367 return container_of(sd, struct adv76xx_state, sd);
54450f59
HV		 368}
369
54450f59
HV		 370static inline unsigned htotal(const struct v4l2_bt_timings *t)
371{
eacf8f9a 372 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 373}
374
54450f59
HV		 375static inline unsigned vtotal(const struct v4l2_bt_timings *t)
376{
eacf8f9a 377 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 378}
379
380/* ----------------------------------------------------------------------- */
381
f862f57d
PA		 382static int adv76xx_read_check(struct adv76xx_state *state,
383 int client_page, u8 reg)
54450f59 384{
f862f57d 385 struct i2c_client *client = state->i2c_clients[client_page];
54450f59 386 int err;
f862f57d 387 unsigned int val;
54450f59 388
f862f57d
PA		 389 err = regmap_read(state->regmap[client_page], reg, &val);
390
391 if (err) {
392 v4l_err(client, "error reading %02x, %02x\n",
393 client->addr, reg);
394 return err;
54450f59 395 }
f862f57d 396 return val;
54450f59
HV		 397}
398
f862f57d
PA		 399/* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
400 * size to one or more registers.
401 *
402 * A value of zero will be returned on success, a negative errno will
403 * be returned in error cases.
404 */
405static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
406 unsigned int init_reg, const void *val,
407 size_t val_len)
54450f59 408{
f862f57d
PA		 409 struct regmap *regmap = state->regmap[client_page];
410
411 if (val_len > I2C_SMBUS_BLOCK_MAX)
412 val_len = I2C_SMBUS_BLOCK_MAX;
54450f59 413
f862f57d 414 return regmap_raw_write(regmap, init_reg, val, val_len);
54450f59
HV		 415}
416
417/* ----------------------------------------------------------------------- */
418
419static inline int io_read(struct v4l2_subdev *sd, u8 reg)
420{
b44b2e06 421 struct adv76xx_state *state = to_state(sd);
54450f59 422
f862f57d 423 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
54450f59
HV		 424}
425
426static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
427{
b44b2e06 428 struct adv76xx_state *state = to_state(sd);
54450f59 429
f862f57d 430 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
54450f59
HV		 431}
432
22d97e56 433static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 434{
22d97e56 435 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 436}
437
438static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
439{
b44b2e06 440 struct adv76xx_state *state = to_state(sd);
54450f59 441
f862f57d 442 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 443}
444
445static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
446{
b44b2e06 447 struct adv76xx_state *state = to_state(sd);
54450f59 448
f862f57d 449 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
54450f59
HV		 450}
451
452static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
453{
b44b2e06 454 struct adv76xx_state *state = to_state(sd);
54450f59 455
f862f57d 456 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
54450f59
HV		 457}
458
459static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
460{
b44b2e06 461 struct adv76xx_state *state = to_state(sd);
54450f59 462
f862f57d 463 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
54450f59
HV		 464}
465
54450f59
HV		 466static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
467{
b44b2e06 468 struct adv76xx_state *state = to_state(sd);
54450f59 469
f862f57d 470 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
54450f59
HV		 471}
472
473static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
474{
b44b2e06 475 struct adv76xx_state *state = to_state(sd);
54450f59 476
f862f57d 477 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
54450f59
HV		 478}
479
54450f59
HV		 480static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
481{
b44b2e06 482 struct adv76xx_state *state = to_state(sd);
54450f59 483
f862f57d 484 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
54450f59
HV		 485}
486
487static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
488{
b44b2e06 489 struct adv76xx_state *state = to_state(sd);
54450f59 490
f862f57d 491 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
54450f59
HV		 492}
493
494static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
495{
b44b2e06 496 struct adv76xx_state *state = to_state(sd);
54450f59 497
f862f57d 498 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
54450f59
HV		 499}
500
501static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
502{
b44b2e06 503 struct adv76xx_state *state = to_state(sd);
54450f59 504
f862f57d 505 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
54450f59
HV		 506}
507
22d97e56 508static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 509{
22d97e56 510 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 511}
512
513static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
514{
b44b2e06 515 struct adv76xx_state *state = to_state(sd);
54450f59 516
f862f57d 517 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
54450f59
HV		 518}
519
520static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
521{
b44b2e06 522 struct adv76xx_state *state = to_state(sd);
54450f59 523
f862f57d 524 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
54450f59
HV		 525}
526
54450f59 527static inline int edid_write_block(struct v4l2_subdev *sd,
f862f57d 528 unsigned int total_len, const u8 *val)
54450f59 529{
b44b2e06 530 struct adv76xx_state *state = to_state(sd);
54450f59 531 int err = 0;
f862f57d
PA		 532 int i = 0;
533 int len = 0;
54450f59 534
f862f57d
PA		 535 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
536 __func__, total_len);
537
538 while (!err && i < total_len) {
539 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
540 I2C_SMBUS_BLOCK_MAX :
541 (total_len - i);
542
543 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
544 i, val + i, len);
545 i += len;
546 }
54450f59 547
dd08beb9
MR		 548 return err;
549}
54450f59 550
b44b2e06 551static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
e9d50e9e
LP		 552{
553 unsigned int i;
554
269bd132 555 for (i = 0; i < state->info->num_dv_ports; ++i)
e9d50e9e 556 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
e9d50e9e 557
b44b2e06 558 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
e9d50e9e
LP		 559}
560
b44b2e06 561static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
dd08beb9
MR		 562{
563 struct delayed_work *dwork = to_delayed_work(work);
b44b2e06 564 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
dd08beb9
MR		 565 delayed_work_enable_hotplug);
566 struct v4l2_subdev *sd = &state->sd;
54450f59 567
dd08beb9 568 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 569
b44b2e06 570 adv76xx_set_hpd(state, state->edid.present);
54450f59
HV		 571}
572
573static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
574{
b44b2e06 575 struct adv76xx_state *state = to_state(sd);
54450f59 576
f862f57d 577 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
54450f59
HV		 578}
579
51182a94
LP		 580static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
581{
582 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
583}
584
54450f59
HV		 585static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
586{
b44b2e06 587 struct adv76xx_state *state = to_state(sd);
54450f59 588
f862f57d 589 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
54450f59
HV		 590}
591
22d97e56 592static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 593{
22d97e56 594 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 595}
596
54450f59
HV		 597static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
598{
b44b2e06 599 struct adv76xx_state *state = to_state(sd);
54450f59 600
f862f57d 601 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
54450f59
HV		 602}
603
604static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
605{
b44b2e06 606 struct adv76xx_state *state = to_state(sd);
54450f59 607
f862f57d 608 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
54450f59
HV		 609}
610
51182a94
LP		 611static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
612{
613 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
614}
615
54450f59
HV		 616static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
617{
b44b2e06 618 struct adv76xx_state *state = to_state(sd);
54450f59 619
f862f57d 620 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
54450f59
HV		 621}
622
22d97e56 623static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 624{
22d97e56 625 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 626}
627
628static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
629{
b44b2e06 630 struct adv76xx_state *state = to_state(sd);
54450f59 631
f862f57d 632 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 633}
634
635static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
636{
b44b2e06 637 struct adv76xx_state *state = to_state(sd);
54450f59 638
f862f57d 639 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
05cacb17 640}
d42010a1 641
b44b2e06
PA		 642#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
643#define ADV76XX_REG_SEQ_TERM 0xffff
d42010a1
LPC		 644
645#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 646static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
d42010a1 647{
b44b2e06 648 struct adv76xx_state *state = to_state(sd);
d42010a1 649 unsigned int page = reg >> 8;
f862f57d
PA		 650 unsigned int val;
651 int err;
d42010a1
LPC		 652
653 if (!(BIT(page) & state->info->page_mask))
654 return -EINVAL;
655
656 reg &= 0xff;
f862f57d 657 err = regmap_read(state->regmap[page], reg, &val);
d42010a1 658
f862f57d 659 return err ? err : val;
d42010a1
LPC		 660}
661#endif
662
b44b2e06 663static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
d42010a1 664{
b44b2e06 665 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 666 unsigned int page = reg >> 8;
667
668 if (!(BIT(page) & state->info->page_mask))
669 return -EINVAL;
670
671 reg &= 0xff;
672
f862f57d 673 return regmap_write(state->regmap[page], reg, val);
d42010a1
LPC		 674}
675
b44b2e06
PA		 676static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
677 const struct adv76xx_reg_seq *reg_seq)
d42010a1
LPC		 678{
679 unsigned int i;
680
b44b2e06
PA		 681 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
682 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
d42010a1
LPC		 683}
684
539b33b0
LP		 685/* -----------------------------------------------------------------------------
686 * Format helpers
687 */
688
b44b2e06
PA		 689static const struct adv76xx_format_info adv7604_formats[] = {
690 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
691 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
692 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
693 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
694 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
695 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
696 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
697 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
698 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
699 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
700 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
701 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
702 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
703 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
704 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
705 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
706 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
707 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
708 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
709 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
710 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
711 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
712 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
713 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
714 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
715 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
716 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
717 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
718 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
719 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
720 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
721 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
722 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
723 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
724 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
726 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 728};
729
b44b2e06
PA		 730static const struct adv76xx_format_info adv7611_formats[] = {
731 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
732 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
733 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
734 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
735 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
736 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
737 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
738 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
739 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
740 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
741 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
742 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
743 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
744 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
745 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
746 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
747 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
748 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
749 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
750 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
751 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
752 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
753 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
754 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
755 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
756 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 757};
758
8331d30b
WT		 759static const struct adv76xx_format_info adv7612_formats[] = {
760 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
761 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
762 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
763 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
764 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
765 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
766 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
767 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
768 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
769 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
770 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
771 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
772 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
773 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
774};
775
b44b2e06
PA		 776static const struct adv76xx_format_info *
777adv76xx_format_info(struct adv76xx_state *state, u32 code)
539b33b0
LP		 778{
779 unsigned int i;
780
781 for (i = 0; i < state->info->nformats; ++i) {
782 if (state->info->formats[i].code == code)
783 return &state->info->formats[i];
784 }
785
786 return NULL;
787}
788
54450f59
HV		 789/* ----------------------------------------------------------------------- */
790
4a31a93a
MR		 791static inline bool is_analog_input(struct v4l2_subdev *sd)
792{
b44b2e06 793 struct adv76xx_state *state = to_state(sd);
4a31a93a 794
c784b1e2
LP		 795 return state->selected_input == ADV7604_PAD_VGA_RGB ||
796 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 797}
798
799static inline bool is_digital_input(struct v4l2_subdev *sd)
800{
b44b2e06 801 struct adv76xx_state *state = to_state(sd);
4a31a93a 802
b44b2e06 803 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
c784b1e2
LP		 804 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
805 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
806 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 807}
808
809/* ----------------------------------------------------------------------- */
810
54450f59 811#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 812static void adv76xx_inv_register(struct v4l2_subdev *sd)
54450f59
HV		 813{
814 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
815 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
816 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
817 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
818 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
819 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
820 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
821 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
822 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
823 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
824 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
825 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
826 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
827}
828
b44b2e06 829static int adv76xx_g_register(struct v4l2_subdev *sd,
54450f59
HV		 830 struct v4l2_dbg_register *reg)
831{
d42010a1
LPC		 832 int ret;
833
b44b2e06 834 ret = adv76xx_read_reg(sd, reg->reg);
d42010a1 835 if (ret < 0) {
54450f59 836 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 837 adv76xx_inv_register(sd);
d42010a1 838 return ret;
54450f59 839 }
d42010a1
LPC		 840
841 reg->size = 1;
842 reg->val = ret;
843
54450f59
HV		 844 return 0;
845}
846
b44b2e06 847static int adv76xx_s_register(struct v4l2_subdev *sd,
977ba3b1 848 const struct v4l2_dbg_register *reg)
54450f59 849{
d42010a1 850 int ret;
1577461b 851
b44b2e06 852 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
d42010a1 853 if (ret < 0) {
54450f59 854 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 855 adv76xx_inv_register(sd);
d42010a1 856 return ret;
54450f59 857 }
d42010a1 858
54450f59
HV		 859 return 0;
860}
861#endif
862
d42010a1
LPC		 863static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
864{
865 u8 value = io_read(sd, 0x6f);
866
867 return ((value & 0x10) >> 4)
868 | ((value & 0x08) >> 2)
869 | ((value & 0x04) << 0)
870 | ((value & 0x02) << 2);
871}
872
873static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
874{
875 u8 value = io_read(sd, 0x6f);
876
877 return value & 1;
878}
879
b44b2e06 880static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
54450f59 881{
b44b2e06
PA		 882 struct adv76xx_state *state = to_state(sd);
883 const struct adv76xx_chip_info *info = state->info;
54450f59 884
54450f59 885 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 886 info->read_cable_det(sd));
54450f59
HV		 887}
888
ccbd5bc4
HV		 889static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
890 u8 prim_mode,
b44b2e06 891 const struct adv76xx_video_standards *predef_vid_timings,
ccbd5bc4
HV		 892 const struct v4l2_dv_timings *timings)
893{
ccbd5bc4
HV		 894 int i;
895
896 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 897 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 898 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 899 continue;
900 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
901 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
902 prim_mode); /* v_freq and prim mode */
903 return 0;
904 }
905
906 return -1;
907}
908
909static int configure_predefined_video_timings(struct v4l2_subdev *sd,
910 struct v4l2_dv_timings *timings)
54450f59 911{
b44b2e06 912 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 913 int err;
914
915 v4l2_dbg(1, debug, sd, "%s", __func__);
916
b44b2e06 917 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 918 /* reset to default values */
919 io_write(sd, 0x16, 0x43);
920 io_write(sd, 0x17, 0x5a);
921 }
ccbd5bc4 922 /* disable embedded syncs for auto graphics mode */
22d97e56 923 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 924 cp_write(sd, 0x8f, 0x00);
925 cp_write(sd, 0x90, 0x00);
926 cp_write(sd, 0xa2, 0x00);
927 cp_write(sd, 0xa3, 0x00);
928 cp_write(sd, 0xa4, 0x00);
929 cp_write(sd, 0xa5, 0x00);
930 cp_write(sd, 0xa6, 0x00);
931 cp_write(sd, 0xa7, 0x00);
932 cp_write(sd, 0xab, 0x00);
933 cp_write(sd, 0xac, 0x00);
934
4a31a93a 935 if (is_analog_input(sd)) {
ccbd5bc4
HV		 936 err = find_and_set_predefined_video_timings(sd,
937 0x01, adv7604_prim_mode_comp, timings);
938 if (err)
939 err = find_and_set_predefined_video_timings(sd,
940 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 941 } else if (is_digital_input(sd)) {
ccbd5bc4 942 err = find_and_set_predefined_video_timings(sd,
b44b2e06 943 0x05, adv76xx_prim_mode_hdmi_comp, timings);
ccbd5bc4
HV		 944 if (err)
945 err = find_and_set_predefined_video_timings(sd,
b44b2e06 946 0x06, adv76xx_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 947 } else {
948 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
949 __func__, state->selected_input);
ccbd5bc4 950 err = -1;
ccbd5bc4
HV		 951 }
952
953
954 return err;
955}
956
957static void configure_custom_video_timings(struct v4l2_subdev *sd,
958 const struct v4l2_bt_timings *bt)
959{
b44b2e06 960 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 961 u32 width = htotal(bt);
962 u32 height = vtotal(bt);
963 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
964 u16 cp_start_eav = width - bt->hfrontporch;
965 u16 cp_start_vbi = height - bt->vfrontporch;
966 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
967 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
b44b2e06 968 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
ccbd5bc4
HV		 969 const u8 pll[2] = {
970 0xc0 | ((width >> 8) & 0x1f),
971 width & 0xff
972 };
54450f59
HV		 973
974 v4l2_dbg(2, debug, sd, "%s\n", __func__);
975
4a31a93a 976 if (is_analog_input(sd)) {
ccbd5bc4
HV		 977 /* auto graphics */
978 io_write(sd, 0x00, 0x07); /* video std */
979 io_write(sd, 0x01, 0x02); /* prim mode */
980 /* enable embedded syncs for auto graphics mode */
22d97e56 981 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 982
ccbd5bc4 983 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 984 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
985 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
f862f57d
PA		 986 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
987 0x16, pll, 2))
54450f59 988 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 989
990 /* active video - horizontal timing */
54450f59 991 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 992 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 993 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 994 cp_write(sd, 0xa4, cp_start_eav & 0xff);
995
996 /* active video - vertical timing */
54450f59 997 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 998 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 999 ((cp_end_vbi >> 8) & 0xf));
54450f59 1000 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 1001 } else if (is_digital_input(sd)) {
ccbd5bc4 1002 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1003 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 1004 io_write(sd, 0x00, 0x02); /* video std */
1005 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 1006 } else {
1007 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1008 __func__, state->selected_input);
54450f59 1009 }
54450f59 1010
ccbd5bc4
HV		 1011 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1012 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1013 cp_write(sd, 0xab, (height >> 4) & 0xff);
1014 cp_write(sd, 0xac, (height & 0x0f) << 4);
1015}
54450f59 1016
b44b2e06 1017static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
5c6c6349 1018{
b44b2e06 1019 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1020 u8 offset_buf[4];
1021
1022 if (auto_offset) {
1023 offset_a = 0x3ff;
1024 offset_b = 0x3ff;
1025 offset_c = 0x3ff;
1026 }
1027
1028 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1029 __func__, auto_offset ? "Auto" : "Manual",
1030 offset_a, offset_b, offset_c);
1031
1032 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1033 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1034 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1035 offset_buf[3] = offset_c & 0x0ff;
1036
1037 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1038 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1039 0x77, offset_buf, 4))
5c6c6349
MR		 1040 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1041}
1042
b44b2e06 1043static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
5c6c6349 1044{
b44b2e06 1045 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1046 u8 gain_buf[4];
1047 u8 gain_man = 1;
1048 u8 agc_mode_man = 1;
1049
1050 if (auto_gain) {
1051 gain_man = 0;
1052 agc_mode_man = 0;
1053 gain_a = 0x100;
1054 gain_b = 0x100;
1055 gain_c = 0x100;
1056 }
1057
1058 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1059 __func__, auto_gain ? "Auto" : "Manual",
1060 gain_a, gain_b, gain_c);
1061
1062 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1063 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1064 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1065 gain_buf[3] = ((gain_c & 0x0ff));
1066
1067 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1068 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1069 0x73, gain_buf, 4))
5c6c6349
MR		 1070 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1071}
1072
54450f59
HV		 1073static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1074{
b44b2e06 1075 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1076 bool rgb_output = io_read(sd, 0x02) & 0x02;
1077 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1078
1079 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1080 __func__, state->rgb_quantization_range,
1081 rgb_output, hdmi_signal);
54450f59 1082
b44b2e06
PA		 1083 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1084 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1085
54450f59
HV		 1086 switch (state->rgb_quantization_range) {
1087 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1088 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1089 /* Receiving analog RGB signal
1090 * Set RGB full range (0-255) */
22d97e56 1091 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1092 break;
1093 }
1094
c784b1e2 1095 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1096 /* Receiving analog YPbPr signal
1097 * Set automode */
22d97e56 1098 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1099 break;
1100 }
1101
5c6c6349 1102 if (hdmi_signal) {
9833239e
MR		 1103 /* Receiving HDMI signal
1104 * Set automode */
22d97e56 1105 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1106 break;
1107 }
1108
1109 /* Receiving DVI-D signal
1110 * ADV7604 selects RGB limited range regardless of
1111 * input format (CE/IT) in automatic mode */
680fee04 1112 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
9833239e 1113 /* RGB limited range (16-235) */
22d97e56 1114 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1115 } else {
1116 /* RGB full range (0-255) */
22d97e56 1117 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1118
1119 if (is_digital_input(sd) && rgb_output) {
b44b2e06 1120 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
5c6c6349 1121 } else {
b44b2e06
PA		 1122 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1123 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
5c6c6349 1124 }
54450f59
HV		 1125 }
1126 break;
1127 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1128 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1129 /* YCrCb limited range (16-235) */
22d97e56 1130 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1131 break;
d261e842 1132 }
5c6c6349
MR		 1133
1134 /* RGB limited range (16-235) */
22d97e56 1135 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1136
54450f59
HV		 1137 break;
1138 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1139 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1140 /* YCrCb full range (0-255) */
22d97e56 1141 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1142 break;
1143 }
1144
1145 /* RGB full range (0-255) */
22d97e56 1146 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1147
1148 if (is_analog_input(sd) || hdmi_signal)
1149 break;
1150
1151 /* Adjust gain/offset for DVI-D signals only */
1152 if (rgb_output) {
b44b2e06 1153 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1154 } else {
b44b2e06
PA		 1155 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1156 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1157 }
54450f59
HV		 1158 break;
1159 }
1160}
1161
b44b2e06 1162static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
54450f59 1163{
c269887c 1164 struct v4l2_subdev *sd =
b44b2e06 1165 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
c269887c 1166
b44b2e06 1167 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1168
1169 switch (ctrl->id) {
1170 case V4L2_CID_BRIGHTNESS:
1171 cp_write(sd, 0x3c, ctrl->val);
1172 return 0;
1173 case V4L2_CID_CONTRAST:
1174 cp_write(sd, 0x3a, ctrl->val);
1175 return 0;
1176 case V4L2_CID_SATURATION:
1177 cp_write(sd, 0x3b, ctrl->val);
1178 return 0;
1179 case V4L2_CID_HUE:
1180 cp_write(sd, 0x3d, ctrl->val);
1181 return 0;
1182 case V4L2_CID_DV_RX_RGB_RANGE:
1183 state->rgb_quantization_range = ctrl->val;
1184 set_rgb_quantization_range(sd);
1185 return 0;
1186 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
b44b2e06 1187 if (!adv76xx_has_afe(state))
d42010a1 1188 return -EINVAL;
54450f59
HV		 1189 /* Set the analog sampling phase. This is needed to find the
1190 best sampling phase for analog video: an application or
1191 driver has to try a number of phases and analyze the picture
1192 quality before settling on the best performing phase. */
1193 afe_write(sd, 0xc8, ctrl->val);
1194 return 0;
1195 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1196 /* Use the default blue color for free running mode,
1197 or supply your own. */
22d97e56 1198 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1199 return 0;
1200 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1201 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1202 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1203 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1204 return 0;
1205 }
1206 return -EINVAL;
1207}
1208
54450f59
HV		 1209/* ----------------------------------------------------------------------- */
1210
1211static inline bool no_power(struct v4l2_subdev *sd)
1212{
1213 /* Entire chip or CP powered off */
1214 return io_read(sd, 0x0c) & 0x24;
1215}
1216
1217static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1218{
b44b2e06 1219 struct adv76xx_state *state = to_state(sd);
4a31a93a
MR		 1220
1221 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1222}
1223
1224static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1225{
b44b2e06
PA		 1226 struct adv76xx_state *state = to_state(sd);
1227 const struct adv76xx_chip_info *info = state->info;
d42010a1
LPC		 1228
1229 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1230}
1231
bb88f325
MB		 1232static inline bool is_hdmi(struct v4l2_subdev *sd)
1233{
1234 return hdmi_read(sd, 0x05) & 0x80;
1235}
1236
54450f59
HV		 1237static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1238{
b44b2e06 1239 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 1240
1241 /*
1242 * Chips without a AFE don't expose registers for the SSPD, so just assume
1243 * that we have a lock.
1244 */
b44b2e06 1245 if (adv76xx_has_afe(state))
d42010a1
LPC		 1246 return false;
1247
54450f59
HV		 1248 /* TODO channel 2 */
1249 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1250}
1251
1252static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1253{
1254 /* TODO channel 2 */
1255 return !(cp_read(sd, 0xb1) & 0x80);
1256}
1257
1258static inline bool no_signal(struct v4l2_subdev *sd)
1259{
54450f59
HV		 1260 bool ret;
1261
1262 ret = no_power(sd);
1263
1264 ret |= no_lock_stdi(sd);
1265 ret |= no_lock_sspd(sd);
1266
4a31a93a 1267 if (is_digital_input(sd)) {
54450f59
HV		 1268 ret |= no_lock_tmds(sd);
1269 ret |= no_signal_tmds(sd);
1270 }
1271
1272 return ret;
1273}
1274
1275static inline bool no_lock_cp(struct v4l2_subdev *sd)
1276{
b44b2e06 1277 struct adv76xx_state *state = to_state(sd);
d42010a1 1278
b44b2e06 1279 if (!adv76xx_has_afe(state))
d42010a1
LPC		 1280 return false;
1281
54450f59
HV		 1282 /* CP has detected a non standard number of lines on the incoming
1283 video compared to what it is configured to receive by s_dv_timings */
1284 return io_read(sd, 0x12) & 0x01;
1285}
1286
58514625 1287static inline bool in_free_run(struct v4l2_subdev *sd)
1288{
1289 return cp_read(sd, 0xff) & 0x10;
1290}
1291
b44b2e06 1292static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
54450f59 1293{
54450f59
HV		 1294 *status = 0;
1295 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1296 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1297 if (!in_free_run(sd) && no_lock_cp(sd))
1298 *status |= is_digital_input(sd) ?
1299 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1300
1301 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1302
1303 return 0;
1304}
1305
1306/* ----------------------------------------------------------------------- */
1307
54450f59
HV		 1308struct stdi_readback {
1309 u16 bl, lcf, lcvs;
1310 u8 hs_pol, vs_pol;
1311 bool interlaced;
1312};
1313
1314static int stdi2dv_timings(struct v4l2_subdev *sd,
1315 struct stdi_readback *stdi,
1316 struct v4l2_dv_timings *timings)
1317{
b44b2e06
PA		 1318 struct adv76xx_state *state = to_state(sd);
1319 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
54450f59
HV		 1320 u32 pix_clk;
1321 int i;
1322
b44b2e06
PA		 1323 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1324 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
54450f59 1325 continue;
b44b2e06 1326 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
54450f59
HV		 1327 continue;
1328
b44b2e06 1329 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
54450f59 1330
b44b2e06
PA		 1331 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1332 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1333 *timings = adv76xx_timings[i];
54450f59
HV		 1334 return 0;
1335 }
1336 }
1337
5fea1bb7 1338 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
54450f59
HV		 1339 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1340 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1341 false, timings))
54450f59
HV		 1342 return 0;
1343 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1344 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1345 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1346 false, state->aspect_ratio, timings))
54450f59
HV		 1347 return 0;
1348
ccbd5bc4
HV		 1349 v4l2_dbg(2, debug, sd,
1350 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1351 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1352 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1353 return -1;
1354}
1355
d42010a1 1356
54450f59
HV		 1357static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1358{
b44b2e06
PA		 1359 struct adv76xx_state *state = to_state(sd);
1360 const struct adv76xx_chip_info *info = state->info;
4a2ccdd2
LP		 1361 u8 polarity;
1362
54450f59
HV		 1363 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1364 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1365 return -1;
1366 }
1367
1368 /* read STDI */
51182a94 1369 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1370 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1371 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1372 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1373
b44b2e06 1374 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1375 /* read SSPD */
1376 polarity = cp_read(sd, 0xb5);
1377 if ((polarity & 0x03) == 0x01) {
1378 stdi->hs_pol = polarity & 0x10
1379 ? (polarity & 0x08 ? '+' : '-') : 'x';
1380 stdi->vs_pol = polarity & 0x40
1381 ? (polarity & 0x20 ? '+' : '-') : 'x';
1382 } else {
1383 stdi->hs_pol = 'x';
1384 stdi->vs_pol = 'x';
1385 }
54450f59 1386 } else {
d42010a1
LPC		 1387 polarity = hdmi_read(sd, 0x05);
1388 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1389 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1390 }
1391
1392 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1393 v4l2_dbg(2, debug, sd,
1394 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1395 return -1;
1396 }
1397
1398 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1399 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1400 memset(stdi, 0, sizeof(struct stdi_readback));
1401 return -1;
1402 }
1403
1404 v4l2_dbg(2, debug, sd,
1405 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1406 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1407 stdi->hs_pol, stdi->vs_pol,
1408 stdi->interlaced ? "interlaced" : "progressive");
1409
1410 return 0;
1411}
1412
b44b2e06 1413static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1414 struct v4l2_enum_dv_timings *timings)
1415{
b44b2e06 1416 struct adv76xx_state *state = to_state(sd);
afec5599 1417
b44b2e06 1418 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
54450f59 1419 return -EINVAL;
afec5599
LP		 1420
1421 if (timings->pad >= state->source_pad)
1422 return -EINVAL;
1423
54450f59 1424 memset(timings->reserved, 0, sizeof(timings->reserved));
b44b2e06 1425 timings->timings = adv76xx_timings[timings->index];
54450f59
HV		 1426 return 0;
1427}
1428
b44b2e06 1429static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
7515e096 1430 struct v4l2_dv_timings_cap *cap)
54450f59 1431{
b44b2e06 1432 struct adv76xx_state *state = to_state(sd);
7515e096
LP		 1433
1434 if (cap->pad >= state->source_pad)
1435 return -EINVAL;
1436
54450f59
HV		 1437 cap->type = V4L2_DV_BT_656_1120;
1438 cap->bt.max_width = 1920;
1439 cap->bt.max_height = 1200;
fe9c2564 1440 cap->bt.min_pixelclock = 25000000;
afec5599 1441
7515e096 1442 switch (cap->pad) {
b44b2e06 1443 case ADV76XX_PAD_HDMI_PORT_A:
afec5599
LP		 1444 case ADV7604_PAD_HDMI_PORT_B:
1445 case ADV7604_PAD_HDMI_PORT_C:
1446 case ADV7604_PAD_HDMI_PORT_D:
54450f59 1447 cap->bt.max_pixelclock = 225000000;
afec5599
LP		 1448 break;
1449 case ADV7604_PAD_VGA_RGB:
1450 case ADV7604_PAD_VGA_COMP:
1451 default:
54450f59 1452 cap->bt.max_pixelclock = 170000000;
afec5599
LP		 1453 break;
1454 }
1455
54450f59
HV		 1456 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1457 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1458 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1459 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1460 return 0;
1461}
1462
1463/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
b44b2e06
PA		 1464 if the format is listed in adv76xx_timings[] */
1465static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
54450f59
HV		 1466 struct v4l2_dv_timings *timings)
1467{
54450f59
HV		 1468 int i;
1469
b44b2e06
PA		 1470 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1471 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
4a31a93a 1472 is_digital_input(sd) ? 250000 : 1000000)) {
b44b2e06 1473 *timings = adv76xx_timings[i];
54450f59
HV		 1474 break;
1475 }
1476 }
1477}
1478
d42010a1
LPC		 1479static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1480{
1481 unsigned int freq;
1482 int a, b;
1483
1484 a = hdmi_read(sd, 0x06);
1485 b = hdmi_read(sd, 0x3b);
1486 if (a < 0 || b < 0)
1487 return 0;
1488 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1489
1490 if (is_hdmi(sd)) {
1491 /* adjust for deep color mode */
1492 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1493
1494 freq = freq * 8 / bits_per_channel;
1495 }
1496
1497 return freq;
1498}
1499
1500static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1501{
1502 int a, b;
1503
1504 a = hdmi_read(sd, 0x51);
1505 b = hdmi_read(sd, 0x52);
1506 if (a < 0 || b < 0)
1507 return 0;
1508 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1509}
1510
b44b2e06 1511static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1512 struct v4l2_dv_timings *timings)
1513{
b44b2e06
PA		 1514 struct adv76xx_state *state = to_state(sd);
1515 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 1516 struct v4l2_bt_timings *bt = &timings->bt;
1517 struct stdi_readback stdi;
1518
1519 if (!timings)
1520 return -EINVAL;
1521
1522 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1523
1524 if (no_signal(sd)) {
1e0b9156 1525 state->restart_stdi_once = true;
54450f59
HV		 1526 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1527 return -ENOLINK;
1528 }
1529
1530 /* read STDI */
1531 if (read_stdi(sd, &stdi)) {
1532 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1533 return -ENOLINK;
1534 }
1535 bt->interlaced = stdi.interlaced ?
1536 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1537
4a31a93a 1538 if (is_digital_input(sd)) {
54450f59
HV		 1539 timings->type = V4L2_DV_BT_656_1120;
1540
5380baaf 1541 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1542 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
d42010a1 1543 bt->pixelclock = info->read_hdmi_pixelclock(sd);
5380baaf 1544 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1545 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1546 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1547 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1548 info->field0_vfrontporch_mask) / 2;
1549 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1550 bt->vbackporch = hdmi_read16(sd, 0x32,
1551 info->field0_vbackporch_mask) / 2;
54450f59
HV		 1552 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1553 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1554 if (bt->interlaced == V4L2_DV_INTERLACED) {
5380baaf 1555 bt->height += hdmi_read16(sd, 0x0b,
1556 info->field1_height_mask);
1557 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1558 info->field1_vfrontporch_mask) / 2;
1559 bt->il_vsync = hdmi_read16(sd, 0x30,
1560 info->field1_vsync_mask) / 2;
1561 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1562 info->field1_vbackporch_mask) / 2;
54450f59 1563 }
b44b2e06 1564 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1565 } else {
1566 /* find format
80939647 1567 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1568 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1569 */
1570 if (!stdi2dv_timings(sd, &stdi, timings))
1571 goto found;
1572 stdi.lcvs += 1;
1573 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1574 if (!stdi2dv_timings(sd, &stdi, timings))
1575 goto found;
1576 stdi.lcvs -= 2;
1577 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1578 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1579 /*
1580 * The STDI block may measure wrong values, especially
1581 * for lcvs and lcf. If the driver can not find any
1582 * valid timing, the STDI block is restarted to measure
1583 * the video timings again. The function will return an
1584 * error, but the restart of STDI will generate a new
1585 * STDI interrupt and the format detection process will
1586 * restart.
1587 */
1588 if (state->restart_stdi_once) {
1589 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1590 /* TODO restart STDI for Sync Channel 2 */
1591 /* enter one-shot mode */
22d97e56 1592 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1593 /* trigger STDI restart */
22d97e56 1594 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1595 /* reset to continuous mode */
22d97e56 1596 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1597 state->restart_stdi_once = false;
1598 return -ENOLINK;
1599 }
54450f59
HV		 1600 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1601 return -ERANGE;
1602 }
cf9afb1d 1603 state->restart_stdi_once = true;
54450f59
HV		 1604 }
1605found:
1606
1607 if (no_signal(sd)) {
1608 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1609 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1610 return -ENOLINK;
1611 }
1612
4a31a93a
MR		 1613 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1614 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1615 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1616 __func__, (u32)bt->pixelclock);
1617 return -ERANGE;
1618 }
1619
1620 if (debug > 1)
b44b2e06 1621 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
11d034c8 1622 timings, true);
54450f59
HV		 1623
1624 return 0;
1625}
1626
b44b2e06 1627static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1628 struct v4l2_dv_timings *timings)
1629{
b44b2e06 1630 struct adv76xx_state *state = to_state(sd);
54450f59 1631 struct v4l2_bt_timings *bt;
ccbd5bc4 1632 int err;
54450f59
HV		 1633
1634 if (!timings)
1635 return -EINVAL;
1636
d48eb48c
MR		 1637 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1638 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1639 return 0;
1640 }
1641
54450f59
HV		 1642 bt = &timings->bt;
1643
4a31a93a
MR		 1644 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1645 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1646 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1647 __func__, (u32)bt->pixelclock);
1648 return -ERANGE;
1649 }
ccbd5bc4 1650
b44b2e06 1651 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1652
1653 state->timings = *timings;
1654
22d97e56 1655 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1656
1657 /* Use prim_mode and vid_std when available */
1658 err = configure_predefined_video_timings(sd, timings);
1659 if (err) {
1660 /* custom settings when the video format
1661 does not have prim_mode/vid_std */
1662 configure_custom_video_timings(sd, bt);
1663 }
54450f59
HV		 1664
1665 set_rgb_quantization_range(sd);
1666
54450f59 1667 if (debug > 1)
b44b2e06 1668 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
11d034c8 1669 timings, true);
54450f59
HV		 1670 return 0;
1671}
1672
b44b2e06 1673static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1674 struct v4l2_dv_timings *timings)
1675{
b44b2e06 1676 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1677
1678 *timings = state->timings;
1679 return 0;
1680}
1681
d42010a1
LPC		 1682static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1683{
1684 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1685}
1686
1687static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1688{
1689 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1690}
1691
6b0d5d34 1692static void enable_input(struct v4l2_subdev *sd)
54450f59 1693{
b44b2e06 1694 struct adv76xx_state *state = to_state(sd);
6b0d5d34 1695
4a31a93a 1696 if (is_analog_input(sd)) {
54450f59 1697 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1698 } else if (is_digital_input(sd)) {
22d97e56 1699 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1700 state->info->set_termination(sd, true);
54450f59 1701 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1702 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1703 } else {
1704 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1705 __func__, state->selected_input);
54450f59
HV		 1706 }
1707}
1708
1709static void disable_input(struct v4l2_subdev *sd)
1710{
b44b2e06 1711 struct adv76xx_state *state = to_state(sd);
d42010a1 1712
22d97e56 1713 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1714 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1715 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1716 state->info->set_termination(sd, false);
54450f59
HV		 1717}
1718
6b0d5d34 1719static void select_input(struct v4l2_subdev *sd)
54450f59 1720{
b44b2e06
PA		 1721 struct adv76xx_state *state = to_state(sd);
1722 const struct adv76xx_chip_info *info = state->info;
54450f59 1723
4a31a93a 1724 if (is_analog_input(sd)) {
b44b2e06 1725 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1726
1727 afe_write(sd, 0x00, 0x08); /* power up ADC */
1728 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1729 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1730 } else if (is_digital_input(sd)) {
1731 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1732
b44b2e06 1733 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
d42010a1 1734
b44b2e06 1735 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1736 afe_write(sd, 0x00, 0xff); /* power down ADC */
1737 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1738 afe_write(sd, 0xc8, 0x40); /* phase control */
1739 }
1740
54450f59
HV		 1741 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1742 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1743 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1744 } else {
1745 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1746 __func__, state->selected_input);
54450f59
HV		 1747 }
1748}
1749
b44b2e06 1750static int adv76xx_s_routing(struct v4l2_subdev *sd,
54450f59
HV		 1751 u32 input, u32 output, u32 config)
1752{
b44b2e06 1753 struct adv76xx_state *state = to_state(sd);
54450f59 1754
ff4f80fd
MR		 1755 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1756 __func__, input, state->selected_input);
1757
1758 if (input == state->selected_input)
1759 return 0;
54450f59 1760
d42010a1
LPC		 1761 if (input > state->info->max_port)
1762 return -EINVAL;
1763
4a31a93a 1764 state->selected_input = input;
54450f59
HV		 1765
1766 disable_input(sd);
6b0d5d34 1767 select_input(sd);
6b0d5d34 1768 enable_input(sd);
54450f59 1769
48519838
HV		 1770 v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT,
1771 (void *)&adv76xx_ev_fmt);
54450f59
HV		 1772 return 0;
1773}
1774
b44b2e06 1775static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1776 struct v4l2_subdev_pad_config *cfg,
539b33b0 1777 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1778{
b44b2e06 1779 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1780
1781 if (code->index >= state->info->nformats)
54450f59 1782 return -EINVAL;
539b33b0
LP		 1783
1784 code->code = state->info->formats[code->index].code;
1785
54450f59
HV		 1786 return 0;
1787}
1788
b44b2e06 1789static void adv76xx_fill_format(struct adv76xx_state *state,
539b33b0 1790 struct v4l2_mbus_framefmt *format)
54450f59 1791{
539b33b0 1792 memset(format, 0, sizeof(*format));
54450f59 1793
539b33b0
LP		 1794 format->width = state->timings.bt.width;
1795 format->height = state->timings.bt.height;
1796 format->field = V4L2_FIELD_NONE;
680fee04 1797 format->colorspace = V4L2_COLORSPACE_SRGB;
539b33b0 1798
680fee04 1799 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
539b33b0 1800 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1801 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1802}
1803
1804/*
1805 * Compute the op_ch_sel value required to obtain on the bus the component order
1806 * corresponding to the selected format taking into account bus reordering
1807 * applied by the board at the output of the device.
1808 *
1809 * The following table gives the op_ch_value from the format component order
1810 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
b44b2e06 1811 * adv76xx_bus_order value in row).
539b33b0
LP		 1812 *
1813 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1814 * ----------+-------------------------------------------------
1815 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1816 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1817 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1818 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1819 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1820 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1821 */
b44b2e06 1822static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
539b33b0
LP		 1823{
1824#define _SEL(a,b,c,d,e,f) { \
b44b2e06
PA		 1825 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1826 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
539b33b0
LP		 1827#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1828
1829 static const unsigned int op_ch_sel[6][6] = {
1830 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1831 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1832 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1833 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1834 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1835 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1836 };
1837
1838 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1839}
1840
b44b2e06 1841static void adv76xx_setup_format(struct adv76xx_state *state)
539b33b0
LP		 1842{
1843 struct v4l2_subdev *sd = &state->sd;
1844
22d97e56 1845 io_write_clr_set(sd, 0x02, 0x02,
b44b2e06 1846 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
539b33b0
LP		 1847 io_write(sd, 0x03, state->format->op_format_sel |
1848 state->pdata.op_format_mode_sel);
b44b2e06 1849 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
22d97e56 1850 io_write_clr_set(sd, 0x05, 0x01,
b44b2e06 1851 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
539b33b0
LP		 1852}
1853
f7234138
HV		 1854static int adv76xx_get_format(struct v4l2_subdev *sd,
1855 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1856 struct v4l2_subdev_format *format)
1857{
b44b2e06 1858 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1859
1860 if (format->pad != state->source_pad)
1861 return -EINVAL;
1862
b44b2e06 1863 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1864
1865 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1866 struct v4l2_mbus_framefmt *fmt;
1867
f7234138 1868 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1869 format->format.code = fmt->code;
1870 } else {
1871 format->format.code = state->format->code;
54450f59 1872 }
539b33b0
LP		 1873
1874 return 0;
1875}
1876
f7234138
HV		 1877static int adv76xx_set_format(struct v4l2_subdev *sd,
1878 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1879 struct v4l2_subdev_format *format)
1880{
b44b2e06
PA		 1881 struct adv76xx_state *state = to_state(sd);
1882 const struct adv76xx_format_info *info;
539b33b0
LP		 1883
1884 if (format->pad != state->source_pad)
1885 return -EINVAL;
1886
b44b2e06 1887 info = adv76xx_format_info(state, format->format.code);
539b33b0 1888 if (info == NULL)
b44b2e06 1889 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0 1890
b44b2e06 1891 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1892 format->format.code = info->code;
1893
1894 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1895 struct v4l2_mbus_framefmt *fmt;
1896
f7234138 1897 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1898 fmt->code = format->format.code;
1899 } else {
1900 state->format = info;
b44b2e06 1901 adv76xx_setup_format(state);
539b33b0
LP		 1902 }
1903
54450f59
HV		 1904 return 0;
1905}
1906
b44b2e06 1907static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
54450f59 1908{
b44b2e06
PA		 1909 struct adv76xx_state *state = to_state(sd);
1910 const struct adv76xx_chip_info *info = state->info;
f24d229c
MR		 1911 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1912 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1913 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1914 u8 fmt_change_digital;
1915 u8 fmt_change;
1916 u8 tx_5v;
1917
1918 if (irq_reg_0x43)
1919 io_write(sd, 0x44, irq_reg_0x43);
1920 if (irq_reg_0x70)
1921 io_write(sd, 0x71, irq_reg_0x70);
1922 if (irq_reg_0x6b)
1923 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1924
ff4f80fd
MR		 1925 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1926
54450f59 1927 /* format change */
f24d229c 1928 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1929 fmt_change_digital = is_digital_input(sd)
1930 ? irq_reg_0x6b & info->fmt_change_digital_mask
1931 : 0;
14d03233 1932
54450f59
HV		 1933 if (fmt_change || fmt_change_digital) {
1934 v4l2_dbg(1, debug, sd,
25a64ac9 1935 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1936 __func__, fmt_change, fmt_change_digital);
25a64ac9 1937
48519838
HV		 1938 v4l2_subdev_notify(sd, V4L2_DEVICE_NOTIFY_EVENT,
1939 (void *)&adv76xx_ev_fmt);
25a64ac9 1940
54450f59
HV		 1941 if (handled)
1942 *handled = true;
1943 }
f24d229c
MR		 1944 /* HDMI/DVI mode */
1945 if (irq_reg_0x6b & 0x01) {
1946 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1947 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1948 set_rgb_quantization_range(sd);
1949 if (handled)
1950 *handled = true;
1951 }
1952
54450f59 1953 /* tx 5v detect */
d42010a1 1954 tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
54450f59
HV		 1955 if (tx_5v) {
1956 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1957 io_write(sd, 0x71, tx_5v);
b44b2e06 1958 adv76xx_s_detect_tx_5v_ctrl(sd);
54450f59
HV		 1959 if (handled)
1960 *handled = true;
1961 }
1962 return 0;
1963}
1964
b44b2e06 1965static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1966{
b44b2e06 1967 struct adv76xx_state *state = to_state(sd);
4a31a93a 1968 u8 *data = NULL;
54450f59 1969
dd9ac11a 1970 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1971
1972 switch (edid->pad) {
b44b2e06 1973 case ADV76XX_PAD_HDMI_PORT_A:
c784b1e2
LP		 1974 case ADV7604_PAD_HDMI_PORT_B:
1975 case ADV7604_PAD_HDMI_PORT_C:
1976 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1977 if (state->edid.present & (1 << edid->pad))
1978 data = state->edid.edid;
1979 break;
1980 default:
1981 return -EINVAL;
4a31a93a 1982 }
dd9ac11a
HV		 1983
1984 if (edid->start_block == 0 && edid->blocks == 0) {
1985 edid->blocks = data ? state->edid.blocks : 0;
1986 return 0;
1987 }
1988
1989 if (data == NULL)
4a31a93a
MR		 1990 return -ENODATA;
1991
dd9ac11a
HV		 1992 if (edid->start_block >= state->edid.blocks)
1993 return -EINVAL;
1994
1995 if (edid->start_block + edid->blocks > state->edid.blocks)
1996 edid->blocks = state->edid.blocks - edid->start_block;
1997
1998 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1999
54450f59
HV		 2000 return 0;
2001}
2002
dd08beb9 2003static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 2004{
2005 u8 d;
2006
2007 if ((edid[0x7e] != 1) ||
2008 (edid[0x80] != 0x02) ||
2009 (edid[0x81] != 0x03)) {
2010 return -1;
2011 }
2012
2013 /* search Vendor Specific Data Block (tag 3) */
2014 d = edid[0x82] & 0x7f;
2015 if (d > 4) {
2016 int i = 0x84;
2017 int end = 0x80 + d;
2018
2019 do {
2020 u8 tag = edid[i] >> 5;
2021 u8 len = edid[i] & 0x1f;
2022
2023 if ((tag == 3) && (len >= 5))
2024 return i + 4;
2025 i += len + 1;
2026 } while (i < end);
2027 }
2028 return -1;
2029}
2030
b44b2e06 2031static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 2032{
b44b2e06
PA		 2033 struct adv76xx_state *state = to_state(sd);
2034 const struct adv76xx_chip_info *info = state->info;
dd08beb9 2035 int spa_loc;
54450f59 2036 int err;
dd08beb9 2037 int i;
54450f59 2038
dd9ac11a
HV		 2039 memset(edid->reserved, 0, sizeof(edid->reserved));
2040
c784b1e2 2041 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2042 return -EINVAL;
2043 if (edid->start_block != 0)
2044 return -EINVAL;
2045 if (edid->blocks == 0) {
3e86aa85 2046 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2047 state->edid.present &= ~(1 << edid->pad);
b44b2e06 2048 adv76xx_set_hpd(state, state->edid.present);
22d97e56 2049 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2050
54450f59
HV		 2051 /* Fall back to a 16:9 aspect ratio */
2052 state->aspect_ratio.numerator = 16;
2053 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2054
2055 if (!state->edid.present)
2056 state->edid.blocks = 0;
2057
2058 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2059 __func__, edid->pad, state->edid.present);
54450f59
HV		 2060 return 0;
2061 }
4a31a93a
MR		 2062 if (edid->blocks > 2) {
2063 edid->blocks = 2;
54450f59 2064 return -E2BIG;
4a31a93a 2065 }
4a31a93a 2066
dd08beb9
MR		 2067 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2068 __func__, edid->pad, state->edid.present);
2069
3e86aa85 2070 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2071 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
b44b2e06 2072 adv76xx_set_hpd(state, 0);
22d97e56 2073 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2074
dd08beb9
MR		 2075 spa_loc = get_edid_spa_location(edid->edid);
2076 if (spa_loc < 0)
2077 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2078
3e86aa85 2079 switch (edid->pad) {
b44b2e06 2080 case ADV76XX_PAD_HDMI_PORT_A:
dd08beb9
MR		 2081 state->spa_port_a[0] = edid->edid[spa_loc];
2082 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2083 break;
c784b1e2 2084 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2085 rep_write(sd, 0x70, edid->edid[spa_loc]);
2086 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2087 break;
c784b1e2 2088 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2089 rep_write(sd, 0x72, edid->edid[spa_loc]);
2090 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2091 break;
c784b1e2 2092 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2093 rep_write(sd, 0x74, edid->edid[spa_loc]);
2094 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2095 break;
dd08beb9
MR		 2096 default:
2097 return -EINVAL;
3e86aa85 2098 }
d42010a1
LPC		 2099
2100 if (info->type == ADV7604) {
2101 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2102 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1
LPC		 2103 } else {
2104 /* FIXME: Where is the SPA location LSB register ? */
22d97e56 2105 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2106 }
3e86aa85 2107
dd08beb9
MR		 2108 edid->edid[spa_loc] = state->spa_port_a[0];
2109 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2110
2111 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2112 state->edid.blocks = edid->blocks;
54450f59
HV		 2113 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2114 edid->edid[0x16]);
3e86aa85 2115 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2116
2117 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2118 if (err < 0) {
3e86aa85 2119 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2120 return err;
2121 }
2122
b44b2e06 2123 /* adv76xx calculates the checksums and enables I2C access to internal
dd08beb9 2124 EDID RAM from DDC port. */
22d97e56 2125 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2126
2127 for (i = 0; i < 1000; i++) {
d42010a1 2128 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2129 break;
2130 mdelay(1);
2131 }
2132 if (i == 1000) {
2133 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2134 return -EIO;
2135 }
2136
4a31a93a
MR		 2137 /* enable hotplug after 100 ms */
2138 queue_delayed_work(state->work_queues,
2139 &state->delayed_work_enable_hotplug, HZ / 10);
2140 return 0;
54450f59
HV		 2141}
2142
2143/*********** avi info frame CEA-861-E **************/
2144
516613c1
HV		 2145static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2146 { "AVI", 0x01, 0xe0, 0x00 },
2147 { "Audio", 0x02, 0xe3, 0x1c },
2148 { "SDP", 0x04, 0xe6, 0x2a },
2149 { "Vendor", 0x10, 0xec, 0x54 }
2150};
2151
2152static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2153 union hdmi_infoframe *frame)
54450f59 2154{
516613c1
HV		 2155 uint8_t buffer[32];
2156 u8 len;
54450f59 2157 int i;
54450f59 2158
516613c1
HV		 2159 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2160 v4l2_info(sd, "%s infoframe not received\n",
2161 adv76xx_cri[index].desc);
2162 return -ENOENT;
54450f59 2163 }
516613c1
HV		 2164
2165 for (i = 0; i < 3; i++)
2166 buffer[i] = infoframe_read(sd,
2167 adv76xx_cri[index].head_addr + i);
2168
2169 len = buffer[2] + 1;
2170
2171 if (len + 3 > sizeof(buffer)) {
2172 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2173 adv76xx_cri[index].desc, len);
2174 return -ENOENT;
54450f59
HV		 2175 }
2176
516613c1
HV		 2177 for (i = 0; i < len; i++)
2178 buffer[i + 3] = infoframe_read(sd,
2179 adv76xx_cri[index].payload_addr + i);
2180
2181 if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2182 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2183 adv76xx_cri[index].desc);
2184 return -ENOENT;
54450f59 2185 }
516613c1
HV		 2186 return 0;
2187}
54450f59 2188
516613c1
HV		 2189static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2190{
2191 int i;
54450f59 2192
516613c1
HV		 2193 if (!is_hdmi(sd)) {
2194 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
54450f59 2195 return;
516613c1 2196 }
54450f59 2197
516613c1
HV		 2198 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2199 union hdmi_infoframe frame;
2200 struct i2c_client *client = v4l2_get_subdevdata(sd);
54450f59 2201
516613c1
HV		 2202 if (adv76xx_read_infoframe(sd, i, &frame))
2203 return;
2204 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2205 }
54450f59
HV		 2206}
2207
b44b2e06 2208static int adv76xx_log_status(struct v4l2_subdev *sd)
54450f59 2209{
b44b2e06
PA		 2210 struct adv76xx_state *state = to_state(sd);
2211 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 2212 struct v4l2_dv_timings timings;
2213 struct stdi_readback stdi;
2214 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2215 u8 edid_enabled;
2216 u8 cable_det;
54450f59 2217
f216ccb3 2218 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2219 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2220 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2221 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2222 "reserved", "reserved", "reserved", "reserved", "manual"
2223 };
f216ccb3 2224 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2225 "RGB limited range (16-235)", "RGB full range (0-255)",
2226 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2227 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2228 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2229 "invalid", "invalid", "invalid", "invalid", "invalid",
2230 "invalid", "invalid", "automatic"
2231 };
7a5d99e7
HV		 2232 static const char * const hdmi_color_space_txt[16] = {
2233 "RGB limited range (16-235)", "RGB full range (0-255)",
2234 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2235 "xvYCC Bt.601", "xvYCC Bt.709",
2236 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2237 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2238 "invalid", "invalid", "invalid"
2239 };
f216ccb3 2240 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2241 "Automatic",
2242 "RGB limited range (16-235)",
2243 "RGB full range (0-255)",
2244 };
f216ccb3 2245 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2246 "8-bits per channel",
2247 "10-bits per channel",
2248 "12-bits per channel",
2249 "16-bits per channel (not supported)"
2250 };
54450f59
HV		 2251
2252 v4l2_info(sd, "-----Chip status-----\n");
2253 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2254 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2255 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2256 ((edid_enabled & 0x01) ? "Yes" : "No"),
2257 ((edid_enabled & 0x02) ? "Yes" : "No"),
2258 ((edid_enabled & 0x04) ? "Yes" : "No"),
2259 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2260 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2261 "enabled" : "disabled");
2262
2263 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2264 cable_det = info->read_cable_det(sd);
4a31a93a 2265 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2266 ((cable_det & 0x01) ? "Yes" : "No"),
2267 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2268 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2269 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2270 v4l2_info(sd, "TMDS signal detected: %s\n",
2271 no_signal_tmds(sd) ? "false" : "true");
2272 v4l2_info(sd, "TMDS signal locked: %s\n",
2273 no_lock_tmds(sd) ? "false" : "true");
2274 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2275 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2276 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2277 v4l2_info(sd, "CP free run: %s\n",
58514625 2278 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2279 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2280 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2281 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2282
2283 v4l2_info(sd, "-----Video Timings-----\n");
2284 if (read_stdi(sd, &stdi))
2285 v4l2_info(sd, "STDI: not locked\n");
2286 else
2287 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2288 stdi.lcf, stdi.bl, stdi.lcvs,
2289 stdi.interlaced ? "interlaced" : "progressive",
2290 stdi.hs_pol, stdi.vs_pol);
b44b2e06 2291 if (adv76xx_query_dv_timings(sd, &timings))
54450f59
HV		 2292 v4l2_info(sd, "No video detected\n");
2293 else
11d034c8
HV		 2294 v4l2_print_dv_timings(sd->name, "Detected format: ",
2295 &timings, true);
2296 v4l2_print_dv_timings(sd->name, "Configured format: ",
2297 &state->timings, true);
54450f59 2298
76eb2d30
MR		 2299 if (no_signal(sd))
2300 return 0;
2301
54450f59
HV		 2302 v4l2_info(sd, "-----Color space-----\n");
2303 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2304 rgb_quantization_range_txt[state->rgb_quantization_range]);
2305 v4l2_info(sd, "Input color space: %s\n",
2306 input_color_space_txt[reg_io_0x02 >> 4]);
7a5d99e7 2307 v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n",
54450f59
HV		 2308 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2309 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
5dd7d88a 2310 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
7a5d99e7
HV		 2311 "enabled" : "disabled",
2312 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
54450f59 2313 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2314 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2315
4a31a93a 2316 if (!is_digital_input(sd))
76eb2d30
MR		 2317 return 0;
2318
2319 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2320 v4l2_info(sd, "Digital video port selected: %c\n",
2321 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2322 v4l2_info(sd, "HDCP encrypted content: %s\n",
2323 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2324 v4l2_info(sd, "HDCP keys read: %s%s\n",
2325 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2326 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2327 if (is_hdmi(sd)) {
76eb2d30
MR		 2328 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2329 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2330 bool audio_mute = io_read(sd, 0x65) & 0x40;
2331
2332 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2333 audio_pll_locked ? "locked" : "not locked",
2334 audio_sample_packet_detect ? "detected" : "not detected",
2335 audio_mute ? "muted" : "enabled");
2336 if (audio_pll_locked && audio_sample_packet_detect) {
2337 v4l2_info(sd, "Audio format: %s\n",
2338 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2339 }
2340 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2341 (hdmi_read(sd, 0x5c) << 8) +
2342 (hdmi_read(sd, 0x5d) & 0xf0));
2343 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2344 (hdmi_read(sd, 0x5e) << 8) +
2345 hdmi_read(sd, 0x5f));
2346 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2347
2348 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
7a5d99e7 2349 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
76eb2d30 2350
516613c1 2351 adv76xx_log_infoframes(sd);
54450f59
HV		 2352 }
2353
2354 return 0;
2355}
2356
2357/* ----------------------------------------------------------------------- */
2358
b44b2e06
PA		 2359static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2360 .s_ctrl = adv76xx_s_ctrl,
54450f59
HV		 2361};
2362
b44b2e06
PA		 2363static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2364 .log_status = adv76xx_log_status,
2365 .interrupt_service_routine = adv76xx_isr,
0975626d
LPC		 2366 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
2367 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
54450f59 2368#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06
PA		 2369 .g_register = adv76xx_g_register,
2370 .s_register = adv76xx_s_register,
54450f59
HV		 2371#endif
2372};
2373
b44b2e06
PA		 2374static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2375 .s_routing = adv76xx_s_routing,
2376 .g_input_status = adv76xx_g_input_status,
2377 .s_dv_timings = adv76xx_s_dv_timings,
2378 .g_dv_timings = adv76xx_g_dv_timings,
2379 .query_dv_timings = adv76xx_query_dv_timings,
54450f59
HV		 2380};
2381
b44b2e06
PA		 2382static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2383 .enum_mbus_code = adv76xx_enum_mbus_code,
2384 .get_fmt = adv76xx_get_format,
2385 .set_fmt = adv76xx_set_format,
2386 .get_edid = adv76xx_get_edid,
2387 .set_edid = adv76xx_set_edid,
2388 .dv_timings_cap = adv76xx_dv_timings_cap,
2389 .enum_dv_timings = adv76xx_enum_dv_timings,
54450f59
HV		 2390};
2391
b44b2e06
PA		 2392static const struct v4l2_subdev_ops adv76xx_ops = {
2393 .core = &adv76xx_core_ops,
2394 .video = &adv76xx_video_ops,
2395 .pad = &adv76xx_pad_ops,
54450f59
HV		 2396};
2397
2398/* -------------------------- custom ctrls ---------------------------------- */
2399
2400static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
b44b2e06 2401 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2402 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2403 .name = "Analog Sampling Phase",
2404 .type = V4L2_CTRL_TYPE_INTEGER,
2405 .min = 0,
2406 .max = 0x1f,
2407 .step = 1,
2408 .def = 0,
2409};
2410
b44b2e06
PA		 2411static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2412 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2413 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2414 .name = "Free Running Color, Manual",
2415 .type = V4L2_CTRL_TYPE_BOOLEAN,
2416 .min = false,
2417 .max = true,
2418 .step = 1,
2419 .def = false,
2420};
2421
b44b2e06
PA		 2422static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2423 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2424 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2425 .name = "Free Running Color",
2426 .type = V4L2_CTRL_TYPE_INTEGER,
2427 .min = 0x0,
2428 .max = 0xffffff,
2429 .step = 0x1,
2430 .def = 0x0,
2431};
2432
2433/* ----------------------------------------------------------------------- */
2434
b44b2e06 2435static int adv76xx_core_init(struct v4l2_subdev *sd)
54450f59 2436{
b44b2e06
PA		 2437 struct adv76xx_state *state = to_state(sd);
2438 const struct adv76xx_chip_info *info = state->info;
2439 struct adv76xx_platform_data *pdata = &state->pdata;
54450f59
HV		 2440
2441 hdmi_write(sd, 0x48,
2442 (pdata->disable_pwrdnb ? 0x80 : 0) |
2443 (pdata->disable_cable_det_rst ? 0x40 : 0));
2444
2445 disable_input(sd);
2446
5ef54b59
LP		 2447 if (pdata->default_input >= 0 &&
2448 pdata->default_input < state->source_pad) {
2449 state->selected_input = pdata->default_input;
2450 select_input(sd);
2451 enable_input(sd);
2452 }
2453
54450f59
HV		 2454 /* power */
2455 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2456 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2457 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2458
2459 /* video format */
22d97e56 2460 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2461 pdata->alt_gamma << 3 |
2462 pdata->op_656_range << 2 |
54450f59 2463 pdata->alt_data_sat << 0);
22d97e56 2464 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2465 pdata->insert_av_codes << 2 |
2466 pdata->replicate_av_codes << 1);
b44b2e06 2467 adv76xx_setup_format(state);
54450f59 2468
54450f59 2469 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2470
2471 /* VS, HS polarities */
1b5ab875
LP		 2472 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2473 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2474
2475 /* Adjust drive strength */
2476 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2477 pdata->dr_str_clk << 2 |
2478 pdata->dr_str_sync);
2479
54450f59
HV		 2480 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2481 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2482 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2483 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2484 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2485 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2486 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2487 for digital formats */
2488
5474b983 2489 /* HDMI audio */
22d97e56
LP		 2490 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2491 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2492 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2493
54450f59
HV		 2494 /* TODO from platform data */
2495 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2496
b44b2e06 2497 if (adv76xx_has_afe(state)) {
d42010a1 2498 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2499 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2500 }
54450f59 2501
54450f59 2502 /* interrupts */
d42010a1 2503 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2504 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2505 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2506 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2507 info->setup_irqs(sd);
54450f59
HV		 2508
2509 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2510}
2511
d42010a1
LPC		 2512static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2513{
2514 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2515}
2516
2517static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2518{
2519 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2520}
2521
8331d30b
WT		 2522static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2523{
2524 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2525}
2526
b44b2e06 2527static void adv76xx_unregister_clients(struct adv76xx_state *state)
54450f59 2528{
05cacb17
LP		 2529 unsigned int i;
2530
2531 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2532 if (state->i2c_clients[i])
2533 i2c_unregister_device(state->i2c_clients[i]);
2534 }
54450f59
HV		 2535}
2536
b44b2e06 2537static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
54450f59
HV		 2538 u8 addr, u8 io_reg)
2539{
2540 struct i2c_client *client = v4l2_get_subdevdata(sd);
2541
2542 if (addr)
2543 io_write(sd, io_reg, addr << 1);
2544 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2545}
2546
b44b2e06 2547static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
d42010a1
LPC		 2548 /* reset ADI recommended settings for HDMI: */
2549 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2550 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2551 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2552 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2553 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2554 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2555 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2556 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2557 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2558 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2559 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2560 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2561 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
d42010a1
LPC		 2562
2563 /* set ADI recommended settings for digitizer */
2564 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2565 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2566 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2567 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2568 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2569 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
d42010a1 2570
b44b2e06 2571 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2572};
2573
b44b2e06 2574static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
d42010a1
LPC		 2575 /* set ADI recommended settings for HDMI: */
2576 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2577 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2578 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2579 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2580 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2581 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2582 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2583 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2584 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2585 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2586 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2587 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
d42010a1
LPC		 2588
2589 /* reset ADI recommended settings for digitizer */
2590 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2591 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2592 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
d42010a1 2593
b44b2e06 2594 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2595};
2596
b44b2e06 2597static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2598 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
b44b2e06
PA		 2599 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2600 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2601 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2602 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2603 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2604 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2605 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2606 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2607 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2608 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2609 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2610
2611 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2612};
2613
8331d30b
WT		 2614static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2615 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2616 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2617 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2618 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2619 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2620 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2621 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2622 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2623 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2624 { ADV76XX_REG_SEQ_TERM, 0 },
2625};
2626
b44b2e06 2627static const struct adv76xx_chip_info adv76xx_chip_info[] = {
d42010a1
LPC		 2628 [ADV7604] = {
2629 .type = ADV7604,
2630 .has_afe = true,
c784b1e2 2631 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2632 .num_dv_ports = 4,
2633 .edid_enable_reg = 0x77,
2634 .edid_status_reg = 0x7d,
2635 .lcf_reg = 0xb3,
2636 .tdms_lock_mask = 0xe0,
2637 .cable_det_mask = 0x1e,
2638 .fmt_change_digital_mask = 0xc1,
80f4944e 2639 .cp_csc = 0xfc,
539b33b0
LP		 2640 .formats = adv7604_formats,
2641 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2642 .set_termination = adv7604_set_termination,
2643 .setup_irqs = adv7604_setup_irqs,
2644 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2645 .read_cable_det = adv7604_read_cable_det,
2646 .recommended_settings = {
2647 [0] = adv7604_recommended_settings_afe,
2648 [1] = adv7604_recommended_settings_hdmi,
2649 },
2650 .num_recommended_settings = {
2651 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2652 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2653 },
b44b2e06
PA		 2654 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2655 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
d42010a1 2656 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
b44b2e06
PA		 2657 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2658 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2659 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
d42010a1 2660 BIT(ADV7604_PAGE_VDP),
5380baaf 2661 .linewidth_mask = 0xfff,
2662 .field0_height_mask = 0xfff,
2663 .field1_height_mask = 0xfff,
2664 .hfrontporch_mask = 0x3ff,
2665 .hsync_mask = 0x3ff,
2666 .hbackporch_mask = 0x3ff,
2667 .field0_vfrontporch_mask = 0x1fff,
2668 .field0_vsync_mask = 0x1fff,
2669 .field0_vbackporch_mask = 0x1fff,
2670 .field1_vfrontporch_mask = 0x1fff,
2671 .field1_vsync_mask = 0x1fff,
2672 .field1_vbackporch_mask = 0x1fff,
d42010a1
LPC		 2673 },
2674 [ADV7611] = {
2675 .type = ADV7611,
2676 .has_afe = false,
b44b2e06 2677 .max_port = ADV76XX_PAD_HDMI_PORT_A,
d42010a1
LPC		 2678 .num_dv_ports = 1,
2679 .edid_enable_reg = 0x74,
2680 .edid_status_reg = 0x76,
2681 .lcf_reg = 0xa3,
2682 .tdms_lock_mask = 0x43,
2683 .cable_det_mask = 0x01,
2684 .fmt_change_digital_mask = 0x03,
80f4944e 2685 .cp_csc = 0xf4,
539b33b0
LP		 2686 .formats = adv7611_formats,
2687 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2688 .set_termination = adv7611_set_termination,
2689 .setup_irqs = adv7611_setup_irqs,
2690 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2691 .read_cable_det = adv7611_read_cable_det,
2692 .recommended_settings = {
2693 [1] = adv7611_recommended_settings_hdmi,
2694 },
2695 .num_recommended_settings = {
2696 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2697 },
b44b2e06
PA		 2698 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2699 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2700 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2701 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
5380baaf 2702 .linewidth_mask = 0x1fff,
2703 .field0_height_mask = 0x1fff,
2704 .field1_height_mask = 0x1fff,
2705 .hfrontporch_mask = 0x1fff,
2706 .hsync_mask = 0x1fff,
2707 .hbackporch_mask = 0x1fff,
2708 .field0_vfrontporch_mask = 0x3fff,
2709 .field0_vsync_mask = 0x3fff,
2710 .field0_vbackporch_mask = 0x3fff,
2711 .field1_vfrontporch_mask = 0x3fff,
2712 .field1_vsync_mask = 0x3fff,
2713 .field1_vbackporch_mask = 0x3fff,
d42010a1 2714 },
8331d30b
WT		 2715 [ADV7612] = {
2716 .type = ADV7612,
2717 .has_afe = false,
2718 .max_port = ADV7604_PAD_HDMI_PORT_B,
2719 .num_dv_ports = 2,
2720 .edid_enable_reg = 0x74,
2721 .edid_status_reg = 0x76,
2722 .lcf_reg = 0xa3,
2723 .tdms_lock_mask = 0x43,
2724 .cable_det_mask = 0x01,
2725 .fmt_change_digital_mask = 0x03,
2726 .formats = adv7612_formats,
2727 .nformats = ARRAY_SIZE(adv7612_formats),
2728 .set_termination = adv7611_set_termination,
2729 .setup_irqs = adv7612_setup_irqs,
2730 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2731 .read_cable_det = adv7611_read_cable_det,
2732 .recommended_settings = {
2733 [1] = adv7612_recommended_settings_hdmi,
2734 },
2735 .num_recommended_settings = {
2736 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
2737 },
2738 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2739 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2740 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2741 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2742 .linewidth_mask = 0x1fff,
2743 .field0_height_mask = 0x1fff,
2744 .field1_height_mask = 0x1fff,
2745 .hfrontporch_mask = 0x1fff,
2746 .hsync_mask = 0x1fff,
2747 .hbackporch_mask = 0x1fff,
2748 .field0_vfrontporch_mask = 0x3fff,
2749 .field0_vsync_mask = 0x3fff,
2750 .field0_vbackporch_mask = 0x3fff,
2751 .field1_vfrontporch_mask = 0x3fff,
2752 .field1_vsync_mask = 0x3fff,
2753 .field1_vbackporch_mask = 0x3fff,
2754 },
d42010a1
LPC		 2755};
2756
7f099a75 2757static const struct i2c_device_id adv76xx_i2c_id[] = {
b44b2e06
PA		 2758 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2759 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
8331d30b 2760 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2761 { }
2762};
b44b2e06 2763MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
f82f313e 2764
7f099a75 2765static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
b44b2e06 2766 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
8331d30b 2767 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2768 { }
2769};
b44b2e06 2770MODULE_DEVICE_TABLE(of, adv76xx_of_id);
f82f313e 2771
b44b2e06 2772static int adv76xx_parse_dt(struct adv76xx_state *state)
f82f313e 2773{
6fa88045
LP		 2774 struct v4l2_of_endpoint bus_cfg;
2775 struct device_node *endpoint;
2776 struct device_node *np;
2777 unsigned int flags;
bf9c8227 2778 u32 v;
6fa88045 2779
b44b2e06 2780 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
6fa88045
LP		 2781
2782 /* Parse the endpoint. */
2783 endpoint = of_graph_get_next_endpoint(np, NULL);
2784 if (!endpoint)
2785 return -EINVAL;
2786
2787 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
bf9c8227
IM		 2788
2789 if (!of_property_read_u32(endpoint, "default-input", &v))
2790 state->pdata.default_input = v;
2791 else
2792 state->pdata.default_input = -1;
2793
6fa88045
LP		 2794 of_node_put(endpoint);
2795
2796 flags = bus_cfg.bus.parallel.flags;
2797
2798 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2799 state->pdata.inv_hs_pol = 1;
2800
2801 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2802 state->pdata.inv_vs_pol = 1;
2803
2804 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2805 state->pdata.inv_llc_pol = 1;
2806
2807 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2808 state->pdata.insert_av_codes = 1;
2809 state->pdata.op_656_range = 1;
2810 }
2811
f82f313e 2812 /* Disable the interrupt for now as no DT-based board uses it. */
b44b2e06 2813 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
f82f313e
LP		 2814
2815 /* Use the default I2C addresses. */
2816 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
b44b2e06
PA		 2817 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2818 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
f82f313e
LP		 2819 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2820 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
b44b2e06
PA		 2821 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2822 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2823 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2824 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2825 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2826 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
f82f313e
LP		 2827 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2828
2829 /* Hardcode the remaining platform data fields. */
2830 state->pdata.disable_pwrdnb = 0;
2831 state->pdata.disable_cable_det_rst = 0;
f82f313e 2832 state->pdata.blank_data = 1;
f82f313e 2833 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2834 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2835 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2836
2837 return 0;
2838}
2839
f862f57d
PA		 2840static const struct regmap_config adv76xx_regmap_cnf[] = {
2841 {
2842 .name = "io",
2843 .reg_bits = 8,
2844 .val_bits = 8,
2845
2846 .max_register = 0xff,
2847 .cache_type = REGCACHE_NONE,
2848 },
2849 {
2850 .name = "avlink",
2851 .reg_bits = 8,
2852 .val_bits = 8,
2853
2854 .max_register = 0xff,
2855 .cache_type = REGCACHE_NONE,
2856 },
2857 {
2858 .name = "cec",
2859 .reg_bits = 8,
2860 .val_bits = 8,
2861
2862 .max_register = 0xff,
2863 .cache_type = REGCACHE_NONE,
2864 },
2865 {
2866 .name = "infoframe",
2867 .reg_bits = 8,
2868 .val_bits = 8,
2869
2870 .max_register = 0xff,
2871 .cache_type = REGCACHE_NONE,
2872 },
2873 {
2874 .name = "esdp",
2875 .reg_bits = 8,
2876 .val_bits = 8,
2877
2878 .max_register = 0xff,
2879 .cache_type = REGCACHE_NONE,
2880 },
2881 {
2882 .name = "epp",
2883 .reg_bits = 8,
2884 .val_bits = 8,
2885
2886 .max_register = 0xff,
2887 .cache_type = REGCACHE_NONE,
2888 },
2889 {
2890 .name = "afe",
2891 .reg_bits = 8,
2892 .val_bits = 8,
2893
2894 .max_register = 0xff,
2895 .cache_type = REGCACHE_NONE,
2896 },
2897 {
2898 .name = "rep",
2899 .reg_bits = 8,
2900 .val_bits = 8,
2901
2902 .max_register = 0xff,
2903 .cache_type = REGCACHE_NONE,
2904 },
2905 {
2906 .name = "edid",
2907 .reg_bits = 8,
2908 .val_bits = 8,
2909
2910 .max_register = 0xff,
2911 .cache_type = REGCACHE_NONE,
2912 },
2913
2914 {
2915 .name = "hdmi",
2916 .reg_bits = 8,
2917 .val_bits = 8,
2918
2919 .max_register = 0xff,
2920 .cache_type = REGCACHE_NONE,
2921 },
2922 {
2923 .name = "test",
2924 .reg_bits = 8,
2925 .val_bits = 8,
2926
2927 .max_register = 0xff,
2928 .cache_type = REGCACHE_NONE,
2929 },
2930 {
2931 .name = "cp",
2932 .reg_bits = 8,
2933 .val_bits = 8,
2934
2935 .max_register = 0xff,
2936 .cache_type = REGCACHE_NONE,
2937 },
2938 {
2939 .name = "vdp",
2940 .reg_bits = 8,
2941 .val_bits = 8,
2942
2943 .max_register = 0xff,
2944 .cache_type = REGCACHE_NONE,
2945 },
2946};
2947
2948static int configure_regmap(struct adv76xx_state *state, int region)
2949{
2950 int err;
2951
2952 if (!state->i2c_clients[region])
2953 return -ENODEV;
2954
2955 state->regmap[region] =
2956 devm_regmap_init_i2c(state->i2c_clients[region],
2957 &adv76xx_regmap_cnf[region]);
2958
2959 if (IS_ERR(state->regmap[region])) {
2960 err = PTR_ERR(state->regmap[region]);
2961 v4l_err(state->i2c_clients[region],
2962 "Error initializing regmap %d with error %d\n",
2963 region, err);
2964 return -EINVAL;
2965 }
2966
2967 return 0;
2968}
2969
2970static int configure_regmaps(struct adv76xx_state *state)
2971{
2972 int i, err;
2973
2974 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
2975 err = configure_regmap(state, i);
2976 if (err && (err != -ENODEV))
2977 return err;
2978 }
2979 return 0;
2980}
2981
b44b2e06 2982static int adv76xx_probe(struct i2c_client *client,
54450f59
HV		 2983 const struct i2c_device_id *id)
2984{
591b72fe
HV		 2985 static const struct v4l2_dv_timings cea640x480 =
2986 V4L2_DV_BT_CEA_640X480P59_94;
b44b2e06 2987 struct adv76xx_state *state;
54450f59
HV		 2988 struct v4l2_ctrl_handler *hdl;
2989 struct v4l2_subdev *sd;
c784b1e2 2990 unsigned int i;
f862f57d 2991 unsigned int val, val2;
54450f59
HV		 2992 int err;
2993
2994 /* Check if the adapter supports the needed features */
2995 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2996 return -EIO;
b44b2e06 2997 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
54450f59
HV		 2998 client->addr << 1);
2999
c02b211d 3000 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59 3001 if (!state) {
b44b2e06 3002 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
54450f59
HV		 3003 return -ENOMEM;
3004 }
3005
b44b2e06 3006 state->i2c_clients[ADV76XX_PAGE_IO] = client;
d42010a1 3007
25a64ac9
MR		 3008 /* initialize variables */
3009 state->restart_stdi_once = true;
ff4f80fd 3010 state->selected_input = ~0;
25a64ac9 3011
f82f313e
LP		 3012 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3013 const struct of_device_id *oid;
3014
b44b2e06 3015 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
f82f313e
LP		 3016 state->info = oid->data;
3017
b44b2e06 3018 err = adv76xx_parse_dt(state);
f82f313e
LP		 3019 if (err < 0) {
3020 v4l_err(client, "DT parsing error\n");
3021 return err;
3022 }
3023 } else if (client->dev.platform_data) {
b44b2e06 3024 struct adv76xx_platform_data *pdata = client->dev.platform_data;
f82f313e 3025
b44b2e06 3026 state->info = (const struct adv76xx_chip_info *)id->driver_data;
f82f313e
LP		 3027 state->pdata = *pdata;
3028 } else {
54450f59 3029 v4l_err(client, "No platform data!\n");
c02b211d 3030 return -ENODEV;
54450f59 3031 }
e9d50e9e
LP		 3032
3033 /* Request GPIOs. */
3034 for (i = 0; i < state->info->num_dv_ports; ++i) {
3035 state->hpd_gpio[i] =
269bd132
UKK		 3036 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3037 GPIOD_OUT_LOW);
e9d50e9e 3038 if (IS_ERR(state->hpd_gpio[i]))
269bd132 3039 return PTR_ERR(state->hpd_gpio[i]);
e9d50e9e 3040
269bd132
UKK		 3041 if (state->hpd_gpio[i])
3042 v4l_info(client, "Handling HPD %u GPIO\n", i);
e9d50e9e
LP		 3043 }
3044
591b72fe 3045 state->timings = cea640x480;
b44b2e06 3046 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 3047
3048 sd = &state->sd;
b44b2e06 3049 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
d42010a1
LPC		 3050 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3051 id->name, i2c_adapter_id(client->adapter),
3052 client->addr);
0975626d 3053 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
54450f59 3054
f862f57d
PA		 3055 /* Configure IO Regmap region */
3056 err = configure_regmap(state, ADV76XX_PAGE_IO);
3057
3058 if (err) {
3059 v4l2_err(sd, "Error configuring IO regmap region\n");
3060 return -ENODEV;
3061 }
3062
d42010a1
LPC		 3063 /*
3064 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3065 * identifies the revision, while on ADV7611 it identifies the model as
3066 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3067 */
8331d30b
WT		 3068 switch (state->info->type) {
3069 case ADV7604:
f862f57d
PA		 3070 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3071 if (err) {
3072 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3073 return -ENODEV;
3074 }
d42010a1 3075 if (val != 0x68) {
f862f57d 3076 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
d42010a1
LPC		 3077 client->addr << 1);
3078 return -ENODEV;
3079 }
8331d30b
WT		 3080 break;
3081 case ADV7611:
3082 case ADV7612:
f862f57d
PA		 3083 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3084 0xea,
3085 &val);
3086 if (err) {
3087 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3088 return -ENODEV;
3089 }
3090 val2 = val << 8;
3091 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3092 0xeb,
3093 &val);
3094 if (err) {
3095 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3096 return -ENODEV;
3097 }
3098 val2 |= val;
8331d30b
WT		 3099 if ((state->info->type == ADV7611 && val != 0x2051) ||
3100 (state->info->type == ADV7612 && val != 0x2041)) {
3101 v4l2_err(sd, "not an adv761x on address 0x%x\n",
d42010a1
LPC		 3102 client->addr << 1);
3103 return -ENODEV;
3104 }
8331d30b 3105 break;
54450f59
HV		 3106 }
3107
3108 /* control handlers */
3109 hdl = &state->hdl;
b44b2e06 3110 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
54450f59 3111
b44b2e06 3112 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3113 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
b44b2e06 3114 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3115 V4L2_CID_CONTRAST, 0, 255, 1, 128);
b44b2e06 3116 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3117 V4L2_CID_SATURATION, 0, 255, 1, 128);
b44b2e06 3118 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 3119 V4L2_CID_HUE, 0, 128, 1, 0);
3120
3121 /* private controls */
3122 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 3123 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3124 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59 3125 state->rgb_quantization_range_ctrl =
b44b2e06 3126 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 3127 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3128 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 3129
3130 /* custom controls */
b44b2e06 3131 if (adv76xx_has_afe(state))
d42010a1
LPC		 3132 state->analog_sampling_phase_ctrl =
3133 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59 3134 state->free_run_color_manual_ctrl =
b44b2e06 3135 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
54450f59 3136 state->free_run_color_ctrl =
b44b2e06 3137 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
54450f59
HV		 3138
3139 sd->ctrl_handler = hdl;
3140 if (hdl->error) {
3141 err = hdl->error;
3142 goto err_hdl;
3143 }
8c0eadb8
HV		 3144 state->detect_tx_5v_ctrl->is_private = true;
3145 state->rgb_quantization_range_ctrl->is_private = true;
b44b2e06 3146 if (adv76xx_has_afe(state))
d42010a1 3147 state->analog_sampling_phase_ctrl->is_private = true;
8c0eadb8
HV		 3148 state->free_run_color_manual_ctrl->is_private = true;
3149 state->free_run_color_ctrl->is_private = true;
3150
b44b2e06 3151 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
54450f59
HV		 3152 err = -ENODEV;
3153 goto err_hdl;
3154 }
3155
b44b2e06 3156 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
05cacb17
LP		 3157 if (!(BIT(i) & state->info->page_mask))
3158 continue;
54450f59 3159
05cacb17 3160 state->i2c_clients[i] =
b44b2e06 3161 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 3162 0xf2 + i);
3163 if (state->i2c_clients[i] == NULL) {
d42010a1 3164 err = -ENOMEM;
05cacb17 3165 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 3166 goto err_i2c;
3167 }
3168 }
05cacb17 3169
54450f59
HV		 3170 /* work queues */
3171 state->work_queues = create_singlethread_workqueue(client->name);
3172 if (!state->work_queues) {
3173 v4l2_err(sd, "Could not create work queue\n");
3174 err = -ENOMEM;
3175 goto err_i2c;
3176 }
3177
3178 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
b44b2e06 3179 adv76xx_delayed_work_enable_hotplug);
54450f59 3180
c784b1e2
LP		 3181 state->source_pad = state->info->num_dv_ports
3182 + (state->info->has_afe ? 2 : 0);
3183 for (i = 0; i < state->source_pad; ++i)
3184 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3185 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3186
3187 err = media_entity_init(&sd->entity, state->source_pad + 1,
3188 state->pads, 0);
54450f59
HV		 3189 if (err)
3190 goto err_work_queues;
3191
f862f57d
PA		 3192 /* Configure regmaps */
3193 err = configure_regmaps(state);
3194 if (err)
3195 goto err_entity;
3196
b44b2e06 3197 err = adv76xx_core_init(sd);
54450f59
HV		 3198 if (err)
3199 goto err_entity;
3200 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3201 client->addr << 1, client->adapter->name);
bedc3939
LPC		 3202
3203 err = v4l2_async_register_subdev(sd);
3204 if (err)
3205 goto err_entity;
3206
54450f59
HV		 3207 return 0;
3208
3209err_entity:
3210 media_entity_cleanup(&sd->entity);
3211err_work_queues:
3212 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3213 destroy_workqueue(state->work_queues);
3214err_i2c:
b44b2e06 3215 adv76xx_unregister_clients(state);
54450f59
HV		 3216err_hdl:
3217 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 3218 return err;
3219}
3220
3221/* ----------------------------------------------------------------------- */
3222
b44b2e06 3223static int adv76xx_remove(struct i2c_client *client)
54450f59
HV		 3224{
3225 struct v4l2_subdev *sd = i2c_get_clientdata(client);
b44b2e06 3226 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 3227
3228 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3229 destroy_workqueue(state->work_queues);
bedc3939 3230 v4l2_async_unregister_subdev(sd);
54450f59 3231 media_entity_cleanup(&sd->entity);
b44b2e06 3232 adv76xx_unregister_clients(to_state(sd));
54450f59 3233 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 3234 return 0;
3235}
3236
3237/* ----------------------------------------------------------------------- */
3238
b44b2e06 3239static struct i2c_driver adv76xx_driver = {
54450f59
HV		 3240 .driver = {
3241 .owner = THIS_MODULE,
3242 .name = "adv7604",
b44b2e06 3243 .of_match_table = of_match_ptr(adv76xx_of_id),
54450f59 3244 },
b44b2e06
PA		 3245 .probe = adv76xx_probe,
3246 .remove = adv76xx_remove,
3247 .id_table = adv76xx_i2c_id,
54450f59
HV		 3248};
3249
b44b2e06 3250module_i2c_driver(adv76xx_driver);
Linux kernel - Deliverables
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