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[media] DocBook media: document the new V4L2_DV_FL_IS_CE_VIDEO flag
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
c72a53ce 32#include <linux/i2c.h>
54450f59
HV		 33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/slab.h>
c72a53ce 36#include <linux/v4l2-dv-timings.h>
54450f59
HV		 37#include <linux/videodev2.h>
38#include <linux/workqueue.h>
c72a53ce
LP		 39
40#include <media/adv7604.h>
54450f59 41#include <media/v4l2-ctrls.h>
c72a53ce 42#include <media/v4l2-device.h>
25764158 43#include <media/v4l2-dv-timings.h>
6fa88045 44#include <media/v4l2-of.h>
54450f59
HV		 45
46static int debug;
47module_param(debug, int, 0644);
48MODULE_PARM_DESC(debug, "debug level (0-2)");
49
50MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
51MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
52MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
53MODULE_LICENSE("GPL");
54
55/* ADV7604 system clock frequency */
b44b2e06 56#define ADV76XX_FSC (28636360)
54450f59 57
b44b2e06 58#define ADV76XX_RGB_OUT (1 << 1)
539b33b0 59
b44b2e06 60#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
539b33b0 61#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
b44b2e06 62#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
539b33b0 63
b44b2e06 64#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
539b33b0 65#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
b44b2e06 66#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
539b33b0 67#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
b44b2e06 68#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
539b33b0
LP		 69#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
70
b44b2e06
PA		 71#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
72#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
73#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
74#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
75#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
76#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
539b33b0 77
b44b2e06 78#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
539b33b0 79
b44b2e06 80enum adv76xx_type {
d42010a1
LPC		 81 ADV7604,
82 ADV7611,
83};
84
b44b2e06 85struct adv76xx_reg_seq {
d42010a1
LPC		 86 unsigned int reg;
87 u8 val;
88};
89
b44b2e06 90struct adv76xx_format_info {
f5fe58fd 91 u32 code;
539b33b0
LP		 92 u8 op_ch_sel;
93 bool rgb_out;
94 bool swap_cb_cr;
95 u8 op_format_sel;
96};
97
b44b2e06
PA		 98struct adv76xx_chip_info {
99 enum adv76xx_type type;
d42010a1
LPC		 100
101 bool has_afe;
102 unsigned int max_port;
103 unsigned int num_dv_ports;
104
105 unsigned int edid_enable_reg;
106 unsigned int edid_status_reg;
107 unsigned int lcf_reg;
108
109 unsigned int cable_det_mask;
110 unsigned int tdms_lock_mask;
111 unsigned int fmt_change_digital_mask;
80f4944e 112 unsigned int cp_csc;
d42010a1 113
b44b2e06 114 const struct adv76xx_format_info *formats;
539b33b0
LP		 115 unsigned int nformats;
116
d42010a1
LPC		 117 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
118 void (*setup_irqs)(struct v4l2_subdev *sd);
119 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
120 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
121
122 /* 0 = AFE, 1 = HDMI */
b44b2e06 123 const struct adv76xx_reg_seq *recommended_settings[2];
d42010a1
LPC		 124 unsigned int num_recommended_settings[2];
125
126 unsigned long page_mask;
127};
128
54450f59
HV		 129/*
130 **********************************************************************
131 *
132 * Arrays with configuration parameters for the ADV7604
133 *
134 **********************************************************************
135 */
c784b1e2 136
b44b2e06
PA		 137struct adv76xx_state {
138 const struct adv76xx_chip_info *info;
139 struct adv76xx_platform_data pdata;
539b33b0 140
e9d50e9e
LP		 141 struct gpio_desc *hpd_gpio[4];
142
54450f59 143 struct v4l2_subdev sd;
b44b2e06 144 struct media_pad pads[ADV76XX_PAD_MAX];
c784b1e2 145 unsigned int source_pad;
539b33b0 146
54450f59 147 struct v4l2_ctrl_handler hdl;
539b33b0 148
b44b2e06 149 enum adv76xx_pad selected_input;
539b33b0 150
54450f59 151 struct v4l2_dv_timings timings;
b44b2e06 152 const struct adv76xx_format_info *format;
539b33b0 153
4a31a93a
MR		 154 struct {
155 u8 edid[256];
156 u32 present;
157 unsigned blocks;
158 } edid;
dd08beb9 159 u16 spa_port_a[2];
54450f59
HV		 160 struct v4l2_fract aspect_ratio;
161 u32 rgb_quantization_range;
162 struct workqueue_struct *work_queues;
163 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 164 bool restart_stdi_once;
54450f59
HV		 165
166 /* i2c clients */
b44b2e06 167 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
54450f59
HV		 168
169 /* controls */
170 struct v4l2_ctrl *detect_tx_5v_ctrl;
171 struct v4l2_ctrl *analog_sampling_phase_ctrl;
172 struct v4l2_ctrl *free_run_color_manual_ctrl;
173 struct v4l2_ctrl *free_run_color_ctrl;
174 struct v4l2_ctrl *rgb_quantization_range_ctrl;
175};
176
b44b2e06 177static bool adv76xx_has_afe(struct adv76xx_state *state)
d42010a1
LPC		 178{
179 return state->info->has_afe;
180}
181
54450f59 182/* Supported CEA and DMT timings */
b44b2e06 183static const struct v4l2_dv_timings adv76xx_timings[] = {
54450f59
HV		 184 V4L2_DV_BT_CEA_720X480P59_94,
185 V4L2_DV_BT_CEA_720X576P50,
186 V4L2_DV_BT_CEA_1280X720P24,
187 V4L2_DV_BT_CEA_1280X720P25,
54450f59
HV		 188 V4L2_DV_BT_CEA_1280X720P50,
189 V4L2_DV_BT_CEA_1280X720P60,
190 V4L2_DV_BT_CEA_1920X1080P24,
191 V4L2_DV_BT_CEA_1920X1080P25,
192 V4L2_DV_BT_CEA_1920X1080P30,
193 V4L2_DV_BT_CEA_1920X1080P50,
194 V4L2_DV_BT_CEA_1920X1080P60,
195
ccbd5bc4 196 /* sorted by DMT ID */
54450f59
HV		 197 V4L2_DV_BT_DMT_640X350P85,
198 V4L2_DV_BT_DMT_640X400P85,
199 V4L2_DV_BT_DMT_720X400P85,
200 V4L2_DV_BT_DMT_640X480P60,
201 V4L2_DV_BT_DMT_640X480P72,
202 V4L2_DV_BT_DMT_640X480P75,
203 V4L2_DV_BT_DMT_640X480P85,
204 V4L2_DV_BT_DMT_800X600P56,
205 V4L2_DV_BT_DMT_800X600P60,
206 V4L2_DV_BT_DMT_800X600P72,
207 V4L2_DV_BT_DMT_800X600P75,
208 V4L2_DV_BT_DMT_800X600P85,
209 V4L2_DV_BT_DMT_848X480P60,
210 V4L2_DV_BT_DMT_1024X768P60,
211 V4L2_DV_BT_DMT_1024X768P70,
212 V4L2_DV_BT_DMT_1024X768P75,
213 V4L2_DV_BT_DMT_1024X768P85,
214 V4L2_DV_BT_DMT_1152X864P75,
215 V4L2_DV_BT_DMT_1280X768P60_RB,
216 V4L2_DV_BT_DMT_1280X768P60,
217 V4L2_DV_BT_DMT_1280X768P75,
218 V4L2_DV_BT_DMT_1280X768P85,
219 V4L2_DV_BT_DMT_1280X800P60_RB,
220 V4L2_DV_BT_DMT_1280X800P60,
221 V4L2_DV_BT_DMT_1280X800P75,
222 V4L2_DV_BT_DMT_1280X800P85,
223 V4L2_DV_BT_DMT_1280X960P60,
224 V4L2_DV_BT_DMT_1280X960P85,
225 V4L2_DV_BT_DMT_1280X1024P60,
226 V4L2_DV_BT_DMT_1280X1024P75,
227 V4L2_DV_BT_DMT_1280X1024P85,
228 V4L2_DV_BT_DMT_1360X768P60,
229 V4L2_DV_BT_DMT_1400X1050P60_RB,
230 V4L2_DV_BT_DMT_1400X1050P60,
231 V4L2_DV_BT_DMT_1400X1050P75,
232 V4L2_DV_BT_DMT_1400X1050P85,
233 V4L2_DV_BT_DMT_1440X900P60_RB,
234 V4L2_DV_BT_DMT_1440X900P60,
235 V4L2_DV_BT_DMT_1600X1200P60,
236 V4L2_DV_BT_DMT_1680X1050P60_RB,
237 V4L2_DV_BT_DMT_1680X1050P60,
238 V4L2_DV_BT_DMT_1792X1344P60,
239 V4L2_DV_BT_DMT_1856X1392P60,
240 V4L2_DV_BT_DMT_1920X1200P60_RB,
547ed542 241 V4L2_DV_BT_DMT_1366X768P60_RB,
54450f59
HV		 242 V4L2_DV_BT_DMT_1366X768P60,
243 V4L2_DV_BT_DMT_1920X1080P60,
244 { },
245};
246
b44b2e06 247struct adv76xx_video_standards {
ccbd5bc4
HV		 248 struct v4l2_dv_timings timings;
249 u8 vid_std;
250 u8 v_freq;
251};
252
253/* sorted by number of lines */
b44b2e06 254static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
ccbd5bc4
HV		 255 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
256 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
257 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
258 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
259 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
260 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
261 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
262 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
263 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
264 /* TODO add 1920x1080P60_RB (CVT timing) */
265 { },
266};
267
268/* sorted by number of lines */
b44b2e06 269static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
ccbd5bc4
HV		 270 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
271 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
272 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
273 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
274 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
275 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
276 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
277 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
278 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
279 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
280 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
281 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
282 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
283 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
284 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
285 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
286 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
287 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
288 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
289 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
290 /* TODO add 1600X1200P60_RB (not a DMT timing) */
291 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
292 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
293 { },
294};
295
296/* sorted by number of lines */
b44b2e06 297static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
ccbd5bc4
HV		 298 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
299 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
300 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
301 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
302 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
303 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
304 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
305 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
306 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
307 { },
308};
309
310/* sorted by number of lines */
b44b2e06 311static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
ccbd5bc4
HV		 312 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
313 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
314 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
315 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
316 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
317 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
318 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
319 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
320 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
321 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
322 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
323 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
324 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
325 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
326 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
327 { },
328};
329
54450f59
HV		 330/* ----------------------------------------------------------------------- */
331
b44b2e06 332static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
54450f59 333{
b44b2e06 334 return container_of(sd, struct adv76xx_state, sd);
54450f59
HV		 335}
336
54450f59
HV		 337static inline unsigned htotal(const struct v4l2_bt_timings *t)
338{
eacf8f9a 339 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 340}
341
54450f59
HV		 342static inline unsigned vtotal(const struct v4l2_bt_timings *t)
343{
eacf8f9a 344 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 345}
346
347/* ----------------------------------------------------------------------- */
348
349static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,
350 u8 command, bool check)
351{
352 union i2c_smbus_data data;
353
354 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,
355 I2C_SMBUS_READ, command,
356 I2C_SMBUS_BYTE_DATA, &data))
357 return data.byte;
358 if (check)
359 v4l_err(client, "error reading %02x, %02x\n",
360 client->addr, command);
361 return -EIO;
362}
363
b44b2e06
PA		 364static s32 adv_smbus_read_byte_data(struct adv76xx_state *state,
365 enum adv76xx_page page, u8 command)
54450f59 366{
05cacb17
LP		 367 return adv_smbus_read_byte_data_check(state->i2c_clients[page],
368 command, true);
54450f59
HV		 369}
370
b44b2e06
PA		 371static s32 adv_smbus_write_byte_data(struct adv76xx_state *state,
372 enum adv76xx_page page, u8 command,
05cacb17 373 u8 value)
54450f59 374{
05cacb17 375 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 376 union i2c_smbus_data data;
377 int err;
378 int i;
379
380 data.byte = value;
381 for (i = 0; i < 3; i++) {
382 err = i2c_smbus_xfer(client->adapter, client->addr,
383 client->flags,
384 I2C_SMBUS_WRITE, command,
385 I2C_SMBUS_BYTE_DATA, &data);
386 if (!err)
387 break;
388 }
389 if (err < 0)
390 v4l_err(client, "error writing %02x, %02x, %02x\n",
391 client->addr, command, value);
392 return err;
393}
394
b44b2e06
PA		 395static s32 adv_smbus_write_i2c_block_data(struct adv76xx_state *state,
396 enum adv76xx_page page, u8 command,
05cacb17 397 unsigned length, const u8 *values)
54450f59 398{
05cacb17 399 struct i2c_client *client = state->i2c_clients[page];
54450f59
HV		 400 union i2c_smbus_data data;
401
402 if (length > I2C_SMBUS_BLOCK_MAX)
403 length = I2C_SMBUS_BLOCK_MAX;
404 data.block[0] = length;
405 memcpy(data.block + 1, values, length);
406 return i2c_smbus_xfer(client->adapter, client->addr, client->flags,
407 I2C_SMBUS_WRITE, command,
408 I2C_SMBUS_I2C_BLOCK_DATA, &data);
409}
410
411/* ----------------------------------------------------------------------- */
412
413static inline int io_read(struct v4l2_subdev *sd, u8 reg)
414{
b44b2e06 415 struct adv76xx_state *state = to_state(sd);
54450f59 416
b44b2e06 417 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_IO, reg);
54450f59
HV		 418}
419
420static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
421{
b44b2e06 422 struct adv76xx_state *state = to_state(sd);
54450f59 423
b44b2e06 424 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_IO, reg, val);
54450f59
HV		 425}
426
22d97e56 427static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 428{
22d97e56 429 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 430}
431
432static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
433{
b44b2e06 434 struct adv76xx_state *state = to_state(sd);
54450f59 435
05cacb17 436 return adv_smbus_read_byte_data(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 437}
438
439static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
440{
b44b2e06 441 struct adv76xx_state *state = to_state(sd);
54450f59 442
05cacb17 443 return adv_smbus_write_byte_data(state, ADV7604_PAGE_AVLINK, reg, val);
54450f59
HV		 444}
445
446static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
447{
b44b2e06 448 struct adv76xx_state *state = to_state(sd);
54450f59 449
b44b2e06 450 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CEC, reg);
54450f59
HV		 451}
452
453static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
454{
b44b2e06 455 struct adv76xx_state *state = to_state(sd);
54450f59 456
b44b2e06 457 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CEC, reg, val);
54450f59
HV		 458}
459
54450f59
HV		 460static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
461{
b44b2e06 462 struct adv76xx_state *state = to_state(sd);
54450f59 463
b44b2e06 464 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_INFOFRAME, reg);
54450f59
HV		 465}
466
467static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
468{
b44b2e06 469 struct adv76xx_state *state = to_state(sd);
54450f59 470
b44b2e06 471 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_INFOFRAME,
05cacb17 472 reg, val);
54450f59
HV		 473}
474
54450f59
HV		 475static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
476{
b44b2e06 477 struct adv76xx_state *state = to_state(sd);
54450f59 478
b44b2e06 479 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_AFE, reg);
54450f59
HV		 480}
481
482static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
483{
b44b2e06 484 struct adv76xx_state *state = to_state(sd);
54450f59 485
b44b2e06 486 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_AFE, reg, val);
54450f59
HV		 487}
488
489static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
490{
b44b2e06 491 struct adv76xx_state *state = to_state(sd);
54450f59 492
b44b2e06 493 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_REP, reg);
54450f59
HV		 494}
495
496static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
497{
b44b2e06 498 struct adv76xx_state *state = to_state(sd);
54450f59 499
b44b2e06 500 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_REP, reg, val);
54450f59
HV		 501}
502
22d97e56 503static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 504{
22d97e56 505 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 506}
507
508static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
509{
b44b2e06 510 struct adv76xx_state *state = to_state(sd);
54450f59 511
b44b2e06 512 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_EDID, reg);
54450f59
HV		 513}
514
515static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
516{
b44b2e06 517 struct adv76xx_state *state = to_state(sd);
54450f59 518
b44b2e06 519 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_EDID, reg, val);
54450f59
HV		 520}
521
54450f59
HV		 522static inline int edid_write_block(struct v4l2_subdev *sd,
523 unsigned len, const u8 *val)
524{
b44b2e06 525 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 526 int err = 0;
527 int i;
528
529 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n", __func__, len);
530
54450f59 531 for (i = 0; !err && i < len; i += I2C_SMBUS_BLOCK_MAX)
b44b2e06 532 err = adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_EDID,
05cacb17 533 i, I2C_SMBUS_BLOCK_MAX, val + i);
dd08beb9
MR		 534 return err;
535}
54450f59 536
b44b2e06 537static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
e9d50e9e
LP		 538{
539 unsigned int i;
540
269bd132 541 for (i = 0; i < state->info->num_dv_ports; ++i)
e9d50e9e 542 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
e9d50e9e 543
b44b2e06 544 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
e9d50e9e
LP		 545}
546
b44b2e06 547static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
dd08beb9
MR		 548{
549 struct delayed_work *dwork = to_delayed_work(work);
b44b2e06 550 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
dd08beb9
MR		 551 delayed_work_enable_hotplug);
552 struct v4l2_subdev *sd = &state->sd;
54450f59 553
dd08beb9 554 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 555
b44b2e06 556 adv76xx_set_hpd(state, state->edid.present);
54450f59
HV		 557}
558
559static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
560{
b44b2e06 561 struct adv76xx_state *state = to_state(sd);
54450f59 562
b44b2e06 563 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_HDMI, reg);
54450f59
HV		 564}
565
51182a94
LP		 566static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
567{
568 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
569}
570
54450f59
HV		 571static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
572{
b44b2e06 573 struct adv76xx_state *state = to_state(sd);
54450f59 574
b44b2e06 575 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_HDMI, reg, val);
54450f59
HV		 576}
577
22d97e56 578static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 579{
22d97e56 580 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 581}
582
54450f59
HV		 583static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
584{
b44b2e06 585 struct adv76xx_state *state = to_state(sd);
54450f59 586
b44b2e06 587 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_TEST, reg, val);
54450f59
HV		 588}
589
590static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
591{
b44b2e06 592 struct adv76xx_state *state = to_state(sd);
54450f59 593
b44b2e06 594 return adv_smbus_read_byte_data(state, ADV76XX_PAGE_CP, reg);
54450f59
HV		 595}
596
51182a94
LP		 597static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
598{
599 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
600}
601
54450f59
HV		 602static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
603{
b44b2e06 604 struct adv76xx_state *state = to_state(sd);
54450f59 605
b44b2e06 606 return adv_smbus_write_byte_data(state, ADV76XX_PAGE_CP, reg, val);
54450f59
HV		 607}
608
22d97e56 609static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 610{
22d97e56 611 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 612}
613
614static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
615{
b44b2e06 616 struct adv76xx_state *state = to_state(sd);
54450f59 617
05cacb17 618 return adv_smbus_read_byte_data(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 619}
620
621static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
622{
b44b2e06 623 struct adv76xx_state *state = to_state(sd);
54450f59 624
05cacb17
LP		 625 return adv_smbus_write_byte_data(state, ADV7604_PAGE_VDP, reg, val);
626}
d42010a1 627
b44b2e06
PA		 628#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
629#define ADV76XX_REG_SEQ_TERM 0xffff
d42010a1
LPC		 630
631#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 632static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
d42010a1 633{
b44b2e06 634 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 635 unsigned int page = reg >> 8;
636
637 if (!(BIT(page) & state->info->page_mask))
638 return -EINVAL;
639
640 reg &= 0xff;
641
05cacb17 642 return adv_smbus_read_byte_data(state, page, reg);
d42010a1
LPC		 643}
644#endif
645
b44b2e06 646static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
d42010a1 647{
b44b2e06 648 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 649 unsigned int page = reg >> 8;
650
651 if (!(BIT(page) & state->info->page_mask))
652 return -EINVAL;
653
654 reg &= 0xff;
655
05cacb17 656 return adv_smbus_write_byte_data(state, page, reg, val);
d42010a1
LPC		 657}
658
b44b2e06
PA		 659static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
660 const struct adv76xx_reg_seq *reg_seq)
d42010a1
LPC		 661{
662 unsigned int i;
663
b44b2e06
PA		 664 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
665 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
d42010a1
LPC		 666}
667
539b33b0
LP		 668/* -----------------------------------------------------------------------------
669 * Format helpers
670 */
671
b44b2e06
PA		 672static const struct adv76xx_format_info adv7604_formats[] = {
673 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
674 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
675 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
677 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
679 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
680 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
681 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
682 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
683 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
684 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
685 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
686 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
687 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
688 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
689 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
690 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
691 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
692 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
693 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
694 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
695 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
696 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
697 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
698 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
699 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
700 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
701 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
702 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
703 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
704 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
705 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
706 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
707 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
708 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
709 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
710 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 711};
712
b44b2e06
PA		 713static const struct adv76xx_format_info adv7611_formats[] = {
714 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
715 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
716 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
717 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
718 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
719 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
720 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
721 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
722 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
723 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
724 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
725 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
726 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
727 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
728 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
729 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
730 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
731 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
732 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
733 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
734 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
735 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
736 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
737 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
738 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
739 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 740};
741
b44b2e06
PA		 742static const struct adv76xx_format_info *
743adv76xx_format_info(struct adv76xx_state *state, u32 code)
539b33b0
LP		 744{
745 unsigned int i;
746
747 for (i = 0; i < state->info->nformats; ++i) {
748 if (state->info->formats[i].code == code)
749 return &state->info->formats[i];
750 }
751
752 return NULL;
753}
754
54450f59
HV		 755/* ----------------------------------------------------------------------- */
756
4a31a93a
MR		 757static inline bool is_analog_input(struct v4l2_subdev *sd)
758{
b44b2e06 759 struct adv76xx_state *state = to_state(sd);
4a31a93a 760
c784b1e2
LP		 761 return state->selected_input == ADV7604_PAD_VGA_RGB ||
762 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 763}
764
765static inline bool is_digital_input(struct v4l2_subdev *sd)
766{
b44b2e06 767 struct adv76xx_state *state = to_state(sd);
4a31a93a 768
b44b2e06 769 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
c784b1e2
LP		 770 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
771 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
772 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 773}
774
775/* ----------------------------------------------------------------------- */
776
54450f59 777#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 778static void adv76xx_inv_register(struct v4l2_subdev *sd)
54450f59
HV		 779{
780 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
781 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
782 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
783 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
784 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
785 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
786 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
787 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
788 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
789 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
790 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
791 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
792 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
793}
794
b44b2e06 795static int adv76xx_g_register(struct v4l2_subdev *sd,
54450f59
HV		 796 struct v4l2_dbg_register *reg)
797{
d42010a1
LPC		 798 int ret;
799
b44b2e06 800 ret = adv76xx_read_reg(sd, reg->reg);
d42010a1 801 if (ret < 0) {
54450f59 802 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 803 adv76xx_inv_register(sd);
d42010a1 804 return ret;
54450f59 805 }
d42010a1
LPC		 806
807 reg->size = 1;
808 reg->val = ret;
809
54450f59
HV		 810 return 0;
811}
812
b44b2e06 813static int adv76xx_s_register(struct v4l2_subdev *sd,
977ba3b1 814 const struct v4l2_dbg_register *reg)
54450f59 815{
d42010a1 816 int ret;
1577461b 817
b44b2e06 818 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
d42010a1 819 if (ret < 0) {
54450f59 820 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 821 adv76xx_inv_register(sd);
d42010a1 822 return ret;
54450f59 823 }
d42010a1 824
54450f59
HV		 825 return 0;
826}
827#endif
828
d42010a1
LPC		 829static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
830{
831 u8 value = io_read(sd, 0x6f);
832
833 return ((value & 0x10) >> 4)
834 | ((value & 0x08) >> 2)
835 | ((value & 0x04) << 0)
836 | ((value & 0x02) << 2);
837}
838
839static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
840{
841 u8 value = io_read(sd, 0x6f);
842
843 return value & 1;
844}
845
b44b2e06 846static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
54450f59 847{
b44b2e06
PA		 848 struct adv76xx_state *state = to_state(sd);
849 const struct adv76xx_chip_info *info = state->info;
54450f59 850
54450f59 851 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 852 info->read_cable_det(sd));
54450f59
HV		 853}
854
ccbd5bc4
HV		 855static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
856 u8 prim_mode,
b44b2e06 857 const struct adv76xx_video_standards *predef_vid_timings,
ccbd5bc4
HV		 858 const struct v4l2_dv_timings *timings)
859{
ccbd5bc4
HV		 860 int i;
861
862 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 863 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
4a31a93a 864 is_digital_input(sd) ? 250000 : 1000000))
ccbd5bc4
HV		 865 continue;
866 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
867 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
868 prim_mode); /* v_freq and prim mode */
869 return 0;
870 }
871
872 return -1;
873}
874
875static int configure_predefined_video_timings(struct v4l2_subdev *sd,
876 struct v4l2_dv_timings *timings)
54450f59 877{
b44b2e06 878 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 879 int err;
880
881 v4l2_dbg(1, debug, sd, "%s", __func__);
882
b44b2e06 883 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 884 /* reset to default values */
885 io_write(sd, 0x16, 0x43);
886 io_write(sd, 0x17, 0x5a);
887 }
ccbd5bc4 888 /* disable embedded syncs for auto graphics mode */
22d97e56 889 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 890 cp_write(sd, 0x8f, 0x00);
891 cp_write(sd, 0x90, 0x00);
892 cp_write(sd, 0xa2, 0x00);
893 cp_write(sd, 0xa3, 0x00);
894 cp_write(sd, 0xa4, 0x00);
895 cp_write(sd, 0xa5, 0x00);
896 cp_write(sd, 0xa6, 0x00);
897 cp_write(sd, 0xa7, 0x00);
898 cp_write(sd, 0xab, 0x00);
899 cp_write(sd, 0xac, 0x00);
900
4a31a93a 901 if (is_analog_input(sd)) {
ccbd5bc4
HV		 902 err = find_and_set_predefined_video_timings(sd,
903 0x01, adv7604_prim_mode_comp, timings);
904 if (err)
905 err = find_and_set_predefined_video_timings(sd,
906 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 907 } else if (is_digital_input(sd)) {
ccbd5bc4 908 err = find_and_set_predefined_video_timings(sd,
b44b2e06 909 0x05, adv76xx_prim_mode_hdmi_comp, timings);
ccbd5bc4
HV		 910 if (err)
911 err = find_and_set_predefined_video_timings(sd,
b44b2e06 912 0x06, adv76xx_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 913 } else {
914 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
915 __func__, state->selected_input);
ccbd5bc4 916 err = -1;
ccbd5bc4
HV		 917 }
918
919
920 return err;
921}
922
923static void configure_custom_video_timings(struct v4l2_subdev *sd,
924 const struct v4l2_bt_timings *bt)
925{
b44b2e06 926 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 927 u32 width = htotal(bt);
928 u32 height = vtotal(bt);
929 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
930 u16 cp_start_eav = width - bt->hfrontporch;
931 u16 cp_start_vbi = height - bt->vfrontporch;
932 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
933 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
b44b2e06 934 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
ccbd5bc4
HV		 935 const u8 pll[2] = {
936 0xc0 | ((width >> 8) & 0x1f),
937 width & 0xff
938 };
54450f59
HV		 939
940 v4l2_dbg(2, debug, sd, "%s\n", __func__);
941
4a31a93a 942 if (is_analog_input(sd)) {
ccbd5bc4
HV		 943 /* auto graphics */
944 io_write(sd, 0x00, 0x07); /* video std */
945 io_write(sd, 0x01, 0x02); /* prim mode */
946 /* enable embedded syncs for auto graphics mode */
22d97e56 947 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 948
ccbd5bc4 949 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 950 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
951 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
b44b2e06 952 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_IO,
05cacb17 953 0x16, 2, pll))
54450f59 954 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 955
956 /* active video - horizontal timing */
54450f59 957 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 958 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 959 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 960 cp_write(sd, 0xa4, cp_start_eav & 0xff);
961
962 /* active video - vertical timing */
54450f59 963 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 964 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 965 ((cp_end_vbi >> 8) & 0xf));
54450f59 966 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 967 } else if (is_digital_input(sd)) {
ccbd5bc4 968 /* set default prim_mode/vid_std for HDMI
39c1cb2b 969 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 970 io_write(sd, 0x00, 0x02); /* video std */
971 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 972 } else {
973 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
974 __func__, state->selected_input);
54450f59 975 }
54450f59 976
ccbd5bc4
HV		 977 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
978 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
979 cp_write(sd, 0xab, (height >> 4) & 0xff);
980 cp_write(sd, 0xac, (height & 0x0f) << 4);
981}
54450f59 982
b44b2e06 983static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
5c6c6349 984{
b44b2e06 985 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 986 u8 offset_buf[4];
987
988 if (auto_offset) {
989 offset_a = 0x3ff;
990 offset_b = 0x3ff;
991 offset_c = 0x3ff;
992 }
993
994 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
995 __func__, auto_offset ? "Auto" : "Manual",
996 offset_a, offset_b, offset_c);
997
998 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
999 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1000 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1001 offset_buf[3] = offset_c & 0x0ff;
1002
1003 /* Registers must be written in this order with no i2c access in between */
b44b2e06 1004 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
05cacb17 1005 0x77, 4, offset_buf))
5c6c6349
MR		 1006 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1007}
1008
b44b2e06 1009static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
5c6c6349 1010{
b44b2e06 1011 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1012 u8 gain_buf[4];
1013 u8 gain_man = 1;
1014 u8 agc_mode_man = 1;
1015
1016 if (auto_gain) {
1017 gain_man = 0;
1018 agc_mode_man = 0;
1019 gain_a = 0x100;
1020 gain_b = 0x100;
1021 gain_c = 0x100;
1022 }
1023
1024 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1025 __func__, auto_gain ? "Auto" : "Manual",
1026 gain_a, gain_b, gain_c);
1027
1028 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1029 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1030 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1031 gain_buf[3] = ((gain_c & 0x0ff));
1032
1033 /* Registers must be written in this order with no i2c access in between */
b44b2e06 1034 if (adv_smbus_write_i2c_block_data(state, ADV76XX_PAGE_CP,
05cacb17 1035 0x73, 4, gain_buf))
5c6c6349
MR		 1036 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1037}
1038
54450f59
HV		 1039static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1040{
b44b2e06 1041 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1042 bool rgb_output = io_read(sd, 0x02) & 0x02;
1043 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1044
1045 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1046 __func__, state->rgb_quantization_range,
1047 rgb_output, hdmi_signal);
54450f59 1048
b44b2e06
PA		 1049 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1050 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1051
54450f59
HV		 1052 switch (state->rgb_quantization_range) {
1053 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1054 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1055 /* Receiving analog RGB signal
1056 * Set RGB full range (0-255) */
22d97e56 1057 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1058 break;
1059 }
1060
c784b1e2 1061 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1062 /* Receiving analog YPbPr signal
1063 * Set automode */
22d97e56 1064 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1065 break;
1066 }
1067
5c6c6349 1068 if (hdmi_signal) {
9833239e
MR		 1069 /* Receiving HDMI signal
1070 * Set automode */
22d97e56 1071 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1072 break;
1073 }
1074
1075 /* Receiving DVI-D signal
1076 * ADV7604 selects RGB limited range regardless of
1077 * input format (CE/IT) in automatic mode */
1078 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861) {
1079 /* RGB limited range (16-235) */
22d97e56 1080 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1081 } else {
1082 /* RGB full range (0-255) */
22d97e56 1083 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1084
1085 if (is_digital_input(sd) && rgb_output) {
b44b2e06 1086 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
5c6c6349 1087 } else {
b44b2e06
PA		 1088 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1089 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
5c6c6349 1090 }
54450f59
HV		 1091 }
1092 break;
1093 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1094 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1095 /* YCrCb limited range (16-235) */
22d97e56 1096 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1097 break;
d261e842 1098 }
5c6c6349
MR		 1099
1100 /* RGB limited range (16-235) */
22d97e56 1101 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1102
54450f59
HV		 1103 break;
1104 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1105 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1106 /* YCrCb full range (0-255) */
22d97e56 1107 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1108 break;
1109 }
1110
1111 /* RGB full range (0-255) */
22d97e56 1112 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1113
1114 if (is_analog_input(sd) || hdmi_signal)
1115 break;
1116
1117 /* Adjust gain/offset for DVI-D signals only */
1118 if (rgb_output) {
b44b2e06 1119 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1120 } else {
b44b2e06
PA		 1121 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1122 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1123 }
54450f59
HV		 1124 break;
1125 }
1126}
1127
b44b2e06 1128static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
54450f59 1129{
c269887c 1130 struct v4l2_subdev *sd =
b44b2e06 1131 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
c269887c 1132
b44b2e06 1133 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1134
1135 switch (ctrl->id) {
1136 case V4L2_CID_BRIGHTNESS:
1137 cp_write(sd, 0x3c, ctrl->val);
1138 return 0;
1139 case V4L2_CID_CONTRAST:
1140 cp_write(sd, 0x3a, ctrl->val);
1141 return 0;
1142 case V4L2_CID_SATURATION:
1143 cp_write(sd, 0x3b, ctrl->val);
1144 return 0;
1145 case V4L2_CID_HUE:
1146 cp_write(sd, 0x3d, ctrl->val);
1147 return 0;
1148 case V4L2_CID_DV_RX_RGB_RANGE:
1149 state->rgb_quantization_range = ctrl->val;
1150 set_rgb_quantization_range(sd);
1151 return 0;
1152 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
b44b2e06 1153 if (!adv76xx_has_afe(state))
d42010a1 1154 return -EINVAL;
54450f59
HV		 1155 /* Set the analog sampling phase. This is needed to find the
1156 best sampling phase for analog video: an application or
1157 driver has to try a number of phases and analyze the picture
1158 quality before settling on the best performing phase. */
1159 afe_write(sd, 0xc8, ctrl->val);
1160 return 0;
1161 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1162 /* Use the default blue color for free running mode,
1163 or supply your own. */
22d97e56 1164 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1165 return 0;
1166 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1167 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1168 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1169 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1170 return 0;
1171 }
1172 return -EINVAL;
1173}
1174
54450f59
HV		 1175/* ----------------------------------------------------------------------- */
1176
1177static inline bool no_power(struct v4l2_subdev *sd)
1178{
1179 /* Entire chip or CP powered off */
1180 return io_read(sd, 0x0c) & 0x24;
1181}
1182
1183static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1184{
b44b2e06 1185 struct adv76xx_state *state = to_state(sd);
4a31a93a
MR		 1186
1187 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1188}
1189
1190static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1191{
b44b2e06
PA		 1192 struct adv76xx_state *state = to_state(sd);
1193 const struct adv76xx_chip_info *info = state->info;
d42010a1
LPC		 1194
1195 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1196}
1197
bb88f325
MB		 1198static inline bool is_hdmi(struct v4l2_subdev *sd)
1199{
1200 return hdmi_read(sd, 0x05) & 0x80;
1201}
1202
54450f59
HV		 1203static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1204{
b44b2e06 1205 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 1206
1207 /*
1208 * Chips without a AFE don't expose registers for the SSPD, so just assume
1209 * that we have a lock.
1210 */
b44b2e06 1211 if (adv76xx_has_afe(state))
d42010a1
LPC		 1212 return false;
1213
54450f59
HV		 1214 /* TODO channel 2 */
1215 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1216}
1217
1218static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1219{
1220 /* TODO channel 2 */
1221 return !(cp_read(sd, 0xb1) & 0x80);
1222}
1223
1224static inline bool no_signal(struct v4l2_subdev *sd)
1225{
54450f59
HV		 1226 bool ret;
1227
1228 ret = no_power(sd);
1229
1230 ret |= no_lock_stdi(sd);
1231 ret |= no_lock_sspd(sd);
1232
4a31a93a 1233 if (is_digital_input(sd)) {
54450f59
HV		 1234 ret |= no_lock_tmds(sd);
1235 ret |= no_signal_tmds(sd);
1236 }
1237
1238 return ret;
1239}
1240
1241static inline bool no_lock_cp(struct v4l2_subdev *sd)
1242{
b44b2e06 1243 struct adv76xx_state *state = to_state(sd);
d42010a1 1244
b44b2e06 1245 if (!adv76xx_has_afe(state))
d42010a1
LPC		 1246 return false;
1247
54450f59
HV		 1248 /* CP has detected a non standard number of lines on the incoming
1249 video compared to what it is configured to receive by s_dv_timings */
1250 return io_read(sd, 0x12) & 0x01;
1251}
1252
58514625 1253static inline bool in_free_run(struct v4l2_subdev *sd)
1254{
1255 return cp_read(sd, 0xff) & 0x10;
1256}
1257
b44b2e06 1258static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
54450f59 1259{
54450f59
HV		 1260 *status = 0;
1261 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1262 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1263 if (!in_free_run(sd) && no_lock_cp(sd))
1264 *status |= is_digital_input(sd) ?
1265 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1266
1267 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1268
1269 return 0;
1270}
1271
1272/* ----------------------------------------------------------------------- */
1273
54450f59
HV		 1274struct stdi_readback {
1275 u16 bl, lcf, lcvs;
1276 u8 hs_pol, vs_pol;
1277 bool interlaced;
1278};
1279
1280static int stdi2dv_timings(struct v4l2_subdev *sd,
1281 struct stdi_readback *stdi,
1282 struct v4l2_dv_timings *timings)
1283{
b44b2e06
PA		 1284 struct adv76xx_state *state = to_state(sd);
1285 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
54450f59
HV		 1286 u32 pix_clk;
1287 int i;
1288
b44b2e06
PA		 1289 for (i = 0; adv76xx_timings[i].bt.height; i++) {
1290 if (vtotal(&adv76xx_timings[i].bt) != stdi->lcf + 1)
54450f59 1291 continue;
b44b2e06 1292 if (adv76xx_timings[i].bt.vsync != stdi->lcvs)
54450f59
HV		 1293 continue;
1294
b44b2e06 1295 pix_clk = hfreq * htotal(&adv76xx_timings[i].bt);
54450f59 1296
b44b2e06
PA		 1297 if ((pix_clk < adv76xx_timings[i].bt.pixelclock + 1000000) &&
1298 (pix_clk > adv76xx_timings[i].bt.pixelclock - 1000000)) {
1299 *timings = adv76xx_timings[i];
54450f59
HV		 1300 return 0;
1301 }
1302 }
1303
1304 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs,
1305 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1306 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1307 timings))
1308 return 0;
1309 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1310 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1311 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1312 state->aspect_ratio, timings))
1313 return 0;
1314
ccbd5bc4
HV		 1315 v4l2_dbg(2, debug, sd,
1316 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1317 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1318 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1319 return -1;
1320}
1321
d42010a1 1322
54450f59
HV		 1323static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1324{
b44b2e06
PA		 1325 struct adv76xx_state *state = to_state(sd);
1326 const struct adv76xx_chip_info *info = state->info;
4a2ccdd2
LP		 1327 u8 polarity;
1328
54450f59
HV		 1329 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1330 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1331 return -1;
1332 }
1333
1334 /* read STDI */
51182a94 1335 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1336 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1337 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1338 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1339
b44b2e06 1340 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1341 /* read SSPD */
1342 polarity = cp_read(sd, 0xb5);
1343 if ((polarity & 0x03) == 0x01) {
1344 stdi->hs_pol = polarity & 0x10
1345 ? (polarity & 0x08 ? '+' : '-') : 'x';
1346 stdi->vs_pol = polarity & 0x40
1347 ? (polarity & 0x20 ? '+' : '-') : 'x';
1348 } else {
1349 stdi->hs_pol = 'x';
1350 stdi->vs_pol = 'x';
1351 }
54450f59 1352 } else {
d42010a1
LPC		 1353 polarity = hdmi_read(sd, 0x05);
1354 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1355 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1356 }
1357
1358 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1359 v4l2_dbg(2, debug, sd,
1360 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1361 return -1;
1362 }
1363
1364 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1365 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1366 memset(stdi, 0, sizeof(struct stdi_readback));
1367 return -1;
1368 }
1369
1370 v4l2_dbg(2, debug, sd,
1371 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1372 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1373 stdi->hs_pol, stdi->vs_pol,
1374 stdi->interlaced ? "interlaced" : "progressive");
1375
1376 return 0;
1377}
1378
b44b2e06 1379static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1380 struct v4l2_enum_dv_timings *timings)
1381{
b44b2e06 1382 struct adv76xx_state *state = to_state(sd);
afec5599 1383
b44b2e06 1384 if (timings->index >= ARRAY_SIZE(adv76xx_timings) - 1)
54450f59 1385 return -EINVAL;
afec5599
LP		 1386
1387 if (timings->pad >= state->source_pad)
1388 return -EINVAL;
1389
54450f59 1390 memset(timings->reserved, 0, sizeof(timings->reserved));
b44b2e06 1391 timings->timings = adv76xx_timings[timings->index];
54450f59
HV		 1392 return 0;
1393}
1394
b44b2e06 1395static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
7515e096 1396 struct v4l2_dv_timings_cap *cap)
54450f59 1397{
b44b2e06 1398 struct adv76xx_state *state = to_state(sd);
7515e096
LP		 1399
1400 if (cap->pad >= state->source_pad)
1401 return -EINVAL;
1402
54450f59
HV		 1403 cap->type = V4L2_DV_BT_656_1120;
1404 cap->bt.max_width = 1920;
1405 cap->bt.max_height = 1200;
fe9c2564 1406 cap->bt.min_pixelclock = 25000000;
afec5599 1407
7515e096 1408 switch (cap->pad) {
b44b2e06 1409 case ADV76XX_PAD_HDMI_PORT_A:
afec5599
LP		 1410 case ADV7604_PAD_HDMI_PORT_B:
1411 case ADV7604_PAD_HDMI_PORT_C:
1412 case ADV7604_PAD_HDMI_PORT_D:
54450f59 1413 cap->bt.max_pixelclock = 225000000;
afec5599
LP		 1414 break;
1415 case ADV7604_PAD_VGA_RGB:
1416 case ADV7604_PAD_VGA_COMP:
1417 default:
54450f59 1418 cap->bt.max_pixelclock = 170000000;
afec5599
LP		 1419 break;
1420 }
1421
54450f59
HV		 1422 cap->bt.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
1423 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;
1424 cap->bt.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
1425 V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM;
1426 return 0;
1427}
1428
1429/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
b44b2e06
PA		 1430 if the format is listed in adv76xx_timings[] */
1431static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
54450f59
HV		 1432 struct v4l2_dv_timings *timings)
1433{
54450f59
HV		 1434 int i;
1435
b44b2e06
PA		 1436 for (i = 0; adv76xx_timings[i].bt.width; i++) {
1437 if (v4l2_match_dv_timings(timings, &adv76xx_timings[i],
4a31a93a 1438 is_digital_input(sd) ? 250000 : 1000000)) {
b44b2e06 1439 *timings = adv76xx_timings[i];
54450f59
HV		 1440 break;
1441 }
1442 }
1443}
1444
d42010a1
LPC		 1445static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1446{
1447 unsigned int freq;
1448 int a, b;
1449
1450 a = hdmi_read(sd, 0x06);
1451 b = hdmi_read(sd, 0x3b);
1452 if (a < 0 || b < 0)
1453 return 0;
1454 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1455
1456 if (is_hdmi(sd)) {
1457 /* adjust for deep color mode */
1458 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1459
1460 freq = freq * 8 / bits_per_channel;
1461 }
1462
1463 return freq;
1464}
1465
1466static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1467{
1468 int a, b;
1469
1470 a = hdmi_read(sd, 0x51);
1471 b = hdmi_read(sd, 0x52);
1472 if (a < 0 || b < 0)
1473 return 0;
1474 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1475}
1476
b44b2e06 1477static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1478 struct v4l2_dv_timings *timings)
1479{
b44b2e06
PA		 1480 struct adv76xx_state *state = to_state(sd);
1481 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 1482 struct v4l2_bt_timings *bt = &timings->bt;
1483 struct stdi_readback stdi;
1484
1485 if (!timings)
1486 return -EINVAL;
1487
1488 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1489
1490 if (no_signal(sd)) {
1e0b9156 1491 state->restart_stdi_once = true;
54450f59
HV		 1492 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1493 return -ENOLINK;
1494 }
1495
1496 /* read STDI */
1497 if (read_stdi(sd, &stdi)) {
1498 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1499 return -ENOLINK;
1500 }
1501 bt->interlaced = stdi.interlaced ?
1502 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1503
4a31a93a 1504 if (is_digital_input(sd)) {
54450f59
HV		 1505 timings->type = V4L2_DV_BT_656_1120;
1506
d42010a1 1507 /* FIXME: All masks are incorrect for ADV7611 */
51182a94
LP		 1508 bt->width = hdmi_read16(sd, 0x07, 0xfff);
1509 bt->height = hdmi_read16(sd, 0x09, 0xfff);
d42010a1 1510 bt->pixelclock = info->read_hdmi_pixelclock(sd);
51182a94
LP		 1511 bt->hfrontporch = hdmi_read16(sd, 0x20, 0x3ff);
1512 bt->hsync = hdmi_read16(sd, 0x22, 0x3ff);
1513 bt->hbackporch = hdmi_read16(sd, 0x24, 0x3ff);
1514 bt->vfrontporch = hdmi_read16(sd, 0x2a, 0x1fff) / 2;
1515 bt->vsync = hdmi_read16(sd, 0x2e, 0x1fff) / 2;
1516 bt->vbackporch = hdmi_read16(sd, 0x32, 0x1fff) / 2;
54450f59
HV		 1517 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1518 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1519 if (bt->interlaced == V4L2_DV_INTERLACED) {
51182a94
LP		 1520 bt->height += hdmi_read16(sd, 0x0b, 0xfff);
1521 bt->il_vfrontporch = hdmi_read16(sd, 0x2c, 0x1fff) / 2;
1522 bt->il_vsync = hdmi_read16(sd, 0x30, 0x1fff) / 2;
f8789e6d 1523 bt->il_vbackporch = hdmi_read16(sd, 0x34, 0x1fff) / 2;
54450f59 1524 }
b44b2e06 1525 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1526 } else {
1527 /* find format
80939647 1528 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1529 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1530 */
1531 if (!stdi2dv_timings(sd, &stdi, timings))
1532 goto found;
1533 stdi.lcvs += 1;
1534 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1535 if (!stdi2dv_timings(sd, &stdi, timings))
1536 goto found;
1537 stdi.lcvs -= 2;
1538 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1539 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1540 /*
1541 * The STDI block may measure wrong values, especially
1542 * for lcvs and lcf. If the driver can not find any
1543 * valid timing, the STDI block is restarted to measure
1544 * the video timings again. The function will return an
1545 * error, but the restart of STDI will generate a new
1546 * STDI interrupt and the format detection process will
1547 * restart.
1548 */
1549 if (state->restart_stdi_once) {
1550 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1551 /* TODO restart STDI for Sync Channel 2 */
1552 /* enter one-shot mode */
22d97e56 1553 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1554 /* trigger STDI restart */
22d97e56 1555 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1556 /* reset to continuous mode */
22d97e56 1557 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1558 state->restart_stdi_once = false;
1559 return -ENOLINK;
1560 }
54450f59
HV		 1561 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1562 return -ERANGE;
1563 }
cf9afb1d 1564 state->restart_stdi_once = true;
54450f59
HV		 1565 }
1566found:
1567
1568 if (no_signal(sd)) {
1569 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1570 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1571 return -ENOLINK;
1572 }
1573
4a31a93a
MR		 1574 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1575 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1576 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1577 __func__, (u32)bt->pixelclock);
1578 return -ERANGE;
1579 }
1580
1581 if (debug > 1)
b44b2e06 1582 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
11d034c8 1583 timings, true);
54450f59
HV		 1584
1585 return 0;
1586}
1587
b44b2e06 1588static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1589 struct v4l2_dv_timings *timings)
1590{
b44b2e06 1591 struct adv76xx_state *state = to_state(sd);
54450f59 1592 struct v4l2_bt_timings *bt;
ccbd5bc4 1593 int err;
54450f59
HV		 1594
1595 if (!timings)
1596 return -EINVAL;
1597
d48eb48c
MR		 1598 if (v4l2_match_dv_timings(&state->timings, timings, 0)) {
1599 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1600 return 0;
1601 }
1602
54450f59
HV		 1603 bt = &timings->bt;
1604
4a31a93a
MR		 1605 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1606 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1607 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1608 __func__, (u32)bt->pixelclock);
1609 return -ERANGE;
1610 }
ccbd5bc4 1611
b44b2e06 1612 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1613
1614 state->timings = *timings;
1615
22d97e56 1616 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1617
1618 /* Use prim_mode and vid_std when available */
1619 err = configure_predefined_video_timings(sd, timings);
1620 if (err) {
1621 /* custom settings when the video format
1622 does not have prim_mode/vid_std */
1623 configure_custom_video_timings(sd, bt);
1624 }
54450f59
HV		 1625
1626 set_rgb_quantization_range(sd);
1627
54450f59 1628 if (debug > 1)
b44b2e06 1629 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
11d034c8 1630 timings, true);
54450f59
HV		 1631 return 0;
1632}
1633
b44b2e06 1634static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1635 struct v4l2_dv_timings *timings)
1636{
b44b2e06 1637 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1638
1639 *timings = state->timings;
1640 return 0;
1641}
1642
d42010a1
LPC		 1643static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1644{
1645 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1646}
1647
1648static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1649{
1650 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1651}
1652
6b0d5d34 1653static void enable_input(struct v4l2_subdev *sd)
54450f59 1654{
b44b2e06 1655 struct adv76xx_state *state = to_state(sd);
6b0d5d34 1656
4a31a93a 1657 if (is_analog_input(sd)) {
54450f59 1658 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1659 } else if (is_digital_input(sd)) {
22d97e56 1660 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1661 state->info->set_termination(sd, true);
54450f59 1662 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1663 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1664 } else {
1665 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1666 __func__, state->selected_input);
54450f59
HV		 1667 }
1668}
1669
1670static void disable_input(struct v4l2_subdev *sd)
1671{
b44b2e06 1672 struct adv76xx_state *state = to_state(sd);
d42010a1 1673
22d97e56 1674 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1675 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1676 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1677 state->info->set_termination(sd, false);
54450f59
HV		 1678}
1679
6b0d5d34 1680static void select_input(struct v4l2_subdev *sd)
54450f59 1681{
b44b2e06
PA		 1682 struct adv76xx_state *state = to_state(sd);
1683 const struct adv76xx_chip_info *info = state->info;
54450f59 1684
4a31a93a 1685 if (is_analog_input(sd)) {
b44b2e06 1686 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1687
1688 afe_write(sd, 0x00, 0x08); /* power up ADC */
1689 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1690 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1691 } else if (is_digital_input(sd)) {
1692 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1693
b44b2e06 1694 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
d42010a1 1695
b44b2e06 1696 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1697 afe_write(sd, 0x00, 0xff); /* power down ADC */
1698 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1699 afe_write(sd, 0xc8, 0x40); /* phase control */
1700 }
1701
54450f59
HV		 1702 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1703 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1704 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1705 } else {
1706 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1707 __func__, state->selected_input);
54450f59
HV		 1708 }
1709}
1710
b44b2e06 1711static int adv76xx_s_routing(struct v4l2_subdev *sd,
54450f59
HV		 1712 u32 input, u32 output, u32 config)
1713{
b44b2e06 1714 struct adv76xx_state *state = to_state(sd);
54450f59 1715
ff4f80fd
MR		 1716 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1717 __func__, input, state->selected_input);
1718
1719 if (input == state->selected_input)
1720 return 0;
54450f59 1721
d42010a1
LPC		 1722 if (input > state->info->max_port)
1723 return -EINVAL;
1724
4a31a93a 1725 state->selected_input = input;
54450f59
HV		 1726
1727 disable_input(sd);
1728
6b0d5d34 1729 select_input(sd);
54450f59 1730
6b0d5d34 1731 enable_input(sd);
54450f59
HV		 1732
1733 return 0;
1734}
1735
b44b2e06 1736static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1737 struct v4l2_subdev_pad_config *cfg,
539b33b0 1738 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1739{
b44b2e06 1740 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1741
1742 if (code->index >= state->info->nformats)
54450f59 1743 return -EINVAL;
539b33b0
LP		 1744
1745 code->code = state->info->formats[code->index].code;
1746
54450f59
HV		 1747 return 0;
1748}
1749
b44b2e06 1750static void adv76xx_fill_format(struct adv76xx_state *state,
539b33b0 1751 struct v4l2_mbus_framefmt *format)
54450f59 1752{
539b33b0 1753 memset(format, 0, sizeof(*format));
54450f59 1754
539b33b0
LP		 1755 format->width = state->timings.bt.width;
1756 format->height = state->timings.bt.height;
1757 format->field = V4L2_FIELD_NONE;
1758
1759 if (state->timings.bt.standards & V4L2_DV_BT_STD_CEA861)
1760 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1761 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1762}
1763
1764/*
1765 * Compute the op_ch_sel value required to obtain on the bus the component order
1766 * corresponding to the selected format taking into account bus reordering
1767 * applied by the board at the output of the device.
1768 *
1769 * The following table gives the op_ch_value from the format component order
1770 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
b44b2e06 1771 * adv76xx_bus_order value in row).
539b33b0
LP		 1772 *
1773 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1774 * ----------+-------------------------------------------------
1775 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1776 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1777 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1778 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1779 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1780 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1781 */
b44b2e06 1782static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
539b33b0
LP		 1783{
1784#define _SEL(a,b,c,d,e,f) { \
b44b2e06
PA		 1785 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1786 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
539b33b0
LP		 1787#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1788
1789 static const unsigned int op_ch_sel[6][6] = {
1790 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1791 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1792 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1793 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1794 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1795 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1796 };
1797
1798 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1799}
1800
b44b2e06 1801static void adv76xx_setup_format(struct adv76xx_state *state)
539b33b0
LP		 1802{
1803 struct v4l2_subdev *sd = &state->sd;
1804
22d97e56 1805 io_write_clr_set(sd, 0x02, 0x02,
b44b2e06 1806 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
539b33b0
LP		 1807 io_write(sd, 0x03, state->format->op_format_sel |
1808 state->pdata.op_format_mode_sel);
b44b2e06 1809 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
22d97e56 1810 io_write_clr_set(sd, 0x05, 0x01,
b44b2e06 1811 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
539b33b0
LP		 1812}
1813
f7234138
HV		 1814static int adv76xx_get_format(struct v4l2_subdev *sd,
1815 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1816 struct v4l2_subdev_format *format)
1817{
b44b2e06 1818 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1819
1820 if (format->pad != state->source_pad)
1821 return -EINVAL;
1822
b44b2e06 1823 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1824
1825 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1826 struct v4l2_mbus_framefmt *fmt;
1827
f7234138 1828 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1829 format->format.code = fmt->code;
1830 } else {
1831 format->format.code = state->format->code;
54450f59 1832 }
539b33b0
LP		 1833
1834 return 0;
1835}
1836
f7234138
HV		 1837static int adv76xx_set_format(struct v4l2_subdev *sd,
1838 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1839 struct v4l2_subdev_format *format)
1840{
b44b2e06
PA		 1841 struct adv76xx_state *state = to_state(sd);
1842 const struct adv76xx_format_info *info;
539b33b0
LP		 1843
1844 if (format->pad != state->source_pad)
1845 return -EINVAL;
1846
b44b2e06 1847 info = adv76xx_format_info(state, format->format.code);
539b33b0 1848 if (info == NULL)
b44b2e06 1849 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0 1850
b44b2e06 1851 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1852 format->format.code = info->code;
1853
1854 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1855 struct v4l2_mbus_framefmt *fmt;
1856
f7234138 1857 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1858 fmt->code = format->format.code;
1859 } else {
1860 state->format = info;
b44b2e06 1861 adv76xx_setup_format(state);
539b33b0
LP		 1862 }
1863
54450f59
HV		 1864 return 0;
1865}
1866
b44b2e06 1867static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
54450f59 1868{
b44b2e06
PA		 1869 struct adv76xx_state *state = to_state(sd);
1870 const struct adv76xx_chip_info *info = state->info;
f24d229c
MR		 1871 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1872 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1873 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1874 u8 fmt_change_digital;
1875 u8 fmt_change;
1876 u8 tx_5v;
1877
1878 if (irq_reg_0x43)
1879 io_write(sd, 0x44, irq_reg_0x43);
1880 if (irq_reg_0x70)
1881 io_write(sd, 0x71, irq_reg_0x70);
1882 if (irq_reg_0x6b)
1883 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1884
ff4f80fd
MR		 1885 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1886
54450f59 1887 /* format change */
f24d229c 1888 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1889 fmt_change_digital = is_digital_input(sd)
1890 ? irq_reg_0x6b & info->fmt_change_digital_mask
1891 : 0;
14d03233 1892
54450f59
HV		 1893 if (fmt_change || fmt_change_digital) {
1894 v4l2_dbg(1, debug, sd,
25a64ac9 1895 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1896 __func__, fmt_change, fmt_change_digital);
25a64ac9 1897
b44b2e06 1898 v4l2_subdev_notify(sd, ADV76XX_FMT_CHANGE, NULL);
25a64ac9 1899
54450f59
HV		 1900 if (handled)
1901 *handled = true;
1902 }
f24d229c
MR		 1903 /* HDMI/DVI mode */
1904 if (irq_reg_0x6b & 0x01) {
1905 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1906 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1907 set_rgb_quantization_range(sd);
1908 if (handled)
1909 *handled = true;
1910 }
1911
54450f59 1912 /* tx 5v detect */
d42010a1 1913 tx_5v = io_read(sd, 0x70) & info->cable_det_mask;
54450f59
HV		 1914 if (tx_5v) {
1915 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
1916 io_write(sd, 0x71, tx_5v);
b44b2e06 1917 adv76xx_s_detect_tx_5v_ctrl(sd);
54450f59
HV		 1918 if (handled)
1919 *handled = true;
1920 }
1921 return 0;
1922}
1923
b44b2e06 1924static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1925{
b44b2e06 1926 struct adv76xx_state *state = to_state(sd);
4a31a93a 1927 u8 *data = NULL;
54450f59 1928
dd9ac11a 1929 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1930
1931 switch (edid->pad) {
b44b2e06 1932 case ADV76XX_PAD_HDMI_PORT_A:
c784b1e2
LP		 1933 case ADV7604_PAD_HDMI_PORT_B:
1934 case ADV7604_PAD_HDMI_PORT_C:
1935 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1936 if (state->edid.present & (1 << edid->pad))
1937 data = state->edid.edid;
1938 break;
1939 default:
1940 return -EINVAL;
4a31a93a 1941 }
dd9ac11a
HV		 1942
1943 if (edid->start_block == 0 && edid->blocks == 0) {
1944 edid->blocks = data ? state->edid.blocks : 0;
1945 return 0;
1946 }
1947
1948 if (data == NULL)
4a31a93a
MR		 1949 return -ENODATA;
1950
dd9ac11a
HV		 1951 if (edid->start_block >= state->edid.blocks)
1952 return -EINVAL;
1953
1954 if (edid->start_block + edid->blocks > state->edid.blocks)
1955 edid->blocks = state->edid.blocks - edid->start_block;
1956
1957 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
1958
54450f59
HV		 1959 return 0;
1960}
1961
dd08beb9 1962static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 1963{
1964 u8 d;
1965
1966 if ((edid[0x7e] != 1) ||
1967 (edid[0x80] != 0x02) ||
1968 (edid[0x81] != 0x03)) {
1969 return -1;
1970 }
1971
1972 /* search Vendor Specific Data Block (tag 3) */
1973 d = edid[0x82] & 0x7f;
1974 if (d > 4) {
1975 int i = 0x84;
1976 int end = 0x80 + d;
1977
1978 do {
1979 u8 tag = edid[i] >> 5;
1980 u8 len = edid[i] & 0x1f;
1981
1982 if ((tag == 3) && (len >= 5))
1983 return i + 4;
1984 i += len + 1;
1985 } while (i < end);
1986 }
1987 return -1;
1988}
1989
b44b2e06 1990static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1991{
b44b2e06
PA		 1992 struct adv76xx_state *state = to_state(sd);
1993 const struct adv76xx_chip_info *info = state->info;
dd08beb9 1994 int spa_loc;
54450f59 1995 int err;
dd08beb9 1996 int i;
54450f59 1997
dd9ac11a
HV		 1998 memset(edid->reserved, 0, sizeof(edid->reserved));
1999
c784b1e2 2000 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2001 return -EINVAL;
2002 if (edid->start_block != 0)
2003 return -EINVAL;
2004 if (edid->blocks == 0) {
3e86aa85 2005 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2006 state->edid.present &= ~(1 << edid->pad);
b44b2e06 2007 adv76xx_set_hpd(state, state->edid.present);
22d97e56 2008 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2009
54450f59
HV		 2010 /* Fall back to a 16:9 aspect ratio */
2011 state->aspect_ratio.numerator = 16;
2012 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2013
2014 if (!state->edid.present)
2015 state->edid.blocks = 0;
2016
2017 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2018 __func__, edid->pad, state->edid.present);
54450f59
HV		 2019 return 0;
2020 }
4a31a93a
MR		 2021 if (edid->blocks > 2) {
2022 edid->blocks = 2;
54450f59 2023 return -E2BIG;
4a31a93a 2024 }
4a31a93a 2025
dd08beb9
MR		 2026 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2027 __func__, edid->pad, state->edid.present);
2028
3e86aa85 2029 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2030 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
b44b2e06 2031 adv76xx_set_hpd(state, 0);
22d97e56 2032 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2033
dd08beb9
MR		 2034 spa_loc = get_edid_spa_location(edid->edid);
2035 if (spa_loc < 0)
2036 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2037
3e86aa85 2038 switch (edid->pad) {
b44b2e06 2039 case ADV76XX_PAD_HDMI_PORT_A:
dd08beb9
MR		 2040 state->spa_port_a[0] = edid->edid[spa_loc];
2041 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2042 break;
c784b1e2 2043 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2044 rep_write(sd, 0x70, edid->edid[spa_loc]);
2045 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2046 break;
c784b1e2 2047 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2048 rep_write(sd, 0x72, edid->edid[spa_loc]);
2049 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2050 break;
c784b1e2 2051 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2052 rep_write(sd, 0x74, edid->edid[spa_loc]);
2053 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2054 break;
dd08beb9
MR		 2055 default:
2056 return -EINVAL;
3e86aa85 2057 }
d42010a1
LPC		 2058
2059 if (info->type == ADV7604) {
2060 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2061 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1
LPC		 2062 } else {
2063 /* FIXME: Where is the SPA location LSB register ? */
22d97e56 2064 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2065 }
3e86aa85 2066
dd08beb9
MR		 2067 edid->edid[spa_loc] = state->spa_port_a[0];
2068 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2069
2070 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2071 state->edid.blocks = edid->blocks;
54450f59
HV		 2072 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2073 edid->edid[0x16]);
3e86aa85 2074 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2075
2076 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2077 if (err < 0) {
3e86aa85 2078 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2079 return err;
2080 }
2081
b44b2e06 2082 /* adv76xx calculates the checksums and enables I2C access to internal
dd08beb9 2083 EDID RAM from DDC port. */
22d97e56 2084 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2085
2086 for (i = 0; i < 1000; i++) {
d42010a1 2087 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2088 break;
2089 mdelay(1);
2090 }
2091 if (i == 1000) {
2092 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2093 return -EIO;
2094 }
2095
4a31a93a
MR		 2096 /* enable hotplug after 100 ms */
2097 queue_delayed_work(state->work_queues,
2098 &state->delayed_work_enable_hotplug, HZ / 10);
2099 return 0;
54450f59
HV		 2100}
2101
2102/*********** avi info frame CEA-861-E **************/
2103
2104static void print_avi_infoframe(struct v4l2_subdev *sd)
2105{
2106 int i;
2107 u8 buf[14];
2108 u8 avi_len;
2109 u8 avi_ver;
2110
bb88f325 2111 if (!is_hdmi(sd)) {
54450f59
HV		 2112 v4l2_info(sd, "receive DVI-D signal (AVI infoframe not supported)\n");
2113 return;
2114 }
2115 if (!(io_read(sd, 0x60) & 0x01)) {
2116 v4l2_info(sd, "AVI infoframe not received\n");
2117 return;
2118 }
2119
2120 if (io_read(sd, 0x83) & 0x01) {
2121 v4l2_info(sd, "AVI infoframe checksum error has occurred earlier\n");
2122 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2123 if (io_read(sd, 0x83) & 0x01) {
2124 v4l2_info(sd, "AVI infoframe checksum error still present\n");
2125 io_write(sd, 0x85, 0x01); /* clear AVI_INF_CKS_ERR_RAW */
2126 }
2127 }
2128
2129 avi_len = infoframe_read(sd, 0xe2);
2130 avi_ver = infoframe_read(sd, 0xe1);
2131 v4l2_info(sd, "AVI infoframe version %d (%d byte)\n",
2132 avi_ver, avi_len);
2133
2134 if (avi_ver != 0x02)
2135 return;
2136
2137 for (i = 0; i < 14; i++)
2138 buf[i] = infoframe_read(sd, i);
2139
2140 v4l2_info(sd,
2141 "\t%02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
2142 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7],
2143 buf[8], buf[9], buf[10], buf[11], buf[12], buf[13]);
2144}
2145
b44b2e06 2146static int adv76xx_log_status(struct v4l2_subdev *sd)
54450f59 2147{
b44b2e06
PA		 2148 struct adv76xx_state *state = to_state(sd);
2149 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 2150 struct v4l2_dv_timings timings;
2151 struct stdi_readback stdi;
2152 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2153 u8 edid_enabled;
2154 u8 cable_det;
54450f59 2155
f216ccb3 2156 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2157 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2158 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2159 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2160 "reserved", "reserved", "reserved", "reserved", "manual"
2161 };
f216ccb3 2162 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2163 "RGB limited range (16-235)", "RGB full range (0-255)",
2164 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2165 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2166 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2167 "invalid", "invalid", "invalid", "invalid", "invalid",
2168 "invalid", "invalid", "automatic"
2169 };
f216ccb3 2170 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2171 "Automatic",
2172 "RGB limited range (16-235)",
2173 "RGB full range (0-255)",
2174 };
f216ccb3 2175 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2176 "8-bits per channel",
2177 "10-bits per channel",
2178 "12-bits per channel",
2179 "16-bits per channel (not supported)"
2180 };
54450f59
HV		 2181
2182 v4l2_info(sd, "-----Chip status-----\n");
2183 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2184 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2185 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2186 ((edid_enabled & 0x01) ? "Yes" : "No"),
2187 ((edid_enabled & 0x02) ? "Yes" : "No"),
2188 ((edid_enabled & 0x04) ? "Yes" : "No"),
2189 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2190 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2191 "enabled" : "disabled");
2192
2193 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2194 cable_det = info->read_cable_det(sd);
4a31a93a 2195 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2196 ((cable_det & 0x01) ? "Yes" : "No"),
2197 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2198 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2199 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2200 v4l2_info(sd, "TMDS signal detected: %s\n",
2201 no_signal_tmds(sd) ? "false" : "true");
2202 v4l2_info(sd, "TMDS signal locked: %s\n",
2203 no_lock_tmds(sd) ? "false" : "true");
2204 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2205 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2206 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2207 v4l2_info(sd, "CP free run: %s\n",
58514625 2208 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2209 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2210 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2211 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2212
2213 v4l2_info(sd, "-----Video Timings-----\n");
2214 if (read_stdi(sd, &stdi))
2215 v4l2_info(sd, "STDI: not locked\n");
2216 else
2217 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2218 stdi.lcf, stdi.bl, stdi.lcvs,
2219 stdi.interlaced ? "interlaced" : "progressive",
2220 stdi.hs_pol, stdi.vs_pol);
b44b2e06 2221 if (adv76xx_query_dv_timings(sd, &timings))
54450f59
HV		 2222 v4l2_info(sd, "No video detected\n");
2223 else
11d034c8
HV		 2224 v4l2_print_dv_timings(sd->name, "Detected format: ",
2225 &timings, true);
2226 v4l2_print_dv_timings(sd->name, "Configured format: ",
2227 &state->timings, true);
54450f59 2228
76eb2d30
MR		 2229 if (no_signal(sd))
2230 return 0;
2231
54450f59
HV		 2232 v4l2_info(sd, "-----Color space-----\n");
2233 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2234 rgb_quantization_range_txt[state->rgb_quantization_range]);
2235 v4l2_info(sd, "Input color space: %s\n",
2236 input_color_space_txt[reg_io_0x02 >> 4]);
2237 v4l2_info(sd, "Output color space: %s %s, saturator %s\n",
2238 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2239 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
2240 ((reg_io_0x02 & 0x04) ^ (reg_io_0x02 & 0x01)) ?
76eb2d30 2241 "enabled" : "disabled");
54450f59 2242 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2243 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2244
4a31a93a 2245 if (!is_digital_input(sd))
76eb2d30
MR		 2246 return 0;
2247
2248 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2249 v4l2_info(sd, "Digital video port selected: %c\n",
2250 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2251 v4l2_info(sd, "HDCP encrypted content: %s\n",
2252 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2253 v4l2_info(sd, "HDCP keys read: %s%s\n",
2254 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2255 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2256 if (is_hdmi(sd)) {
76eb2d30
MR		 2257 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2258 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2259 bool audio_mute = io_read(sd, 0x65) & 0x40;
2260
2261 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2262 audio_pll_locked ? "locked" : "not locked",
2263 audio_sample_packet_detect ? "detected" : "not detected",
2264 audio_mute ? "muted" : "enabled");
2265 if (audio_pll_locked && audio_sample_packet_detect) {
2266 v4l2_info(sd, "Audio format: %s\n",
2267 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2268 }
2269 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2270 (hdmi_read(sd, 0x5c) << 8) +
2271 (hdmi_read(sd, 0x5d) & 0xf0));
2272 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2273 (hdmi_read(sd, 0x5e) << 8) +
2274 hdmi_read(sd, 0x5f));
2275 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2276
2277 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2278
54450f59
HV		 2279 print_avi_infoframe(sd);
2280 }
2281
2282 return 0;
2283}
2284
2285/* ----------------------------------------------------------------------- */
2286
b44b2e06
PA		 2287static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2288 .s_ctrl = adv76xx_s_ctrl,
54450f59
HV		 2289};
2290
b44b2e06
PA		 2291static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2292 .log_status = adv76xx_log_status,
2293 .interrupt_service_routine = adv76xx_isr,
54450f59 2294#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06
PA		 2295 .g_register = adv76xx_g_register,
2296 .s_register = adv76xx_s_register,
54450f59
HV		 2297#endif
2298};
2299
b44b2e06
PA		 2300static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2301 .s_routing = adv76xx_s_routing,
2302 .g_input_status = adv76xx_g_input_status,
2303 .s_dv_timings = adv76xx_s_dv_timings,
2304 .g_dv_timings = adv76xx_g_dv_timings,
2305 .query_dv_timings = adv76xx_query_dv_timings,
54450f59
HV		 2306};
2307
b44b2e06
PA		 2308static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2309 .enum_mbus_code = adv76xx_enum_mbus_code,
2310 .get_fmt = adv76xx_get_format,
2311 .set_fmt = adv76xx_set_format,
2312 .get_edid = adv76xx_get_edid,
2313 .set_edid = adv76xx_set_edid,
2314 .dv_timings_cap = adv76xx_dv_timings_cap,
2315 .enum_dv_timings = adv76xx_enum_dv_timings,
54450f59
HV		 2316};
2317
b44b2e06
PA		 2318static const struct v4l2_subdev_ops adv76xx_ops = {
2319 .core = &adv76xx_core_ops,
2320 .video = &adv76xx_video_ops,
2321 .pad = &adv76xx_pad_ops,
54450f59
HV		 2322};
2323
2324/* -------------------------- custom ctrls ---------------------------------- */
2325
2326static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
b44b2e06 2327 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2328 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2329 .name = "Analog Sampling Phase",
2330 .type = V4L2_CTRL_TYPE_INTEGER,
2331 .min = 0,
2332 .max = 0x1f,
2333 .step = 1,
2334 .def = 0,
2335};
2336
b44b2e06
PA		 2337static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2338 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2339 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2340 .name = "Free Running Color, Manual",
2341 .type = V4L2_CTRL_TYPE_BOOLEAN,
2342 .min = false,
2343 .max = true,
2344 .step = 1,
2345 .def = false,
2346};
2347
b44b2e06
PA		 2348static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2349 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2350 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2351 .name = "Free Running Color",
2352 .type = V4L2_CTRL_TYPE_INTEGER,
2353 .min = 0x0,
2354 .max = 0xffffff,
2355 .step = 0x1,
2356 .def = 0x0,
2357};
2358
2359/* ----------------------------------------------------------------------- */
2360
b44b2e06 2361static int adv76xx_core_init(struct v4l2_subdev *sd)
54450f59 2362{
b44b2e06
PA		 2363 struct adv76xx_state *state = to_state(sd);
2364 const struct adv76xx_chip_info *info = state->info;
2365 struct adv76xx_platform_data *pdata = &state->pdata;
54450f59
HV		 2366
2367 hdmi_write(sd, 0x48,
2368 (pdata->disable_pwrdnb ? 0x80 : 0) |
2369 (pdata->disable_cable_det_rst ? 0x40 : 0));
2370
2371 disable_input(sd);
2372
5ef54b59
LP		 2373 if (pdata->default_input >= 0 &&
2374 pdata->default_input < state->source_pad) {
2375 state->selected_input = pdata->default_input;
2376 select_input(sd);
2377 enable_input(sd);
2378 }
2379
54450f59
HV		 2380 /* power */
2381 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2382 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2383 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2384
2385 /* video format */
22d97e56 2386 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2387 pdata->alt_gamma << 3 |
2388 pdata->op_656_range << 2 |
54450f59 2389 pdata->alt_data_sat << 0);
22d97e56 2390 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2391 pdata->insert_av_codes << 2 |
2392 pdata->replicate_av_codes << 1);
b44b2e06 2393 adv76xx_setup_format(state);
54450f59 2394
54450f59 2395 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2396
2397 /* VS, HS polarities */
1b5ab875
LP		 2398 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2399 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2400
2401 /* Adjust drive strength */
2402 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2403 pdata->dr_str_clk << 2 |
2404 pdata->dr_str_sync);
2405
54450f59
HV		 2406 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2407 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2408 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2409 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2410 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2411 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2412 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2413 for digital formats */
2414
5474b983 2415 /* HDMI audio */
22d97e56
LP		 2416 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2417 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2418 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2419
54450f59
HV		 2420 /* TODO from platform data */
2421 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2422
b44b2e06 2423 if (adv76xx_has_afe(state)) {
d42010a1 2424 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2425 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2426 }
54450f59 2427
54450f59 2428 /* interrupts */
d42010a1 2429 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2430 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2431 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2432 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2433 info->setup_irqs(sd);
54450f59
HV		 2434
2435 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2436}
2437
d42010a1
LPC		 2438static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2439{
2440 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2441}
2442
2443static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2444{
2445 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2446}
2447
b44b2e06 2448static void adv76xx_unregister_clients(struct adv76xx_state *state)
54450f59 2449{
05cacb17
LP		 2450 unsigned int i;
2451
2452 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2453 if (state->i2c_clients[i])
2454 i2c_unregister_device(state->i2c_clients[i]);
2455 }
54450f59
HV		 2456}
2457
b44b2e06 2458static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
54450f59
HV		 2459 u8 addr, u8 io_reg)
2460{
2461 struct i2c_client *client = v4l2_get_subdevdata(sd);
2462
2463 if (addr)
2464 io_write(sd, io_reg, addr << 1);
2465 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2466}
2467
b44b2e06 2468static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
d42010a1
LPC		 2469 /* reset ADI recommended settings for HDMI: */
2470 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2471 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2472 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2473 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2474 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2475 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2476 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2477 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2478 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2479 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2480 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2481 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2482 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
d42010a1
LPC		 2483
2484 /* set ADI recommended settings for digitizer */
2485 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2486 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2487 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2488 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2489 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2490 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
d42010a1 2491
b44b2e06 2492 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2493};
2494
b44b2e06 2495static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
d42010a1
LPC		 2496 /* set ADI recommended settings for HDMI: */
2497 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2498 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2499 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2500 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2501 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2502 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2503 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2504 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2505 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2506 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2507 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2508 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
d42010a1
LPC		 2509
2510 /* reset ADI recommended settings for digitizer */
2511 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2512 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2513 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
d42010a1 2514
b44b2e06 2515 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2516};
2517
b44b2e06 2518static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2519 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
b44b2e06
PA		 2520 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2521 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2522 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2523 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2524 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2525 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2526 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2527 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2528 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2529 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2530 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2531
2532 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2533};
2534
b44b2e06 2535static const struct adv76xx_chip_info adv76xx_chip_info[] = {
d42010a1
LPC		 2536 [ADV7604] = {
2537 .type = ADV7604,
2538 .has_afe = true,
c784b1e2 2539 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2540 .num_dv_ports = 4,
2541 .edid_enable_reg = 0x77,
2542 .edid_status_reg = 0x7d,
2543 .lcf_reg = 0xb3,
2544 .tdms_lock_mask = 0xe0,
2545 .cable_det_mask = 0x1e,
2546 .fmt_change_digital_mask = 0xc1,
80f4944e 2547 .cp_csc = 0xfc,
539b33b0
LP		 2548 .formats = adv7604_formats,
2549 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2550 .set_termination = adv7604_set_termination,
2551 .setup_irqs = adv7604_setup_irqs,
2552 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2553 .read_cable_det = adv7604_read_cable_det,
2554 .recommended_settings = {
2555 [0] = adv7604_recommended_settings_afe,
2556 [1] = adv7604_recommended_settings_hdmi,
2557 },
2558 .num_recommended_settings = {
2559 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2560 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2561 },
b44b2e06
PA		 2562 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2563 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
d42010a1 2564 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
b44b2e06
PA		 2565 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2566 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2567 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
d42010a1
LPC		 2568 BIT(ADV7604_PAGE_VDP),
2569 },
2570 [ADV7611] = {
2571 .type = ADV7611,
2572 .has_afe = false,
b44b2e06 2573 .max_port = ADV76XX_PAD_HDMI_PORT_A,
d42010a1
LPC		 2574 .num_dv_ports = 1,
2575 .edid_enable_reg = 0x74,
2576 .edid_status_reg = 0x76,
2577 .lcf_reg = 0xa3,
2578 .tdms_lock_mask = 0x43,
2579 .cable_det_mask = 0x01,
2580 .fmt_change_digital_mask = 0x03,
80f4944e 2581 .cp_csc = 0xf4,
539b33b0
LP		 2582 .formats = adv7611_formats,
2583 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2584 .set_termination = adv7611_set_termination,
2585 .setup_irqs = adv7611_setup_irqs,
2586 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2587 .read_cable_det = adv7611_read_cable_det,
2588 .recommended_settings = {
2589 [1] = adv7611_recommended_settings_hdmi,
2590 },
2591 .num_recommended_settings = {
2592 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2593 },
b44b2e06
PA		 2594 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2595 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2596 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2597 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
d42010a1
LPC		 2598 },
2599};
2600
b44b2e06
PA		 2601static struct i2c_device_id adv76xx_i2c_id[] = {
2602 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2603 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
f82f313e
LP		 2604 { }
2605};
b44b2e06 2606MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
f82f313e 2607
b44b2e06
PA		 2608static struct of_device_id adv76xx_of_id[] __maybe_unused = {
2609 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
f82f313e
LP		 2610 { }
2611};
b44b2e06 2612MODULE_DEVICE_TABLE(of, adv76xx_of_id);
f82f313e 2613
b44b2e06 2614static int adv76xx_parse_dt(struct adv76xx_state *state)
f82f313e 2615{
6fa88045
LP		 2616 struct v4l2_of_endpoint bus_cfg;
2617 struct device_node *endpoint;
2618 struct device_node *np;
2619 unsigned int flags;
2620
b44b2e06 2621 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
6fa88045
LP		 2622
2623 /* Parse the endpoint. */
2624 endpoint = of_graph_get_next_endpoint(np, NULL);
2625 if (!endpoint)
2626 return -EINVAL;
2627
2628 v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2629 of_node_put(endpoint);
2630
2631 flags = bus_cfg.bus.parallel.flags;
2632
2633 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2634 state->pdata.inv_hs_pol = 1;
2635
2636 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2637 state->pdata.inv_vs_pol = 1;
2638
2639 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2640 state->pdata.inv_llc_pol = 1;
2641
2642 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2643 state->pdata.insert_av_codes = 1;
2644 state->pdata.op_656_range = 1;
2645 }
2646
f82f313e 2647 /* Disable the interrupt for now as no DT-based board uses it. */
b44b2e06 2648 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
f82f313e
LP		 2649
2650 /* Use the default I2C addresses. */
2651 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
b44b2e06
PA		 2652 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2653 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
f82f313e
LP		 2654 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2655 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
b44b2e06
PA		 2656 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2657 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2658 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2659 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2660 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2661 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
f82f313e
LP		 2662 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2663
2664 /* Hardcode the remaining platform data fields. */
2665 state->pdata.disable_pwrdnb = 0;
2666 state->pdata.disable_cable_det_rst = 0;
2667 state->pdata.default_input = -1;
2668 state->pdata.blank_data = 1;
f82f313e 2669 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2670 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2671 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2672
2673 return 0;
2674}
2675
b44b2e06 2676static int adv76xx_probe(struct i2c_client *client,
54450f59
HV		 2677 const struct i2c_device_id *id)
2678{
591b72fe
HV		 2679 static const struct v4l2_dv_timings cea640x480 =
2680 V4L2_DV_BT_CEA_640X480P59_94;
b44b2e06 2681 struct adv76xx_state *state;
54450f59
HV		 2682 struct v4l2_ctrl_handler *hdl;
2683 struct v4l2_subdev *sd;
c784b1e2 2684 unsigned int i;
d42010a1 2685 u16 val;
54450f59
HV		 2686 int err;
2687
2688 /* Check if the adapter supports the needed features */
2689 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
2690 return -EIO;
b44b2e06 2691 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
54450f59
HV		 2692 client->addr << 1);
2693
c02b211d 2694 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59 2695 if (!state) {
b44b2e06 2696 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
54450f59
HV		 2697 return -ENOMEM;
2698 }
2699
b44b2e06 2700 state->i2c_clients[ADV76XX_PAGE_IO] = client;
d42010a1 2701
25a64ac9
MR		 2702 /* initialize variables */
2703 state->restart_stdi_once = true;
ff4f80fd 2704 state->selected_input = ~0;
25a64ac9 2705
f82f313e
LP		 2706 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
2707 const struct of_device_id *oid;
2708
b44b2e06 2709 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
f82f313e
LP		 2710 state->info = oid->data;
2711
b44b2e06 2712 err = adv76xx_parse_dt(state);
f82f313e
LP		 2713 if (err < 0) {
2714 v4l_err(client, "DT parsing error\n");
2715 return err;
2716 }
2717 } else if (client->dev.platform_data) {
b44b2e06 2718 struct adv76xx_platform_data *pdata = client->dev.platform_data;
f82f313e 2719
b44b2e06 2720 state->info = (const struct adv76xx_chip_info *)id->driver_data;
f82f313e
LP		 2721 state->pdata = *pdata;
2722 } else {
54450f59 2723 v4l_err(client, "No platform data!\n");
c02b211d 2724 return -ENODEV;
54450f59 2725 }
e9d50e9e
LP		 2726
2727 /* Request GPIOs. */
2728 for (i = 0; i < state->info->num_dv_ports; ++i) {
2729 state->hpd_gpio[i] =
269bd132
UKK		 2730 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
2731 GPIOD_OUT_LOW);
e9d50e9e 2732 if (IS_ERR(state->hpd_gpio[i]))
269bd132 2733 return PTR_ERR(state->hpd_gpio[i]);
e9d50e9e 2734
269bd132
UKK		 2735 if (state->hpd_gpio[i])
2736 v4l_info(client, "Handling HPD %u GPIO\n", i);
e9d50e9e
LP		 2737 }
2738
591b72fe 2739 state->timings = cea640x480;
b44b2e06 2740 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 2741
2742 sd = &state->sd;
b44b2e06 2743 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
d42010a1
LPC		 2744 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
2745 id->name, i2c_adapter_id(client->adapter),
2746 client->addr);
54450f59 2747 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
54450f59 2748
d42010a1
LPC		 2749 /*
2750 * Verify that the chip is present. On ADV7604 the RD_INFO register only
2751 * identifies the revision, while on ADV7611 it identifies the model as
2752 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
2753 */
2754 if (state->info->type == ADV7604) {
2755 val = adv_smbus_read_byte_data_check(client, 0xfb, false);
2756 if (val != 0x68) {
2757 v4l2_info(sd, "not an adv7604 on address 0x%x\n",
2758 client->addr << 1);
2759 return -ENODEV;
2760 }
2761 } else {
2762 val = (adv_smbus_read_byte_data_check(client, 0xea, false) << 8)
2763 | (adv_smbus_read_byte_data_check(client, 0xeb, false) << 0);
2764 if (val != 0x2051) {
2765 v4l2_info(sd, "not an adv7611 on address 0x%x\n",
2766 client->addr << 1);
2767 return -ENODEV;
2768 }
54450f59
HV		 2769 }
2770
2771 /* control handlers */
2772 hdl = &state->hdl;
b44b2e06 2773 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
54450f59 2774
b44b2e06 2775 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 2776 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
b44b2e06 2777 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 2778 V4L2_CID_CONTRAST, 0, 255, 1, 128);
b44b2e06 2779 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 2780 V4L2_CID_SATURATION, 0, 255, 1, 128);
b44b2e06 2781 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 2782 V4L2_CID_HUE, 0, 128, 1, 0);
2783
2784 /* private controls */
2785 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 2786 V4L2_CID_DV_RX_POWER_PRESENT, 0,
2787 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59 2788 state->rgb_quantization_range_ctrl =
b44b2e06 2789 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 2790 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
2791 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 2792
2793 /* custom controls */
b44b2e06 2794 if (adv76xx_has_afe(state))
d42010a1
LPC		 2795 state->analog_sampling_phase_ctrl =
2796 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59 2797 state->free_run_color_manual_ctrl =
b44b2e06 2798 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
54450f59 2799 state->free_run_color_ctrl =
b44b2e06 2800 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
54450f59
HV		 2801
2802 sd->ctrl_handler = hdl;
2803 if (hdl->error) {
2804 err = hdl->error;
2805 goto err_hdl;
2806 }
8c0eadb8
HV		 2807 state->detect_tx_5v_ctrl->is_private = true;
2808 state->rgb_quantization_range_ctrl->is_private = true;
b44b2e06 2809 if (adv76xx_has_afe(state))
d42010a1 2810 state->analog_sampling_phase_ctrl->is_private = true;
8c0eadb8
HV		 2811 state->free_run_color_manual_ctrl->is_private = true;
2812 state->free_run_color_ctrl->is_private = true;
2813
b44b2e06 2814 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
54450f59
HV		 2815 err = -ENODEV;
2816 goto err_hdl;
2817 }
2818
b44b2e06 2819 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
05cacb17
LP		 2820 if (!(BIT(i) & state->info->page_mask))
2821 continue;
54450f59 2822
05cacb17 2823 state->i2c_clients[i] =
b44b2e06 2824 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 2825 0xf2 + i);
2826 if (state->i2c_clients[i] == NULL) {
d42010a1 2827 err = -ENOMEM;
05cacb17 2828 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 2829 goto err_i2c;
2830 }
2831 }
05cacb17 2832
54450f59
HV		 2833 /* work queues */
2834 state->work_queues = create_singlethread_workqueue(client->name);
2835 if (!state->work_queues) {
2836 v4l2_err(sd, "Could not create work queue\n");
2837 err = -ENOMEM;
2838 goto err_i2c;
2839 }
2840
2841 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
b44b2e06 2842 adv76xx_delayed_work_enable_hotplug);
54450f59 2843
c784b1e2
LP		 2844 state->source_pad = state->info->num_dv_ports
2845 + (state->info->has_afe ? 2 : 0);
2846 for (i = 0; i < state->source_pad; ++i)
2847 state->pads[i].flags = MEDIA_PAD_FL_SINK;
2848 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
2849
2850 err = media_entity_init(&sd->entity, state->source_pad + 1,
2851 state->pads, 0);
54450f59
HV		 2852 if (err)
2853 goto err_work_queues;
2854
b44b2e06 2855 err = adv76xx_core_init(sd);
54450f59
HV		 2856 if (err)
2857 goto err_entity;
2858 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
2859 client->addr << 1, client->adapter->name);
bedc3939
LPC		 2860
2861 err = v4l2_async_register_subdev(sd);
2862 if (err)
2863 goto err_entity;
2864
54450f59
HV		 2865 return 0;
2866
2867err_entity:
2868 media_entity_cleanup(&sd->entity);
2869err_work_queues:
2870 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2871 destroy_workqueue(state->work_queues);
2872err_i2c:
b44b2e06 2873 adv76xx_unregister_clients(state);
54450f59
HV		 2874err_hdl:
2875 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 2876 return err;
2877}
2878
2879/* ----------------------------------------------------------------------- */
2880
b44b2e06 2881static int adv76xx_remove(struct i2c_client *client)
54450f59
HV		 2882{
2883 struct v4l2_subdev *sd = i2c_get_clientdata(client);
b44b2e06 2884 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 2885
2886 cancel_delayed_work(&state->delayed_work_enable_hotplug);
2887 destroy_workqueue(state->work_queues);
bedc3939 2888 v4l2_async_unregister_subdev(sd);
54450f59 2889 media_entity_cleanup(&sd->entity);
b44b2e06 2890 adv76xx_unregister_clients(to_state(sd));
54450f59 2891 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 2892 return 0;
2893}
2894
2895/* ----------------------------------------------------------------------- */
2896
b44b2e06 2897static struct i2c_driver adv76xx_driver = {
54450f59
HV		 2898 .driver = {
2899 .owner = THIS_MODULE,
2900 .name = "adv7604",
b44b2e06 2901 .of_match_table = of_match_ptr(adv76xx_of_id),
54450f59 2902 },
b44b2e06
PA		 2903 .probe = adv76xx_probe,
2904 .remove = adv76xx_remove,
2905 .id_table = adv76xx_i2c_id,
54450f59
HV		 2906};
2907
b44b2e06 2908module_i2c_driver(adv76xx_driver);
Linux kernel - Deliverables
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