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Merge tag 'v4.7-rc6' into patchwork
[deliverable/linux.git] / drivers / media / i2c / adv7604.c
CommitLineData
54450f59
HV		 1/*
2 * adv7604 - Analog Devices ADV7604 video decoder driver
3 *
4 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
5 *
6 * This program is free software; you may redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
11 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
12 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
13 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
14 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
15 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
16 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
17 * SOFTWARE.
18 *
19 */
20
21/*
22 * References (c = chapter, p = page):
23 * REF_01 - Analog devices, ADV7604, Register Settings Recommendations,
24 * Revision 2.5, June 2010
25 * REF_02 - Analog devices, Register map documentation, Documentation of
26 * the register maps, Software manual, Rev. F, June 2010
27 * REF_03 - Analog devices, ADV7604, Hardware Manual, Rev. F, August 2010
28 */
29
c72a53ce 30#include <linux/delay.h>
e9d50e9e 31#include <linux/gpio/consumer.h>
516613c1 32#include <linux/hdmi.h>
c72a53ce 33#include <linux/i2c.h>
54450f59
HV		 34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/slab.h>
c72a53ce 37#include <linux/v4l2-dv-timings.h>
54450f59
HV		 38#include <linux/videodev2.h>
39#include <linux/workqueue.h>
f862f57d 40#include <linux/regmap.h>
c72a53ce 41
b5dcee22 42#include <media/i2c/adv7604.h>
54450f59 43#include <media/v4l2-ctrls.h>
c72a53ce 44#include <media/v4l2-device.h>
0975626d 45#include <media/v4l2-event.h>
25764158 46#include <media/v4l2-dv-timings.h>
6fa88045 47#include <media/v4l2-of.h>
54450f59
HV		 48
49static int debug;
50module_param(debug, int, 0644);
51MODULE_PARM_DESC(debug, "debug level (0-2)");
52
53MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
54MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
55MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
56MODULE_LICENSE("GPL");
57
58/* ADV7604 system clock frequency */
b44b2e06 59#define ADV76XX_FSC (28636360)
54450f59 60
b44b2e06 61#define ADV76XX_RGB_OUT (1 << 1)
539b33b0 62
b44b2e06 63#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
539b33b0 64#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
b44b2e06 65#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
539b33b0 66
b44b2e06 67#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
539b33b0 68#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
b44b2e06 69#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
539b33b0 70#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
b44b2e06 71#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
539b33b0
LP		 72#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
73
b44b2e06
PA		 74#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
75#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
76#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
77#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
78#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
79#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
539b33b0 80
b44b2e06 81#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
539b33b0 82
b44b2e06 83enum adv76xx_type {
d42010a1
LPC		 84 ADV7604,
85 ADV7611,
8331d30b 86 ADV7612,
d42010a1
LPC		 87};
88
b44b2e06 89struct adv76xx_reg_seq {
d42010a1
LPC		 90 unsigned int reg;
91 u8 val;
92};
93
b44b2e06 94struct adv76xx_format_info {
f5fe58fd 95 u32 code;
539b33b0
LP		 96 u8 op_ch_sel;
97 bool rgb_out;
98 bool swap_cb_cr;
99 u8 op_format_sel;
100};
101
516613c1
HV		 102struct adv76xx_cfg_read_infoframe {
103 const char *desc;
104 u8 present_mask;
105 u8 head_addr;
106 u8 payload_addr;
107};
108
b44b2e06
PA		 109struct adv76xx_chip_info {
110 enum adv76xx_type type;
d42010a1
LPC		 111
112 bool has_afe;
113 unsigned int max_port;
114 unsigned int num_dv_ports;
115
116 unsigned int edid_enable_reg;
117 unsigned int edid_status_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
80f4944e 123 unsigned int cp_csc;
d42010a1 124
b44b2e06 125 const struct adv76xx_format_info *formats;
539b33b0
LP		 126 unsigned int nformats;
127
d42010a1
LPC		 128 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
129 void (*setup_irqs)(struct v4l2_subdev *sd);
130 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
131 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
132
133 /* 0 = AFE, 1 = HDMI */
b44b2e06 134 const struct adv76xx_reg_seq *recommended_settings[2];
d42010a1
LPC		 135 unsigned int num_recommended_settings[2];
136
137 unsigned long page_mask;
5380baaf 138
139 /* Masks for timings */
140 unsigned int linewidth_mask;
141 unsigned int field0_height_mask;
142 unsigned int field1_height_mask;
143 unsigned int hfrontporch_mask;
144 unsigned int hsync_mask;
145 unsigned int hbackporch_mask;
146 unsigned int field0_vfrontporch_mask;
147 unsigned int field1_vfrontporch_mask;
148 unsigned int field0_vsync_mask;
149 unsigned int field1_vsync_mask;
150 unsigned int field0_vbackporch_mask;
151 unsigned int field1_vbackporch_mask;
d42010a1
LPC		 152};
153
54450f59
HV		 154/*
155 **********************************************************************
156 *
157 * Arrays with configuration parameters for the ADV7604
158 *
159 **********************************************************************
160 */
c784b1e2 161
b44b2e06
PA		 162struct adv76xx_state {
163 const struct adv76xx_chip_info *info;
164 struct adv76xx_platform_data pdata;
539b33b0 165
e9d50e9e 166 struct gpio_desc *hpd_gpio[4];
f5591da9 167 struct gpio_desc *reset_gpio;
e9d50e9e 168
54450f59 169 struct v4l2_subdev sd;
b44b2e06 170 struct media_pad pads[ADV76XX_PAD_MAX];
c784b1e2 171 unsigned int source_pad;
539b33b0 172
54450f59 173 struct v4l2_ctrl_handler hdl;
539b33b0 174
b44b2e06 175 enum adv76xx_pad selected_input;
539b33b0 176
54450f59 177 struct v4l2_dv_timings timings;
b44b2e06 178 const struct adv76xx_format_info *format;
539b33b0 179
4a31a93a
MR		 180 struct {
181 u8 edid[256];
182 u32 present;
183 unsigned blocks;
184 } edid;
dd08beb9 185 u16 spa_port_a[2];
54450f59
HV		 186 struct v4l2_fract aspect_ratio;
187 u32 rgb_quantization_range;
54450f59 188 struct delayed_work delayed_work_enable_hotplug;
cf9afb1d 189 bool restart_stdi_once;
54450f59
HV		 190
191 /* i2c clients */
b44b2e06 192 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
54450f59 193
f862f57d
PA		 194 /* Regmaps */
195 struct regmap *regmap[ADV76XX_PAGE_MAX];
196
54450f59
HV		 197 /* controls */
198 struct v4l2_ctrl *detect_tx_5v_ctrl;
199 struct v4l2_ctrl *analog_sampling_phase_ctrl;
200 struct v4l2_ctrl *free_run_color_manual_ctrl;
201 struct v4l2_ctrl *free_run_color_ctrl;
202 struct v4l2_ctrl *rgb_quantization_range_ctrl;
203};
204
b44b2e06 205static bool adv76xx_has_afe(struct adv76xx_state *state)
d42010a1
LPC		 206{
207 return state->info->has_afe;
208}
209
bd3e275f
JMH		 210/* Unsupported timings. This device cannot support 720p30. */
211static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
212 V4L2_DV_BT_CEA_1280X720P30,
213 { }
54450f59
HV		 214};
215
bd3e275f
JMH		 216static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
217{
218 int i;
219
220 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
221 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
222 return false;
223 return true;
224}
225
b44b2e06 226struct adv76xx_video_standards {
ccbd5bc4
HV		 227 struct v4l2_dv_timings timings;
228 u8 vid_std;
229 u8 v_freq;
230};
231
232/* sorted by number of lines */
b44b2e06 233static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
ccbd5bc4
HV		 234 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */
235 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
236 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
237 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
238 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
239 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
240 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
241 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
242 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
243 /* TODO add 1920x1080P60_RB (CVT timing) */
244 { },
245};
246
247/* sorted by number of lines */
b44b2e06 248static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
ccbd5bc4
HV		 249 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
250 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
251 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
252 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
253 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
254 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
255 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
256 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
257 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
258 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
259 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
260 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
261 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
262 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
263 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
264 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
265 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
266 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
267 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
268 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */
269 /* TODO add 1600X1200P60_RB (not a DMT timing) */
270 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
271 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */
272 { },
273};
274
275/* sorted by number of lines */
b44b2e06 276static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
ccbd5bc4
HV		 277 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
278 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
279 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
280 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
281 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
282 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
283 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
284 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
285 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
286 { },
287};
288
289/* sorted by number of lines */
b44b2e06 290static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
ccbd5bc4
HV		 291 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
292 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
293 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
294 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
295 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
296 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
297 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
298 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
299 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
300 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
301 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
302 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
303 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
304 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
305 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
306 { },
307};
308
48519838
HV		 309static const struct v4l2_event adv76xx_ev_fmt = {
310 .type = V4L2_EVENT_SOURCE_CHANGE,
311 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
312};
313
54450f59
HV		 314/* ----------------------------------------------------------------------- */
315
b44b2e06 316static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
54450f59 317{
b44b2e06 318 return container_of(sd, struct adv76xx_state, sd);
54450f59
HV		 319}
320
54450f59
HV		 321static inline unsigned htotal(const struct v4l2_bt_timings *t)
322{
eacf8f9a 323 return V4L2_DV_BT_FRAME_WIDTH(t);
54450f59
HV		 324}
325
54450f59
HV		 326static inline unsigned vtotal(const struct v4l2_bt_timings *t)
327{
eacf8f9a 328 return V4L2_DV_BT_FRAME_HEIGHT(t);
54450f59
HV		 329}
330
331/* ----------------------------------------------------------------------- */
332
f862f57d
PA		 333static int adv76xx_read_check(struct adv76xx_state *state,
334 int client_page, u8 reg)
54450f59 335{
f862f57d 336 struct i2c_client *client = state->i2c_clients[client_page];
54450f59 337 int err;
f862f57d 338 unsigned int val;
54450f59 339
f862f57d
PA		 340 err = regmap_read(state->regmap[client_page], reg, &val);
341
342 if (err) {
343 v4l_err(client, "error reading %02x, %02x\n",
344 client->addr, reg);
345 return err;
54450f59 346 }
f862f57d 347 return val;
54450f59
HV		 348}
349
f862f57d
PA		 350/* adv76xx_write_block(): Write raw data with a maximum of I2C_SMBUS_BLOCK_MAX
351 * size to one or more registers.
352 *
353 * A value of zero will be returned on success, a negative errno will
354 * be returned in error cases.
355 */
356static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
357 unsigned int init_reg, const void *val,
358 size_t val_len)
54450f59 359{
f862f57d
PA		 360 struct regmap *regmap = state->regmap[client_page];
361
362 if (val_len > I2C_SMBUS_BLOCK_MAX)
363 val_len = I2C_SMBUS_BLOCK_MAX;
54450f59 364
f862f57d 365 return regmap_raw_write(regmap, init_reg, val, val_len);
54450f59
HV		 366}
367
368/* ----------------------------------------------------------------------- */
369
370static inline int io_read(struct v4l2_subdev *sd, u8 reg)
371{
b44b2e06 372 struct adv76xx_state *state = to_state(sd);
54450f59 373
f862f57d 374 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
54450f59
HV		 375}
376
377static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
378{
b44b2e06 379 struct adv76xx_state *state = to_state(sd);
54450f59 380
f862f57d 381 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
54450f59
HV		 382}
383
22d97e56 384static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 385{
22d97e56 386 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
54450f59
HV		 387}
388
389static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
390{
b44b2e06 391 struct adv76xx_state *state = to_state(sd);
54450f59 392
f862f57d 393 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
54450f59
HV		 394}
395
396static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
397{
b44b2e06 398 struct adv76xx_state *state = to_state(sd);
54450f59 399
f862f57d 400 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
54450f59
HV		 401}
402
403static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
404{
b44b2e06 405 struct adv76xx_state *state = to_state(sd);
54450f59 406
f862f57d 407 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
54450f59
HV		 408}
409
410static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
411{
b44b2e06 412 struct adv76xx_state *state = to_state(sd);
54450f59 413
f862f57d 414 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
54450f59
HV		 415}
416
54450f59
HV		 417static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
418{
b44b2e06 419 struct adv76xx_state *state = to_state(sd);
54450f59 420
f862f57d 421 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
54450f59
HV		 422}
423
424static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
425{
b44b2e06 426 struct adv76xx_state *state = to_state(sd);
54450f59 427
f862f57d 428 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
54450f59
HV		 429}
430
54450f59
HV		 431static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
432{
b44b2e06 433 struct adv76xx_state *state = to_state(sd);
54450f59 434
f862f57d 435 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
54450f59
HV		 436}
437
438static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
439{
b44b2e06 440 struct adv76xx_state *state = to_state(sd);
54450f59 441
f862f57d 442 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
54450f59
HV		 443}
444
445static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
446{
b44b2e06 447 struct adv76xx_state *state = to_state(sd);
54450f59 448
f862f57d 449 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
54450f59
HV		 450}
451
452static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
453{
b44b2e06 454 struct adv76xx_state *state = to_state(sd);
54450f59 455
f862f57d 456 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
54450f59
HV		 457}
458
22d97e56 459static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 460{
22d97e56 461 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
54450f59
HV		 462}
463
464static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
465{
b44b2e06 466 struct adv76xx_state *state = to_state(sd);
54450f59 467
f862f57d 468 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
54450f59
HV		 469}
470
471static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
472{
b44b2e06 473 struct adv76xx_state *state = to_state(sd);
54450f59 474
f862f57d 475 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
54450f59
HV		 476}
477
54450f59 478static inline int edid_write_block(struct v4l2_subdev *sd,
f862f57d 479 unsigned int total_len, const u8 *val)
54450f59 480{
b44b2e06 481 struct adv76xx_state *state = to_state(sd);
54450f59 482 int err = 0;
f862f57d
PA		 483 int i = 0;
484 int len = 0;
54450f59 485
f862f57d
PA		 486 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
487 __func__, total_len);
488
489 while (!err && i < total_len) {
490 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
491 I2C_SMBUS_BLOCK_MAX :
492 (total_len - i);
493
494 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
495 i, val + i, len);
496 i += len;
497 }
54450f59 498
dd08beb9
MR		 499 return err;
500}
54450f59 501
b44b2e06 502static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
e9d50e9e
LP		 503{
504 unsigned int i;
505
269bd132 506 for (i = 0; i < state->info->num_dv_ports; ++i)
e9d50e9e 507 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
e9d50e9e 508
b44b2e06 509 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
e9d50e9e
LP		 510}
511
b44b2e06 512static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
dd08beb9
MR		 513{
514 struct delayed_work *dwork = to_delayed_work(work);
b44b2e06 515 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
dd08beb9
MR		 516 delayed_work_enable_hotplug);
517 struct v4l2_subdev *sd = &state->sd;
54450f59 518
dd08beb9 519 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
54450f59 520
b44b2e06 521 adv76xx_set_hpd(state, state->edid.present);
54450f59
HV		 522}
523
524static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
525{
b44b2e06 526 struct adv76xx_state *state = to_state(sd);
54450f59 527
f862f57d 528 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
54450f59
HV		 529}
530
51182a94
LP		 531static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
532{
533 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
534}
535
54450f59
HV		 536static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
537{
b44b2e06 538 struct adv76xx_state *state = to_state(sd);
54450f59 539
f862f57d 540 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
54450f59
HV		 541}
542
22d97e56 543static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
4a31a93a 544{
22d97e56 545 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
4a31a93a
MR		 546}
547
54450f59
HV		 548static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
549{
b44b2e06 550 struct adv76xx_state *state = to_state(sd);
54450f59 551
f862f57d 552 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
54450f59
HV		 553}
554
555static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
556{
b44b2e06 557 struct adv76xx_state *state = to_state(sd);
54450f59 558
f862f57d 559 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
54450f59
HV		 560}
561
51182a94
LP		 562static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
563{
564 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
565}
566
54450f59
HV		 567static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
568{
b44b2e06 569 struct adv76xx_state *state = to_state(sd);
54450f59 570
f862f57d 571 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
54450f59
HV		 572}
573
22d97e56 574static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
54450f59 575{
22d97e56 576 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
54450f59
HV		 577}
578
579static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
580{
b44b2e06 581 struct adv76xx_state *state = to_state(sd);
54450f59 582
f862f57d 583 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
54450f59
HV		 584}
585
586static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
587{
b44b2e06 588 struct adv76xx_state *state = to_state(sd);
54450f59 589
f862f57d 590 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
05cacb17 591}
d42010a1 592
b44b2e06
PA		 593#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
594#define ADV76XX_REG_SEQ_TERM 0xffff
d42010a1
LPC		 595
596#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 597static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
d42010a1 598{
b44b2e06 599 struct adv76xx_state *state = to_state(sd);
d42010a1 600 unsigned int page = reg >> 8;
f862f57d
PA		 601 unsigned int val;
602 int err;
d42010a1
LPC		 603
604 if (!(BIT(page) & state->info->page_mask))
605 return -EINVAL;
606
607 reg &= 0xff;
f862f57d 608 err = regmap_read(state->regmap[page], reg, &val);
d42010a1 609
f862f57d 610 return err ? err : val;
d42010a1
LPC		 611}
612#endif
613
b44b2e06 614static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
d42010a1 615{
b44b2e06 616 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 617 unsigned int page = reg >> 8;
618
619 if (!(BIT(page) & state->info->page_mask))
620 return -EINVAL;
621
622 reg &= 0xff;
623
f862f57d 624 return regmap_write(state->regmap[page], reg, val);
d42010a1
LPC		 625}
626
b44b2e06
PA		 627static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
628 const struct adv76xx_reg_seq *reg_seq)
d42010a1
LPC		 629{
630 unsigned int i;
631
b44b2e06
PA		 632 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
633 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
d42010a1
LPC		 634}
635
539b33b0
LP		 636/* -----------------------------------------------------------------------------
637 * Format helpers
638 */
639
b44b2e06
PA		 640static const struct adv76xx_format_info adv7604_formats[] = {
641 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
642 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
643 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
644 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
645 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
646 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
647 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
648 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
649 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
650 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
651 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
652 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
653 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
654 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
655 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
656 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
657 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
658 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
659 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
660 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
661 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
662 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
663 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
664 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
665 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
666 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
667 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
668 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
669 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
670 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
671 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
672 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
673 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
674 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
675 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
676 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
677 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
678 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 679};
680
b44b2e06
PA		 681static const struct adv76xx_format_info adv7611_formats[] = {
682 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
683 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
684 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
685 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
686 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
687 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
688 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
689 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
690 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
691 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
692 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
693 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
694 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
695 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
696 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
697 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
698 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
699 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
700 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
701 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
702 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
704 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
705 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
706 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
707 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
539b33b0
LP		 708};
709
8331d30b
WT		 710static const struct adv76xx_format_info adv7612_formats[] = {
711 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
712 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
713 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
714 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
715 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
716 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
717 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
719 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
721 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
723 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
725};
726
b44b2e06
PA		 727static const struct adv76xx_format_info *
728adv76xx_format_info(struct adv76xx_state *state, u32 code)
539b33b0
LP		 729{
730 unsigned int i;
731
732 for (i = 0; i < state->info->nformats; ++i) {
733 if (state->info->formats[i].code == code)
734 return &state->info->formats[i];
735 }
736
737 return NULL;
738}
739
54450f59
HV		 740/* ----------------------------------------------------------------------- */
741
4a31a93a
MR		 742static inline bool is_analog_input(struct v4l2_subdev *sd)
743{
b44b2e06 744 struct adv76xx_state *state = to_state(sd);
4a31a93a 745
c784b1e2
LP		 746 return state->selected_input == ADV7604_PAD_VGA_RGB ||
747 state->selected_input == ADV7604_PAD_VGA_COMP;
4a31a93a
MR		 748}
749
750static inline bool is_digital_input(struct v4l2_subdev *sd)
751{
b44b2e06 752 struct adv76xx_state *state = to_state(sd);
4a31a93a 753
b44b2e06 754 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
c784b1e2
LP		 755 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
756 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
757 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
4a31a93a
MR		 758}
759
bd3e275f
JMH		 760static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
761 .type = V4L2_DV_BT_656_1120,
762 /* keep this initialization for compatibility with GCC < 4.4.6 */
763 .reserved = { 0 },
764 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
765 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
766 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
767 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
768 V4L2_DV_BT_CAP_CUSTOM)
769};
770
771static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
772 .type = V4L2_DV_BT_656_1120,
773 /* keep this initialization for compatibility with GCC < 4.4.6 */
774 .reserved = { 0 },
775 V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
776 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
777 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
778 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
779 V4L2_DV_BT_CAP_CUSTOM)
780};
781
9c41e690
LP		 782/*
783 * Return the DV timings capabilities for the requested sink pad. As a special
784 * case, pad value -1 returns the capabilities for the currently selected input.
785 */
786static const struct v4l2_dv_timings_cap *
787adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
bd3e275f 788{
9c41e690
LP		 789 if (pad == -1) {
790 struct adv76xx_state *state = to_state(sd);
791
792 pad = state->selected_input;
793 }
794
795 switch (pad) {
796 case ADV76XX_PAD_HDMI_PORT_A:
797 case ADV7604_PAD_HDMI_PORT_B:
798 case ADV7604_PAD_HDMI_PORT_C:
799 case ADV7604_PAD_HDMI_PORT_D:
800 return &adv76xx_timings_cap_digital;
801
802 case ADV7604_PAD_VGA_RGB:
803 case ADV7604_PAD_VGA_COMP:
804 default:
805 return &adv7604_timings_cap_analog;
806 }
bd3e275f
JMH		 807}
808
809
4a31a93a
MR		 810/* ----------------------------------------------------------------------- */
811
54450f59 812#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06 813static void adv76xx_inv_register(struct v4l2_subdev *sd)
54450f59
HV		 814{
815 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
816 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
817 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
818 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
819 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
820 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
821 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
822 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
823 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
824 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
825 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
826 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
827 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
828}
829
b44b2e06 830static int adv76xx_g_register(struct v4l2_subdev *sd,
54450f59
HV		 831 struct v4l2_dbg_register *reg)
832{
d42010a1
LPC		 833 int ret;
834
b44b2e06 835 ret = adv76xx_read_reg(sd, reg->reg);
d42010a1 836 if (ret < 0) {
54450f59 837 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 838 adv76xx_inv_register(sd);
d42010a1 839 return ret;
54450f59 840 }
d42010a1
LPC		 841
842 reg->size = 1;
843 reg->val = ret;
844
54450f59
HV		 845 return 0;
846}
847
b44b2e06 848static int adv76xx_s_register(struct v4l2_subdev *sd,
977ba3b1 849 const struct v4l2_dbg_register *reg)
54450f59 850{
d42010a1 851 int ret;
1577461b 852
b44b2e06 853 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
d42010a1 854 if (ret < 0) {
54450f59 855 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
b44b2e06 856 adv76xx_inv_register(sd);
d42010a1 857 return ret;
54450f59 858 }
d42010a1 859
54450f59
HV		 860 return 0;
861}
862#endif
863
d42010a1
LPC		 864static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
865{
866 u8 value = io_read(sd, 0x6f);
867
868 return ((value & 0x10) >> 4)
869 | ((value & 0x08) >> 2)
870 | ((value & 0x04) << 0)
871 | ((value & 0x02) << 2);
872}
873
874static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
875{
876 u8 value = io_read(sd, 0x6f);
877
878 return value & 1;
879}
880
7111cddd
WT		 881static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
882{
883 /* Reads CABLE_DET_A_RAW. For input B support, need to
884 * account for bit 7 [MSB] of 0x6a (ie. CABLE_DET_B_RAW)
885 */
886 u8 value = io_read(sd, 0x6f);
887
888 return value & 1;
889}
890
b44b2e06 891static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
54450f59 892{
b44b2e06
PA		 893 struct adv76xx_state *state = to_state(sd);
894 const struct adv76xx_chip_info *info = state->info;
54450f59 895
54450f59 896 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
d42010a1 897 info->read_cable_det(sd));
54450f59
HV		 898}
899
ccbd5bc4
HV		 900static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
901 u8 prim_mode,
b44b2e06 902 const struct adv76xx_video_standards *predef_vid_timings,
ccbd5bc4
HV		 903 const struct v4l2_dv_timings *timings)
904{
ccbd5bc4
HV		 905 int i;
906
907 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
ef1ed8f5 908 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
85f9e06c 909 is_digital_input(sd) ? 250000 : 1000000, false))
ccbd5bc4
HV		 910 continue;
911 io_write(sd, 0x00, predef_vid_timings[i].vid_std); /* video std */
912 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
913 prim_mode); /* v_freq and prim mode */
914 return 0;
915 }
916
917 return -1;
918}
919
920static int configure_predefined_video_timings(struct v4l2_subdev *sd,
921 struct v4l2_dv_timings *timings)
54450f59 922{
b44b2e06 923 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 924 int err;
925
926 v4l2_dbg(1, debug, sd, "%s", __func__);
927
b44b2e06 928 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 929 /* reset to default values */
930 io_write(sd, 0x16, 0x43);
931 io_write(sd, 0x17, 0x5a);
932 }
ccbd5bc4 933 /* disable embedded syncs for auto graphics mode */
22d97e56 934 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
ccbd5bc4
HV		 935 cp_write(sd, 0x8f, 0x00);
936 cp_write(sd, 0x90, 0x00);
937 cp_write(sd, 0xa2, 0x00);
938 cp_write(sd, 0xa3, 0x00);
939 cp_write(sd, 0xa4, 0x00);
940 cp_write(sd, 0xa5, 0x00);
941 cp_write(sd, 0xa6, 0x00);
942 cp_write(sd, 0xa7, 0x00);
943 cp_write(sd, 0xab, 0x00);
944 cp_write(sd, 0xac, 0x00);
945
4a31a93a 946 if (is_analog_input(sd)) {
ccbd5bc4
HV		 947 err = find_and_set_predefined_video_timings(sd,
948 0x01, adv7604_prim_mode_comp, timings);
949 if (err)
950 err = find_and_set_predefined_video_timings(sd,
951 0x02, adv7604_prim_mode_gr, timings);
4a31a93a 952 } else if (is_digital_input(sd)) {
ccbd5bc4 953 err = find_and_set_predefined_video_timings(sd,
b44b2e06 954 0x05, adv76xx_prim_mode_hdmi_comp, timings);
ccbd5bc4
HV		 955 if (err)
956 err = find_and_set_predefined_video_timings(sd,
b44b2e06 957 0x06, adv76xx_prim_mode_hdmi_gr, timings);
4a31a93a
MR		 958 } else {
959 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
960 __func__, state->selected_input);
ccbd5bc4 961 err = -1;
ccbd5bc4
HV		 962 }
963
964
965 return err;
966}
967
968static void configure_custom_video_timings(struct v4l2_subdev *sd,
969 const struct v4l2_bt_timings *bt)
970{
b44b2e06 971 struct adv76xx_state *state = to_state(sd);
ccbd5bc4
HV		 972 u32 width = htotal(bt);
973 u32 height = vtotal(bt);
974 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
975 u16 cp_start_eav = width - bt->hfrontporch;
976 u16 cp_start_vbi = height - bt->vfrontporch;
977 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
978 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
b44b2e06 979 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
ccbd5bc4
HV		 980 const u8 pll[2] = {
981 0xc0 | ((width >> 8) & 0x1f),
982 width & 0xff
983 };
54450f59
HV		 984
985 v4l2_dbg(2, debug, sd, "%s\n", __func__);
986
4a31a93a 987 if (is_analog_input(sd)) {
ccbd5bc4
HV		 988 /* auto graphics */
989 io_write(sd, 0x00, 0x07); /* video std */
990 io_write(sd, 0x01, 0x02); /* prim mode */
991 /* enable embedded syncs for auto graphics mode */
22d97e56 992 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
54450f59 993
ccbd5bc4 994 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */
54450f59
HV		 995 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */
996 /* IO-map reg. 0x16 and 0x17 should be written in sequence */
f862f57d
PA		 997 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
998 0x16, pll, 2))
54450f59 999 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
54450f59
HV		 1000
1001 /* active video - horizontal timing */
54450f59 1002 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
ccbd5bc4 1003 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
4a31a93a 1004 ((cp_start_eav >> 8) & 0x0f));
54450f59
HV		 1005 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1006
1007 /* active video - vertical timing */
54450f59 1008 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
ccbd5bc4 1009 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
4a31a93a 1010 ((cp_end_vbi >> 8) & 0xf));
54450f59 1011 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
4a31a93a 1012 } else if (is_digital_input(sd)) {
ccbd5bc4 1013 /* set default prim_mode/vid_std for HDMI
39c1cb2b 1014 according to [REF_03, c. 4.2] */
ccbd5bc4
HV		 1015 io_write(sd, 0x00, 0x02); /* video std */
1016 io_write(sd, 0x01, 0x06); /* prim mode */
4a31a93a
MR		 1017 } else {
1018 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1019 __func__, state->selected_input);
54450f59 1020 }
54450f59 1021
ccbd5bc4
HV		 1022 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1023 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1024 cp_write(sd, 0xab, (height >> 4) & 0xff);
1025 cp_write(sd, 0xac, (height & 0x0f) << 4);
1026}
54450f59 1027
b44b2e06 1028static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
5c6c6349 1029{
b44b2e06 1030 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1031 u8 offset_buf[4];
1032
1033 if (auto_offset) {
1034 offset_a = 0x3ff;
1035 offset_b = 0x3ff;
1036 offset_c = 0x3ff;
1037 }
1038
1039 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1040 __func__, auto_offset ? "Auto" : "Manual",
1041 offset_a, offset_b, offset_c);
1042
1043 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1044 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1045 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1046 offset_buf[3] = offset_c & 0x0ff;
1047
1048 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1049 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1050 0x77, offset_buf, 4))
5c6c6349
MR		 1051 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1052}
1053
b44b2e06 1054static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
5c6c6349 1055{
b44b2e06 1056 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1057 u8 gain_buf[4];
1058 u8 gain_man = 1;
1059 u8 agc_mode_man = 1;
1060
1061 if (auto_gain) {
1062 gain_man = 0;
1063 agc_mode_man = 0;
1064 gain_a = 0x100;
1065 gain_b = 0x100;
1066 gain_c = 0x100;
1067 }
1068
1069 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1070 __func__, auto_gain ? "Auto" : "Manual",
1071 gain_a, gain_b, gain_c);
1072
1073 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1074 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1075 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1076 gain_buf[3] = ((gain_c & 0x0ff));
1077
1078 /* Registers must be written in this order with no i2c access in between */
f862f57d
PA		 1079 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1080 0x73, gain_buf, 4))
5c6c6349
MR		 1081 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1082}
1083
54450f59
HV		 1084static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1085{
b44b2e06 1086 struct adv76xx_state *state = to_state(sd);
5c6c6349
MR		 1087 bool rgb_output = io_read(sd, 0x02) & 0x02;
1088 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1089
1090 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1091 __func__, state->rgb_quantization_range,
1092 rgb_output, hdmi_signal);
54450f59 1093
b44b2e06
PA		 1094 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1095 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
9833239e 1096
54450f59
HV		 1097 switch (state->rgb_quantization_range) {
1098 case V4L2_DV_RGB_RANGE_AUTO:
c784b1e2 1099 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
9833239e
MR		 1100 /* Receiving analog RGB signal
1101 * Set RGB full range (0-255) */
22d97e56 1102 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
9833239e
MR		 1103 break;
1104 }
1105
c784b1e2 1106 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
9833239e
MR		 1107 /* Receiving analog YPbPr signal
1108 * Set automode */
22d97e56 1109 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1110 break;
1111 }
1112
5c6c6349 1113 if (hdmi_signal) {
9833239e
MR		 1114 /* Receiving HDMI signal
1115 * Set automode */
22d97e56 1116 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
9833239e
MR		 1117 break;
1118 }
1119
1120 /* Receiving DVI-D signal
1121 * ADV7604 selects RGB limited range regardless of
1122 * input format (CE/IT) in automatic mode */
680fee04 1123 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
9833239e 1124 /* RGB limited range (16-235) */
22d97e56 1125 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
9833239e
MR		 1126 } else {
1127 /* RGB full range (0-255) */
22d97e56 1128 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1129
1130 if (is_digital_input(sd) && rgb_output) {
b44b2e06 1131 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
5c6c6349 1132 } else {
b44b2e06
PA		 1133 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1134 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
5c6c6349 1135 }
54450f59
HV		 1136 }
1137 break;
1138 case V4L2_DV_RGB_RANGE_LIMITED:
c784b1e2 1139 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1140 /* YCrCb limited range (16-235) */
22d97e56 1141 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
5c6c6349 1142 break;
d261e842 1143 }
5c6c6349
MR		 1144
1145 /* RGB limited range (16-235) */
22d97e56 1146 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
5c6c6349 1147
54450f59
HV		 1148 break;
1149 case V4L2_DV_RGB_RANGE_FULL:
c784b1e2 1150 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
d261e842 1151 /* YCrCb full range (0-255) */
22d97e56 1152 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
5c6c6349
MR		 1153 break;
1154 }
1155
1156 /* RGB full range (0-255) */
22d97e56 1157 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
5c6c6349
MR		 1158
1159 if (is_analog_input(sd) || hdmi_signal)
1160 break;
1161
1162 /* Adjust gain/offset for DVI-D signals only */
1163 if (rgb_output) {
b44b2e06 1164 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
d261e842 1165 } else {
b44b2e06
PA		 1166 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1167 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
d261e842 1168 }
54450f59
HV		 1169 break;
1170 }
1171}
1172
b44b2e06 1173static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
54450f59 1174{
c269887c 1175 struct v4l2_subdev *sd =
b44b2e06 1176 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
c269887c 1177
b44b2e06 1178 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1179
1180 switch (ctrl->id) {
1181 case V4L2_CID_BRIGHTNESS:
1182 cp_write(sd, 0x3c, ctrl->val);
1183 return 0;
1184 case V4L2_CID_CONTRAST:
1185 cp_write(sd, 0x3a, ctrl->val);
1186 return 0;
1187 case V4L2_CID_SATURATION:
1188 cp_write(sd, 0x3b, ctrl->val);
1189 return 0;
1190 case V4L2_CID_HUE:
1191 cp_write(sd, 0x3d, ctrl->val);
1192 return 0;
1193 case V4L2_CID_DV_RX_RGB_RANGE:
1194 state->rgb_quantization_range = ctrl->val;
1195 set_rgb_quantization_range(sd);
1196 return 0;
1197 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
b44b2e06 1198 if (!adv76xx_has_afe(state))
d42010a1 1199 return -EINVAL;
54450f59
HV		 1200 /* Set the analog sampling phase. This is needed to find the
1201 best sampling phase for analog video: an application or
1202 driver has to try a number of phases and analyze the picture
1203 quality before settling on the best performing phase. */
1204 afe_write(sd, 0xc8, ctrl->val);
1205 return 0;
1206 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1207 /* Use the default blue color for free running mode,
1208 or supply your own. */
22d97e56 1209 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
54450f59
HV		 1210 return 0;
1211 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1212 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1213 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1214 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1215 return 0;
1216 }
1217 return -EINVAL;
1218}
1219
297a4144
HV		 1220static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1221{
1222 struct v4l2_subdev *sd =
1223 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1224
1225 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1226 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1227 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1228 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1229 return 0;
1230 }
1231 return -EINVAL;
1232}
1233
54450f59
HV		 1234/* ----------------------------------------------------------------------- */
1235
1236static inline bool no_power(struct v4l2_subdev *sd)
1237{
1238 /* Entire chip or CP powered off */
1239 return io_read(sd, 0x0c) & 0x24;
1240}
1241
1242static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1243{
b44b2e06 1244 struct adv76xx_state *state = to_state(sd);
4a31a93a
MR		 1245
1246 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
54450f59
HV		 1247}
1248
1249static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1250{
b44b2e06
PA		 1251 struct adv76xx_state *state = to_state(sd);
1252 const struct adv76xx_chip_info *info = state->info;
d42010a1
LPC		 1253
1254 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
54450f59
HV		 1255}
1256
bb88f325
MB		 1257static inline bool is_hdmi(struct v4l2_subdev *sd)
1258{
1259 return hdmi_read(sd, 0x05) & 0x80;
1260}
1261
54450f59
HV		 1262static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1263{
b44b2e06 1264 struct adv76xx_state *state = to_state(sd);
d42010a1
LPC		 1265
1266 /*
1267 * Chips without a AFE don't expose registers for the SSPD, so just assume
1268 * that we have a lock.
1269 */
b44b2e06 1270 if (adv76xx_has_afe(state))
d42010a1
LPC		 1271 return false;
1272
54450f59
HV		 1273 /* TODO channel 2 */
1274 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1275}
1276
1277static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1278{
1279 /* TODO channel 2 */
1280 return !(cp_read(sd, 0xb1) & 0x80);
1281}
1282
1283static inline bool no_signal(struct v4l2_subdev *sd)
1284{
54450f59
HV		 1285 bool ret;
1286
1287 ret = no_power(sd);
1288
1289 ret |= no_lock_stdi(sd);
1290 ret |= no_lock_sspd(sd);
1291
4a31a93a 1292 if (is_digital_input(sd)) {
54450f59
HV		 1293 ret |= no_lock_tmds(sd);
1294 ret |= no_signal_tmds(sd);
1295 }
1296
1297 return ret;
1298}
1299
1300static inline bool no_lock_cp(struct v4l2_subdev *sd)
1301{
b44b2e06 1302 struct adv76xx_state *state = to_state(sd);
d42010a1 1303
b44b2e06 1304 if (!adv76xx_has_afe(state))
d42010a1
LPC		 1305 return false;
1306
54450f59
HV		 1307 /* CP has detected a non standard number of lines on the incoming
1308 video compared to what it is configured to receive by s_dv_timings */
1309 return io_read(sd, 0x12) & 0x01;
1310}
1311
58514625 1312static inline bool in_free_run(struct v4l2_subdev *sd)
1313{
1314 return cp_read(sd, 0xff) & 0x10;
1315}
1316
b44b2e06 1317static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
54450f59 1318{
54450f59
HV		 1319 *status = 0;
1320 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1321 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
58514625 1322 if (!in_free_run(sd) && no_lock_cp(sd))
1323 *status |= is_digital_input(sd) ?
1324 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
54450f59
HV		 1325
1326 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1327
1328 return 0;
1329}
1330
1331/* ----------------------------------------------------------------------- */
1332
54450f59
HV		 1333struct stdi_readback {
1334 u16 bl, lcf, lcvs;
1335 u8 hs_pol, vs_pol;
1336 bool interlaced;
1337};
1338
1339static int stdi2dv_timings(struct v4l2_subdev *sd,
1340 struct stdi_readback *stdi,
1341 struct v4l2_dv_timings *timings)
1342{
b44b2e06
PA		 1343 struct adv76xx_state *state = to_state(sd);
1344 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
54450f59
HV		 1345 u32 pix_clk;
1346 int i;
1347
bd3e275f
JMH		 1348 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1349 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1350
1351 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
9c41e690 1352 adv76xx_get_dv_timings_cap(sd, -1),
bd3e275f 1353 adv76xx_check_dv_timings, NULL))
54450f59 1354 continue;
bd3e275f
JMH		 1355 if (vtotal(bt) != stdi->lcf + 1)
1356 continue;
1357 if (bt->vsync != stdi->lcvs)
54450f59
HV		 1358 continue;
1359
bd3e275f 1360 pix_clk = hfreq * htotal(bt);
54450f59 1361
bd3e275f
JMH		 1362 if ((pix_clk < bt->pixelclock + 1000000) &&
1363 (pix_clk > bt->pixelclock - 1000000)) {
1364 *timings = v4l2_dv_timings_presets[i];
54450f59
HV		 1365 return 0;
1366 }
1367 }
1368
5fea1bb7 1369 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
54450f59
HV		 1370 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1371 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1372 false, timings))
54450f59
HV		 1373 return 0;
1374 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1375 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1376 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
061ddda6 1377 false, state->aspect_ratio, timings))
54450f59
HV		 1378 return 0;
1379
ccbd5bc4
HV		 1380 v4l2_dbg(2, debug, sd,
1381 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1382 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1383 stdi->hs_pol, stdi->vs_pol);
54450f59
HV		 1384 return -1;
1385}
1386
d42010a1 1387
54450f59
HV		 1388static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1389{
b44b2e06
PA		 1390 struct adv76xx_state *state = to_state(sd);
1391 const struct adv76xx_chip_info *info = state->info;
4a2ccdd2
LP		 1392 u8 polarity;
1393
54450f59
HV		 1394 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1395 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1396 return -1;
1397 }
1398
1399 /* read STDI */
51182a94 1400 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
d42010a1 1401 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
54450f59
HV		 1402 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1403 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1404
b44b2e06 1405 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1406 /* read SSPD */
1407 polarity = cp_read(sd, 0xb5);
1408 if ((polarity & 0x03) == 0x01) {
1409 stdi->hs_pol = polarity & 0x10
1410 ? (polarity & 0x08 ? '+' : '-') : 'x';
1411 stdi->vs_pol = polarity & 0x40
1412 ? (polarity & 0x20 ? '+' : '-') : 'x';
1413 } else {
1414 stdi->hs_pol = 'x';
1415 stdi->vs_pol = 'x';
1416 }
54450f59 1417 } else {
d42010a1
LPC		 1418 polarity = hdmi_read(sd, 0x05);
1419 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1420 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
54450f59
HV		 1421 }
1422
1423 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1424 v4l2_dbg(2, debug, sd,
1425 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1426 return -1;
1427 }
1428
1429 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1430 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1431 memset(stdi, 0, sizeof(struct stdi_readback));
1432 return -1;
1433 }
1434
1435 v4l2_dbg(2, debug, sd,
1436 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1437 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1438 stdi->hs_pol, stdi->vs_pol,
1439 stdi->interlaced ? "interlaced" : "progressive");
1440
1441 return 0;
1442}
1443
b44b2e06 1444static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1445 struct v4l2_enum_dv_timings *timings)
1446{
b44b2e06 1447 struct adv76xx_state *state = to_state(sd);
afec5599 1448
afec5599
LP		 1449 if (timings->pad >= state->source_pad)
1450 return -EINVAL;
1451
bd3e275f 1452 return v4l2_enum_dv_timings_cap(timings,
9c41e690
LP		 1453 adv76xx_get_dv_timings_cap(sd, timings->pad),
1454 adv76xx_check_dv_timings, NULL);
54450f59
HV		 1455}
1456
b44b2e06 1457static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
7515e096 1458 struct v4l2_dv_timings_cap *cap)
54450f59 1459{
b44b2e06 1460 struct adv76xx_state *state = to_state(sd);
9c41e690 1461 unsigned int pad = cap->pad;
7515e096
LP		 1462
1463 if (cap->pad >= state->source_pad)
1464 return -EINVAL;
1465
9c41e690
LP		 1466 *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1467 cap->pad = pad;
1468
54450f59
HV		 1469 return 0;
1470}
1471
1472/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
b44b2e06
PA		 1473 if the format is listed in adv76xx_timings[] */
1474static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
54450f59
HV		 1475 struct v4l2_dv_timings *timings)
1476{
9c41e690
LP		 1477 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1478 is_digital_input(sd) ? 250000 : 1000000,
1479 adv76xx_check_dv_timings, NULL);
54450f59
HV		 1480}
1481
d42010a1
LPC		 1482static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1483{
1484 unsigned int freq;
1485 int a, b;
1486
1487 a = hdmi_read(sd, 0x06);
1488 b = hdmi_read(sd, 0x3b);
1489 if (a < 0 || b < 0)
1490 return 0;
1491 freq = a * 1000000 + ((b & 0x30) >> 4) * 250000;
1492
1493 if (is_hdmi(sd)) {
1494 /* adjust for deep color mode */
1495 unsigned bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1496
1497 freq = freq * 8 / bits_per_channel;
1498 }
1499
1500 return freq;
1501}
1502
1503static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1504{
1505 int a, b;
1506
1507 a = hdmi_read(sd, 0x51);
1508 b = hdmi_read(sd, 0x52);
1509 if (a < 0 || b < 0)
1510 return 0;
1511 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1512}
1513
b44b2e06 1514static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1515 struct v4l2_dv_timings *timings)
1516{
b44b2e06
PA		 1517 struct adv76xx_state *state = to_state(sd);
1518 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 1519 struct v4l2_bt_timings *bt = &timings->bt;
1520 struct stdi_readback stdi;
1521
1522 if (!timings)
1523 return -EINVAL;
1524
1525 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1526
1527 if (no_signal(sd)) {
1e0b9156 1528 state->restart_stdi_once = true;
54450f59
HV		 1529 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1530 return -ENOLINK;
1531 }
1532
1533 /* read STDI */
1534 if (read_stdi(sd, &stdi)) {
1535 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1536 return -ENOLINK;
1537 }
1538 bt->interlaced = stdi.interlaced ?
1539 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1540
4a31a93a 1541 if (is_digital_input(sd)) {
54450f59
HV		 1542 timings->type = V4L2_DV_BT_656_1120;
1543
5380baaf 1544 bt->width = hdmi_read16(sd, 0x07, info->linewidth_mask);
1545 bt->height = hdmi_read16(sd, 0x09, info->field0_height_mask);
d42010a1 1546 bt->pixelclock = info->read_hdmi_pixelclock(sd);
5380baaf 1547 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1548 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1549 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1550 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1551 info->field0_vfrontporch_mask) / 2;
1552 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1553 bt->vbackporch = hdmi_read16(sd, 0x32,
1554 info->field0_vbackporch_mask) / 2;
54450f59
HV		 1555 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1556 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1557 if (bt->interlaced == V4L2_DV_INTERLACED) {
5380baaf 1558 bt->height += hdmi_read16(sd, 0x0b,
1559 info->field1_height_mask);
1560 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1561 info->field1_vfrontporch_mask) / 2;
1562 bt->il_vsync = hdmi_read16(sd, 0x30,
1563 info->field1_vsync_mask) / 2;
1564 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1565 info->field1_vbackporch_mask) / 2;
54450f59 1566 }
b44b2e06 1567 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1568 } else {
1569 /* find format
80939647 1570 * Since LCVS values are inaccurate [REF_03, p. 275-276],
54450f59
HV		 1571 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.
1572 */
1573 if (!stdi2dv_timings(sd, &stdi, timings))
1574 goto found;
1575 stdi.lcvs += 1;
1576 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1577 if (!stdi2dv_timings(sd, &stdi, timings))
1578 goto found;
1579 stdi.lcvs -= 2;
1580 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1581 if (stdi2dv_timings(sd, &stdi, timings)) {
cf9afb1d
HV		 1582 /*
1583 * The STDI block may measure wrong values, especially
1584 * for lcvs and lcf. If the driver can not find any
1585 * valid timing, the STDI block is restarted to measure
1586 * the video timings again. The function will return an
1587 * error, but the restart of STDI will generate a new
1588 * STDI interrupt and the format detection process will
1589 * restart.
1590 */
1591 if (state->restart_stdi_once) {
1592 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1593 /* TODO restart STDI for Sync Channel 2 */
1594 /* enter one-shot mode */
22d97e56 1595 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
cf9afb1d 1596 /* trigger STDI restart */
22d97e56 1597 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
cf9afb1d 1598 /* reset to continuous mode */
22d97e56 1599 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
cf9afb1d
HV		 1600 state->restart_stdi_once = false;
1601 return -ENOLINK;
1602 }
54450f59
HV		 1603 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1604 return -ERANGE;
1605 }
cf9afb1d 1606 state->restart_stdi_once = true;
54450f59
HV		 1607 }
1608found:
1609
1610 if (no_signal(sd)) {
1611 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1612 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1613 return -ENOLINK;
1614 }
1615
4a31a93a
MR		 1616 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1617 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
54450f59
HV		 1618 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1619 __func__, (u32)bt->pixelclock);
1620 return -ERANGE;
1621 }
1622
1623 if (debug > 1)
b44b2e06 1624 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
11d034c8 1625 timings, true);
54450f59
HV		 1626
1627 return 0;
1628}
1629
b44b2e06 1630static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1631 struct v4l2_dv_timings *timings)
1632{
b44b2e06 1633 struct adv76xx_state *state = to_state(sd);
54450f59 1634 struct v4l2_bt_timings *bt;
ccbd5bc4 1635 int err;
54450f59
HV		 1636
1637 if (!timings)
1638 return -EINVAL;
1639
85f9e06c 1640 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
d48eb48c
MR		 1641 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1642 return 0;
1643 }
1644
54450f59
HV		 1645 bt = &timings->bt;
1646
9c41e690 1647 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
bd3e275f 1648 adv76xx_check_dv_timings, NULL))
54450f59 1649 return -ERANGE;
ccbd5bc4 1650
b44b2e06 1651 adv76xx_fill_optional_dv_timings_fields(sd, timings);
54450f59
HV		 1652
1653 state->timings = *timings;
1654
22d97e56 1655 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
ccbd5bc4
HV		 1656
1657 /* Use prim_mode and vid_std when available */
1658 err = configure_predefined_video_timings(sd, timings);
1659 if (err) {
1660 /* custom settings when the video format
1661 does not have prim_mode/vid_std */
1662 configure_custom_video_timings(sd, bt);
1663 }
54450f59
HV		 1664
1665 set_rgb_quantization_range(sd);
1666
54450f59 1667 if (debug > 1)
b44b2e06 1668 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
11d034c8 1669 timings, true);
54450f59
HV		 1670 return 0;
1671}
1672
b44b2e06 1673static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
54450f59
HV		 1674 struct v4l2_dv_timings *timings)
1675{
b44b2e06 1676 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 1677
1678 *timings = state->timings;
1679 return 0;
1680}
1681
d42010a1
LPC		 1682static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1683{
1684 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1685}
1686
1687static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1688{
1689 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1690}
1691
6b0d5d34 1692static void enable_input(struct v4l2_subdev *sd)
54450f59 1693{
b44b2e06 1694 struct adv76xx_state *state = to_state(sd);
6b0d5d34 1695
4a31a93a 1696 if (is_analog_input(sd)) {
54450f59 1697 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */
4a31a93a 1698 } else if (is_digital_input(sd)) {
22d97e56 1699 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
d42010a1 1700 state->info->set_termination(sd, true);
54450f59 1701 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */
22d97e56 1702 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00); /* Unmute audio */
4a31a93a
MR		 1703 } else {
1704 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1705 __func__, state->selected_input);
54450f59
HV		 1706 }
1707}
1708
1709static void disable_input(struct v4l2_subdev *sd)
1710{
b44b2e06 1711 struct adv76xx_state *state = to_state(sd);
d42010a1 1712
22d97e56 1713 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10); /* Mute audio */
5474b983 1714 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 7.16.10] */
54450f59 1715 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */
d42010a1 1716 state->info->set_termination(sd, false);
54450f59
HV		 1717}
1718
6b0d5d34 1719static void select_input(struct v4l2_subdev *sd)
54450f59 1720{
b44b2e06
PA		 1721 struct adv76xx_state *state = to_state(sd);
1722 const struct adv76xx_chip_info *info = state->info;
54450f59 1723
4a31a93a 1724 if (is_analog_input(sd)) {
b44b2e06 1725 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
54450f59
HV		 1726
1727 afe_write(sd, 0x00, 0x08); /* power up ADC */
1728 afe_write(sd, 0x01, 0x06); /* power up Analog Front End */
1729 afe_write(sd, 0xc8, 0x00); /* phase control */
4a31a93a
MR		 1730 } else if (is_digital_input(sd)) {
1731 hdmi_write(sd, 0x00, state->selected_input & 0x03);
54450f59 1732
b44b2e06 1733 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
d42010a1 1734
b44b2e06 1735 if (adv76xx_has_afe(state)) {
d42010a1
LPC		 1736 afe_write(sd, 0x00, 0xff); /* power down ADC */
1737 afe_write(sd, 0x01, 0xfe); /* power down Analog Front End */
1738 afe_write(sd, 0xc8, 0x40); /* phase control */
1739 }
1740
54450f59
HV		 1741 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */
1742 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */
1743 cp_write(sd, 0x40, 0x80); /* CP core pre-gain control. Graphics mode */
4a31a93a
MR		 1744 } else {
1745 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1746 __func__, state->selected_input);
54450f59
HV		 1747 }
1748}
1749
b44b2e06 1750static int adv76xx_s_routing(struct v4l2_subdev *sd,
54450f59
HV		 1751 u32 input, u32 output, u32 config)
1752{
b44b2e06 1753 struct adv76xx_state *state = to_state(sd);
54450f59 1754
ff4f80fd
MR		 1755 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1756 __func__, input, state->selected_input);
1757
1758 if (input == state->selected_input)
1759 return 0;
54450f59 1760
d42010a1
LPC		 1761 if (input > state->info->max_port)
1762 return -EINVAL;
1763
4a31a93a 1764 state->selected_input = input;
54450f59
HV		 1765
1766 disable_input(sd);
6b0d5d34 1767 select_input(sd);
6b0d5d34 1768 enable_input(sd);
54450f59 1769
6f5bcfc3
LPC		 1770 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1771
54450f59
HV		 1772 return 0;
1773}
1774
b44b2e06 1775static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
f7234138 1776 struct v4l2_subdev_pad_config *cfg,
539b33b0 1777 struct v4l2_subdev_mbus_code_enum *code)
54450f59 1778{
b44b2e06 1779 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1780
1781 if (code->index >= state->info->nformats)
54450f59 1782 return -EINVAL;
539b33b0
LP		 1783
1784 code->code = state->info->formats[code->index].code;
1785
54450f59
HV		 1786 return 0;
1787}
1788
b44b2e06 1789static void adv76xx_fill_format(struct adv76xx_state *state,
539b33b0 1790 struct v4l2_mbus_framefmt *format)
54450f59 1791{
539b33b0 1792 memset(format, 0, sizeof(*format));
54450f59 1793
539b33b0
LP		 1794 format->width = state->timings.bt.width;
1795 format->height = state->timings.bt.height;
1796 format->field = V4L2_FIELD_NONE;
680fee04 1797 format->colorspace = V4L2_COLORSPACE_SRGB;
539b33b0 1798
680fee04 1799 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
539b33b0 1800 format->colorspace = (state->timings.bt.height <= 576) ?
54450f59 1801 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
539b33b0
LP		 1802}
1803
1804/*
1805 * Compute the op_ch_sel value required to obtain on the bus the component order
1806 * corresponding to the selected format taking into account bus reordering
1807 * applied by the board at the output of the device.
1808 *
1809 * The following table gives the op_ch_value from the format component order
1810 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as
b44b2e06 1811 * adv76xx_bus_order value in row).
539b33b0
LP		 1812 *
1813 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)
1814 * ----------+-------------------------------------------------
1815 * RGB (NOP) | GBR GRB BGR RGB BRG RBG
1816 * GRB (1-2) | BGR RGB GBR GRB RBG BRG
1817 * RBG (2-3) | GRB GBR BRG RBG BGR RGB
1818 * BGR (1-3) | RBG BRG RGB BGR GRB GBR
1819 * BRG (ROR) | BRG RBG GRB GBR RGB BGR
1820 * GBR (ROL) | RGB BGR RBG BRG GBR GRB
1821 */
b44b2e06 1822static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
539b33b0
LP		 1823{
1824#define _SEL(a,b,c,d,e,f) { \
b44b2e06
PA		 1825 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1826 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
539b33b0
LP		 1827#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1828
1829 static const unsigned int op_ch_sel[6][6] = {
1830 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1831 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1832 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1833 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1834 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1835 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1836 };
1837
1838 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1839}
1840
b44b2e06 1841static void adv76xx_setup_format(struct adv76xx_state *state)
539b33b0
LP		 1842{
1843 struct v4l2_subdev *sd = &state->sd;
1844
22d97e56 1845 io_write_clr_set(sd, 0x02, 0x02,
b44b2e06 1846 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
539b33b0
LP		 1847 io_write(sd, 0x03, state->format->op_format_sel |
1848 state->pdata.op_format_mode_sel);
b44b2e06 1849 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
22d97e56 1850 io_write_clr_set(sd, 0x05, 0x01,
b44b2e06 1851 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
539b33b0
LP		 1852}
1853
f7234138
HV		 1854static int adv76xx_get_format(struct v4l2_subdev *sd,
1855 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1856 struct v4l2_subdev_format *format)
1857{
b44b2e06 1858 struct adv76xx_state *state = to_state(sd);
539b33b0
LP		 1859
1860 if (format->pad != state->source_pad)
1861 return -EINVAL;
1862
b44b2e06 1863 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1864
1865 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1866 struct v4l2_mbus_framefmt *fmt;
1867
f7234138 1868 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1869 format->format.code = fmt->code;
1870 } else {
1871 format->format.code = state->format->code;
54450f59 1872 }
539b33b0
LP		 1873
1874 return 0;
1875}
1876
b7d4d2f8
UH		 1877static int adv76xx_get_selection(struct v4l2_subdev *sd,
1878 struct v4l2_subdev_pad_config *cfg,
1879 struct v4l2_subdev_selection *sel)
1880{
1881 struct adv76xx_state *state = to_state(sd);
1882
1883 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1884 return -EINVAL;
1885 /* Only CROP, CROP_DEFAULT and CROP_BOUNDS are supported */
1886 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1887 return -EINVAL;
1888
1889 sel->r.left = 0;
1890 sel->r.top = 0;
1891 sel->r.width = state->timings.bt.width;
1892 sel->r.height = state->timings.bt.height;
1893
1894 return 0;
1895}
1896
f7234138
HV		 1897static int adv76xx_set_format(struct v4l2_subdev *sd,
1898 struct v4l2_subdev_pad_config *cfg,
539b33b0
LP		 1899 struct v4l2_subdev_format *format)
1900{
b44b2e06
PA		 1901 struct adv76xx_state *state = to_state(sd);
1902 const struct adv76xx_format_info *info;
539b33b0
LP		 1903
1904 if (format->pad != state->source_pad)
1905 return -EINVAL;
1906
b44b2e06 1907 info = adv76xx_format_info(state, format->format.code);
539b33b0 1908 if (info == NULL)
b44b2e06 1909 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
539b33b0 1910
b44b2e06 1911 adv76xx_fill_format(state, &format->format);
539b33b0
LP		 1912 format->format.code = info->code;
1913
1914 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1915 struct v4l2_mbus_framefmt *fmt;
1916
f7234138 1917 fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
539b33b0
LP		 1918 fmt->code = format->format.code;
1919 } else {
1920 state->format = info;
b44b2e06 1921 adv76xx_setup_format(state);
539b33b0
LP		 1922 }
1923
54450f59
HV		 1924 return 0;
1925}
1926
b44b2e06 1927static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
54450f59 1928{
b44b2e06
PA		 1929 struct adv76xx_state *state = to_state(sd);
1930 const struct adv76xx_chip_info *info = state->info;
f24d229c
MR		 1931 const u8 irq_reg_0x43 = io_read(sd, 0x43);
1932 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
1933 const u8 irq_reg_0x70 = io_read(sd, 0x70);
1934 u8 fmt_change_digital;
1935 u8 fmt_change;
1936 u8 tx_5v;
1937
1938 if (irq_reg_0x43)
1939 io_write(sd, 0x44, irq_reg_0x43);
1940 if (irq_reg_0x70)
1941 io_write(sd, 0x71, irq_reg_0x70);
1942 if (irq_reg_0x6b)
1943 io_write(sd, 0x6c, irq_reg_0x6b);
54450f59 1944
ff4f80fd
MR		 1945 v4l2_dbg(2, debug, sd, "%s: ", __func__);
1946
54450f59 1947 /* format change */
f24d229c 1948 fmt_change = irq_reg_0x43 & 0x98;
d42010a1
LPC		 1949 fmt_change_digital = is_digital_input(sd)
1950 ? irq_reg_0x6b & info->fmt_change_digital_mask
1951 : 0;
14d03233 1952
54450f59
HV		 1953 if (fmt_change || fmt_change_digital) {
1954 v4l2_dbg(1, debug, sd,
25a64ac9 1955 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
54450f59 1956 __func__, fmt_change, fmt_change_digital);
25a64ac9 1957
6f5bcfc3 1958 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
25a64ac9 1959
54450f59
HV		 1960 if (handled)
1961 *handled = true;
1962 }
f24d229c
MR		 1963 /* HDMI/DVI mode */
1964 if (irq_reg_0x6b & 0x01) {
1965 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
1966 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
1967 set_rgb_quantization_range(sd);
1968 if (handled)
1969 *handled = true;
1970 }
1971
54450f59 1972 /* tx 5v detect */
0ba4581c 1973 tx_5v = irq_reg_0x70 & info->cable_det_mask;
54450f59
HV		 1974 if (tx_5v) {
1975 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
b44b2e06 1976 adv76xx_s_detect_tx_5v_ctrl(sd);
54450f59
HV		 1977 if (handled)
1978 *handled = true;
1979 }
1980 return 0;
1981}
1982
b44b2e06 1983static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 1984{
b44b2e06 1985 struct adv76xx_state *state = to_state(sd);
4a31a93a 1986 u8 *data = NULL;
54450f59 1987
dd9ac11a 1988 memset(edid->reserved, 0, sizeof(edid->reserved));
4a31a93a
MR		 1989
1990 switch (edid->pad) {
b44b2e06 1991 case ADV76XX_PAD_HDMI_PORT_A:
c784b1e2
LP		 1992 case ADV7604_PAD_HDMI_PORT_B:
1993 case ADV7604_PAD_HDMI_PORT_C:
1994 case ADV7604_PAD_HDMI_PORT_D:
4a31a93a
MR		 1995 if (state->edid.present & (1 << edid->pad))
1996 data = state->edid.edid;
1997 break;
1998 default:
1999 return -EINVAL;
4a31a93a 2000 }
dd9ac11a
HV		 2001
2002 if (edid->start_block == 0 && edid->blocks == 0) {
2003 edid->blocks = data ? state->edid.blocks : 0;
2004 return 0;
2005 }
2006
2007 if (data == NULL)
4a31a93a
MR		 2008 return -ENODATA;
2009
dd9ac11a
HV		 2010 if (edid->start_block >= state->edid.blocks)
2011 return -EINVAL;
2012
2013 if (edid->start_block + edid->blocks > state->edid.blocks)
2014 edid->blocks = state->edid.blocks - edid->start_block;
2015
2016 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2017
54450f59
HV		 2018 return 0;
2019}
2020
dd08beb9 2021static int get_edid_spa_location(const u8 *edid)
3e86aa85
MR		 2022{
2023 u8 d;
2024
2025 if ((edid[0x7e] != 1) ||
2026 (edid[0x80] != 0x02) ||
2027 (edid[0x81] != 0x03)) {
2028 return -1;
2029 }
2030
2031 /* search Vendor Specific Data Block (tag 3) */
2032 d = edid[0x82] & 0x7f;
2033 if (d > 4) {
2034 int i = 0x84;
2035 int end = 0x80 + d;
2036
2037 do {
2038 u8 tag = edid[i] >> 5;
2039 u8 len = edid[i] & 0x1f;
2040
2041 if ((tag == 3) && (len >= 5))
2042 return i + 4;
2043 i += len + 1;
2044 } while (i < end);
2045 }
2046 return -1;
2047}
2048
b44b2e06 2049static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
54450f59 2050{
b44b2e06
PA		 2051 struct adv76xx_state *state = to_state(sd);
2052 const struct adv76xx_chip_info *info = state->info;
dd08beb9 2053 int spa_loc;
54450f59 2054 int err;
dd08beb9 2055 int i;
54450f59 2056
dd9ac11a
HV		 2057 memset(edid->reserved, 0, sizeof(edid->reserved));
2058
c784b1e2 2059 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
54450f59
HV		 2060 return -EINVAL;
2061 if (edid->start_block != 0)
2062 return -EINVAL;
2063 if (edid->blocks == 0) {
3e86aa85 2064 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2065 state->edid.present &= ~(1 << edid->pad);
b44b2e06 2066 adv76xx_set_hpd(state, state->edid.present);
22d97e56 2067 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
3e86aa85 2068
54450f59
HV		 2069 /* Fall back to a 16:9 aspect ratio */
2070 state->aspect_ratio.numerator = 16;
2071 state->aspect_ratio.denominator = 9;
3e86aa85
MR		 2072
2073 if (!state->edid.present)
2074 state->edid.blocks = 0;
2075
2076 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2077 __func__, edid->pad, state->edid.present);
54450f59
HV		 2078 return 0;
2079 }
4a31a93a
MR		 2080 if (edid->blocks > 2) {
2081 edid->blocks = 2;
54450f59 2082 return -E2BIG;
4a31a93a 2083 }
4a31a93a 2084
dd08beb9
MR		 2085 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2086 __func__, edid->pad, state->edid.present);
2087
3e86aa85 2088 /* Disable hotplug and I2C access to EDID RAM from DDC port */
4a31a93a 2089 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
b44b2e06 2090 adv76xx_set_hpd(state, 0);
22d97e56 2091 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
3e86aa85 2092
dd08beb9
MR		 2093 spa_loc = get_edid_spa_location(edid->edid);
2094 if (spa_loc < 0)
2095 spa_loc = 0xc0; /* Default value [REF_02, p. 116] */
2096
3e86aa85 2097 switch (edid->pad) {
b44b2e06 2098 case ADV76XX_PAD_HDMI_PORT_A:
dd08beb9
MR		 2099 state->spa_port_a[0] = edid->edid[spa_loc];
2100 state->spa_port_a[1] = edid->edid[spa_loc + 1];
3e86aa85 2101 break;
c784b1e2 2102 case ADV7604_PAD_HDMI_PORT_B:
dd08beb9
MR		 2103 rep_write(sd, 0x70, edid->edid[spa_loc]);
2104 rep_write(sd, 0x71, edid->edid[spa_loc + 1]);
3e86aa85 2105 break;
c784b1e2 2106 case ADV7604_PAD_HDMI_PORT_C:
dd08beb9
MR		 2107 rep_write(sd, 0x72, edid->edid[spa_loc]);
2108 rep_write(sd, 0x73, edid->edid[spa_loc + 1]);
3e86aa85 2109 break;
c784b1e2 2110 case ADV7604_PAD_HDMI_PORT_D:
dd08beb9
MR		 2111 rep_write(sd, 0x74, edid->edid[spa_loc]);
2112 rep_write(sd, 0x75, edid->edid[spa_loc + 1]);
3e86aa85 2113 break;
dd08beb9
MR		 2114 default:
2115 return -EINVAL;
3e86aa85 2116 }
d42010a1
LPC		 2117
2118 if (info->type == ADV7604) {
2119 rep_write(sd, 0x76, spa_loc & 0xff);
22d97e56 2120 rep_write_clr_set(sd, 0x77, 0x40, (spa_loc & 0x100) >> 2);
d42010a1 2121 } else {
b5a442aa
UH		 2122 /* ADV7612 Software Manual Rev. A, p. 15 */
2123 rep_write(sd, 0x70, spa_loc & 0xff);
22d97e56 2124 rep_write_clr_set(sd, 0x71, 0x01, (spa_loc & 0x100) >> 8);
d42010a1 2125 }
3e86aa85 2126
dd08beb9
MR		 2127 edid->edid[spa_loc] = state->spa_port_a[0];
2128 edid->edid[spa_loc + 1] = state->spa_port_a[1];
4a31a93a
MR		 2129
2130 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2131 state->edid.blocks = edid->blocks;
54450f59
HV		 2132 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2133 edid->edid[0x16]);
3e86aa85 2134 state->edid.present |= 1 << edid->pad;
4a31a93a
MR		 2135
2136 err = edid_write_block(sd, 128 * edid->blocks, state->edid.edid);
2137 if (err < 0) {
3e86aa85 2138 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
4a31a93a
MR		 2139 return err;
2140 }
2141
b44b2e06 2142 /* adv76xx calculates the checksums and enables I2C access to internal
dd08beb9 2143 EDID RAM from DDC port. */
22d97e56 2144 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
dd08beb9
MR		 2145
2146 for (i = 0; i < 1000; i++) {
d42010a1 2147 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
dd08beb9
MR		 2148 break;
2149 mdelay(1);
2150 }
2151 if (i == 1000) {
2152 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2153 return -EIO;
2154 }
2155
4a31a93a 2156 /* enable hotplug after 100 ms */
0423ff9b 2157 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
4a31a93a 2158 return 0;
54450f59
HV		 2159}
2160
2161/*********** avi info frame CEA-861-E **************/
2162
516613c1
HV		 2163static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2164 { "AVI", 0x01, 0xe0, 0x00 },
2165 { "Audio", 0x02, 0xe3, 0x1c },
2166 { "SDP", 0x04, 0xe6, 0x2a },
2167 { "Vendor", 0x10, 0xec, 0x54 }
2168};
2169
2170static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2171 union hdmi_infoframe *frame)
54450f59 2172{
516613c1
HV		 2173 uint8_t buffer[32];
2174 u8 len;
54450f59 2175 int i;
54450f59 2176
516613c1
HV		 2177 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2178 v4l2_info(sd, "%s infoframe not received\n",
2179 adv76xx_cri[index].desc);
2180 return -ENOENT;
54450f59 2181 }
516613c1
HV		 2182
2183 for (i = 0; i < 3; i++)
2184 buffer[i] = infoframe_read(sd,
2185 adv76xx_cri[index].head_addr + i);
2186
2187 len = buffer[2] + 1;
2188
2189 if (len + 3 > sizeof(buffer)) {
2190 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2191 adv76xx_cri[index].desc, len);
2192 return -ENOENT;
54450f59
HV		 2193 }
2194
516613c1
HV		 2195 for (i = 0; i < len; i++)
2196 buffer[i + 3] = infoframe_read(sd,
2197 adv76xx_cri[index].payload_addr + i);
2198
2199 if (hdmi_infoframe_unpack(frame, buffer) < 0) {
2200 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2201 adv76xx_cri[index].desc);
2202 return -ENOENT;
54450f59 2203 }
516613c1
HV		 2204 return 0;
2205}
54450f59 2206
516613c1
HV		 2207static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2208{
2209 int i;
54450f59 2210
516613c1
HV		 2211 if (!is_hdmi(sd)) {
2212 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
54450f59 2213 return;
516613c1 2214 }
54450f59 2215
516613c1
HV		 2216 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2217 union hdmi_infoframe frame;
2218 struct i2c_client *client = v4l2_get_subdevdata(sd);
54450f59 2219
516613c1
HV		 2220 if (adv76xx_read_infoframe(sd, i, &frame))
2221 return;
2222 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2223 }
54450f59
HV		 2224}
2225
b44b2e06 2226static int adv76xx_log_status(struct v4l2_subdev *sd)
54450f59 2227{
b44b2e06
PA		 2228 struct adv76xx_state *state = to_state(sd);
2229 const struct adv76xx_chip_info *info = state->info;
54450f59
HV		 2230 struct v4l2_dv_timings timings;
2231 struct stdi_readback stdi;
2232 u8 reg_io_0x02 = io_read(sd, 0x02);
4a2ccdd2
LP		 2233 u8 edid_enabled;
2234 u8 cable_det;
54450f59 2235
f216ccb3 2236 static const char * const csc_coeff_sel_rb[16] = {
54450f59
HV		 2237 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2238 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2239 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2240 "reserved", "reserved", "reserved", "reserved", "manual"
2241 };
f216ccb3 2242 static const char * const input_color_space_txt[16] = {
54450f59
HV		 2243 "RGB limited range (16-235)", "RGB full range (0-255)",
2244 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
9833239e 2245 "xvYCC Bt.601", "xvYCC Bt.709",
54450f59
HV		 2246 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2247 "invalid", "invalid", "invalid", "invalid", "invalid",
2248 "invalid", "invalid", "automatic"
2249 };
7a5d99e7
HV		 2250 static const char * const hdmi_color_space_txt[16] = {
2251 "RGB limited range (16-235)", "RGB full range (0-255)",
2252 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2253 "xvYCC Bt.601", "xvYCC Bt.709",
2254 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2255 "sYCC", "Adobe YCC 601", "AdobeRGB", "invalid", "invalid",
2256 "invalid", "invalid", "invalid"
2257 };
f216ccb3 2258 static const char * const rgb_quantization_range_txt[] = {
54450f59
HV		 2259 "Automatic",
2260 "RGB limited range (16-235)",
2261 "RGB full range (0-255)",
2262 };
f216ccb3 2263 static const char * const deep_color_mode_txt[4] = {
bb88f325
MB		 2264 "8-bits per channel",
2265 "10-bits per channel",
2266 "12-bits per channel",
2267 "16-bits per channel (not supported)"
2268 };
54450f59
HV		 2269
2270 v4l2_info(sd, "-----Chip status-----\n");
2271 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
d42010a1 2272 edid_enabled = rep_read(sd, info->edid_status_reg);
4a31a93a 2273 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
4a2ccdd2
LP		 2274 ((edid_enabled & 0x01) ? "Yes" : "No"),
2275 ((edid_enabled & 0x02) ? "Yes" : "No"),
2276 ((edid_enabled & 0x04) ? "Yes" : "No"),
2277 ((edid_enabled & 0x08) ? "Yes" : "No"));
54450f59
HV		 2278 v4l2_info(sd, "CEC: %s\n", !!(cec_read(sd, 0x2a) & 0x01) ?
2279 "enabled" : "disabled");
2280
2281 v4l2_info(sd, "-----Signal status-----\n");
d42010a1 2282 cable_det = info->read_cable_det(sd);
4a31a93a 2283 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
d42010a1
LPC		 2284 ((cable_det & 0x01) ? "Yes" : "No"),
2285 ((cable_det & 0x02) ? "Yes" : "No"),
4a2ccdd2 2286 ((cable_det & 0x04) ? "Yes" : "No"),
d42010a1 2287 ((cable_det & 0x08) ? "Yes" : "No"));
54450f59
HV		 2288 v4l2_info(sd, "TMDS signal detected: %s\n",
2289 no_signal_tmds(sd) ? "false" : "true");
2290 v4l2_info(sd, "TMDS signal locked: %s\n",
2291 no_lock_tmds(sd) ? "false" : "true");
2292 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2293 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2294 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2295 v4l2_info(sd, "CP free run: %s\n",
58514625 2296 (in_free_run(sd)) ? "on" : "off");
ccbd5bc4
HV		 2297 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2298 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2299 (io_read(sd, 0x01) & 0x70) >> 4);
54450f59
HV		 2300
2301 v4l2_info(sd, "-----Video Timings-----\n");
2302 if (read_stdi(sd, &stdi))
2303 v4l2_info(sd, "STDI: not locked\n");
2304 else
2305 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2306 stdi.lcf, stdi.bl, stdi.lcvs,
2307 stdi.interlaced ? "interlaced" : "progressive",
2308 stdi.hs_pol, stdi.vs_pol);
b44b2e06 2309 if (adv76xx_query_dv_timings(sd, &timings))
54450f59
HV		 2310 v4l2_info(sd, "No video detected\n");
2311 else
11d034c8
HV		 2312 v4l2_print_dv_timings(sd->name, "Detected format: ",
2313 &timings, true);
2314 v4l2_print_dv_timings(sd->name, "Configured format: ",
2315 &state->timings, true);
54450f59 2316
76eb2d30
MR		 2317 if (no_signal(sd))
2318 return 0;
2319
54450f59
HV		 2320 v4l2_info(sd, "-----Color space-----\n");
2321 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2322 rgb_quantization_range_txt[state->rgb_quantization_range]);
2323 v4l2_info(sd, "Input color space: %s\n",
2324 input_color_space_txt[reg_io_0x02 >> 4]);
7a5d99e7 2325 v4l2_info(sd, "Output color space: %s %s, saturator %s, alt-gamma %s\n",
54450f59
HV		 2326 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2327 (reg_io_0x02 & 0x04) ? "(16-235)" : "(0-255)",
5dd7d88a 2328 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
7a5d99e7
HV		 2329 "enabled" : "disabled",
2330 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
54450f59 2331 v4l2_info(sd, "Color space conversion: %s\n",
80f4944e 2332 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
54450f59 2333
4a31a93a 2334 if (!is_digital_input(sd))
76eb2d30
MR		 2335 return 0;
2336
2337 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
4a31a93a
MR		 2338 v4l2_info(sd, "Digital video port selected: %c\n",
2339 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2340 v4l2_info(sd, "HDCP encrypted content: %s\n",
2341 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
76eb2d30
MR		 2342 v4l2_info(sd, "HDCP keys read: %s%s\n",
2343 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2344 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
77639ff2 2345 if (is_hdmi(sd)) {
76eb2d30
MR		 2346 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2347 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2348 bool audio_mute = io_read(sd, 0x65) & 0x40;
2349
2350 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2351 audio_pll_locked ? "locked" : "not locked",
2352 audio_sample_packet_detect ? "detected" : "not detected",
2353 audio_mute ? "muted" : "enabled");
2354 if (audio_pll_locked && audio_sample_packet_detect) {
2355 v4l2_info(sd, "Audio format: %s\n",
2356 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2357 }
2358 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2359 (hdmi_read(sd, 0x5c) << 8) +
2360 (hdmi_read(sd, 0x5d) & 0xf0));
2361 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2362 (hdmi_read(sd, 0x5e) << 8) +
2363 hdmi_read(sd, 0x5f));
2364 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2365
2366 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
7a5d99e7 2367 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
76eb2d30 2368
516613c1 2369 adv76xx_log_infoframes(sd);
54450f59
HV		 2370 }
2371
2372 return 0;
2373}
2374
6f5bcfc3
LPC		 2375static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2376 struct v4l2_fh *fh,
2377 struct v4l2_event_subscription *sub)
2378{
2379 switch (sub->type) {
2380 case V4L2_EVENT_SOURCE_CHANGE:
2381 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2382 case V4L2_EVENT_CTRL:
2383 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2384 default:
2385 return -EINVAL;
2386 }
2387}
2388
54450f59
HV		 2389/* ----------------------------------------------------------------------- */
2390
b44b2e06
PA		 2391static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2392 .s_ctrl = adv76xx_s_ctrl,
297a4144 2393 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
54450f59
HV		 2394};
2395
b44b2e06
PA		 2396static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2397 .log_status = adv76xx_log_status,
2398 .interrupt_service_routine = adv76xx_isr,
6f5bcfc3 2399 .subscribe_event = adv76xx_subscribe_event,
0975626d 2400 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
54450f59 2401#ifdef CONFIG_VIDEO_ADV_DEBUG
b44b2e06
PA		 2402 .g_register = adv76xx_g_register,
2403 .s_register = adv76xx_s_register,
54450f59
HV		 2404#endif
2405};
2406
b44b2e06
PA		 2407static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2408 .s_routing = adv76xx_s_routing,
2409 .g_input_status = adv76xx_g_input_status,
2410 .s_dv_timings = adv76xx_s_dv_timings,
2411 .g_dv_timings = adv76xx_g_dv_timings,
2412 .query_dv_timings = adv76xx_query_dv_timings,
54450f59
HV		 2413};
2414
b44b2e06
PA		 2415static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2416 .enum_mbus_code = adv76xx_enum_mbus_code,
b7d4d2f8 2417 .get_selection = adv76xx_get_selection,
b44b2e06
PA		 2418 .get_fmt = adv76xx_get_format,
2419 .set_fmt = adv76xx_set_format,
2420 .get_edid = adv76xx_get_edid,
2421 .set_edid = adv76xx_set_edid,
2422 .dv_timings_cap = adv76xx_dv_timings_cap,
2423 .enum_dv_timings = adv76xx_enum_dv_timings,
54450f59
HV		 2424};
2425
b44b2e06
PA		 2426static const struct v4l2_subdev_ops adv76xx_ops = {
2427 .core = &adv76xx_core_ops,
2428 .video = &adv76xx_video_ops,
2429 .pad = &adv76xx_pad_ops,
54450f59
HV		 2430};
2431
2432/* -------------------------- custom ctrls ---------------------------------- */
2433
2434static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
b44b2e06 2435 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2436 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2437 .name = "Analog Sampling Phase",
2438 .type = V4L2_CTRL_TYPE_INTEGER,
2439 .min = 0,
2440 .max = 0x1f,
2441 .step = 1,
2442 .def = 0,
2443};
2444
b44b2e06
PA		 2445static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2446 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2447 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2448 .name = "Free Running Color, Manual",
2449 .type = V4L2_CTRL_TYPE_BOOLEAN,
2450 .min = false,
2451 .max = true,
2452 .step = 1,
2453 .def = false,
2454};
2455
b44b2e06
PA		 2456static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2457 .ops = &adv76xx_ctrl_ops,
54450f59
HV		 2458 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2459 .name = "Free Running Color",
2460 .type = V4L2_CTRL_TYPE_INTEGER,
2461 .min = 0x0,
2462 .max = 0xffffff,
2463 .step = 0x1,
2464 .def = 0x0,
2465};
2466
2467/* ----------------------------------------------------------------------- */
2468
b44b2e06 2469static int adv76xx_core_init(struct v4l2_subdev *sd)
54450f59 2470{
b44b2e06
PA		 2471 struct adv76xx_state *state = to_state(sd);
2472 const struct adv76xx_chip_info *info = state->info;
2473 struct adv76xx_platform_data *pdata = &state->pdata;
54450f59
HV		 2474
2475 hdmi_write(sd, 0x48,
2476 (pdata->disable_pwrdnb ? 0x80 : 0) |
2477 (pdata->disable_cable_det_rst ? 0x40 : 0));
2478
2479 disable_input(sd);
2480
5ef54b59
LP		 2481 if (pdata->default_input >= 0 &&
2482 pdata->default_input < state->source_pad) {
2483 state->selected_input = pdata->default_input;
2484 select_input(sd);
2485 enable_input(sd);
2486 }
2487
54450f59
HV		 2488 /* power */
2489 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */
2490 io_write(sd, 0x0b, 0x44); /* Power down ESDP block */
2491 cp_write(sd, 0xcf, 0x01); /* Power down macrovision */
2492
2493 /* video format */
22d97e56 2494 io_write_clr_set(sd, 0x02, 0x0f,
54450f59
HV		 2495 pdata->alt_gamma << 3 |
2496 pdata->op_656_range << 2 |
54450f59 2497 pdata->alt_data_sat << 0);
22d97e56 2498 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
539b33b0
LP		 2499 pdata->insert_av_codes << 2 |
2500 pdata->replicate_av_codes << 1);
b44b2e06 2501 adv76xx_setup_format(state);
54450f59 2502
54450f59 2503 cp_write(sd, 0x69, 0x30); /* Enable CP CSC */
98908696
MB		 2504
2505 /* VS, HS polarities */
1b5ab875
LP		 2506 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2507 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
f31b62e1
MK		 2508
2509 /* Adjust drive strength */
2510 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2511 pdata->dr_str_clk << 2 |
2512 pdata->dr_str_sync);
2513
54450f59
HV		 2514 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01); /* HDMI free run */
2515 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */
2516 cp_write(sd, 0xf9, 0x23); /* STDI ch. 1 - LCVS change threshold -
80939647 2517 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59 2518 cp_write(sd, 0x45, 0x23); /* STDI ch. 2 - LCVS change threshold -
80939647 2519 ADI recommended setting [REF_01, c. 2.3.3] */
54450f59
HV		 2520 cp_write(sd, 0xc9, 0x2d); /* use prim_mode and vid_std as free run resolution
2521 for digital formats */
2522
5474b983 2523 /* HDMI audio */
22d97e56
LP		 2524 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03); /* Mute on FIFO over-/underflow [REF_01, c. 1.2.18] */
2525 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08); /* Wait 1 s before unmute */
2526 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06); /* FIFO reset on over-/underflow [REF_01, c. 1.2.19] */
5474b983 2527
54450f59
HV		 2528 /* TODO from platform data */
2529 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */
2530
b44b2e06 2531 if (adv76xx_has_afe(state)) {
d42010a1 2532 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */
22d97e56 2533 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
d42010a1 2534 }
54450f59 2535
54450f59 2536 /* interrupts */
d42010a1 2537 io_write(sd, 0x40, 0xc0 | pdata->int1_config); /* Configure INT1 */
54450f59 2538 io_write(sd, 0x46, 0x98); /* Enable SSPD, STDI and CP unlocked interrupts */
d42010a1
LPC		 2539 io_write(sd, 0x6e, info->fmt_change_digital_mask); /* Enable V_LOCKED and DE_REGEN_LCK interrupts */
2540 io_write(sd, 0x73, info->cable_det_mask); /* Enable cable detection (+5v) interrupts */
2541 info->setup_irqs(sd);
54450f59
HV		 2542
2543 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2544}
2545
d42010a1
LPC		 2546static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2547{
2548 io_write(sd, 0x41, 0xd7); /* STDI irq for any change, disable INT2 */
2549}
2550
2551static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2552{
2553 io_write(sd, 0x41, 0xd0); /* STDI irq for any change, disable INT2 */
2554}
2555
8331d30b
WT		 2556static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2557{
2558 io_write(sd, 0x41, 0xd0); /* disable INT2 */
2559}
2560
b44b2e06 2561static void adv76xx_unregister_clients(struct adv76xx_state *state)
54450f59 2562{
05cacb17
LP		 2563 unsigned int i;
2564
2565 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i) {
2566 if (state->i2c_clients[i])
2567 i2c_unregister_device(state->i2c_clients[i]);
2568 }
54450f59
HV		 2569}
2570
b44b2e06 2571static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
54450f59
HV		 2572 u8 addr, u8 io_reg)
2573{
2574 struct i2c_client *client = v4l2_get_subdevdata(sd);
2575
2576 if (addr)
2577 io_write(sd, io_reg, addr << 1);
2578 return i2c_new_dummy(client->adapter, io_read(sd, io_reg) >> 1);
2579}
2580
b44b2e06 2581static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
d42010a1
LPC		 2582 /* reset ADI recommended settings for HDMI: */
2583 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2584 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2585 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 }, /* HDMI filter optimization */
2586 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 }, /* DDC bus active pull-up control */
2587 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 }, /* TMDS PLL optimization */
2588 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2589 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 }, /* TMDS PLL optimization */
2590 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 }, /* TMDS PLL optimization */
2591 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2592 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2593 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 }, /* equaliser */
2594 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e }, /* equaliser */
2595 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 }, /* enable automatic EQ changing */
d42010a1
LPC		 2596
2597 /* set ADI recommended settings for digitizer */
2598 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2599 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b }, /* ADC noise shaping filter controls */
2600 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f }, /* CP core gain controls */
2601 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 }, /* CP core pre-gain control */
2602 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 }, /* CP coast control. Graphics mode */
2603 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c }, /* CP core pre-gain control. Graphics mode */
d42010a1 2604
b44b2e06 2605 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2606};
2607
b44b2e06 2608static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
d42010a1
LPC		 2609 /* set ADI recommended settings for HDMI: */
2610 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 4. */
b44b2e06
PA		 2611 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 }, /* HDMI filter optimization */
2612 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 }, /* DDC bus active pull-up control */
2613 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 }, /* TMDS PLL optimization */
2614 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b }, /* TMDS PLL optimization */
2615 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 }, /* TMDS PLL optimization */
2616 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 }, /* TMDS PLL optimization */
2617 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 }, /* equaliser */
2618 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 }, /* equaliser */
2619 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b }, /* equaliser */
2620 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d }, /* equaliser */
2621 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 }, /* enable automatic EQ changing */
d42010a1
LPC		 2622
2623 /* reset ADI recommended settings for digitizer */
2624 /* "ADV7604 Register Settings Recommendations (rev. 2.5, June 2010)" p. 17. */
b44b2e06
PA		 2625 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb }, /* ADC noise shaping filter controls */
2626 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d }, /* CP core gain controls */
d42010a1 2627
b44b2e06 2628 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2629};
2630
b44b2e06 2631static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
c41ad9c3 2632 /* ADV7611 Register Settings Recommendations Rev 1.5, May 2014 */
b44b2e06
PA		 2633 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2634 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2635 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2636 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2637 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2638 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2639 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2640 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2641 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2642 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
2643 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
2644
2645 { ADV76XX_REG_SEQ_TERM, 0 },
d42010a1
LPC		 2646};
2647
8331d30b
WT		 2648static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
2649 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2650 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2651 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2652 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
2653 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
2654 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
2655 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
2656 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
2657 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
2658 { ADV76XX_REG_SEQ_TERM, 0 },
2659};
2660
b44b2e06 2661static const struct adv76xx_chip_info adv76xx_chip_info[] = {
d42010a1
LPC		 2662 [ADV7604] = {
2663 .type = ADV7604,
2664 .has_afe = true,
c784b1e2 2665 .max_port = ADV7604_PAD_VGA_COMP,
d42010a1
LPC		 2666 .num_dv_ports = 4,
2667 .edid_enable_reg = 0x77,
2668 .edid_status_reg = 0x7d,
2669 .lcf_reg = 0xb3,
2670 .tdms_lock_mask = 0xe0,
2671 .cable_det_mask = 0x1e,
2672 .fmt_change_digital_mask = 0xc1,
80f4944e 2673 .cp_csc = 0xfc,
539b33b0
LP		 2674 .formats = adv7604_formats,
2675 .nformats = ARRAY_SIZE(adv7604_formats),
d42010a1
LPC		 2676 .set_termination = adv7604_set_termination,
2677 .setup_irqs = adv7604_setup_irqs,
2678 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
2679 .read_cable_det = adv7604_read_cable_det,
2680 .recommended_settings = {
2681 [0] = adv7604_recommended_settings_afe,
2682 [1] = adv7604_recommended_settings_hdmi,
2683 },
2684 .num_recommended_settings = {
2685 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
2686 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
2687 },
b44b2e06
PA		 2688 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
2689 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
d42010a1 2690 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
b44b2e06
PA		 2691 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
2692 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
2693 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
d42010a1 2694 BIT(ADV7604_PAGE_VDP),
5380baaf 2695 .linewidth_mask = 0xfff,
2696 .field0_height_mask = 0xfff,
2697 .field1_height_mask = 0xfff,
2698 .hfrontporch_mask = 0x3ff,
2699 .hsync_mask = 0x3ff,
2700 .hbackporch_mask = 0x3ff,
2701 .field0_vfrontporch_mask = 0x1fff,
2702 .field0_vsync_mask = 0x1fff,
2703 .field0_vbackporch_mask = 0x1fff,
2704 .field1_vfrontporch_mask = 0x1fff,
2705 .field1_vsync_mask = 0x1fff,
2706 .field1_vbackporch_mask = 0x1fff,
d42010a1
LPC		 2707 },
2708 [ADV7611] = {
2709 .type = ADV7611,
2710 .has_afe = false,
b44b2e06 2711 .max_port = ADV76XX_PAD_HDMI_PORT_A,
d42010a1
LPC		 2712 .num_dv_ports = 1,
2713 .edid_enable_reg = 0x74,
2714 .edid_status_reg = 0x76,
2715 .lcf_reg = 0xa3,
2716 .tdms_lock_mask = 0x43,
2717 .cable_det_mask = 0x01,
2718 .fmt_change_digital_mask = 0x03,
80f4944e 2719 .cp_csc = 0xf4,
539b33b0
LP		 2720 .formats = adv7611_formats,
2721 .nformats = ARRAY_SIZE(adv7611_formats),
d42010a1
LPC		 2722 .set_termination = adv7611_set_termination,
2723 .setup_irqs = adv7611_setup_irqs,
2724 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
2725 .read_cable_det = adv7611_read_cable_det,
2726 .recommended_settings = {
2727 [1] = adv7611_recommended_settings_hdmi,
2728 },
2729 .num_recommended_settings = {
2730 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
2731 },
b44b2e06
PA		 2732 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2733 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2734 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2735 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
5380baaf 2736 .linewidth_mask = 0x1fff,
2737 .field0_height_mask = 0x1fff,
2738 .field1_height_mask = 0x1fff,
2739 .hfrontporch_mask = 0x1fff,
2740 .hsync_mask = 0x1fff,
2741 .hbackporch_mask = 0x1fff,
2742 .field0_vfrontporch_mask = 0x3fff,
2743 .field0_vsync_mask = 0x3fff,
2744 .field0_vbackporch_mask = 0x3fff,
2745 .field1_vfrontporch_mask = 0x3fff,
2746 .field1_vsync_mask = 0x3fff,
2747 .field1_vbackporch_mask = 0x3fff,
d42010a1 2748 },
8331d30b
WT		 2749 [ADV7612] = {
2750 .type = ADV7612,
2751 .has_afe = false,
7111cddd
WT		 2752 .max_port = ADV76XX_PAD_HDMI_PORT_A, /* B not supported */
2753 .num_dv_ports = 1, /* normally 2 */
8331d30b
WT		 2754 .edid_enable_reg = 0x74,
2755 .edid_status_reg = 0x76,
2756 .lcf_reg = 0xa3,
2757 .tdms_lock_mask = 0x43,
2758 .cable_det_mask = 0x01,
2759 .fmt_change_digital_mask = 0x03,
7111cddd 2760 .cp_csc = 0xf4,
8331d30b
WT		 2761 .formats = adv7612_formats,
2762 .nformats = ARRAY_SIZE(adv7612_formats),
2763 .set_termination = adv7611_set_termination,
2764 .setup_irqs = adv7612_setup_irqs,
2765 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
7111cddd 2766 .read_cable_det = adv7612_read_cable_det,
8331d30b
WT		 2767 .recommended_settings = {
2768 [1] = adv7612_recommended_settings_hdmi,
2769 },
2770 .num_recommended_settings = {
2771 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
2772 },
2773 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
2774 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
2775 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
2776 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
2777 .linewidth_mask = 0x1fff,
2778 .field0_height_mask = 0x1fff,
2779 .field1_height_mask = 0x1fff,
2780 .hfrontporch_mask = 0x1fff,
2781 .hsync_mask = 0x1fff,
2782 .hbackporch_mask = 0x1fff,
2783 .field0_vfrontporch_mask = 0x3fff,
2784 .field0_vsync_mask = 0x3fff,
2785 .field0_vbackporch_mask = 0x3fff,
2786 .field1_vfrontporch_mask = 0x3fff,
2787 .field1_vsync_mask = 0x3fff,
2788 .field1_vbackporch_mask = 0x3fff,
2789 },
d42010a1
LPC		 2790};
2791
7f099a75 2792static const struct i2c_device_id adv76xx_i2c_id[] = {
b44b2e06
PA		 2793 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
2794 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
8331d30b 2795 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2796 { }
2797};
b44b2e06 2798MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
f82f313e 2799
7f099a75 2800static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
b44b2e06 2801 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
8331d30b 2802 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
f82f313e
LP		 2803 { }
2804};
b44b2e06 2805MODULE_DEVICE_TABLE(of, adv76xx_of_id);
f82f313e 2806
b44b2e06 2807static int adv76xx_parse_dt(struct adv76xx_state *state)
f82f313e 2808{
6fa88045
LP		 2809 struct v4l2_of_endpoint bus_cfg;
2810 struct device_node *endpoint;
2811 struct device_node *np;
2812 unsigned int flags;
7f6cd6c4 2813 int ret;
bf9c8227 2814 u32 v;
6fa88045 2815
b44b2e06 2816 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
6fa88045
LP		 2817
2818 /* Parse the endpoint. */
2819 endpoint = of_graph_get_next_endpoint(np, NULL);
2820 if (!endpoint)
2821 return -EINVAL;
2822
7f6cd6c4
JMC		 2823 ret = v4l2_of_parse_endpoint(endpoint, &bus_cfg);
2824 if (ret) {
2825 of_node_put(endpoint);
2826 return ret;
2827 }
bf9c8227
IM		 2828
2829 if (!of_property_read_u32(endpoint, "default-input", &v))
2830 state->pdata.default_input = v;
2831 else
2832 state->pdata.default_input = -1;
2833
6fa88045
LP		 2834 of_node_put(endpoint);
2835
2836 flags = bus_cfg.bus.parallel.flags;
2837
2838 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
2839 state->pdata.inv_hs_pol = 1;
2840
2841 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
2842 state->pdata.inv_vs_pol = 1;
2843
2844 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2845 state->pdata.inv_llc_pol = 1;
2846
2847 if (bus_cfg.bus_type == V4L2_MBUS_BT656) {
2848 state->pdata.insert_av_codes = 1;
2849 state->pdata.op_656_range = 1;
2850 }
2851
f82f313e 2852 /* Disable the interrupt for now as no DT-based board uses it. */
b44b2e06 2853 state->pdata.int1_config = ADV76XX_INT1_CONFIG_DISABLED;
f82f313e
LP		 2854
2855 /* Use the default I2C addresses. */
2856 state->pdata.i2c_addresses[ADV7604_PAGE_AVLINK] = 0x42;
b44b2e06
PA		 2857 state->pdata.i2c_addresses[ADV76XX_PAGE_CEC] = 0x40;
2858 state->pdata.i2c_addresses[ADV76XX_PAGE_INFOFRAME] = 0x3e;
f82f313e
LP		 2859 state->pdata.i2c_addresses[ADV7604_PAGE_ESDP] = 0x38;
2860 state->pdata.i2c_addresses[ADV7604_PAGE_DPP] = 0x3c;
b44b2e06
PA		 2861 state->pdata.i2c_addresses[ADV76XX_PAGE_AFE] = 0x26;
2862 state->pdata.i2c_addresses[ADV76XX_PAGE_REP] = 0x32;
2863 state->pdata.i2c_addresses[ADV76XX_PAGE_EDID] = 0x36;
2864 state->pdata.i2c_addresses[ADV76XX_PAGE_HDMI] = 0x34;
2865 state->pdata.i2c_addresses[ADV76XX_PAGE_TEST] = 0x30;
2866 state->pdata.i2c_addresses[ADV76XX_PAGE_CP] = 0x22;
f82f313e
LP		 2867 state->pdata.i2c_addresses[ADV7604_PAGE_VDP] = 0x24;
2868
2869 /* Hardcode the remaining platform data fields. */
2870 state->pdata.disable_pwrdnb = 0;
2871 state->pdata.disable_cable_det_rst = 0;
f82f313e 2872 state->pdata.blank_data = 1;
f82f313e 2873 state->pdata.alt_data_sat = 1;
f82f313e
LP		 2874 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
2875 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
2876
2877 return 0;
2878}
2879
f862f57d
PA		 2880static const struct regmap_config adv76xx_regmap_cnf[] = {
2881 {
2882 .name = "io",
2883 .reg_bits = 8,
2884 .val_bits = 8,
2885
2886 .max_register = 0xff,
2887 .cache_type = REGCACHE_NONE,
2888 },
2889 {
2890 .name = "avlink",
2891 .reg_bits = 8,
2892 .val_bits = 8,
2893
2894 .max_register = 0xff,
2895 .cache_type = REGCACHE_NONE,
2896 },
2897 {
2898 .name = "cec",
2899 .reg_bits = 8,
2900 .val_bits = 8,
2901
2902 .max_register = 0xff,
2903 .cache_type = REGCACHE_NONE,
2904 },
2905 {
2906 .name = "infoframe",
2907 .reg_bits = 8,
2908 .val_bits = 8,
2909
2910 .max_register = 0xff,
2911 .cache_type = REGCACHE_NONE,
2912 },
2913 {
2914 .name = "esdp",
2915 .reg_bits = 8,
2916 .val_bits = 8,
2917
2918 .max_register = 0xff,
2919 .cache_type = REGCACHE_NONE,
2920 },
2921 {
2922 .name = "epp",
2923 .reg_bits = 8,
2924 .val_bits = 8,
2925
2926 .max_register = 0xff,
2927 .cache_type = REGCACHE_NONE,
2928 },
2929 {
2930 .name = "afe",
2931 .reg_bits = 8,
2932 .val_bits = 8,
2933
2934 .max_register = 0xff,
2935 .cache_type = REGCACHE_NONE,
2936 },
2937 {
2938 .name = "rep",
2939 .reg_bits = 8,
2940 .val_bits = 8,
2941
2942 .max_register = 0xff,
2943 .cache_type = REGCACHE_NONE,
2944 },
2945 {
2946 .name = "edid",
2947 .reg_bits = 8,
2948 .val_bits = 8,
2949
2950 .max_register = 0xff,
2951 .cache_type = REGCACHE_NONE,
2952 },
2953
2954 {
2955 .name = "hdmi",
2956 .reg_bits = 8,
2957 .val_bits = 8,
2958
2959 .max_register = 0xff,
2960 .cache_type = REGCACHE_NONE,
2961 },
2962 {
2963 .name = "test",
2964 .reg_bits = 8,
2965 .val_bits = 8,
2966
2967 .max_register = 0xff,
2968 .cache_type = REGCACHE_NONE,
2969 },
2970 {
2971 .name = "cp",
2972 .reg_bits = 8,
2973 .val_bits = 8,
2974
2975 .max_register = 0xff,
2976 .cache_type = REGCACHE_NONE,
2977 },
2978 {
2979 .name = "vdp",
2980 .reg_bits = 8,
2981 .val_bits = 8,
2982
2983 .max_register = 0xff,
2984 .cache_type = REGCACHE_NONE,
2985 },
2986};
2987
2988static int configure_regmap(struct adv76xx_state *state, int region)
2989{
2990 int err;
2991
2992 if (!state->i2c_clients[region])
2993 return -ENODEV;
2994
2995 state->regmap[region] =
2996 devm_regmap_init_i2c(state->i2c_clients[region],
2997 &adv76xx_regmap_cnf[region]);
2998
2999 if (IS_ERR(state->regmap[region])) {
3000 err = PTR_ERR(state->regmap[region]);
3001 v4l_err(state->i2c_clients[region],
3002 "Error initializing regmap %d with error %d\n",
3003 region, err);
3004 return -EINVAL;
3005 }
3006
3007 return 0;
3008}
3009
3010static int configure_regmaps(struct adv76xx_state *state)
3011{
3012 int i, err;
3013
3014 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3015 err = configure_regmap(state, i);
3016 if (err && (err != -ENODEV))
3017 return err;
3018 }
3019 return 0;
3020}
3021
f5591da9
DB		 3022static void adv76xx_reset(struct adv76xx_state *state)
3023{
3024 if (state->reset_gpio) {
3025 /* ADV76XX can be reset by a low reset pulse of minimum 5 ms. */
3026 gpiod_set_value_cansleep(state->reset_gpio, 0);
3027 usleep_range(5000, 10000);
3028 gpiod_set_value_cansleep(state->reset_gpio, 1);
3029 /* It is recommended to wait 5 ms after the low pulse before */
3030 /* an I2C write is performed to the ADV76XX. */
3031 usleep_range(5000, 10000);
3032 }
3033}
3034
b44b2e06 3035static int adv76xx_probe(struct i2c_client *client,
54450f59
HV		 3036 const struct i2c_device_id *id)
3037{
591b72fe
HV		 3038 static const struct v4l2_dv_timings cea640x480 =
3039 V4L2_DV_BT_CEA_640X480P59_94;
b44b2e06 3040 struct adv76xx_state *state;
54450f59 3041 struct v4l2_ctrl_handler *hdl;
297a4144 3042 struct v4l2_ctrl *ctrl;
54450f59 3043 struct v4l2_subdev *sd;
c784b1e2 3044 unsigned int i;
f862f57d 3045 unsigned int val, val2;
54450f59
HV		 3046 int err;
3047
3048 /* Check if the adapter supports the needed features */
3049 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3050 return -EIO;
b44b2e06 3051 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
54450f59
HV		 3052 client->addr << 1);
3053
c02b211d 3054 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
54450f59 3055 if (!state) {
b44b2e06 3056 v4l_err(client, "Could not allocate adv76xx_state memory!\n");
54450f59
HV		 3057 return -ENOMEM;
3058 }
3059
b44b2e06 3060 state->i2c_clients[ADV76XX_PAGE_IO] = client;
d42010a1 3061
25a64ac9
MR		 3062 /* initialize variables */
3063 state->restart_stdi_once = true;
ff4f80fd 3064 state->selected_input = ~0;
25a64ac9 3065
f82f313e
LP		 3066 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3067 const struct of_device_id *oid;
3068
b44b2e06 3069 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
f82f313e
LP		 3070 state->info = oid->data;
3071
b44b2e06 3072 err = adv76xx_parse_dt(state);
f82f313e
LP		 3073 if (err < 0) {
3074 v4l_err(client, "DT parsing error\n");
3075 return err;
3076 }
3077 } else if (client->dev.platform_data) {
b44b2e06 3078 struct adv76xx_platform_data *pdata = client->dev.platform_data;
f82f313e 3079
b44b2e06 3080 state->info = (const struct adv76xx_chip_info *)id->driver_data;
f82f313e
LP		 3081 state->pdata = *pdata;
3082 } else {
54450f59 3083 v4l_err(client, "No platform data!\n");
c02b211d 3084 return -ENODEV;
54450f59 3085 }
e9d50e9e
LP		 3086
3087 /* Request GPIOs. */
3088 for (i = 0; i < state->info->num_dv_ports; ++i) {
3089 state->hpd_gpio[i] =
269bd132
UKK		 3090 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3091 GPIOD_OUT_LOW);
e9d50e9e 3092 if (IS_ERR(state->hpd_gpio[i]))
269bd132 3093 return PTR_ERR(state->hpd_gpio[i]);
e9d50e9e 3094
269bd132
UKK		 3095 if (state->hpd_gpio[i])
3096 v4l_info(client, "Handling HPD %u GPIO\n", i);
e9d50e9e 3097 }
f5591da9
DB		 3098 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3099 GPIOD_OUT_HIGH);
3100 if (IS_ERR(state->reset_gpio))
3101 return PTR_ERR(state->reset_gpio);
3102
3103 adv76xx_reset(state);
e9d50e9e 3104
591b72fe 3105 state->timings = cea640x480;
b44b2e06 3106 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
54450f59
HV		 3107
3108 sd = &state->sd;
b44b2e06 3109 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
d42010a1
LPC		 3110 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3111 id->name, i2c_adapter_id(client->adapter),
3112 client->addr);
0975626d 3113 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
54450f59 3114
f862f57d
PA		 3115 /* Configure IO Regmap region */
3116 err = configure_regmap(state, ADV76XX_PAGE_IO);
3117
3118 if (err) {
3119 v4l2_err(sd, "Error configuring IO regmap region\n");
3120 return -ENODEV;
3121 }
3122
d42010a1
LPC		 3123 /*
3124 * Verify that the chip is present. On ADV7604 the RD_INFO register only
3125 * identifies the revision, while on ADV7611 it identifies the model as
3126 * well. Use the HDMI slave address on ADV7604 and RD_INFO on ADV7611.
3127 */
8331d30b
WT		 3128 switch (state->info->type) {
3129 case ADV7604:
f862f57d
PA		 3130 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3131 if (err) {
3132 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3133 return -ENODEV;
3134 }
d42010a1 3135 if (val != 0x68) {
f862f57d 3136 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
d42010a1
LPC		 3137 client->addr << 1);
3138 return -ENODEV;
3139 }
8331d30b
WT		 3140 break;
3141 case ADV7611:
3142 case ADV7612:
f862f57d
PA		 3143 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3144 0xea,
3145 &val);
3146 if (err) {
3147 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3148 return -ENODEV;
3149 }
3150 val2 = val << 8;
3151 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3152 0xeb,
3153 &val);
3154 if (err) {
3155 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3156 return -ENODEV;
3157 }
c1362384 3158 val |= val2;
8331d30b
WT		 3159 if ((state->info->type == ADV7611 && val != 0x2051) ||
3160 (state->info->type == ADV7612 && val != 0x2041)) {
3161 v4l2_err(sd, "not an adv761x on address 0x%x\n",
d42010a1
LPC		 3162 client->addr << 1);
3163 return -ENODEV;
3164 }
8331d30b 3165 break;
54450f59
HV		 3166 }
3167
3168 /* control handlers */
3169 hdl = &state->hdl;
b44b2e06 3170 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
54450f59 3171
b44b2e06 3172 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3173 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
b44b2e06 3174 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3175 V4L2_CID_CONTRAST, 0, 255, 1, 128);
b44b2e06 3176 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3177 V4L2_CID_SATURATION, 0, 255, 1, 128);
b44b2e06 3178 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
54450f59 3179 V4L2_CID_HUE, 0, 128, 1, 0);
297a4144
HV		 3180 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3181 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3182 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3183 if (ctrl)
3184 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
54450f59 3185
54450f59 3186 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
d42010a1
LPC		 3187 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3188 (1 << state->info->num_dv_ports) - 1, 0, 0);
54450f59 3189 state->rgb_quantization_range_ctrl =
b44b2e06 3190 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
54450f59
HV		 3191 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3192 0, V4L2_DV_RGB_RANGE_AUTO);
54450f59
HV		 3193
3194 /* custom controls */
b44b2e06 3195 if (adv76xx_has_afe(state))
d42010a1
LPC		 3196 state->analog_sampling_phase_ctrl =
3197 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
54450f59 3198 state->free_run_color_manual_ctrl =
b44b2e06 3199 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
54450f59 3200 state->free_run_color_ctrl =
b44b2e06 3201 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
54450f59
HV		 3202
3203 sd->ctrl_handler = hdl;
3204 if (hdl->error) {
3205 err = hdl->error;
3206 goto err_hdl;
3207 }
b44b2e06 3208 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
54450f59
HV		 3209 err = -ENODEV;
3210 goto err_hdl;
3211 }
3212
b44b2e06 3213 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
05cacb17
LP		 3214 if (!(BIT(i) & state->info->page_mask))
3215 continue;
54450f59 3216
05cacb17 3217 state->i2c_clients[i] =
b44b2e06 3218 adv76xx_dummy_client(sd, state->pdata.i2c_addresses[i],
05cacb17
LP		 3219 0xf2 + i);
3220 if (state->i2c_clients[i] == NULL) {
d42010a1 3221 err = -ENOMEM;
05cacb17 3222 v4l2_err(sd, "failed to create i2c client %u\n", i);
d42010a1
LPC		 3223 goto err_i2c;
3224 }
3225 }
05cacb17 3226
54450f59 3227 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
b44b2e06 3228 adv76xx_delayed_work_enable_hotplug);
54450f59 3229
c784b1e2
LP		 3230 state->source_pad = state->info->num_dv_ports
3231 + (state->info->has_afe ? 2 : 0);
3232 for (i = 0; i < state->source_pad; ++i)
3233 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3234 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3235
ab22e77c 3236 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
18095107 3237 state->pads);
54450f59
HV		 3238 if (err)
3239 goto err_work_queues;
3240
f862f57d
PA		 3241 /* Configure regmaps */
3242 err = configure_regmaps(state);
3243 if (err)
3244 goto err_entity;
3245
b44b2e06 3246 err = adv76xx_core_init(sd);
54450f59
HV		 3247 if (err)
3248 goto err_entity;
3249 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3250 client->addr << 1, client->adapter->name);
bedc3939
LPC		 3251
3252 err = v4l2_async_register_subdev(sd);
3253 if (err)
3254 goto err_entity;
3255
54450f59
HV		 3256 return 0;
3257
3258err_entity:
3259 media_entity_cleanup(&sd->entity);
3260err_work_queues:
3261 cancel_delayed_work(&state->delayed_work_enable_hotplug);
54450f59 3262err_i2c:
b44b2e06 3263 adv76xx_unregister_clients(state);
54450f59
HV		 3264err_hdl:
3265 v4l2_ctrl_handler_free(hdl);
54450f59
HV		 3266 return err;
3267}
3268
3269/* ----------------------------------------------------------------------- */
3270
b44b2e06 3271static int adv76xx_remove(struct i2c_client *client)
54450f59
HV		 3272{
3273 struct v4l2_subdev *sd = i2c_get_clientdata(client);
b44b2e06 3274 struct adv76xx_state *state = to_state(sd);
54450f59
HV		 3275
3276 cancel_delayed_work(&state->delayed_work_enable_hotplug);
bedc3939 3277 v4l2_async_unregister_subdev(sd);
54450f59 3278 media_entity_cleanup(&sd->entity);
b44b2e06 3279 adv76xx_unregister_clients(to_state(sd));
54450f59 3280 v4l2_ctrl_handler_free(sd->ctrl_handler);
54450f59
HV		 3281 return 0;
3282}
3283
3284/* ----------------------------------------------------------------------- */
3285
b44b2e06 3286static struct i2c_driver adv76xx_driver = {
54450f59 3287 .driver = {
54450f59 3288 .name = "adv7604",
b44b2e06 3289 .of_match_table = of_match_ptr(adv76xx_of_id),
54450f59 3290 },
b44b2e06
PA		 3291 .probe = adv76xx_probe,
3292 .remove = adv76xx_remove,
3293 .id_table = adv76xx_i2c_id,
54450f59
HV		 3294};
3295
b44b2e06 3296module_i2c_driver(adv76xx_driver);
Linux kernel - Deliverables
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