Commit | Line | Data |
---|---|---|
111f3356 JC |
1 | /* |
2 | * A V4L2 driver for OmniVision OV7670 cameras. | |
3 | * | |
4 | * Copyright 2006 One Laptop Per Child Association, Inc. Written | |
5 | * by Jonathan Corbet with substantial inspiration from Mark | |
6 | * McClelland's ovcamchip code. | |
7 | * | |
77d5140f JC |
8 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> |
9 | * | |
111f3356 JC |
10 | * This file may be distributed under the terms of the GNU General |
11 | * Public License, version 2. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
14386c2b | 16 | #include <linux/i2c.h> |
111f3356 | 17 | #include <linux/delay.h> |
7e0a16f6 | 18 | #include <linux/videodev2.h> |
14386c2b | 19 | #include <media/v4l2-device.h> |
3434eb7e | 20 | #include <media/v4l2-chip-ident.h> |
492959c7 | 21 | #include <media/v4l2-ctrls.h> |
959f3bda | 22 | #include <media/v4l2-mediabus.h> |
f8fc7298 | 23 | #include <media/ov7670.h> |
111f3356 | 24 | |
5e614475 | 25 | MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); |
111f3356 JC |
26 | MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); |
27 | MODULE_LICENSE("GPL"); | |
28 | ||
90ab5ee9 | 29 | static bool debug; |
14386c2b HV |
30 | module_param(debug, bool, 0644); |
31 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
32 | ||
111f3356 JC |
33 | /* |
34 | * Basic window sizes. These probably belong somewhere more globally | |
35 | * useful. | |
36 | */ | |
37 | #define VGA_WIDTH 640 | |
38 | #define VGA_HEIGHT 480 | |
39 | #define QVGA_WIDTH 320 | |
40 | #define QVGA_HEIGHT 240 | |
41 | #define CIF_WIDTH 352 | |
42 | #define CIF_HEIGHT 288 | |
43 | #define QCIF_WIDTH 176 | |
44 | #define QCIF_HEIGHT 144 | |
45 | ||
46 | /* | |
47 | * The 7670 sits on i2c with ID 0x42 | |
48 | */ | |
49 | #define OV7670_I2C_ADDR 0x42 | |
50 | ||
f6dd927f JM |
51 | #define PLL_FACTOR 4 |
52 | ||
111f3356 JC |
53 | /* Registers */ |
54 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ | |
55 | #define REG_BLUE 0x01 /* blue gain */ | |
56 | #define REG_RED 0x02 /* red gain */ | |
57 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ | |
58 | #define REG_COM1 0x04 /* Control 1 */ | |
59 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ | |
60 | #define REG_BAVE 0x05 /* U/B Average level */ | |
61 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ | |
62 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ | |
63 | #define REG_RAVE 0x08 /* V/R Average level */ | |
64 | #define REG_COM2 0x09 /* Control 2 */ | |
65 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ | |
66 | #define REG_PID 0x0a /* Product ID MSB */ | |
67 | #define REG_VER 0x0b /* Product ID LSB */ | |
68 | #define REG_COM3 0x0c /* Control 3 */ | |
69 | #define COM3_SWAP 0x40 /* Byte swap */ | |
70 | #define COM3_SCALEEN 0x08 /* Enable scaling */ | |
71 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ | |
72 | #define REG_COM4 0x0d /* Control 4 */ | |
73 | #define REG_COM5 0x0e /* All "reserved" */ | |
74 | #define REG_COM6 0x0f /* Control 6 */ | |
75 | #define REG_AECH 0x10 /* More bits of AEC value */ | |
76 | #define REG_CLKRC 0x11 /* Clocl control */ | |
77 | #define CLK_EXT 0x40 /* Use external clock directly */ | |
78 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ | |
79 | #define REG_COM7 0x12 /* Control 7 */ | |
80 | #define COM7_RESET 0x80 /* Register reset */ | |
81 | #define COM7_FMT_MASK 0x38 | |
82 | #define COM7_FMT_VGA 0x00 | |
83 | #define COM7_FMT_CIF 0x20 /* CIF format */ | |
84 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ | |
85 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ | |
86 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ | |
87 | #define COM7_YUV 0x00 /* YUV */ | |
88 | #define COM7_BAYER 0x01 /* Bayer format */ | |
89 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ | |
90 | #define REG_COM8 0x13 /* Control 8 */ | |
91 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ | |
92 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ | |
93 | #define COM8_BFILT 0x20 /* Band filter enable */ | |
94 | #define COM8_AGC 0x04 /* Auto gain enable */ | |
95 | #define COM8_AWB 0x02 /* White balance enable */ | |
96 | #define COM8_AEC 0x01 /* Auto exposure enable */ | |
97 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ | |
98 | #define REG_COM10 0x15 /* Control 10 */ | |
99 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ | |
100 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ | |
101 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ | |
102 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ | |
103 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ | |
104 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ | |
105 | #define REG_HSTART 0x17 /* Horiz start high bits */ | |
106 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ | |
107 | #define REG_VSTART 0x19 /* Vert start high bits */ | |
108 | #define REG_VSTOP 0x1a /* Vert stop high bits */ | |
109 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ | |
110 | #define REG_MIDH 0x1c /* Manuf. ID high */ | |
111 | #define REG_MIDL 0x1d /* Manuf. ID low */ | |
112 | #define REG_MVFP 0x1e /* Mirror / vflip */ | |
113 | #define MVFP_MIRROR 0x20 /* Mirror image */ | |
114 | #define MVFP_FLIP 0x10 /* Vertical flip */ | |
115 | ||
116 | #define REG_AEW 0x24 /* AGC upper limit */ | |
117 | #define REG_AEB 0x25 /* AGC lower limit */ | |
118 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ | |
119 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ | |
120 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ | |
121 | #define REG_HREF 0x32 /* HREF pieces */ | |
122 | #define REG_TSLB 0x3a /* lots of stuff */ | |
123 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ | |
124 | #define REG_COM11 0x3b /* Control 11 */ | |
125 | #define COM11_NIGHT 0x80 /* NIght mode enable */ | |
126 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ | |
127 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ | |
128 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ | |
129 | #define COM11_EXP 0x02 | |
130 | #define REG_COM12 0x3c /* Control 12 */ | |
131 | #define COM12_HREF 0x80 /* HREF always */ | |
132 | #define REG_COM13 0x3d /* Control 13 */ | |
133 | #define COM13_GAMMA 0x80 /* Gamma enable */ | |
134 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ | |
135 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ | |
136 | #define REG_COM14 0x3e /* Control 14 */ | |
137 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ | |
138 | #define REG_EDGE 0x3f /* Edge enhancement factor */ | |
139 | #define REG_COM15 0x40 /* Control 15 */ | |
140 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ | |
141 | #define COM15_R01FE 0x80 /* 01 to FE */ | |
142 | #define COM15_R00FF 0xc0 /* 00 to FF */ | |
143 | #define COM15_RGB565 0x10 /* RGB565 output */ | |
144 | #define COM15_RGB555 0x30 /* RGB555 output */ | |
145 | #define REG_COM16 0x41 /* Control 16 */ | |
146 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ | |
147 | #define REG_COM17 0x42 /* Control 17 */ | |
148 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ | |
149 | #define COM17_CBAR 0x08 /* DSP Color bar */ | |
150 | ||
f9a76156 JC |
151 | /* |
152 | * This matrix defines how the colors are generated, must be | |
153 | * tweaked to adjust hue and saturation. | |
154 | * | |
155 | * Order: v-red, v-green, v-blue, u-red, u-green, u-blue | |
156 | * | |
157 | * They are nine-bit signed quantities, with the sign bit | |
158 | * stored in 0x58. Sign for v-red is bit 0, and up from there. | |
159 | */ | |
160 | #define REG_CMATRIX_BASE 0x4f | |
161 | #define CMATRIX_LEN 6 | |
162 | #define REG_CMATRIX_SIGN 0x58 | |
163 | ||
164 | ||
111f3356 JC |
165 | #define REG_BRIGHT 0x55 /* Brightness */ |
166 | #define REG_CONTRAS 0x56 /* Contrast control */ | |
167 | ||
168 | #define REG_GFIX 0x69 /* Fix gain control */ | |
169 | ||
f6dd927f JM |
170 | #define REG_DBLV 0x6b /* PLL control an debugging */ |
171 | #define DBLV_BYPASS 0x00 /* Bypass PLL */ | |
172 | #define DBLV_X4 0x01 /* clock x4 */ | |
173 | #define DBLV_X6 0x10 /* clock x6 */ | |
174 | #define DBLV_X8 0x11 /* clock x8 */ | |
175 | ||
585553ec JC |
176 | #define REG_REG76 0x76 /* OV's name */ |
177 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ | |
178 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ | |
179 | ||
111f3356 JC |
180 | #define REG_RGB444 0x8c /* RGB 444 control */ |
181 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ | |
182 | #define R444_RGBX 0x01 /* Empty nibble at end */ | |
183 | ||
184 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ | |
185 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ | |
186 | ||
187 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ | |
188 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ | |
189 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ | |
190 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ | |
191 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ | |
192 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ | |
193 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ | |
194 | ||
d058e237 JM |
195 | enum ov7670_model { |
196 | MODEL_OV7670 = 0, | |
197 | MODEL_OV7675, | |
198 | }; | |
199 | ||
200 | struct ov7670_win_size { | |
201 | int width; | |
202 | int height; | |
203 | unsigned char com7_bit; | |
204 | int hstart; /* Start/stop values for the camera. Note */ | |
205 | int hstop; /* that they do not always make complete */ | |
206 | int vstart; /* sense to humans, but evidently the sensor */ | |
207 | int vstop; /* will do the right thing... */ | |
208 | struct regval_list *regs; /* Regs to tweak */ | |
209 | }; | |
210 | ||
211 | struct ov7670_devtype { | |
212 | /* formats supported for each model */ | |
213 | struct ov7670_win_size *win_sizes; | |
214 | unsigned int n_win_sizes; | |
f6dd927f JM |
215 | /* callbacks for frame rate control */ |
216 | int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *); | |
217 | void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *); | |
d058e237 | 218 | }; |
111f3356 | 219 | |
f9a76156 JC |
220 | /* |
221 | * Information we maintain about a known sensor. | |
222 | */ | |
223 | struct ov7670_format_struct; /* coming later */ | |
224 | struct ov7670_info { | |
14386c2b | 225 | struct v4l2_subdev sd; |
492959c7 JM |
226 | struct v4l2_ctrl_handler hdl; |
227 | struct { | |
228 | /* gain cluster */ | |
229 | struct v4l2_ctrl *auto_gain; | |
230 | struct v4l2_ctrl *gain; | |
231 | }; | |
232 | struct { | |
233 | /* exposure cluster */ | |
234 | struct v4l2_ctrl *auto_exposure; | |
235 | struct v4l2_ctrl *exposure; | |
236 | }; | |
237 | struct { | |
238 | /* saturation/hue cluster */ | |
239 | struct v4l2_ctrl *saturation; | |
240 | struct v4l2_ctrl *hue; | |
241 | }; | |
f9a76156 | 242 | struct ov7670_format_struct *fmt; /* Current format */ |
75e2bdad DD |
243 | int min_width; /* Filter out smaller sizes */ |
244 | int min_height; /* Filter out smaller sizes */ | |
245 | int clock_speed; /* External clock speed (MHz) */ | |
d8d20155 | 246 | u8 clkrc; /* Clock divider value */ |
75e2bdad | 247 | bool use_smbus; /* Use smbus I/O instead of I2C */ |
04ee6d92 | 248 | bool pll_bypass; |
ee95258e | 249 | bool pclk_hb_disable; |
d058e237 | 250 | const struct ov7670_devtype *devtype; /* Device specifics */ |
f9a76156 JC |
251 | }; |
252 | ||
14386c2b HV |
253 | static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) |
254 | { | |
255 | return container_of(sd, struct ov7670_info, sd); | |
256 | } | |
f9a76156 | 257 | |
492959c7 JM |
258 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) |
259 | { | |
260 | return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd; | |
261 | } | |
262 | ||
f9a76156 JC |
263 | |
264 | ||
111f3356 JC |
265 | /* |
266 | * The default register settings, as obtained from OmniVision. There | |
267 | * is really no making sense of most of these - lots of "reserved" values | |
268 | * and such. | |
269 | * | |
270 | * These settings give VGA YUYV. | |
271 | */ | |
272 | ||
273 | struct regval_list { | |
274 | unsigned char reg_num; | |
275 | unsigned char value; | |
276 | }; | |
277 | ||
278 | static struct regval_list ov7670_default_regs[] = { | |
279 | { REG_COM7, COM7_RESET }, | |
280 | /* | |
281 | * Clock scale: 3 = 15fps | |
282 | * 2 = 20fps | |
283 | * 1 = 30fps | |
284 | */ | |
f9a76156 | 285 | { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ |
111f3356 JC |
286 | { REG_TSLB, 0x04 }, /* OV */ |
287 | { REG_COM7, 0 }, /* VGA */ | |
288 | /* | |
289 | * Set the hardware window. These values from OV don't entirely | |
290 | * make sense - hstop is less than hstart. But they work... | |
291 | */ | |
292 | { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, | |
293 | { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, | |
294 | { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, | |
295 | ||
296 | { REG_COM3, 0 }, { REG_COM14, 0 }, | |
297 | /* Mystery scaling numbers */ | |
298 | { 0x70, 0x3a }, { 0x71, 0x35 }, | |
299 | { 0x72, 0x11 }, { 0x73, 0xf0 }, | |
300 | { 0xa2, 0x02 }, { REG_COM10, 0x0 }, | |
301 | ||
302 | /* Gamma curve values */ | |
303 | { 0x7a, 0x20 }, { 0x7b, 0x10 }, | |
304 | { 0x7c, 0x1e }, { 0x7d, 0x35 }, | |
305 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, | |
306 | { 0x80, 0x76 }, { 0x81, 0x80 }, | |
307 | { 0x82, 0x88 }, { 0x83, 0x8f }, | |
308 | { 0x84, 0x96 }, { 0x85, 0xa3 }, | |
309 | { 0x86, 0xaf }, { 0x87, 0xc4 }, | |
310 | { 0x88, 0xd7 }, { 0x89, 0xe8 }, | |
311 | ||
312 | /* AGC and AEC parameters. Note we start by disabling those features, | |
313 | then turn them only after tweaking the values. */ | |
314 | { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, | |
315 | { REG_GAIN, 0 }, { REG_AECH, 0 }, | |
316 | { REG_COM4, 0x40 }, /* magic reserved bit */ | |
317 | { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ | |
318 | { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, | |
319 | { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, | |
320 | { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, | |
321 | { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ | |
322 | { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, | |
323 | { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, | |
324 | { REG_HAECC7, 0x94 }, | |
325 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, | |
326 | ||
327 | /* Almost all of these are magic "reserved" values. */ | |
328 | { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, | |
7f7b12f0 | 329 | { 0x16, 0x02 }, { REG_MVFP, 0x07 }, |
111f3356 JC |
330 | { 0x21, 0x02 }, { 0x22, 0x91 }, |
331 | { 0x29, 0x07 }, { 0x33, 0x0b }, | |
332 | { 0x35, 0x0b }, { 0x37, 0x1d }, | |
333 | { 0x38, 0x71 }, { 0x39, 0x2a }, | |
334 | { REG_COM12, 0x78 }, { 0x4d, 0x40 }, | |
335 | { 0x4e, 0x20 }, { REG_GFIX, 0 }, | |
336 | { 0x6b, 0x4a }, { 0x74, 0x10 }, | |
337 | { 0x8d, 0x4f }, { 0x8e, 0 }, | |
338 | { 0x8f, 0 }, { 0x90, 0 }, | |
339 | { 0x91, 0 }, { 0x96, 0 }, | |
340 | { 0x9a, 0 }, { 0xb0, 0x84 }, | |
341 | { 0xb1, 0x0c }, { 0xb2, 0x0e }, | |
342 | { 0xb3, 0x82 }, { 0xb8, 0x0a }, | |
343 | ||
344 | /* More reserved magic, some of which tweaks white balance */ | |
345 | { 0x43, 0x0a }, { 0x44, 0xf0 }, | |
346 | { 0x45, 0x34 }, { 0x46, 0x58 }, | |
347 | { 0x47, 0x28 }, { 0x48, 0x3a }, | |
348 | { 0x59, 0x88 }, { 0x5a, 0x88 }, | |
349 | { 0x5b, 0x44 }, { 0x5c, 0x67 }, | |
350 | { 0x5d, 0x49 }, { 0x5e, 0x0e }, | |
351 | { 0x6c, 0x0a }, { 0x6d, 0x55 }, | |
352 | { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ | |
353 | { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, | |
354 | { REG_RED, 0x60 }, | |
355 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, | |
356 | ||
357 | /* Matrix coefficients */ | |
358 | { 0x4f, 0x80 }, { 0x50, 0x80 }, | |
359 | { 0x51, 0 }, { 0x52, 0x22 }, | |
360 | { 0x53, 0x5e }, { 0x54, 0x80 }, | |
361 | { 0x58, 0x9e }, | |
362 | ||
363 | { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, | |
364 | { 0x75, 0x05 }, { 0x76, 0xe1 }, | |
365 | { 0x4c, 0 }, { 0x77, 0x01 }, | |
366 | { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, | |
367 | { 0xc9, 0x60 }, { REG_COM16, 0x38 }, | |
368 | { 0x56, 0x40 }, | |
369 | ||
c8f5b2f5 | 370 | { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, |
111f3356 JC |
371 | { 0xa4, 0x88 }, { 0x96, 0 }, |
372 | { 0x97, 0x30 }, { 0x98, 0x20 }, | |
373 | { 0x99, 0x30 }, { 0x9a, 0x84 }, | |
374 | { 0x9b, 0x29 }, { 0x9c, 0x03 }, | |
375 | { 0x9d, 0x4c }, { 0x9e, 0x3f }, | |
376 | { 0x78, 0x04 }, | |
377 | ||
378 | /* Extra-weird stuff. Some sort of multiplexor register */ | |
379 | { 0x79, 0x01 }, { 0xc8, 0xf0 }, | |
380 | { 0x79, 0x0f }, { 0xc8, 0x00 }, | |
381 | { 0x79, 0x10 }, { 0xc8, 0x7e }, | |
382 | { 0x79, 0x0a }, { 0xc8, 0x80 }, | |
383 | { 0x79, 0x0b }, { 0xc8, 0x01 }, | |
384 | { 0x79, 0x0c }, { 0xc8, 0x0f }, | |
385 | { 0x79, 0x0d }, { 0xc8, 0x20 }, | |
386 | { 0x79, 0x09 }, { 0xc8, 0x80 }, | |
387 | { 0x79, 0x02 }, { 0xc8, 0xc0 }, | |
388 | { 0x79, 0x03 }, { 0xc8, 0x40 }, | |
389 | { 0x79, 0x05 }, { 0xc8, 0x30 }, | |
390 | { 0x79, 0x26 }, | |
391 | ||
111f3356 JC |
392 | { 0xff, 0xff }, /* END MARKER */ |
393 | }; | |
394 | ||
395 | ||
396 | /* | |
397 | * Here we'll try to encapsulate the changes for just the output | |
398 | * video format. | |
399 | * | |
400 | * RGB656 and YUV422 come from OV; RGB444 is homebrewed. | |
401 | * | |
402 | * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. | |
403 | */ | |
404 | ||
405 | ||
406 | static struct regval_list ov7670_fmt_yuv422[] = { | |
407 | { REG_COM7, 0x0 }, /* Selects YUV mode */ | |
408 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 409 | { REG_COM1, 0 }, /* CCIR601 */ |
111f3356 | 410 | { REG_COM15, COM15_R00FF }, |
c01b7429 | 411 | { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */ |
111f3356 JC |
412 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ |
413 | { 0x50, 0x80 }, /* "matrix coefficient 2" */ | |
f9a76156 | 414 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
415 | { 0x52, 0x22 }, /* "matrix coefficient 4" */ |
416 | { 0x53, 0x5e }, /* "matrix coefficient 5" */ | |
417 | { 0x54, 0x80 }, /* "matrix coefficient 6" */ | |
418 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
419 | { 0xff, 0xff }, | |
420 | }; | |
421 | ||
422 | static struct regval_list ov7670_fmt_rgb565[] = { | |
423 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
424 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 425 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
426 | { REG_COM15, COM15_RGB565 }, |
427 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
428 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
429 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 430 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
431 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
432 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
433 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
434 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
435 | { 0xff, 0xff }, | |
436 | }; | |
437 | ||
438 | static struct regval_list ov7670_fmt_rgb444[] = { | |
439 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
440 | { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ | |
97693f91 | 441 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
442 | { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ |
443 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
444 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
445 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 446 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
447 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
448 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
449 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
450 | { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ | |
451 | { 0xff, 0xff }, | |
452 | }; | |
453 | ||
585553ec JC |
454 | static struct regval_list ov7670_fmt_raw[] = { |
455 | { REG_COM7, COM7_BAYER }, | |
456 | { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ | |
457 | { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ | |
458 | { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ | |
459 | { 0xff, 0xff }, | |
460 | }; | |
111f3356 JC |
461 | |
462 | ||
463 | ||
464 | /* | |
465 | * Low-level register I/O. | |
46714209 JC |
466 | * |
467 | * Note that there are two versions of these. On the XO 1, the | |
468 | * i2c controller only does SMBUS, so that's what we use. The | |
469 | * ov7670 is not really an SMBUS device, though, so the communication | |
470 | * is not always entirely reliable. | |
471 | */ | |
75e2bdad | 472 | static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
473 | unsigned char *value) |
474 | { | |
475 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
476 | int ret; | |
477 | ||
478 | ret = i2c_smbus_read_byte_data(client, reg); | |
479 | if (ret >= 0) { | |
480 | *value = (unsigned char)ret; | |
481 | ret = 0; | |
482 | } | |
483 | return ret; | |
484 | } | |
485 | ||
486 | ||
75e2bdad | 487 | static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
488 | unsigned char value) |
489 | { | |
490 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
491 | int ret = i2c_smbus_write_byte_data(client, reg, value); | |
492 | ||
493 | if (reg == REG_COM7 && (value & COM7_RESET)) | |
494 | msleep(5); /* Wait for reset to run */ | |
495 | return ret; | |
496 | } | |
497 | ||
46714209 JC |
498 | /* |
499 | * On most platforms, we'd rather do straight i2c I/O. | |
111f3356 | 500 | */ |
75e2bdad | 501 | static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
502 | unsigned char *value) |
503 | { | |
14386c2b | 504 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
505 | u8 data = reg; |
506 | struct i2c_msg msg; | |
111f3356 JC |
507 | int ret; |
508 | ||
2bf7de48 JC |
509 | /* |
510 | * Send out the register address... | |
511 | */ | |
512 | msg.addr = client->addr; | |
513 | msg.flags = 0; | |
514 | msg.len = 1; | |
515 | msg.buf = &data; | |
516 | ret = i2c_transfer(client->adapter, &msg, 1); | |
517 | if (ret < 0) { | |
518 | printk(KERN_ERR "Error %d on register write\n", ret); | |
519 | return ret; | |
520 | } | |
521 | /* | |
522 | * ...then read back the result. | |
523 | */ | |
524 | msg.flags = I2C_M_RD; | |
525 | ret = i2c_transfer(client->adapter, &msg, 1); | |
bca5c2c5 | 526 | if (ret >= 0) { |
2bf7de48 | 527 | *value = data; |
bca5c2c5 AS |
528 | ret = 0; |
529 | } | |
111f3356 JC |
530 | return ret; |
531 | } | |
532 | ||
533 | ||
75e2bdad | 534 | static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
535 | unsigned char value) |
536 | { | |
14386c2b | 537 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
538 | struct i2c_msg msg; |
539 | unsigned char data[2] = { reg, value }; | |
540 | int ret; | |
14386c2b | 541 | |
2bf7de48 JC |
542 | msg.addr = client->addr; |
543 | msg.flags = 0; | |
544 | msg.len = 2; | |
545 | msg.buf = data; | |
546 | ret = i2c_transfer(client->adapter, &msg, 1); | |
547 | if (ret > 0) | |
548 | ret = 0; | |
6d77444a | 549 | if (reg == REG_COM7 && (value & COM7_RESET)) |
97693f91 | 550 | msleep(5); /* Wait for reset to run */ |
6d77444a | 551 | return ret; |
111f3356 JC |
552 | } |
553 | ||
75e2bdad DD |
554 | static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, |
555 | unsigned char *value) | |
556 | { | |
557 | struct ov7670_info *info = to_state(sd); | |
558 | if (info->use_smbus) | |
559 | return ov7670_read_smbus(sd, reg, value); | |
560 | else | |
561 | return ov7670_read_i2c(sd, reg, value); | |
562 | } | |
563 | ||
564 | static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, | |
565 | unsigned char value) | |
566 | { | |
567 | struct ov7670_info *info = to_state(sd); | |
568 | if (info->use_smbus) | |
569 | return ov7670_write_smbus(sd, reg, value); | |
570 | else | |
571 | return ov7670_write_i2c(sd, reg, value); | |
572 | } | |
111f3356 JC |
573 | |
574 | /* | |
575 | * Write a list of register settings; ff/ff stops the process. | |
576 | */ | |
14386c2b | 577 | static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) |
111f3356 JC |
578 | { |
579 | while (vals->reg_num != 0xff || vals->value != 0xff) { | |
14386c2b | 580 | int ret = ov7670_write(sd, vals->reg_num, vals->value); |
111f3356 JC |
581 | if (ret < 0) |
582 | return ret; | |
583 | vals++; | |
584 | } | |
585 | return 0; | |
586 | } | |
587 | ||
588 | ||
589 | /* | |
590 | * Stuff that knows about the sensor. | |
591 | */ | |
14386c2b | 592 | static int ov7670_reset(struct v4l2_subdev *sd, u32 val) |
111f3356 | 593 | { |
14386c2b | 594 | ov7670_write(sd, REG_COM7, COM7_RESET); |
111f3356 | 595 | msleep(1); |
14386c2b | 596 | return 0; |
111f3356 JC |
597 | } |
598 | ||
599 | ||
14386c2b | 600 | static int ov7670_init(struct v4l2_subdev *sd, u32 val) |
111f3356 | 601 | { |
14386c2b | 602 | return ov7670_write_array(sd, ov7670_default_regs); |
111f3356 JC |
603 | } |
604 | ||
605 | ||
606 | ||
14386c2b | 607 | static int ov7670_detect(struct v4l2_subdev *sd) |
111f3356 JC |
608 | { |
609 | unsigned char v; | |
610 | int ret; | |
611 | ||
14386c2b | 612 | ret = ov7670_init(sd, 0); |
111f3356 JC |
613 | if (ret < 0) |
614 | return ret; | |
14386c2b | 615 | ret = ov7670_read(sd, REG_MIDH, &v); |
111f3356 JC |
616 | if (ret < 0) |
617 | return ret; | |
618 | if (v != 0x7f) /* OV manuf. id. */ | |
619 | return -ENODEV; | |
14386c2b | 620 | ret = ov7670_read(sd, REG_MIDL, &v); |
111f3356 JC |
621 | if (ret < 0) |
622 | return ret; | |
623 | if (v != 0xa2) | |
624 | return -ENODEV; | |
625 | /* | |
626 | * OK, we know we have an OmniVision chip...but which one? | |
627 | */ | |
14386c2b | 628 | ret = ov7670_read(sd, REG_PID, &v); |
111f3356 JC |
629 | if (ret < 0) |
630 | return ret; | |
631 | if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ | |
632 | return -ENODEV; | |
14386c2b | 633 | ret = ov7670_read(sd, REG_VER, &v); |
111f3356 JC |
634 | if (ret < 0) |
635 | return ret; | |
636 | if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ | |
637 | return -ENODEV; | |
638 | return 0; | |
639 | } | |
640 | ||
641 | ||
f9a76156 JC |
642 | /* |
643 | * Store information about the video data format. The color matrix | |
644 | * is deeply tied into the format, so keep the relevant values here. | |
959f3bda | 645 | * The magic matrix numbers come from OmniVision. |
f9a76156 | 646 | */ |
111f3356 | 647 | static struct ov7670_format_struct { |
959f3bda HV |
648 | enum v4l2_mbus_pixelcode mbus_code; |
649 | enum v4l2_colorspace colorspace; | |
111f3356 | 650 | struct regval_list *regs; |
f9a76156 | 651 | int cmatrix[CMATRIX_LEN]; |
111f3356 JC |
652 | } ov7670_formats[] = { |
653 | { | |
959f3bda HV |
654 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, |
655 | .colorspace = V4L2_COLORSPACE_JPEG, | |
111f3356 | 656 | .regs = ov7670_fmt_yuv422, |
f9a76156 | 657 | .cmatrix = { 128, -128, 0, -34, -94, 128 }, |
111f3356 JC |
658 | }, |
659 | { | |
959f3bda HV |
660 | .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE, |
661 | .colorspace = V4L2_COLORSPACE_SRGB, | |
111f3356 | 662 | .regs = ov7670_fmt_rgb444, |
f9a76156 | 663 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
111f3356 JC |
664 | }, |
665 | { | |
959f3bda HV |
666 | .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE, |
667 | .colorspace = V4L2_COLORSPACE_SRGB, | |
111f3356 | 668 | .regs = ov7670_fmt_rgb565, |
f9a76156 | 669 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
585553ec JC |
670 | }, |
671 | { | |
959f3bda HV |
672 | .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8, |
673 | .colorspace = V4L2_COLORSPACE_SRGB, | |
585553ec JC |
674 | .regs = ov7670_fmt_raw, |
675 | .cmatrix = { 0, 0, 0, 0, 0, 0 }, | |
111f3356 | 676 | }, |
111f3356 | 677 | }; |
585553ec | 678 | #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) |
111f3356 | 679 | |
111f3356 JC |
680 | |
681 | /* | |
682 | * Then there is the issue of window sizes. Try to capture the info here. | |
683 | */ | |
f9a76156 JC |
684 | |
685 | /* | |
686 | * QCIF mode is done (by OV) in a very strange way - it actually looks like | |
687 | * VGA with weird scaling options - they do *not* use the canned QCIF mode | |
688 | * which is allegedly provided by the sensor. So here's the weird register | |
689 | * settings. | |
690 | */ | |
691 | static struct regval_list ov7670_qcif_regs[] = { | |
692 | { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, | |
693 | { REG_COM3, COM3_DCWEN }, | |
694 | { REG_COM14, COM14_DCWEN | 0x01}, | |
695 | { 0x73, 0xf1 }, | |
696 | { 0xa2, 0x52 }, | |
697 | { 0x7b, 0x1c }, | |
698 | { 0x7c, 0x28 }, | |
699 | { 0x7d, 0x3c }, | |
700 | { 0x7f, 0x69 }, | |
701 | { REG_COM9, 0x38 }, | |
702 | { 0xa1, 0x0b }, | |
703 | { 0x74, 0x19 }, | |
704 | { 0x9a, 0x80 }, | |
705 | { 0x43, 0x14 }, | |
706 | { REG_COM13, 0xc0 }, | |
707 | { 0xff, 0xff }, | |
708 | }; | |
709 | ||
d058e237 | 710 | static struct ov7670_win_size ov7670_win_sizes[] = { |
111f3356 JC |
711 | /* VGA */ |
712 | { | |
713 | .width = VGA_WIDTH, | |
714 | .height = VGA_HEIGHT, | |
715 | .com7_bit = COM7_FMT_VGA, | |
d058e237 JM |
716 | .hstart = 158, /* These values from */ |
717 | .hstop = 14, /* Omnivision */ | |
111f3356 JC |
718 | .vstart = 10, |
719 | .vstop = 490, | |
d058e237 | 720 | .regs = NULL, |
111f3356 JC |
721 | }, |
722 | /* CIF */ | |
723 | { | |
724 | .width = CIF_WIDTH, | |
725 | .height = CIF_HEIGHT, | |
726 | .com7_bit = COM7_FMT_CIF, | |
d058e237 | 727 | .hstart = 170, /* Empirically determined */ |
111f3356 JC |
728 | .hstop = 90, |
729 | .vstart = 14, | |
730 | .vstop = 494, | |
d058e237 | 731 | .regs = NULL, |
111f3356 JC |
732 | }, |
733 | /* QVGA */ | |
734 | { | |
735 | .width = QVGA_WIDTH, | |
736 | .height = QVGA_HEIGHT, | |
737 | .com7_bit = COM7_FMT_QVGA, | |
d058e237 | 738 | .hstart = 168, /* Empirically determined */ |
dc4589c8 DD |
739 | .hstop = 24, |
740 | .vstart = 12, | |
741 | .vstop = 492, | |
d058e237 | 742 | .regs = NULL, |
f9a76156 JC |
743 | }, |
744 | /* QCIF */ | |
745 | { | |
746 | .width = QCIF_WIDTH, | |
747 | .height = QCIF_HEIGHT, | |
748 | .com7_bit = COM7_FMT_VGA, /* see comment above */ | |
d058e237 | 749 | .hstart = 456, /* Empirically determined */ |
f9a76156 JC |
750 | .hstop = 24, |
751 | .vstart = 14, | |
752 | .vstop = 494, | |
d058e237 JM |
753 | .regs = ov7670_qcif_regs, |
754 | } | |
111f3356 JC |
755 | }; |
756 | ||
d058e237 JM |
757 | static struct ov7670_win_size ov7675_win_sizes[] = { |
758 | /* | |
759 | * Currently, only VGA is supported. Theoretically it could be possible | |
760 | * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a | |
761 | * base and tweak them empirically could be required. | |
762 | */ | |
763 | { | |
764 | .width = VGA_WIDTH, | |
765 | .height = VGA_HEIGHT, | |
766 | .com7_bit = COM7_FMT_VGA, | |
767 | .hstart = 158, /* These values from */ | |
768 | .hstop = 14, /* Omnivision */ | |
769 | .vstart = 14, /* Empirically determined */ | |
770 | .vstop = 494, | |
771 | .regs = NULL, | |
772 | } | |
773 | }; | |
111f3356 | 774 | |
f6dd927f JM |
775 | static void ov7675_get_framerate(struct v4l2_subdev *sd, |
776 | struct v4l2_fract *tpf) | |
777 | { | |
778 | struct ov7670_info *info = to_state(sd); | |
779 | u32 clkrc = info->clkrc; | |
04ee6d92 JM |
780 | int pll_factor; |
781 | ||
782 | if (info->pll_bypass) | |
783 | pll_factor = 1; | |
784 | else | |
785 | pll_factor = PLL_FACTOR; | |
f6dd927f JM |
786 | |
787 | clkrc++; | |
788 | if (info->fmt->mbus_code == V4L2_MBUS_FMT_SBGGR8_1X8) | |
789 | clkrc = (clkrc >> 1); | |
790 | ||
791 | tpf->numerator = 1; | |
792 | tpf->denominator = (5 * pll_factor * info->clock_speed) / | |
793 | (4 * clkrc); | |
794 | } | |
795 | ||
796 | static int ov7675_set_framerate(struct v4l2_subdev *sd, | |
797 | struct v4l2_fract *tpf) | |
798 | { | |
799 | struct ov7670_info *info = to_state(sd); | |
800 | u32 clkrc; | |
04ee6d92 | 801 | int pll_factor; |
f6dd927f JM |
802 | int ret; |
803 | ||
804 | /* | |
805 | * The formula is fps = 5/4*pixclk for YUV/RGB and | |
806 | * fps = 5/2*pixclk for RAW. | |
807 | * | |
808 | * pixclk = clock_speed / (clkrc + 1) * PLLfactor | |
809 | * | |
810 | */ | |
04ee6d92 JM |
811 | if (info->pll_bypass) { |
812 | pll_factor = 1; | |
813 | ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS); | |
814 | } else { | |
815 | pll_factor = PLL_FACTOR; | |
816 | ret = ov7670_write(sd, REG_DBLV, DBLV_X4); | |
817 | } | |
818 | if (ret < 0) | |
819 | return ret; | |
820 | ||
f6dd927f JM |
821 | if (tpf->numerator == 0 || tpf->denominator == 0) { |
822 | clkrc = 0; | |
823 | } else { | |
824 | clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) / | |
825 | (4 * tpf->denominator); | |
826 | if (info->fmt->mbus_code == V4L2_MBUS_FMT_SBGGR8_1X8) | |
827 | clkrc = (clkrc << 1); | |
828 | clkrc--; | |
829 | } | |
830 | ||
831 | /* | |
832 | * The datasheet claims that clkrc = 0 will divide the input clock by 1 | |
833 | * but we've checked with an oscilloscope that it divides by 2 instead. | |
834 | * So, if clkrc = 0 just bypass the divider. | |
835 | */ | |
836 | if (clkrc <= 0) | |
837 | clkrc = CLK_EXT; | |
838 | else if (clkrc > CLK_SCALE) | |
839 | clkrc = CLK_SCALE; | |
840 | info->clkrc = clkrc; | |
841 | ||
842 | /* Recalculate frame rate */ | |
843 | ov7675_get_framerate(sd, tpf); | |
844 | ||
845 | ret = ov7670_write(sd, REG_CLKRC, info->clkrc); | |
846 | if (ret < 0) | |
847 | return ret; | |
04ee6d92 | 848 | |
f6dd927f JM |
849 | return ov7670_write(sd, REG_DBLV, DBLV_X4); |
850 | } | |
851 | ||
852 | static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd, | |
853 | struct v4l2_fract *tpf) | |
854 | { | |
855 | struct ov7670_info *info = to_state(sd); | |
856 | ||
857 | tpf->numerator = 1; | |
858 | tpf->denominator = info->clock_speed; | |
859 | if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) | |
860 | tpf->denominator /= (info->clkrc & CLK_SCALE); | |
861 | } | |
862 | ||
863 | static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd, | |
864 | struct v4l2_fract *tpf) | |
865 | { | |
866 | struct ov7670_info *info = to_state(sd); | |
867 | int div; | |
868 | ||
869 | if (tpf->numerator == 0 || tpf->denominator == 0) | |
870 | div = 1; /* Reset to full rate */ | |
871 | else | |
872 | div = (tpf->numerator * info->clock_speed) / tpf->denominator; | |
873 | if (div == 0) | |
874 | div = 1; | |
875 | else if (div > CLK_SCALE) | |
876 | div = CLK_SCALE; | |
877 | info->clkrc = (info->clkrc & 0x80) | div; | |
878 | tpf->numerator = 1; | |
879 | tpf->denominator = info->clock_speed / div; | |
880 | return ov7670_write(sd, REG_CLKRC, info->clkrc); | |
881 | } | |
882 | ||
111f3356 JC |
883 | /* |
884 | * Store a set of start/stop values into the camera. | |
885 | */ | |
14386c2b | 886 | static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, |
111f3356 JC |
887 | int vstart, int vstop) |
888 | { | |
889 | int ret; | |
890 | unsigned char v; | |
891 | /* | |
892 | * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of | |
893 | * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is | |
894 | * a mystery "edge offset" value in the top two bits of href. | |
895 | */ | |
14386c2b HV |
896 | ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); |
897 | ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); | |
898 | ret += ov7670_read(sd, REG_HREF, &v); | |
111f3356 JC |
899 | v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); |
900 | msleep(10); | |
14386c2b | 901 | ret += ov7670_write(sd, REG_HREF, v); |
111f3356 JC |
902 | /* |
903 | * Vertical: similar arrangement, but only 10 bits. | |
904 | */ | |
14386c2b HV |
905 | ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); |
906 | ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); | |
907 | ret += ov7670_read(sd, REG_VREF, &v); | |
111f3356 JC |
908 | v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); |
909 | msleep(10); | |
14386c2b | 910 | ret += ov7670_write(sd, REG_VREF, v); |
111f3356 JC |
911 | return ret; |
912 | } | |
913 | ||
914 | ||
959f3bda HV |
915 | static int ov7670_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index, |
916 | enum v4l2_mbus_pixelcode *code) | |
917 | { | |
918 | if (index >= N_OV7670_FMTS) | |
919 | return -EINVAL; | |
920 | ||
921 | *code = ov7670_formats[index].mbus_code; | |
922 | return 0; | |
923 | } | |
111f3356 | 924 | |
14386c2b | 925 | static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, |
959f3bda | 926 | struct v4l2_mbus_framefmt *fmt, |
111f3356 JC |
927 | struct ov7670_format_struct **ret_fmt, |
928 | struct ov7670_win_size **ret_wsize) | |
929 | { | |
f748cd3e | 930 | int index, i; |
111f3356 | 931 | struct ov7670_win_size *wsize; |
d058e237 JM |
932 | struct ov7670_info *info = to_state(sd); |
933 | unsigned int n_win_sizes = info->devtype->n_win_sizes; | |
f748cd3e | 934 | unsigned int win_sizes_limit = n_win_sizes; |
111f3356 JC |
935 | |
936 | for (index = 0; index < N_OV7670_FMTS; index++) | |
959f3bda | 937 | if (ov7670_formats[index].mbus_code == fmt->code) |
111f3356 | 938 | break; |
cd257a6f DD |
939 | if (index >= N_OV7670_FMTS) { |
940 | /* default to first format */ | |
941 | index = 0; | |
959f3bda | 942 | fmt->code = ov7670_formats[0].mbus_code; |
cd257a6f | 943 | } |
111f3356 JC |
944 | if (ret_fmt != NULL) |
945 | *ret_fmt = ov7670_formats + index; | |
946 | /* | |
947 | * Fields: the OV devices claim to be progressive. | |
948 | */ | |
959f3bda | 949 | fmt->field = V4L2_FIELD_NONE; |
f748cd3e JM |
950 | |
951 | /* | |
952 | * Don't consider values that don't match min_height and min_width | |
953 | * constraints. | |
954 | */ | |
955 | if (info->min_width || info->min_height) | |
956 | for (i = 0; i < n_win_sizes; i++) { | |
957 | wsize = info->devtype->win_sizes + i; | |
958 | ||
959 | if (wsize->width < info->min_width || | |
960 | wsize->height < info->min_height) { | |
961 | win_sizes_limit = i; | |
962 | break; | |
963 | } | |
964 | } | |
111f3356 JC |
965 | /* |
966 | * Round requested image size down to the nearest | |
967 | * we support, but not below the smallest. | |
968 | */ | |
d058e237 | 969 | for (wsize = info->devtype->win_sizes; |
f748cd3e | 970 | wsize < info->devtype->win_sizes + win_sizes_limit; wsize++) |
959f3bda | 971 | if (fmt->width >= wsize->width && fmt->height >= wsize->height) |
111f3356 | 972 | break; |
f748cd3e | 973 | if (wsize >= info->devtype->win_sizes + win_sizes_limit) |
111f3356 JC |
974 | wsize--; /* Take the smallest one */ |
975 | if (ret_wsize != NULL) | |
976 | *ret_wsize = wsize; | |
977 | /* | |
978 | * Note the size we'll actually handle. | |
979 | */ | |
959f3bda HV |
980 | fmt->width = wsize->width; |
981 | fmt->height = wsize->height; | |
982 | fmt->colorspace = ov7670_formats[index].colorspace; | |
111f3356 | 983 | return 0; |
111f3356 JC |
984 | } |
985 | ||
959f3bda HV |
986 | static int ov7670_try_mbus_fmt(struct v4l2_subdev *sd, |
987 | struct v4l2_mbus_framefmt *fmt) | |
14386c2b HV |
988 | { |
989 | return ov7670_try_fmt_internal(sd, fmt, NULL, NULL); | |
990 | } | |
991 | ||
111f3356 JC |
992 | /* |
993 | * Set a format. | |
994 | */ | |
959f3bda HV |
995 | static int ov7670_s_mbus_fmt(struct v4l2_subdev *sd, |
996 | struct v4l2_mbus_framefmt *fmt) | |
111f3356 | 997 | { |
111f3356 JC |
998 | struct ov7670_format_struct *ovfmt; |
999 | struct ov7670_win_size *wsize; | |
14386c2b | 1000 | struct ov7670_info *info = to_state(sd); |
d8d20155 | 1001 | unsigned char com7; |
959f3bda | 1002 | int ret; |
111f3356 | 1003 | |
14386c2b | 1004 | ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize); |
959f3bda | 1005 | |
111f3356 JC |
1006 | if (ret) |
1007 | return ret; | |
1008 | /* | |
1009 | * COM7 is a pain in the ass, it doesn't like to be read then | |
1010 | * quickly written afterward. But we have everything we need | |
1011 | * to set it absolutely here, as long as the format-specific | |
1012 | * register sets list it first. | |
1013 | */ | |
1014 | com7 = ovfmt->regs[0].value; | |
1015 | com7 |= wsize->com7_bit; | |
14386c2b | 1016 | ov7670_write(sd, REG_COM7, com7); |
111f3356 JC |
1017 | /* |
1018 | * Now write the rest of the array. Also store start/stops | |
1019 | */ | |
14386c2b HV |
1020 | ov7670_write_array(sd, ovfmt->regs + 1); |
1021 | ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, | |
111f3356 | 1022 | wsize->vstop); |
f9a76156 JC |
1023 | ret = 0; |
1024 | if (wsize->regs) | |
14386c2b | 1025 | ret = ov7670_write_array(sd, wsize->regs); |
f9a76156 | 1026 | info->fmt = ovfmt; |
edd75ede | 1027 | |
d8d20155 JC |
1028 | /* |
1029 | * If we're running RGB565, we must rewrite clkrc after setting | |
1030 | * the other parameters or the image looks poor. If we're *not* | |
1031 | * doing RGB565, we must not rewrite clkrc or the image looks | |
1032 | * *really* poor. | |
a8e68c37 JC |
1033 | * |
1034 | * (Update) Now that we retain clkrc state, we should be able | |
1035 | * to write it unconditionally, and that will make the frame | |
1036 | * rate persistent too. | |
d8d20155 | 1037 | */ |
a8e68c37 | 1038 | if (ret == 0) |
d8d20155 | 1039 | ret = ov7670_write(sd, REG_CLKRC, info->clkrc); |
959f3bda HV |
1040 | return 0; |
1041 | } | |
1042 | ||
c8f5b2f5 JC |
1043 | /* |
1044 | * Implement G/S_PARM. There is a "high quality" mode we could try | |
1045 | * to do someday; for now, we just do the frame rate tweak. | |
1046 | */ | |
14386c2b | 1047 | static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
1048 | { |
1049 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
d8d20155 | 1050 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 JC |
1051 | |
1052 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1053 | return -EINVAL; | |
d8d20155 | 1054 | |
c8f5b2f5 JC |
1055 | memset(cp, 0, sizeof(struct v4l2_captureparm)); |
1056 | cp->capability = V4L2_CAP_TIMEPERFRAME; | |
f6dd927f JM |
1057 | info->devtype->get_framerate(sd, &cp->timeperframe); |
1058 | ||
c8f5b2f5 JC |
1059 | return 0; |
1060 | } | |
1061 | ||
14386c2b | 1062 | static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
1063 | { |
1064 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
1065 | struct v4l2_fract *tpf = &cp->timeperframe; | |
d8d20155 | 1066 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 JC |
1067 | |
1068 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
1069 | return -EINVAL; | |
1070 | if (cp->extendedmode != 0) | |
1071 | return -EINVAL; | |
d8d20155 | 1072 | |
f6dd927f | 1073 | return info->devtype->set_framerate(sd, tpf); |
c8f5b2f5 JC |
1074 | } |
1075 | ||
1076 | ||
111f3356 | 1077 | /* |
e99dfcf7 JC |
1078 | * Frame intervals. Since frame rates are controlled with the clock |
1079 | * divider, we can only do 30/n for integer n values. So no continuous | |
1080 | * or stepwise options. Here we just pick a handful of logical values. | |
111f3356 JC |
1081 | */ |
1082 | ||
e99dfcf7 | 1083 | static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; |
f9a76156 | 1084 | |
e99dfcf7 JC |
1085 | static int ov7670_enum_frameintervals(struct v4l2_subdev *sd, |
1086 | struct v4l2_frmivalenum *interval) | |
1087 | { | |
1088 | if (interval->index >= ARRAY_SIZE(ov7670_frame_rates)) | |
1089 | return -EINVAL; | |
1090 | interval->type = V4L2_FRMIVAL_TYPE_DISCRETE; | |
1091 | interval->discrete.numerator = 1; | |
1092 | interval->discrete.denominator = ov7670_frame_rates[interval->index]; | |
1093 | return 0; | |
1094 | } | |
f9a76156 | 1095 | |
b0326b7f DD |
1096 | /* |
1097 | * Frame size enumeration | |
1098 | */ | |
1099 | static int ov7670_enum_framesizes(struct v4l2_subdev *sd, | |
1100 | struct v4l2_frmsizeenum *fsize) | |
1101 | { | |
75e2bdad DD |
1102 | struct ov7670_info *info = to_state(sd); |
1103 | int i; | |
1104 | int num_valid = -1; | |
b0326b7f | 1105 | __u32 index = fsize->index; |
d058e237 | 1106 | unsigned int n_win_sizes = info->devtype->n_win_sizes; |
b0326b7f | 1107 | |
75e2bdad DD |
1108 | /* |
1109 | * If a minimum width/height was requested, filter out the capture | |
1110 | * windows that fall outside that. | |
1111 | */ | |
d058e237 JM |
1112 | for (i = 0; i < n_win_sizes; i++) { |
1113 | struct ov7670_win_size *win = &info->devtype->win_sizes[index]; | |
75e2bdad DD |
1114 | if (info->min_width && win->width < info->min_width) |
1115 | continue; | |
1116 | if (info->min_height && win->height < info->min_height) | |
1117 | continue; | |
1118 | if (index == ++num_valid) { | |
1119 | fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; | |
1120 | fsize->discrete.width = win->width; | |
1121 | fsize->discrete.height = win->height; | |
1122 | return 0; | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | return -EINVAL; | |
b0326b7f DD |
1127 | } |
1128 | ||
e99dfcf7 JC |
1129 | /* |
1130 | * Code for dealing with controls. | |
1131 | */ | |
f9a76156 | 1132 | |
14386c2b | 1133 | static int ov7670_store_cmatrix(struct v4l2_subdev *sd, |
f9a76156 JC |
1134 | int matrix[CMATRIX_LEN]) |
1135 | { | |
1136 | int i, ret; | |
e3bf20de | 1137 | unsigned char signbits = 0; |
f9a76156 JC |
1138 | |
1139 | /* | |
1140 | * Weird crap seems to exist in the upper part of | |
1141 | * the sign bits register, so let's preserve it. | |
1142 | */ | |
14386c2b | 1143 | ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); |
f9a76156 JC |
1144 | signbits &= 0xc0; |
1145 | ||
1146 | for (i = 0; i < CMATRIX_LEN; i++) { | |
1147 | unsigned char raw; | |
1148 | ||
1149 | if (matrix[i] < 0) { | |
1150 | signbits |= (1 << i); | |
1151 | if (matrix[i] < -255) | |
1152 | raw = 0xff; | |
1153 | else | |
1154 | raw = (-1 * matrix[i]) & 0xff; | |
1155 | } | |
1156 | else { | |
1157 | if (matrix[i] > 255) | |
1158 | raw = 0xff; | |
1159 | else | |
1160 | raw = matrix[i] & 0xff; | |
1161 | } | |
14386c2b | 1162 | ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); |
f9a76156 | 1163 | } |
14386c2b | 1164 | ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); |
f9a76156 JC |
1165 | return ret; |
1166 | } | |
1167 | ||
1168 | ||
1169 | /* | |
1170 | * Hue also requires messing with the color matrix. It also requires | |
1171 | * trig functions, which tend not to be well supported in the kernel. | |
1172 | * So here is a simple table of sine values, 0-90 degrees, in steps | |
1173 | * of five degrees. Values are multiplied by 1000. | |
1174 | * | |
1175 | * The following naive approximate trig functions require an argument | |
1176 | * carefully limited to -180 <= theta <= 180. | |
1177 | */ | |
1178 | #define SIN_STEP 5 | |
1179 | static const int ov7670_sin_table[] = { | |
1180 | 0, 87, 173, 258, 342, 422, | |
1181 | 499, 573, 642, 707, 766, 819, | |
1182 | 866, 906, 939, 965, 984, 996, | |
1183 | 1000 | |
1184 | }; | |
1185 | ||
1186 | static int ov7670_sine(int theta) | |
1187 | { | |
1188 | int chs = 1; | |
1189 | int sine; | |
1190 | ||
1191 | if (theta < 0) { | |
1192 | theta = -theta; | |
1193 | chs = -1; | |
1194 | } | |
1195 | if (theta <= 90) | |
1196 | sine = ov7670_sin_table[theta/SIN_STEP]; | |
1197 | else { | |
1198 | theta -= 90; | |
1199 | sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; | |
1200 | } | |
1201 | return sine*chs; | |
1202 | } | |
1203 | ||
1204 | static int ov7670_cosine(int theta) | |
1205 | { | |
1206 | theta = 90 - theta; | |
1207 | if (theta > 180) | |
1208 | theta -= 360; | |
1209 | else if (theta < -180) | |
1210 | theta += 360; | |
1211 | return ov7670_sine(theta); | |
1212 | } | |
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | static void ov7670_calc_cmatrix(struct ov7670_info *info, | |
492959c7 | 1218 | int matrix[CMATRIX_LEN], int sat, int hue) |
f9a76156 JC |
1219 | { |
1220 | int i; | |
1221 | /* | |
1222 | * Apply the current saturation setting first. | |
1223 | */ | |
1224 | for (i = 0; i < CMATRIX_LEN; i++) | |
492959c7 | 1225 | matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7; |
f9a76156 JC |
1226 | /* |
1227 | * Then, if need be, rotate the hue value. | |
1228 | */ | |
492959c7 | 1229 | if (hue != 0) { |
f9a76156 JC |
1230 | int sinth, costh, tmpmatrix[CMATRIX_LEN]; |
1231 | ||
1232 | memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); | |
492959c7 JM |
1233 | sinth = ov7670_sine(hue); |
1234 | costh = ov7670_cosine(hue); | |
f9a76156 JC |
1235 | |
1236 | matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; | |
1237 | matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; | |
1238 | matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; | |
1239 | matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; | |
1240 | matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; | |
1241 | matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; | |
1242 | } | |
1243 | } | |
1244 | ||
1245 | ||
1246 | ||
492959c7 | 1247 | static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue) |
f9a76156 | 1248 | { |
14386c2b | 1249 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1250 | int matrix[CMATRIX_LEN]; |
1251 | int ret; | |
1252 | ||
492959c7 | 1253 | ov7670_calc_cmatrix(info, matrix, sat, hue); |
14386c2b | 1254 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1255 | return ret; |
1256 | } | |
1257 | ||
f9a76156 | 1258 | |
111f3356 JC |
1259 | /* |
1260 | * Some weird registers seem to store values in a sign/magnitude format! | |
1261 | */ | |
111f3356 JC |
1262 | |
1263 | static unsigned char ov7670_abs_to_sm(unsigned char v) | |
1264 | { | |
1265 | if (v > 127) | |
1266 | return v & 0x7f; | |
14386c2b | 1267 | return (128 - v) | 0x80; |
111f3356 JC |
1268 | } |
1269 | ||
ca07561a | 1270 | static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) |
111f3356 | 1271 | { |
e3bf20de | 1272 | unsigned char com8 = 0, v; |
111f3356 JC |
1273 | int ret; |
1274 | ||
14386c2b | 1275 | ov7670_read(sd, REG_COM8, &com8); |
111f3356 | 1276 | com8 &= ~COM8_AEC; |
14386c2b | 1277 | ov7670_write(sd, REG_COM8, com8); |
f9a76156 | 1278 | v = ov7670_abs_to_sm(value); |
14386c2b | 1279 | ret = ov7670_write(sd, REG_BRIGHT, v); |
111f3356 JC |
1280 | return ret; |
1281 | } | |
1282 | ||
ca07561a | 1283 | static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) |
111f3356 | 1284 | { |
14386c2b | 1285 | return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); |
111f3356 JC |
1286 | } |
1287 | ||
ca07561a | 1288 | static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1289 | { |
e3bf20de | 1290 | unsigned char v = 0; |
111f3356 JC |
1291 | int ret; |
1292 | ||
14386c2b | 1293 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1294 | if (value) |
1295 | v |= MVFP_MIRROR; | |
1296 | else | |
1297 | v &= ~MVFP_MIRROR; | |
1298 | msleep(10); /* FIXME */ | |
14386c2b | 1299 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1300 | return ret; |
1301 | } | |
1302 | ||
ca07561a | 1303 | static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1304 | { |
e3bf20de | 1305 | unsigned char v = 0; |
111f3356 JC |
1306 | int ret; |
1307 | ||
14386c2b | 1308 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1309 | if (value) |
1310 | v |= MVFP_FLIP; | |
1311 | else | |
1312 | v &= ~MVFP_FLIP; | |
1313 | msleep(10); /* FIXME */ | |
14386c2b | 1314 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1315 | return ret; |
1316 | } | |
1317 | ||
81898671 JC |
1318 | /* |
1319 | * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes | |
1320 | * the data sheet, the VREF parts should be the most significant, but | |
1321 | * experience shows otherwise. There seems to be little value in | |
1322 | * messing with the VREF bits, so we leave them alone. | |
1323 | */ | |
1324 | static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) | |
1325 | { | |
1326 | int ret; | |
1327 | unsigned char gain; | |
1328 | ||
1329 | ret = ov7670_read(sd, REG_GAIN, &gain); | |
1330 | *value = gain; | |
1331 | return ret; | |
1332 | } | |
1333 | ||
1334 | static int ov7670_s_gain(struct v4l2_subdev *sd, int value) | |
1335 | { | |
1336 | int ret; | |
1337 | unsigned char com8; | |
1338 | ||
1339 | ret = ov7670_write(sd, REG_GAIN, value & 0xff); | |
1340 | /* Have to turn off AGC as well */ | |
1341 | if (ret == 0) { | |
1342 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1343 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); | |
1344 | } | |
1345 | return ret; | |
1346 | } | |
1347 | ||
1348 | /* | |
1349 | * Tweak autogain. | |
1350 | */ | |
81898671 JC |
1351 | static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) |
1352 | { | |
1353 | int ret; | |
1354 | unsigned char com8; | |
1355 | ||
1356 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1357 | if (ret == 0) { | |
1358 | if (value) | |
1359 | com8 |= COM8_AGC; | |
1360 | else | |
1361 | com8 &= ~COM8_AGC; | |
1362 | ret = ov7670_write(sd, REG_COM8, com8); | |
1363 | } | |
1364 | return ret; | |
1365 | } | |
1366 | ||
364e9337 JC |
1367 | static int ov7670_s_exp(struct v4l2_subdev *sd, int value) |
1368 | { | |
1369 | int ret; | |
1370 | unsigned char com1, com8, aech, aechh; | |
1371 | ||
1372 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
1373 | ov7670_read(sd, REG_COM8, &com8); | |
1374 | ov7670_read(sd, REG_AECHH, &aechh); | |
1375 | if (ret) | |
1376 | return ret; | |
1377 | ||
1378 | com1 = (com1 & 0xfc) | (value & 0x03); | |
1379 | aech = (value >> 2) & 0xff; | |
1380 | aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); | |
1381 | ret = ov7670_write(sd, REG_COM1, com1) + | |
1382 | ov7670_write(sd, REG_AECH, aech) + | |
1383 | ov7670_write(sd, REG_AECHH, aechh); | |
1384 | /* Have to turn off AEC as well */ | |
1385 | if (ret == 0) | |
1386 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); | |
1387 | return ret; | |
1388 | } | |
1389 | ||
1390 | /* | |
1391 | * Tweak autoexposure. | |
1392 | */ | |
364e9337 JC |
1393 | static int ov7670_s_autoexp(struct v4l2_subdev *sd, |
1394 | enum v4l2_exposure_auto_type value) | |
1395 | { | |
1396 | int ret; | |
1397 | unsigned char com8; | |
1398 | ||
1399 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1400 | if (ret == 0) { | |
1401 | if (value == V4L2_EXPOSURE_AUTO) | |
1402 | com8 |= COM8_AEC; | |
1403 | else | |
1404 | com8 &= ~COM8_AEC; | |
1405 | ret = ov7670_write(sd, REG_COM8, com8); | |
1406 | } | |
1407 | return ret; | |
1408 | } | |
1409 | ||
81898671 | 1410 | |
492959c7 | 1411 | static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
111f3356 | 1412 | { |
492959c7 JM |
1413 | struct v4l2_subdev *sd = to_sd(ctrl); |
1414 | struct ov7670_info *info = to_state(sd); | |
111f3356 | 1415 | |
ca07561a | 1416 | switch (ctrl->id) { |
81898671 | 1417 | case V4L2_CID_AUTOGAIN: |
492959c7 | 1418 | return ov7670_g_gain(sd, &info->gain->val); |
ca07561a HV |
1419 | } |
1420 | return -EINVAL; | |
111f3356 JC |
1421 | } |
1422 | ||
492959c7 | 1423 | static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl) |
111f3356 | 1424 | { |
492959c7 JM |
1425 | struct v4l2_subdev *sd = to_sd(ctrl); |
1426 | struct ov7670_info *info = to_state(sd); | |
1427 | ||
ca07561a HV |
1428 | switch (ctrl->id) { |
1429 | case V4L2_CID_BRIGHTNESS: | |
492959c7 | 1430 | return ov7670_s_brightness(sd, ctrl->val); |
ca07561a | 1431 | case V4L2_CID_CONTRAST: |
492959c7 | 1432 | return ov7670_s_contrast(sd, ctrl->val); |
ca07561a | 1433 | case V4L2_CID_SATURATION: |
492959c7 JM |
1434 | return ov7670_s_sat_hue(sd, |
1435 | info->saturation->val, info->hue->val); | |
ca07561a | 1436 | case V4L2_CID_VFLIP: |
492959c7 | 1437 | return ov7670_s_vflip(sd, ctrl->val); |
ca07561a | 1438 | case V4L2_CID_HFLIP: |
492959c7 | 1439 | return ov7670_s_hflip(sd, ctrl->val); |
81898671 | 1440 | case V4L2_CID_AUTOGAIN: |
492959c7 JM |
1441 | /* Only set manual gain if auto gain is not explicitly |
1442 | turned on. */ | |
1443 | if (!ctrl->val) { | |
1444 | /* ov7670_s_gain turns off auto gain */ | |
1445 | return ov7670_s_gain(sd, info->gain->val); | |
1446 | } | |
1447 | return ov7670_s_autogain(sd, ctrl->val); | |
364e9337 | 1448 | case V4L2_CID_EXPOSURE_AUTO: |
492959c7 JM |
1449 | /* Only set manual exposure if auto exposure is not explicitly |
1450 | turned on. */ | |
1451 | if (ctrl->val == V4L2_EXPOSURE_MANUAL) { | |
1452 | /* ov7670_s_exp turns off auto exposure */ | |
1453 | return ov7670_s_exp(sd, info->exposure->val); | |
1454 | } | |
1455 | return ov7670_s_autoexp(sd, ctrl->val); | |
ca07561a HV |
1456 | } |
1457 | return -EINVAL; | |
111f3356 JC |
1458 | } |
1459 | ||
492959c7 JM |
1460 | static const struct v4l2_ctrl_ops ov7670_ctrl_ops = { |
1461 | .s_ctrl = ov7670_s_ctrl, | |
1462 | .g_volatile_ctrl = ov7670_g_volatile_ctrl, | |
1463 | }; | |
1464 | ||
14386c2b HV |
1465 | static int ov7670_g_chip_ident(struct v4l2_subdev *sd, |
1466 | struct v4l2_dbg_chip_ident *chip) | |
1467 | { | |
1468 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1469 | ||
1470 | return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0); | |
1471 | } | |
1472 | ||
b794aabf HV |
1473 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1474 | static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1475 | { | |
1476 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1477 | unsigned char val = 0; | |
1478 | int ret; | |
1479 | ||
1480 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1481 | return -EINVAL; | |
1482 | if (!capable(CAP_SYS_ADMIN)) | |
1483 | return -EPERM; | |
1484 | ret = ov7670_read(sd, reg->reg & 0xff, &val); | |
1485 | reg->val = val; | |
1486 | reg->size = 1; | |
1487 | return ret; | |
1488 | } | |
1489 | ||
977ba3b1 | 1490 | static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) |
b794aabf HV |
1491 | { |
1492 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1493 | ||
1494 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1495 | return -EINVAL; | |
1496 | if (!capable(CAP_SYS_ADMIN)) | |
1497 | return -EPERM; | |
1498 | ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); | |
1499 | return 0; | |
1500 | } | |
1501 | #endif | |
1502 | ||
14386c2b | 1503 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1504 | |
14386c2b HV |
1505 | static const struct v4l2_subdev_core_ops ov7670_core_ops = { |
1506 | .g_chip_ident = ov7670_g_chip_ident, | |
14386c2b HV |
1507 | .reset = ov7670_reset, |
1508 | .init = ov7670_init, | |
b794aabf HV |
1509 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1510 | .g_register = ov7670_g_register, | |
1511 | .s_register = ov7670_s_register, | |
1512 | #endif | |
14386c2b | 1513 | }; |
111f3356 | 1514 | |
14386c2b | 1515 | static const struct v4l2_subdev_video_ops ov7670_video_ops = { |
959f3bda HV |
1516 | .enum_mbus_fmt = ov7670_enum_mbus_fmt, |
1517 | .try_mbus_fmt = ov7670_try_mbus_fmt, | |
1518 | .s_mbus_fmt = ov7670_s_mbus_fmt, | |
14386c2b HV |
1519 | .s_parm = ov7670_s_parm, |
1520 | .g_parm = ov7670_g_parm, | |
e99dfcf7 | 1521 | .enum_frameintervals = ov7670_enum_frameintervals, |
b0326b7f | 1522 | .enum_framesizes = ov7670_enum_framesizes, |
14386c2b | 1523 | }; |
111f3356 | 1524 | |
14386c2b HV |
1525 | static const struct v4l2_subdev_ops ov7670_ops = { |
1526 | .core = &ov7670_core_ops, | |
1527 | .video = &ov7670_video_ops, | |
1528 | }; | |
111f3356 | 1529 | |
14386c2b | 1530 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1531 | |
d058e237 JM |
1532 | static const struct ov7670_devtype ov7670_devdata[] = { |
1533 | [MODEL_OV7670] = { | |
1534 | .win_sizes = ov7670_win_sizes, | |
1535 | .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes), | |
f6dd927f JM |
1536 | .set_framerate = ov7670_set_framerate_legacy, |
1537 | .get_framerate = ov7670_get_framerate_legacy, | |
d058e237 JM |
1538 | }, |
1539 | [MODEL_OV7675] = { | |
1540 | .win_sizes = ov7675_win_sizes, | |
1541 | .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes), | |
f6dd927f JM |
1542 | .set_framerate = ov7675_set_framerate, |
1543 | .get_framerate = ov7675_get_framerate, | |
d058e237 JM |
1544 | }, |
1545 | }; | |
1546 | ||
14386c2b HV |
1547 | static int ov7670_probe(struct i2c_client *client, |
1548 | const struct i2c_device_id *id) | |
111f3356 | 1549 | { |
f6dd927f | 1550 | struct v4l2_fract tpf; |
14386c2b | 1551 | struct v4l2_subdev *sd; |
f9a76156 | 1552 | struct ov7670_info *info; |
3c7c9370 | 1553 | int ret; |
111f3356 | 1554 | |
14386c2b HV |
1555 | info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL); |
1556 | if (info == NULL) | |
111f3356 | 1557 | return -ENOMEM; |
14386c2b HV |
1558 | sd = &info->sd; |
1559 | v4l2_i2c_subdev_init(sd, client, &ov7670_ops); | |
1560 | ||
3c7c9370 HV |
1561 | info->clock_speed = 30; /* default: a guess */ |
1562 | if (client->dev.platform_data) { | |
1563 | struct ov7670_config *config = client->dev.platform_data; | |
1564 | ||
1565 | /* | |
1566 | * Must apply configuration before initializing device, because it | |
1567 | * selects I/O method. | |
1568 | */ | |
1569 | info->min_width = config->min_width; | |
1570 | info->min_height = config->min_height; | |
1571 | info->use_smbus = config->use_smbus; | |
1572 | ||
1573 | if (config->clock_speed) | |
1574 | info->clock_speed = config->clock_speed; | |
04ee6d92 JM |
1575 | |
1576 | /* | |
1577 | * It should be allowed for ov7670 too when it is migrated to | |
1578 | * the new frame rate formula. | |
1579 | */ | |
1580 | if (config->pll_bypass && id->driver_data != MODEL_OV7670) | |
1581 | info->pll_bypass = true; | |
ee95258e JM |
1582 | |
1583 | if (config->pclk_hb_disable) | |
1584 | info->pclk_hb_disable = true; | |
3c7c9370 HV |
1585 | } |
1586 | ||
1587 | /* Make sure it's an ov7670 */ | |
1588 | ret = ov7670_detect(sd); | |
1589 | if (ret) { | |
1590 | v4l_dbg(1, debug, client, | |
1591 | "chip found @ 0x%x (%s) is not an ov7670 chip.\n", | |
1592 | client->addr << 1, client->adapter->name); | |
1593 | kfree(info); | |
1594 | return ret; | |
1595 | } | |
1596 | v4l_info(client, "chip found @ 0x%02x (%s)\n", | |
1597 | client->addr << 1, client->adapter->name); | |
1598 | ||
d058e237 | 1599 | info->devtype = &ov7670_devdata[id->driver_data]; |
3c7c9370 | 1600 | info->fmt = &ov7670_formats[0]; |
f6dd927f JM |
1601 | info->clkrc = 0; |
1602 | ||
1603 | /* Set default frame rate to 30 fps */ | |
1604 | tpf.numerator = 1; | |
1605 | tpf.denominator = 30; | |
1606 | info->devtype->set_framerate(sd, &tpf); | |
1607 | ||
ee95258e JM |
1608 | if (info->pclk_hb_disable) |
1609 | ov7670_write(sd, REG_COM10, COM10_PCLK_HB); | |
1610 | ||
492959c7 JM |
1611 | v4l2_ctrl_handler_init(&info->hdl, 10); |
1612 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1613 | V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); | |
1614 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1615 | V4L2_CID_CONTRAST, 0, 127, 1, 64); | |
1616 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1617 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
1618 | v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1619 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
1620 | info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1621 | V4L2_CID_SATURATION, 0, 256, 1, 128); | |
1622 | info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1623 | V4L2_CID_HUE, -180, 180, 5, 0); | |
1624 | info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1625 | V4L2_CID_GAIN, 0, 255, 1, 128); | |
1626 | info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1627 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
1628 | info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops, | |
1629 | V4L2_CID_EXPOSURE, 0, 65535, 1, 500); | |
1630 | info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops, | |
1631 | V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0, | |
1632 | V4L2_EXPOSURE_AUTO); | |
1633 | sd->ctrl_handler = &info->hdl; | |
1634 | if (info->hdl.error) { | |
1635 | int err = info->hdl.error; | |
1636 | ||
1637 | v4l2_ctrl_handler_free(&info->hdl); | |
1638 | kfree(info); | |
1639 | return err; | |
1640 | } | |
1641 | /* | |
1642 | * We have checked empirically that hw allows to read back the gain | |
1643 | * value chosen by auto gain but that's not the case for auto exposure. | |
1644 | */ | |
1645 | v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true); | |
1646 | v4l2_ctrl_auto_cluster(2, &info->auto_exposure, | |
1647 | V4L2_EXPOSURE_MANUAL, false); | |
1648 | v4l2_ctrl_cluster(2, &info->saturation); | |
1649 | v4l2_ctrl_handler_setup(&info->hdl); | |
1650 | ||
111f3356 | 1651 | return 0; |
111f3356 JC |
1652 | } |
1653 | ||
1654 | ||
14386c2b | 1655 | static int ov7670_remove(struct i2c_client *client) |
111f3356 | 1656 | { |
14386c2b | 1657 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
492959c7 | 1658 | struct ov7670_info *info = to_state(sd); |
111f3356 | 1659 | |
14386c2b | 1660 | v4l2_device_unregister_subdev(sd); |
492959c7 JM |
1661 | v4l2_ctrl_handler_free(&info->hdl); |
1662 | kfree(info); | |
14386c2b | 1663 | return 0; |
111f3356 JC |
1664 | } |
1665 | ||
14386c2b | 1666 | static const struct i2c_device_id ov7670_id[] = { |
d058e237 JM |
1667 | { "ov7670", MODEL_OV7670 }, |
1668 | { "ov7675", MODEL_OV7675 }, | |
14386c2b HV |
1669 | { } |
1670 | }; | |
1671 | MODULE_DEVICE_TABLE(i2c, ov7670_id); | |
1672 | ||
ef2ac770 HV |
1673 | static struct i2c_driver ov7670_driver = { |
1674 | .driver = { | |
1675 | .owner = THIS_MODULE, | |
1676 | .name = "ov7670", | |
1677 | }, | |
1678 | .probe = ov7670_probe, | |
1679 | .remove = ov7670_remove, | |
1680 | .id_table = ov7670_id, | |
111f3356 | 1681 | }; |
ef2ac770 | 1682 | |
c6e8d86f | 1683 | module_i2c_driver(ov7670_driver); |