Commit | Line | Data |
---|---|---|
111f3356 JC |
1 | /* |
2 | * A V4L2 driver for OmniVision OV7670 cameras. | |
3 | * | |
4 | * Copyright 2006 One Laptop Per Child Association, Inc. Written | |
5 | * by Jonathan Corbet with substantial inspiration from Mark | |
6 | * McClelland's ovcamchip code. | |
7 | * | |
77d5140f JC |
8 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> |
9 | * | |
111f3356 JC |
10 | * This file may be distributed under the terms of the GNU General |
11 | * Public License, version 2. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/module.h> | |
5a0e3ad6 | 15 | #include <linux/slab.h> |
14386c2b | 16 | #include <linux/i2c.h> |
111f3356 | 17 | #include <linux/delay.h> |
7e0a16f6 | 18 | #include <linux/videodev2.h> |
14386c2b | 19 | #include <media/v4l2-device.h> |
3434eb7e | 20 | #include <media/v4l2-chip-ident.h> |
959f3bda | 21 | #include <media/v4l2-mediabus.h> |
f8fc7298 | 22 | #include <media/ov7670.h> |
111f3356 | 23 | |
5e614475 | 24 | MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>"); |
111f3356 JC |
25 | MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors"); |
26 | MODULE_LICENSE("GPL"); | |
27 | ||
90ab5ee9 | 28 | static bool debug; |
14386c2b HV |
29 | module_param(debug, bool, 0644); |
30 | MODULE_PARM_DESC(debug, "Debug level (0-1)"); | |
31 | ||
111f3356 JC |
32 | /* |
33 | * Basic window sizes. These probably belong somewhere more globally | |
34 | * useful. | |
35 | */ | |
36 | #define VGA_WIDTH 640 | |
37 | #define VGA_HEIGHT 480 | |
38 | #define QVGA_WIDTH 320 | |
39 | #define QVGA_HEIGHT 240 | |
40 | #define CIF_WIDTH 352 | |
41 | #define CIF_HEIGHT 288 | |
42 | #define QCIF_WIDTH 176 | |
43 | #define QCIF_HEIGHT 144 | |
44 | ||
45 | /* | |
46 | * The 7670 sits on i2c with ID 0x42 | |
47 | */ | |
48 | #define OV7670_I2C_ADDR 0x42 | |
49 | ||
50 | /* Registers */ | |
51 | #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */ | |
52 | #define REG_BLUE 0x01 /* blue gain */ | |
53 | #define REG_RED 0x02 /* red gain */ | |
54 | #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */ | |
55 | #define REG_COM1 0x04 /* Control 1 */ | |
56 | #define COM1_CCIR656 0x40 /* CCIR656 enable */ | |
57 | #define REG_BAVE 0x05 /* U/B Average level */ | |
58 | #define REG_GbAVE 0x06 /* Y/Gb Average level */ | |
59 | #define REG_AECHH 0x07 /* AEC MS 5 bits */ | |
60 | #define REG_RAVE 0x08 /* V/R Average level */ | |
61 | #define REG_COM2 0x09 /* Control 2 */ | |
62 | #define COM2_SSLEEP 0x10 /* Soft sleep mode */ | |
63 | #define REG_PID 0x0a /* Product ID MSB */ | |
64 | #define REG_VER 0x0b /* Product ID LSB */ | |
65 | #define REG_COM3 0x0c /* Control 3 */ | |
66 | #define COM3_SWAP 0x40 /* Byte swap */ | |
67 | #define COM3_SCALEEN 0x08 /* Enable scaling */ | |
68 | #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */ | |
69 | #define REG_COM4 0x0d /* Control 4 */ | |
70 | #define REG_COM5 0x0e /* All "reserved" */ | |
71 | #define REG_COM6 0x0f /* Control 6 */ | |
72 | #define REG_AECH 0x10 /* More bits of AEC value */ | |
73 | #define REG_CLKRC 0x11 /* Clocl control */ | |
74 | #define CLK_EXT 0x40 /* Use external clock directly */ | |
75 | #define CLK_SCALE 0x3f /* Mask for internal clock scale */ | |
76 | #define REG_COM7 0x12 /* Control 7 */ | |
77 | #define COM7_RESET 0x80 /* Register reset */ | |
78 | #define COM7_FMT_MASK 0x38 | |
79 | #define COM7_FMT_VGA 0x00 | |
80 | #define COM7_FMT_CIF 0x20 /* CIF format */ | |
81 | #define COM7_FMT_QVGA 0x10 /* QVGA format */ | |
82 | #define COM7_FMT_QCIF 0x08 /* QCIF format */ | |
83 | #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */ | |
84 | #define COM7_YUV 0x00 /* YUV */ | |
85 | #define COM7_BAYER 0x01 /* Bayer format */ | |
86 | #define COM7_PBAYER 0x05 /* "Processed bayer" */ | |
87 | #define REG_COM8 0x13 /* Control 8 */ | |
88 | #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */ | |
89 | #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */ | |
90 | #define COM8_BFILT 0x20 /* Band filter enable */ | |
91 | #define COM8_AGC 0x04 /* Auto gain enable */ | |
92 | #define COM8_AWB 0x02 /* White balance enable */ | |
93 | #define COM8_AEC 0x01 /* Auto exposure enable */ | |
94 | #define REG_COM9 0x14 /* Control 9 - gain ceiling */ | |
95 | #define REG_COM10 0x15 /* Control 10 */ | |
96 | #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */ | |
97 | #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */ | |
98 | #define COM10_HREF_REV 0x08 /* Reverse HREF */ | |
99 | #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */ | |
100 | #define COM10_VS_NEG 0x02 /* VSYNC negative */ | |
101 | #define COM10_HS_NEG 0x01 /* HSYNC negative */ | |
102 | #define REG_HSTART 0x17 /* Horiz start high bits */ | |
103 | #define REG_HSTOP 0x18 /* Horiz stop high bits */ | |
104 | #define REG_VSTART 0x19 /* Vert start high bits */ | |
105 | #define REG_VSTOP 0x1a /* Vert stop high bits */ | |
106 | #define REG_PSHFT 0x1b /* Pixel delay after HREF */ | |
107 | #define REG_MIDH 0x1c /* Manuf. ID high */ | |
108 | #define REG_MIDL 0x1d /* Manuf. ID low */ | |
109 | #define REG_MVFP 0x1e /* Mirror / vflip */ | |
110 | #define MVFP_MIRROR 0x20 /* Mirror image */ | |
111 | #define MVFP_FLIP 0x10 /* Vertical flip */ | |
112 | ||
113 | #define REG_AEW 0x24 /* AGC upper limit */ | |
114 | #define REG_AEB 0x25 /* AGC lower limit */ | |
115 | #define REG_VPT 0x26 /* AGC/AEC fast mode op region */ | |
116 | #define REG_HSYST 0x30 /* HSYNC rising edge delay */ | |
117 | #define REG_HSYEN 0x31 /* HSYNC falling edge delay */ | |
118 | #define REG_HREF 0x32 /* HREF pieces */ | |
119 | #define REG_TSLB 0x3a /* lots of stuff */ | |
120 | #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */ | |
121 | #define REG_COM11 0x3b /* Control 11 */ | |
122 | #define COM11_NIGHT 0x80 /* NIght mode enable */ | |
123 | #define COM11_NMFR 0x60 /* Two bit NM frame rate */ | |
124 | #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */ | |
125 | #define COM11_50HZ 0x08 /* Manual 50Hz select */ | |
126 | #define COM11_EXP 0x02 | |
127 | #define REG_COM12 0x3c /* Control 12 */ | |
128 | #define COM12_HREF 0x80 /* HREF always */ | |
129 | #define REG_COM13 0x3d /* Control 13 */ | |
130 | #define COM13_GAMMA 0x80 /* Gamma enable */ | |
131 | #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */ | |
132 | #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */ | |
133 | #define REG_COM14 0x3e /* Control 14 */ | |
134 | #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */ | |
135 | #define REG_EDGE 0x3f /* Edge enhancement factor */ | |
136 | #define REG_COM15 0x40 /* Control 15 */ | |
137 | #define COM15_R10F0 0x00 /* Data range 10 to F0 */ | |
138 | #define COM15_R01FE 0x80 /* 01 to FE */ | |
139 | #define COM15_R00FF 0xc0 /* 00 to FF */ | |
140 | #define COM15_RGB565 0x10 /* RGB565 output */ | |
141 | #define COM15_RGB555 0x30 /* RGB555 output */ | |
142 | #define REG_COM16 0x41 /* Control 16 */ | |
143 | #define COM16_AWBGAIN 0x08 /* AWB gain enable */ | |
144 | #define REG_COM17 0x42 /* Control 17 */ | |
145 | #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */ | |
146 | #define COM17_CBAR 0x08 /* DSP Color bar */ | |
147 | ||
f9a76156 JC |
148 | /* |
149 | * This matrix defines how the colors are generated, must be | |
150 | * tweaked to adjust hue and saturation. | |
151 | * | |
152 | * Order: v-red, v-green, v-blue, u-red, u-green, u-blue | |
153 | * | |
154 | * They are nine-bit signed quantities, with the sign bit | |
155 | * stored in 0x58. Sign for v-red is bit 0, and up from there. | |
156 | */ | |
157 | #define REG_CMATRIX_BASE 0x4f | |
158 | #define CMATRIX_LEN 6 | |
159 | #define REG_CMATRIX_SIGN 0x58 | |
160 | ||
161 | ||
111f3356 JC |
162 | #define REG_BRIGHT 0x55 /* Brightness */ |
163 | #define REG_CONTRAS 0x56 /* Contrast control */ | |
164 | ||
165 | #define REG_GFIX 0x69 /* Fix gain control */ | |
166 | ||
585553ec JC |
167 | #define REG_REG76 0x76 /* OV's name */ |
168 | #define R76_BLKPCOR 0x80 /* Black pixel correction enable */ | |
169 | #define R76_WHTPCOR 0x40 /* White pixel correction enable */ | |
170 | ||
111f3356 JC |
171 | #define REG_RGB444 0x8c /* RGB 444 control */ |
172 | #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */ | |
173 | #define R444_RGBX 0x01 /* Empty nibble at end */ | |
174 | ||
175 | #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */ | |
176 | #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */ | |
177 | ||
178 | #define REG_BD50MAX 0xa5 /* 50hz banding step limit */ | |
179 | #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */ | |
180 | #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */ | |
181 | #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */ | |
182 | #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */ | |
183 | #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ | |
184 | #define REG_BD60MAX 0xab /* 60hz banding step limit */ | |
185 | ||
186 | ||
f9a76156 JC |
187 | /* |
188 | * Information we maintain about a known sensor. | |
189 | */ | |
190 | struct ov7670_format_struct; /* coming later */ | |
191 | struct ov7670_info { | |
14386c2b | 192 | struct v4l2_subdev sd; |
f9a76156 JC |
193 | struct ov7670_format_struct *fmt; /* Current format */ |
194 | unsigned char sat; /* Saturation value */ | |
195 | int hue; /* Hue value */ | |
75e2bdad DD |
196 | int min_width; /* Filter out smaller sizes */ |
197 | int min_height; /* Filter out smaller sizes */ | |
198 | int clock_speed; /* External clock speed (MHz) */ | |
d8d20155 | 199 | u8 clkrc; /* Clock divider value */ |
75e2bdad | 200 | bool use_smbus; /* Use smbus I/O instead of I2C */ |
f9a76156 JC |
201 | }; |
202 | ||
14386c2b HV |
203 | static inline struct ov7670_info *to_state(struct v4l2_subdev *sd) |
204 | { | |
205 | return container_of(sd, struct ov7670_info, sd); | |
206 | } | |
f9a76156 JC |
207 | |
208 | ||
209 | ||
111f3356 JC |
210 | /* |
211 | * The default register settings, as obtained from OmniVision. There | |
212 | * is really no making sense of most of these - lots of "reserved" values | |
213 | * and such. | |
214 | * | |
215 | * These settings give VGA YUYV. | |
216 | */ | |
217 | ||
218 | struct regval_list { | |
219 | unsigned char reg_num; | |
220 | unsigned char value; | |
221 | }; | |
222 | ||
223 | static struct regval_list ov7670_default_regs[] = { | |
224 | { REG_COM7, COM7_RESET }, | |
225 | /* | |
226 | * Clock scale: 3 = 15fps | |
227 | * 2 = 20fps | |
228 | * 1 = 30fps | |
229 | */ | |
f9a76156 | 230 | { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */ |
111f3356 JC |
231 | { REG_TSLB, 0x04 }, /* OV */ |
232 | { REG_COM7, 0 }, /* VGA */ | |
233 | /* | |
234 | * Set the hardware window. These values from OV don't entirely | |
235 | * make sense - hstop is less than hstart. But they work... | |
236 | */ | |
237 | { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 }, | |
238 | { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 }, | |
239 | { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a }, | |
240 | ||
241 | { REG_COM3, 0 }, { REG_COM14, 0 }, | |
242 | /* Mystery scaling numbers */ | |
243 | { 0x70, 0x3a }, { 0x71, 0x35 }, | |
244 | { 0x72, 0x11 }, { 0x73, 0xf0 }, | |
245 | { 0xa2, 0x02 }, { REG_COM10, 0x0 }, | |
246 | ||
247 | /* Gamma curve values */ | |
248 | { 0x7a, 0x20 }, { 0x7b, 0x10 }, | |
249 | { 0x7c, 0x1e }, { 0x7d, 0x35 }, | |
250 | { 0x7e, 0x5a }, { 0x7f, 0x69 }, | |
251 | { 0x80, 0x76 }, { 0x81, 0x80 }, | |
252 | { 0x82, 0x88 }, { 0x83, 0x8f }, | |
253 | { 0x84, 0x96 }, { 0x85, 0xa3 }, | |
254 | { 0x86, 0xaf }, { 0x87, 0xc4 }, | |
255 | { 0x88, 0xd7 }, { 0x89, 0xe8 }, | |
256 | ||
257 | /* AGC and AEC parameters. Note we start by disabling those features, | |
258 | then turn them only after tweaking the values. */ | |
259 | { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT }, | |
260 | { REG_GAIN, 0 }, { REG_AECH, 0 }, | |
261 | { REG_COM4, 0x40 }, /* magic reserved bit */ | |
262 | { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ | |
263 | { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 }, | |
264 | { REG_AEW, 0x95 }, { REG_AEB, 0x33 }, | |
265 | { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 }, | |
266 | { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */ | |
267 | { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 }, | |
268 | { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 }, | |
269 | { REG_HAECC7, 0x94 }, | |
270 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC }, | |
271 | ||
272 | /* Almost all of these are magic "reserved" values. */ | |
273 | { REG_COM5, 0x61 }, { REG_COM6, 0x4b }, | |
7f7b12f0 | 274 | { 0x16, 0x02 }, { REG_MVFP, 0x07 }, |
111f3356 JC |
275 | { 0x21, 0x02 }, { 0x22, 0x91 }, |
276 | { 0x29, 0x07 }, { 0x33, 0x0b }, | |
277 | { 0x35, 0x0b }, { 0x37, 0x1d }, | |
278 | { 0x38, 0x71 }, { 0x39, 0x2a }, | |
279 | { REG_COM12, 0x78 }, { 0x4d, 0x40 }, | |
280 | { 0x4e, 0x20 }, { REG_GFIX, 0 }, | |
281 | { 0x6b, 0x4a }, { 0x74, 0x10 }, | |
282 | { 0x8d, 0x4f }, { 0x8e, 0 }, | |
283 | { 0x8f, 0 }, { 0x90, 0 }, | |
284 | { 0x91, 0 }, { 0x96, 0 }, | |
285 | { 0x9a, 0 }, { 0xb0, 0x84 }, | |
286 | { 0xb1, 0x0c }, { 0xb2, 0x0e }, | |
287 | { 0xb3, 0x82 }, { 0xb8, 0x0a }, | |
288 | ||
289 | /* More reserved magic, some of which tweaks white balance */ | |
290 | { 0x43, 0x0a }, { 0x44, 0xf0 }, | |
291 | { 0x45, 0x34 }, { 0x46, 0x58 }, | |
292 | { 0x47, 0x28 }, { 0x48, 0x3a }, | |
293 | { 0x59, 0x88 }, { 0x5a, 0x88 }, | |
294 | { 0x5b, 0x44 }, { 0x5c, 0x67 }, | |
295 | { 0x5d, 0x49 }, { 0x5e, 0x0e }, | |
296 | { 0x6c, 0x0a }, { 0x6d, 0x55 }, | |
297 | { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */ | |
298 | { 0x6a, 0x40 }, { REG_BLUE, 0x40 }, | |
299 | { REG_RED, 0x60 }, | |
300 | { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB }, | |
301 | ||
302 | /* Matrix coefficients */ | |
303 | { 0x4f, 0x80 }, { 0x50, 0x80 }, | |
304 | { 0x51, 0 }, { 0x52, 0x22 }, | |
305 | { 0x53, 0x5e }, { 0x54, 0x80 }, | |
306 | { 0x58, 0x9e }, | |
307 | ||
308 | { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 }, | |
309 | { 0x75, 0x05 }, { 0x76, 0xe1 }, | |
310 | { 0x4c, 0 }, { 0x77, 0x01 }, | |
311 | { REG_COM13, 0xc3 }, { 0x4b, 0x09 }, | |
312 | { 0xc9, 0x60 }, { REG_COM16, 0x38 }, | |
313 | { 0x56, 0x40 }, | |
314 | ||
c8f5b2f5 | 315 | { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO }, |
111f3356 JC |
316 | { 0xa4, 0x88 }, { 0x96, 0 }, |
317 | { 0x97, 0x30 }, { 0x98, 0x20 }, | |
318 | { 0x99, 0x30 }, { 0x9a, 0x84 }, | |
319 | { 0x9b, 0x29 }, { 0x9c, 0x03 }, | |
320 | { 0x9d, 0x4c }, { 0x9e, 0x3f }, | |
321 | { 0x78, 0x04 }, | |
322 | ||
323 | /* Extra-weird stuff. Some sort of multiplexor register */ | |
324 | { 0x79, 0x01 }, { 0xc8, 0xf0 }, | |
325 | { 0x79, 0x0f }, { 0xc8, 0x00 }, | |
326 | { 0x79, 0x10 }, { 0xc8, 0x7e }, | |
327 | { 0x79, 0x0a }, { 0xc8, 0x80 }, | |
328 | { 0x79, 0x0b }, { 0xc8, 0x01 }, | |
329 | { 0x79, 0x0c }, { 0xc8, 0x0f }, | |
330 | { 0x79, 0x0d }, { 0xc8, 0x20 }, | |
331 | { 0x79, 0x09 }, { 0xc8, 0x80 }, | |
332 | { 0x79, 0x02 }, { 0xc8, 0xc0 }, | |
333 | { 0x79, 0x03 }, { 0xc8, 0x40 }, | |
334 | { 0x79, 0x05 }, { 0xc8, 0x30 }, | |
335 | { 0x79, 0x26 }, | |
336 | ||
111f3356 JC |
337 | { 0xff, 0xff }, /* END MARKER */ |
338 | }; | |
339 | ||
340 | ||
341 | /* | |
342 | * Here we'll try to encapsulate the changes for just the output | |
343 | * video format. | |
344 | * | |
345 | * RGB656 and YUV422 come from OV; RGB444 is homebrewed. | |
346 | * | |
347 | * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why. | |
348 | */ | |
349 | ||
350 | ||
351 | static struct regval_list ov7670_fmt_yuv422[] = { | |
352 | { REG_COM7, 0x0 }, /* Selects YUV mode */ | |
353 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 354 | { REG_COM1, 0 }, /* CCIR601 */ |
111f3356 JC |
355 | { REG_COM15, COM15_R00FF }, |
356 | { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */ | |
357 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ | |
358 | { 0x50, 0x80 }, /* "matrix coefficient 2" */ | |
f9a76156 | 359 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
360 | { 0x52, 0x22 }, /* "matrix coefficient 4" */ |
361 | { 0x53, 0x5e }, /* "matrix coefficient 5" */ | |
362 | { 0x54, 0x80 }, /* "matrix coefficient 6" */ | |
363 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
364 | { 0xff, 0xff }, | |
365 | }; | |
366 | ||
367 | static struct regval_list ov7670_fmt_rgb565[] = { | |
368 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
369 | { REG_RGB444, 0 }, /* No RGB444 please */ | |
97693f91 | 370 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
371 | { REG_COM15, COM15_RGB565 }, |
372 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
373 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
374 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 375 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
376 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
377 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
378 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
379 | { REG_COM13, COM13_GAMMA|COM13_UVSAT }, | |
380 | { 0xff, 0xff }, | |
381 | }; | |
382 | ||
383 | static struct regval_list ov7670_fmt_rgb444[] = { | |
384 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | |
385 | { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ | |
97693f91 | 386 | { REG_COM1, 0x0 }, /* CCIR601 */ |
111f3356 JC |
387 | { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ |
388 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | |
389 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | |
390 | { 0x50, 0xb3 }, /* "matrix coefficient 2" */ | |
f9a76156 | 391 | { 0x51, 0 }, /* vb */ |
111f3356 JC |
392 | { 0x52, 0x3d }, /* "matrix coefficient 4" */ |
393 | { 0x53, 0xa7 }, /* "matrix coefficient 5" */ | |
394 | { 0x54, 0xe4 }, /* "matrix coefficient 6" */ | |
395 | { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */ | |
396 | { 0xff, 0xff }, | |
397 | }; | |
398 | ||
585553ec JC |
399 | static struct regval_list ov7670_fmt_raw[] = { |
400 | { REG_COM7, COM7_BAYER }, | |
401 | { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */ | |
402 | { REG_COM16, 0x3d }, /* Edge enhancement, denoise */ | |
403 | { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */ | |
404 | { 0xff, 0xff }, | |
405 | }; | |
111f3356 JC |
406 | |
407 | ||
408 | ||
409 | /* | |
410 | * Low-level register I/O. | |
46714209 JC |
411 | * |
412 | * Note that there are two versions of these. On the XO 1, the | |
413 | * i2c controller only does SMBUS, so that's what we use. The | |
414 | * ov7670 is not really an SMBUS device, though, so the communication | |
415 | * is not always entirely reliable. | |
416 | */ | |
75e2bdad | 417 | static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
418 | unsigned char *value) |
419 | { | |
420 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
421 | int ret; | |
422 | ||
423 | ret = i2c_smbus_read_byte_data(client, reg); | |
424 | if (ret >= 0) { | |
425 | *value = (unsigned char)ret; | |
426 | ret = 0; | |
427 | } | |
428 | return ret; | |
429 | } | |
430 | ||
431 | ||
75e2bdad | 432 | static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg, |
46714209 JC |
433 | unsigned char value) |
434 | { | |
435 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
436 | int ret = i2c_smbus_write_byte_data(client, reg, value); | |
437 | ||
438 | if (reg == REG_COM7 && (value & COM7_RESET)) | |
439 | msleep(5); /* Wait for reset to run */ | |
440 | return ret; | |
441 | } | |
442 | ||
46714209 JC |
443 | /* |
444 | * On most platforms, we'd rather do straight i2c I/O. | |
111f3356 | 445 | */ |
75e2bdad | 446 | static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
447 | unsigned char *value) |
448 | { | |
14386c2b | 449 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
450 | u8 data = reg; |
451 | struct i2c_msg msg; | |
111f3356 JC |
452 | int ret; |
453 | ||
2bf7de48 JC |
454 | /* |
455 | * Send out the register address... | |
456 | */ | |
457 | msg.addr = client->addr; | |
458 | msg.flags = 0; | |
459 | msg.len = 1; | |
460 | msg.buf = &data; | |
461 | ret = i2c_transfer(client->adapter, &msg, 1); | |
462 | if (ret < 0) { | |
463 | printk(KERN_ERR "Error %d on register write\n", ret); | |
464 | return ret; | |
465 | } | |
466 | /* | |
467 | * ...then read back the result. | |
468 | */ | |
469 | msg.flags = I2C_M_RD; | |
470 | ret = i2c_transfer(client->adapter, &msg, 1); | |
bca5c2c5 | 471 | if (ret >= 0) { |
2bf7de48 | 472 | *value = data; |
bca5c2c5 AS |
473 | ret = 0; |
474 | } | |
111f3356 JC |
475 | return ret; |
476 | } | |
477 | ||
478 | ||
75e2bdad | 479 | static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg, |
111f3356 JC |
480 | unsigned char value) |
481 | { | |
14386c2b | 482 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2bf7de48 JC |
483 | struct i2c_msg msg; |
484 | unsigned char data[2] = { reg, value }; | |
485 | int ret; | |
14386c2b | 486 | |
2bf7de48 JC |
487 | msg.addr = client->addr; |
488 | msg.flags = 0; | |
489 | msg.len = 2; | |
490 | msg.buf = data; | |
491 | ret = i2c_transfer(client->adapter, &msg, 1); | |
492 | if (ret > 0) | |
493 | ret = 0; | |
6d77444a | 494 | if (reg == REG_COM7 && (value & COM7_RESET)) |
97693f91 | 495 | msleep(5); /* Wait for reset to run */ |
6d77444a | 496 | return ret; |
111f3356 JC |
497 | } |
498 | ||
75e2bdad DD |
499 | static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg, |
500 | unsigned char *value) | |
501 | { | |
502 | struct ov7670_info *info = to_state(sd); | |
503 | if (info->use_smbus) | |
504 | return ov7670_read_smbus(sd, reg, value); | |
505 | else | |
506 | return ov7670_read_i2c(sd, reg, value); | |
507 | } | |
508 | ||
509 | static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, | |
510 | unsigned char value) | |
511 | { | |
512 | struct ov7670_info *info = to_state(sd); | |
513 | if (info->use_smbus) | |
514 | return ov7670_write_smbus(sd, reg, value); | |
515 | else | |
516 | return ov7670_write_i2c(sd, reg, value); | |
517 | } | |
111f3356 JC |
518 | |
519 | /* | |
520 | * Write a list of register settings; ff/ff stops the process. | |
521 | */ | |
14386c2b | 522 | static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals) |
111f3356 JC |
523 | { |
524 | while (vals->reg_num != 0xff || vals->value != 0xff) { | |
14386c2b | 525 | int ret = ov7670_write(sd, vals->reg_num, vals->value); |
111f3356 JC |
526 | if (ret < 0) |
527 | return ret; | |
528 | vals++; | |
529 | } | |
530 | return 0; | |
531 | } | |
532 | ||
533 | ||
534 | /* | |
535 | * Stuff that knows about the sensor. | |
536 | */ | |
14386c2b | 537 | static int ov7670_reset(struct v4l2_subdev *sd, u32 val) |
111f3356 | 538 | { |
14386c2b | 539 | ov7670_write(sd, REG_COM7, COM7_RESET); |
111f3356 | 540 | msleep(1); |
14386c2b | 541 | return 0; |
111f3356 JC |
542 | } |
543 | ||
544 | ||
14386c2b | 545 | static int ov7670_init(struct v4l2_subdev *sd, u32 val) |
111f3356 | 546 | { |
14386c2b | 547 | return ov7670_write_array(sd, ov7670_default_regs); |
111f3356 JC |
548 | } |
549 | ||
550 | ||
551 | ||
14386c2b | 552 | static int ov7670_detect(struct v4l2_subdev *sd) |
111f3356 JC |
553 | { |
554 | unsigned char v; | |
555 | int ret; | |
556 | ||
14386c2b | 557 | ret = ov7670_init(sd, 0); |
111f3356 JC |
558 | if (ret < 0) |
559 | return ret; | |
14386c2b | 560 | ret = ov7670_read(sd, REG_MIDH, &v); |
111f3356 JC |
561 | if (ret < 0) |
562 | return ret; | |
563 | if (v != 0x7f) /* OV manuf. id. */ | |
564 | return -ENODEV; | |
14386c2b | 565 | ret = ov7670_read(sd, REG_MIDL, &v); |
111f3356 JC |
566 | if (ret < 0) |
567 | return ret; | |
568 | if (v != 0xa2) | |
569 | return -ENODEV; | |
570 | /* | |
571 | * OK, we know we have an OmniVision chip...but which one? | |
572 | */ | |
14386c2b | 573 | ret = ov7670_read(sd, REG_PID, &v); |
111f3356 JC |
574 | if (ret < 0) |
575 | return ret; | |
576 | if (v != 0x76) /* PID + VER = 0x76 / 0x73 */ | |
577 | return -ENODEV; | |
14386c2b | 578 | ret = ov7670_read(sd, REG_VER, &v); |
111f3356 JC |
579 | if (ret < 0) |
580 | return ret; | |
581 | if (v != 0x73) /* PID + VER = 0x76 / 0x73 */ | |
582 | return -ENODEV; | |
583 | return 0; | |
584 | } | |
585 | ||
586 | ||
f9a76156 JC |
587 | /* |
588 | * Store information about the video data format. The color matrix | |
589 | * is deeply tied into the format, so keep the relevant values here. | |
959f3bda | 590 | * The magic matrix numbers come from OmniVision. |
f9a76156 | 591 | */ |
111f3356 | 592 | static struct ov7670_format_struct { |
959f3bda HV |
593 | enum v4l2_mbus_pixelcode mbus_code; |
594 | enum v4l2_colorspace colorspace; | |
111f3356 | 595 | struct regval_list *regs; |
f9a76156 | 596 | int cmatrix[CMATRIX_LEN]; |
111f3356 JC |
597 | } ov7670_formats[] = { |
598 | { | |
959f3bda HV |
599 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, |
600 | .colorspace = V4L2_COLORSPACE_JPEG, | |
111f3356 | 601 | .regs = ov7670_fmt_yuv422, |
f9a76156 | 602 | .cmatrix = { 128, -128, 0, -34, -94, 128 }, |
111f3356 JC |
603 | }, |
604 | { | |
959f3bda HV |
605 | .mbus_code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_LE, |
606 | .colorspace = V4L2_COLORSPACE_SRGB, | |
111f3356 | 607 | .regs = ov7670_fmt_rgb444, |
f9a76156 | 608 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
111f3356 JC |
609 | }, |
610 | { | |
959f3bda HV |
611 | .mbus_code = V4L2_MBUS_FMT_RGB565_2X8_LE, |
612 | .colorspace = V4L2_COLORSPACE_SRGB, | |
111f3356 | 613 | .regs = ov7670_fmt_rgb565, |
f9a76156 | 614 | .cmatrix = { 179, -179, 0, -61, -176, 228 }, |
585553ec JC |
615 | }, |
616 | { | |
959f3bda HV |
617 | .mbus_code = V4L2_MBUS_FMT_SBGGR8_1X8, |
618 | .colorspace = V4L2_COLORSPACE_SRGB, | |
585553ec JC |
619 | .regs = ov7670_fmt_raw, |
620 | .cmatrix = { 0, 0, 0, 0, 0, 0 }, | |
111f3356 | 621 | }, |
111f3356 | 622 | }; |
585553ec | 623 | #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats) |
111f3356 | 624 | |
111f3356 JC |
625 | |
626 | /* | |
627 | * Then there is the issue of window sizes. Try to capture the info here. | |
628 | */ | |
f9a76156 JC |
629 | |
630 | /* | |
631 | * QCIF mode is done (by OV) in a very strange way - it actually looks like | |
632 | * VGA with weird scaling options - they do *not* use the canned QCIF mode | |
633 | * which is allegedly provided by the sensor. So here's the weird register | |
634 | * settings. | |
635 | */ | |
636 | static struct regval_list ov7670_qcif_regs[] = { | |
637 | { REG_COM3, COM3_SCALEEN|COM3_DCWEN }, | |
638 | { REG_COM3, COM3_DCWEN }, | |
639 | { REG_COM14, COM14_DCWEN | 0x01}, | |
640 | { 0x73, 0xf1 }, | |
641 | { 0xa2, 0x52 }, | |
642 | { 0x7b, 0x1c }, | |
643 | { 0x7c, 0x28 }, | |
644 | { 0x7d, 0x3c }, | |
645 | { 0x7f, 0x69 }, | |
646 | { REG_COM9, 0x38 }, | |
647 | { 0xa1, 0x0b }, | |
648 | { 0x74, 0x19 }, | |
649 | { 0x9a, 0x80 }, | |
650 | { 0x43, 0x14 }, | |
651 | { REG_COM13, 0xc0 }, | |
652 | { 0xff, 0xff }, | |
653 | }; | |
654 | ||
111f3356 JC |
655 | static struct ov7670_win_size { |
656 | int width; | |
657 | int height; | |
658 | unsigned char com7_bit; | |
659 | int hstart; /* Start/stop values for the camera. Note */ | |
660 | int hstop; /* that they do not always make complete */ | |
661 | int vstart; /* sense to humans, but evidently the sensor */ | |
662 | int vstop; /* will do the right thing... */ | |
f9a76156 | 663 | struct regval_list *regs; /* Regs to tweak */ |
111f3356 JC |
664 | /* h/vref stuff */ |
665 | } ov7670_win_sizes[] = { | |
666 | /* VGA */ | |
667 | { | |
668 | .width = VGA_WIDTH, | |
669 | .height = VGA_HEIGHT, | |
670 | .com7_bit = COM7_FMT_VGA, | |
671 | .hstart = 158, /* These values from */ | |
672 | .hstop = 14, /* Omnivision */ | |
673 | .vstart = 10, | |
674 | .vstop = 490, | |
f9a76156 | 675 | .regs = NULL, |
111f3356 JC |
676 | }, |
677 | /* CIF */ | |
678 | { | |
679 | .width = CIF_WIDTH, | |
680 | .height = CIF_HEIGHT, | |
681 | .com7_bit = COM7_FMT_CIF, | |
682 | .hstart = 170, /* Empirically determined */ | |
683 | .hstop = 90, | |
684 | .vstart = 14, | |
685 | .vstop = 494, | |
f9a76156 | 686 | .regs = NULL, |
111f3356 JC |
687 | }, |
688 | /* QVGA */ | |
689 | { | |
690 | .width = QVGA_WIDTH, | |
691 | .height = QVGA_HEIGHT, | |
692 | .com7_bit = COM7_FMT_QVGA, | |
dc4589c8 DD |
693 | .hstart = 168, /* Empirically determined */ |
694 | .hstop = 24, | |
695 | .vstart = 12, | |
696 | .vstop = 492, | |
f9a76156 JC |
697 | .regs = NULL, |
698 | }, | |
699 | /* QCIF */ | |
700 | { | |
701 | .width = QCIF_WIDTH, | |
702 | .height = QCIF_HEIGHT, | |
703 | .com7_bit = COM7_FMT_VGA, /* see comment above */ | |
704 | .hstart = 456, /* Empirically determined */ | |
705 | .hstop = 24, | |
706 | .vstart = 14, | |
707 | .vstop = 494, | |
708 | .regs = ov7670_qcif_regs, | |
111f3356 JC |
709 | }, |
710 | }; | |
711 | ||
0c71bf1c | 712 | #define N_WIN_SIZES (ARRAY_SIZE(ov7670_win_sizes)) |
111f3356 JC |
713 | |
714 | ||
715 | /* | |
716 | * Store a set of start/stop values into the camera. | |
717 | */ | |
14386c2b | 718 | static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop, |
111f3356 JC |
719 | int vstart, int vstop) |
720 | { | |
721 | int ret; | |
722 | unsigned char v; | |
723 | /* | |
724 | * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of | |
725 | * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is | |
726 | * a mystery "edge offset" value in the top two bits of href. | |
727 | */ | |
14386c2b HV |
728 | ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff); |
729 | ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff); | |
730 | ret += ov7670_read(sd, REG_HREF, &v); | |
111f3356 JC |
731 | v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7); |
732 | msleep(10); | |
14386c2b | 733 | ret += ov7670_write(sd, REG_HREF, v); |
111f3356 JC |
734 | /* |
735 | * Vertical: similar arrangement, but only 10 bits. | |
736 | */ | |
14386c2b HV |
737 | ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff); |
738 | ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff); | |
739 | ret += ov7670_read(sd, REG_VREF, &v); | |
111f3356 JC |
740 | v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3); |
741 | msleep(10); | |
14386c2b | 742 | ret += ov7670_write(sd, REG_VREF, v); |
111f3356 JC |
743 | return ret; |
744 | } | |
745 | ||
746 | ||
959f3bda HV |
747 | static int ov7670_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index, |
748 | enum v4l2_mbus_pixelcode *code) | |
749 | { | |
750 | if (index >= N_OV7670_FMTS) | |
751 | return -EINVAL; | |
752 | ||
753 | *code = ov7670_formats[index].mbus_code; | |
754 | return 0; | |
755 | } | |
111f3356 | 756 | |
14386c2b | 757 | static int ov7670_try_fmt_internal(struct v4l2_subdev *sd, |
959f3bda | 758 | struct v4l2_mbus_framefmt *fmt, |
111f3356 JC |
759 | struct ov7670_format_struct **ret_fmt, |
760 | struct ov7670_win_size **ret_wsize) | |
761 | { | |
762 | int index; | |
763 | struct ov7670_win_size *wsize; | |
111f3356 JC |
764 | |
765 | for (index = 0; index < N_OV7670_FMTS; index++) | |
959f3bda | 766 | if (ov7670_formats[index].mbus_code == fmt->code) |
111f3356 | 767 | break; |
cd257a6f DD |
768 | if (index >= N_OV7670_FMTS) { |
769 | /* default to first format */ | |
770 | index = 0; | |
959f3bda | 771 | fmt->code = ov7670_formats[0].mbus_code; |
cd257a6f | 772 | } |
111f3356 JC |
773 | if (ret_fmt != NULL) |
774 | *ret_fmt = ov7670_formats + index; | |
775 | /* | |
776 | * Fields: the OV devices claim to be progressive. | |
777 | */ | |
959f3bda | 778 | fmt->field = V4L2_FIELD_NONE; |
111f3356 JC |
779 | /* |
780 | * Round requested image size down to the nearest | |
781 | * we support, but not below the smallest. | |
782 | */ | |
783 | for (wsize = ov7670_win_sizes; wsize < ov7670_win_sizes + N_WIN_SIZES; | |
784 | wsize++) | |
959f3bda | 785 | if (fmt->width >= wsize->width && fmt->height >= wsize->height) |
111f3356 | 786 | break; |
f9a76156 | 787 | if (wsize >= ov7670_win_sizes + N_WIN_SIZES) |
111f3356 JC |
788 | wsize--; /* Take the smallest one */ |
789 | if (ret_wsize != NULL) | |
790 | *ret_wsize = wsize; | |
791 | /* | |
792 | * Note the size we'll actually handle. | |
793 | */ | |
959f3bda HV |
794 | fmt->width = wsize->width; |
795 | fmt->height = wsize->height; | |
796 | fmt->colorspace = ov7670_formats[index].colorspace; | |
111f3356 | 797 | return 0; |
111f3356 JC |
798 | } |
799 | ||
959f3bda HV |
800 | static int ov7670_try_mbus_fmt(struct v4l2_subdev *sd, |
801 | struct v4l2_mbus_framefmt *fmt) | |
14386c2b HV |
802 | { |
803 | return ov7670_try_fmt_internal(sd, fmt, NULL, NULL); | |
804 | } | |
805 | ||
111f3356 JC |
806 | /* |
807 | * Set a format. | |
808 | */ | |
959f3bda HV |
809 | static int ov7670_s_mbus_fmt(struct v4l2_subdev *sd, |
810 | struct v4l2_mbus_framefmt *fmt) | |
111f3356 | 811 | { |
111f3356 JC |
812 | struct ov7670_format_struct *ovfmt; |
813 | struct ov7670_win_size *wsize; | |
14386c2b | 814 | struct ov7670_info *info = to_state(sd); |
d8d20155 | 815 | unsigned char com7; |
959f3bda | 816 | int ret; |
111f3356 | 817 | |
14386c2b | 818 | ret = ov7670_try_fmt_internal(sd, fmt, &ovfmt, &wsize); |
959f3bda | 819 | |
111f3356 JC |
820 | if (ret) |
821 | return ret; | |
822 | /* | |
823 | * COM7 is a pain in the ass, it doesn't like to be read then | |
824 | * quickly written afterward. But we have everything we need | |
825 | * to set it absolutely here, as long as the format-specific | |
826 | * register sets list it first. | |
827 | */ | |
828 | com7 = ovfmt->regs[0].value; | |
829 | com7 |= wsize->com7_bit; | |
14386c2b | 830 | ov7670_write(sd, REG_COM7, com7); |
111f3356 JC |
831 | /* |
832 | * Now write the rest of the array. Also store start/stops | |
833 | */ | |
14386c2b HV |
834 | ov7670_write_array(sd, ovfmt->regs + 1); |
835 | ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart, | |
111f3356 | 836 | wsize->vstop); |
f9a76156 JC |
837 | ret = 0; |
838 | if (wsize->regs) | |
14386c2b | 839 | ret = ov7670_write_array(sd, wsize->regs); |
f9a76156 | 840 | info->fmt = ovfmt; |
edd75ede | 841 | |
d8d20155 JC |
842 | /* |
843 | * If we're running RGB565, we must rewrite clkrc after setting | |
844 | * the other parameters or the image looks poor. If we're *not* | |
845 | * doing RGB565, we must not rewrite clkrc or the image looks | |
846 | * *really* poor. | |
a8e68c37 JC |
847 | * |
848 | * (Update) Now that we retain clkrc state, we should be able | |
849 | * to write it unconditionally, and that will make the frame | |
850 | * rate persistent too. | |
d8d20155 | 851 | */ |
a8e68c37 | 852 | if (ret == 0) |
d8d20155 | 853 | ret = ov7670_write(sd, REG_CLKRC, info->clkrc); |
959f3bda HV |
854 | return 0; |
855 | } | |
856 | ||
c8f5b2f5 JC |
857 | /* |
858 | * Implement G/S_PARM. There is a "high quality" mode we could try | |
859 | * to do someday; for now, we just do the frame rate tweak. | |
860 | */ | |
14386c2b | 861 | static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
862 | { |
863 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
d8d20155 | 864 | struct ov7670_info *info = to_state(sd); |
c8f5b2f5 JC |
865 | |
866 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
867 | return -EINVAL; | |
d8d20155 | 868 | |
c8f5b2f5 JC |
869 | memset(cp, 0, sizeof(struct v4l2_captureparm)); |
870 | cp->capability = V4L2_CAP_TIMEPERFRAME; | |
871 | cp->timeperframe.numerator = 1; | |
75e2bdad | 872 | cp->timeperframe.denominator = info->clock_speed; |
d8d20155 JC |
873 | if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1) |
874 | cp->timeperframe.denominator /= (info->clkrc & CLK_SCALE); | |
c8f5b2f5 JC |
875 | return 0; |
876 | } | |
877 | ||
14386c2b | 878 | static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) |
c8f5b2f5 JC |
879 | { |
880 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
881 | struct v4l2_fract *tpf = &cp->timeperframe; | |
d8d20155 | 882 | struct ov7670_info *info = to_state(sd); |
380de498 | 883 | int div; |
c8f5b2f5 JC |
884 | |
885 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
886 | return -EINVAL; | |
887 | if (cp->extendedmode != 0) | |
888 | return -EINVAL; | |
d8d20155 | 889 | |
c8f5b2f5 JC |
890 | if (tpf->numerator == 0 || tpf->denominator == 0) |
891 | div = 1; /* Reset to full rate */ | |
892 | else | |
75e2bdad | 893 | div = (tpf->numerator * info->clock_speed) / tpf->denominator; |
c8f5b2f5 JC |
894 | if (div == 0) |
895 | div = 1; | |
896 | else if (div > CLK_SCALE) | |
897 | div = CLK_SCALE; | |
d8d20155 | 898 | info->clkrc = (info->clkrc & 0x80) | div; |
c8f5b2f5 | 899 | tpf->numerator = 1; |
75e2bdad | 900 | tpf->denominator = info->clock_speed / div; |
d8d20155 | 901 | return ov7670_write(sd, REG_CLKRC, info->clkrc); |
c8f5b2f5 JC |
902 | } |
903 | ||
904 | ||
111f3356 | 905 | /* |
e99dfcf7 JC |
906 | * Frame intervals. Since frame rates are controlled with the clock |
907 | * divider, we can only do 30/n for integer n values. So no continuous | |
908 | * or stepwise options. Here we just pick a handful of logical values. | |
111f3356 JC |
909 | */ |
910 | ||
e99dfcf7 | 911 | static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 }; |
f9a76156 | 912 | |
e99dfcf7 JC |
913 | static int ov7670_enum_frameintervals(struct v4l2_subdev *sd, |
914 | struct v4l2_frmivalenum *interval) | |
915 | { | |
916 | if (interval->index >= ARRAY_SIZE(ov7670_frame_rates)) | |
917 | return -EINVAL; | |
918 | interval->type = V4L2_FRMIVAL_TYPE_DISCRETE; | |
919 | interval->discrete.numerator = 1; | |
920 | interval->discrete.denominator = ov7670_frame_rates[interval->index]; | |
921 | return 0; | |
922 | } | |
f9a76156 | 923 | |
b0326b7f DD |
924 | /* |
925 | * Frame size enumeration | |
926 | */ | |
927 | static int ov7670_enum_framesizes(struct v4l2_subdev *sd, | |
928 | struct v4l2_frmsizeenum *fsize) | |
929 | { | |
75e2bdad DD |
930 | struct ov7670_info *info = to_state(sd); |
931 | int i; | |
932 | int num_valid = -1; | |
b0326b7f | 933 | __u32 index = fsize->index; |
b0326b7f | 934 | |
75e2bdad DD |
935 | /* |
936 | * If a minimum width/height was requested, filter out the capture | |
937 | * windows that fall outside that. | |
938 | */ | |
939 | for (i = 0; i < N_WIN_SIZES; i++) { | |
940 | struct ov7670_win_size *win = &ov7670_win_sizes[index]; | |
941 | if (info->min_width && win->width < info->min_width) | |
942 | continue; | |
943 | if (info->min_height && win->height < info->min_height) | |
944 | continue; | |
945 | if (index == ++num_valid) { | |
946 | fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE; | |
947 | fsize->discrete.width = win->width; | |
948 | fsize->discrete.height = win->height; | |
949 | return 0; | |
950 | } | |
951 | } | |
952 | ||
953 | return -EINVAL; | |
b0326b7f DD |
954 | } |
955 | ||
e99dfcf7 JC |
956 | /* |
957 | * Code for dealing with controls. | |
958 | */ | |
f9a76156 | 959 | |
14386c2b | 960 | static int ov7670_store_cmatrix(struct v4l2_subdev *sd, |
f9a76156 JC |
961 | int matrix[CMATRIX_LEN]) |
962 | { | |
963 | int i, ret; | |
e3bf20de | 964 | unsigned char signbits = 0; |
f9a76156 JC |
965 | |
966 | /* | |
967 | * Weird crap seems to exist in the upper part of | |
968 | * the sign bits register, so let's preserve it. | |
969 | */ | |
14386c2b | 970 | ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits); |
f9a76156 JC |
971 | signbits &= 0xc0; |
972 | ||
973 | for (i = 0; i < CMATRIX_LEN; i++) { | |
974 | unsigned char raw; | |
975 | ||
976 | if (matrix[i] < 0) { | |
977 | signbits |= (1 << i); | |
978 | if (matrix[i] < -255) | |
979 | raw = 0xff; | |
980 | else | |
981 | raw = (-1 * matrix[i]) & 0xff; | |
982 | } | |
983 | else { | |
984 | if (matrix[i] > 255) | |
985 | raw = 0xff; | |
986 | else | |
987 | raw = matrix[i] & 0xff; | |
988 | } | |
14386c2b | 989 | ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw); |
f9a76156 | 990 | } |
14386c2b | 991 | ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits); |
f9a76156 JC |
992 | return ret; |
993 | } | |
994 | ||
995 | ||
996 | /* | |
997 | * Hue also requires messing with the color matrix. It also requires | |
998 | * trig functions, which tend not to be well supported in the kernel. | |
999 | * So here is a simple table of sine values, 0-90 degrees, in steps | |
1000 | * of five degrees. Values are multiplied by 1000. | |
1001 | * | |
1002 | * The following naive approximate trig functions require an argument | |
1003 | * carefully limited to -180 <= theta <= 180. | |
1004 | */ | |
1005 | #define SIN_STEP 5 | |
1006 | static const int ov7670_sin_table[] = { | |
1007 | 0, 87, 173, 258, 342, 422, | |
1008 | 499, 573, 642, 707, 766, 819, | |
1009 | 866, 906, 939, 965, 984, 996, | |
1010 | 1000 | |
1011 | }; | |
1012 | ||
1013 | static int ov7670_sine(int theta) | |
1014 | { | |
1015 | int chs = 1; | |
1016 | int sine; | |
1017 | ||
1018 | if (theta < 0) { | |
1019 | theta = -theta; | |
1020 | chs = -1; | |
1021 | } | |
1022 | if (theta <= 90) | |
1023 | sine = ov7670_sin_table[theta/SIN_STEP]; | |
1024 | else { | |
1025 | theta -= 90; | |
1026 | sine = 1000 - ov7670_sin_table[theta/SIN_STEP]; | |
1027 | } | |
1028 | return sine*chs; | |
1029 | } | |
1030 | ||
1031 | static int ov7670_cosine(int theta) | |
1032 | { | |
1033 | theta = 90 - theta; | |
1034 | if (theta > 180) | |
1035 | theta -= 360; | |
1036 | else if (theta < -180) | |
1037 | theta += 360; | |
1038 | return ov7670_sine(theta); | |
1039 | } | |
1040 | ||
1041 | ||
1042 | ||
1043 | ||
1044 | static void ov7670_calc_cmatrix(struct ov7670_info *info, | |
1045 | int matrix[CMATRIX_LEN]) | |
1046 | { | |
1047 | int i; | |
1048 | /* | |
1049 | * Apply the current saturation setting first. | |
1050 | */ | |
1051 | for (i = 0; i < CMATRIX_LEN; i++) | |
1052 | matrix[i] = (info->fmt->cmatrix[i]*info->sat) >> 7; | |
1053 | /* | |
1054 | * Then, if need be, rotate the hue value. | |
1055 | */ | |
1056 | if (info->hue != 0) { | |
1057 | int sinth, costh, tmpmatrix[CMATRIX_LEN]; | |
1058 | ||
1059 | memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int)); | |
1060 | sinth = ov7670_sine(info->hue); | |
1061 | costh = ov7670_cosine(info->hue); | |
1062 | ||
1063 | matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000; | |
1064 | matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000; | |
1065 | matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000; | |
1066 | matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000; | |
1067 | matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000; | |
1068 | matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000; | |
1069 | } | |
1070 | } | |
1071 | ||
1072 | ||
1073 | ||
ca07561a | 1074 | static int ov7670_s_sat(struct v4l2_subdev *sd, int value) |
f9a76156 | 1075 | { |
14386c2b | 1076 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1077 | int matrix[CMATRIX_LEN]; |
1078 | int ret; | |
1079 | ||
1080 | info->sat = value; | |
1081 | ov7670_calc_cmatrix(info, matrix); | |
14386c2b | 1082 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1083 | return ret; |
1084 | } | |
1085 | ||
ca07561a | 1086 | static int ov7670_g_sat(struct v4l2_subdev *sd, __s32 *value) |
f9a76156 | 1087 | { |
14386c2b | 1088 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1089 | |
1090 | *value = info->sat; | |
1091 | return 0; | |
1092 | } | |
1093 | ||
ca07561a | 1094 | static int ov7670_s_hue(struct v4l2_subdev *sd, int value) |
f9a76156 | 1095 | { |
14386c2b | 1096 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1097 | int matrix[CMATRIX_LEN]; |
1098 | int ret; | |
1099 | ||
1100 | if (value < -180 || value > 180) | |
1101 | return -EINVAL; | |
1102 | info->hue = value; | |
1103 | ov7670_calc_cmatrix(info, matrix); | |
14386c2b | 1104 | ret = ov7670_store_cmatrix(sd, matrix); |
f9a76156 JC |
1105 | return ret; |
1106 | } | |
1107 | ||
1108 | ||
ca07561a | 1109 | static int ov7670_g_hue(struct v4l2_subdev *sd, __s32 *value) |
f9a76156 | 1110 | { |
14386c2b | 1111 | struct ov7670_info *info = to_state(sd); |
f9a76156 JC |
1112 | |
1113 | *value = info->hue; | |
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | ||
111f3356 JC |
1118 | /* |
1119 | * Some weird registers seem to store values in a sign/magnitude format! | |
1120 | */ | |
1121 | static unsigned char ov7670_sm_to_abs(unsigned char v) | |
1122 | { | |
1123 | if ((v & 0x80) == 0) | |
1124 | return v + 128; | |
14386c2b | 1125 | return 128 - (v & 0x7f); |
111f3356 JC |
1126 | } |
1127 | ||
1128 | ||
1129 | static unsigned char ov7670_abs_to_sm(unsigned char v) | |
1130 | { | |
1131 | if (v > 127) | |
1132 | return v & 0x7f; | |
14386c2b | 1133 | return (128 - v) | 0x80; |
111f3356 JC |
1134 | } |
1135 | ||
ca07561a | 1136 | static int ov7670_s_brightness(struct v4l2_subdev *sd, int value) |
111f3356 | 1137 | { |
e3bf20de | 1138 | unsigned char com8 = 0, v; |
111f3356 JC |
1139 | int ret; |
1140 | ||
14386c2b | 1141 | ov7670_read(sd, REG_COM8, &com8); |
111f3356 | 1142 | com8 &= ~COM8_AEC; |
14386c2b | 1143 | ov7670_write(sd, REG_COM8, com8); |
f9a76156 | 1144 | v = ov7670_abs_to_sm(value); |
14386c2b | 1145 | ret = ov7670_write(sd, REG_BRIGHT, v); |
111f3356 JC |
1146 | return ret; |
1147 | } | |
1148 | ||
ca07561a | 1149 | static int ov7670_g_brightness(struct v4l2_subdev *sd, __s32 *value) |
111f3356 | 1150 | { |
e3bf20de | 1151 | unsigned char v = 0; |
14386c2b | 1152 | int ret = ov7670_read(sd, REG_BRIGHT, &v); |
f9a76156 JC |
1153 | |
1154 | *value = ov7670_sm_to_abs(v); | |
111f3356 JC |
1155 | return ret; |
1156 | } | |
1157 | ||
ca07561a | 1158 | static int ov7670_s_contrast(struct v4l2_subdev *sd, int value) |
111f3356 | 1159 | { |
14386c2b | 1160 | return ov7670_write(sd, REG_CONTRAS, (unsigned char) value); |
111f3356 JC |
1161 | } |
1162 | ||
ca07561a | 1163 | static int ov7670_g_contrast(struct v4l2_subdev *sd, __s32 *value) |
111f3356 | 1164 | { |
e3bf20de | 1165 | unsigned char v = 0; |
14386c2b | 1166 | int ret = ov7670_read(sd, REG_CONTRAS, &v); |
f9a76156 JC |
1167 | |
1168 | *value = v; | |
1169 | return ret; | |
111f3356 JC |
1170 | } |
1171 | ||
ca07561a | 1172 | static int ov7670_g_hflip(struct v4l2_subdev *sd, __s32 *value) |
111f3356 JC |
1173 | { |
1174 | int ret; | |
e3bf20de | 1175 | unsigned char v = 0; |
111f3356 | 1176 | |
14386c2b | 1177 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1178 | *value = (v & MVFP_MIRROR) == MVFP_MIRROR; |
1179 | return ret; | |
1180 | } | |
1181 | ||
1182 | ||
ca07561a | 1183 | static int ov7670_s_hflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1184 | { |
e3bf20de | 1185 | unsigned char v = 0; |
111f3356 JC |
1186 | int ret; |
1187 | ||
14386c2b | 1188 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1189 | if (value) |
1190 | v |= MVFP_MIRROR; | |
1191 | else | |
1192 | v &= ~MVFP_MIRROR; | |
1193 | msleep(10); /* FIXME */ | |
14386c2b | 1194 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1195 | return ret; |
1196 | } | |
1197 | ||
1198 | ||
1199 | ||
ca07561a | 1200 | static int ov7670_g_vflip(struct v4l2_subdev *sd, __s32 *value) |
111f3356 JC |
1201 | { |
1202 | int ret; | |
e3bf20de | 1203 | unsigned char v = 0; |
111f3356 | 1204 | |
14386c2b | 1205 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1206 | *value = (v & MVFP_FLIP) == MVFP_FLIP; |
1207 | return ret; | |
1208 | } | |
1209 | ||
1210 | ||
ca07561a | 1211 | static int ov7670_s_vflip(struct v4l2_subdev *sd, int value) |
111f3356 | 1212 | { |
e3bf20de | 1213 | unsigned char v = 0; |
111f3356 JC |
1214 | int ret; |
1215 | ||
14386c2b | 1216 | ret = ov7670_read(sd, REG_MVFP, &v); |
111f3356 JC |
1217 | if (value) |
1218 | v |= MVFP_FLIP; | |
1219 | else | |
1220 | v &= ~MVFP_FLIP; | |
1221 | msleep(10); /* FIXME */ | |
14386c2b | 1222 | ret += ov7670_write(sd, REG_MVFP, v); |
111f3356 JC |
1223 | return ret; |
1224 | } | |
1225 | ||
81898671 JC |
1226 | /* |
1227 | * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes | |
1228 | * the data sheet, the VREF parts should be the most significant, but | |
1229 | * experience shows otherwise. There seems to be little value in | |
1230 | * messing with the VREF bits, so we leave them alone. | |
1231 | */ | |
1232 | static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value) | |
1233 | { | |
1234 | int ret; | |
1235 | unsigned char gain; | |
1236 | ||
1237 | ret = ov7670_read(sd, REG_GAIN, &gain); | |
1238 | *value = gain; | |
1239 | return ret; | |
1240 | } | |
1241 | ||
1242 | static int ov7670_s_gain(struct v4l2_subdev *sd, int value) | |
1243 | { | |
1244 | int ret; | |
1245 | unsigned char com8; | |
1246 | ||
1247 | ret = ov7670_write(sd, REG_GAIN, value & 0xff); | |
1248 | /* Have to turn off AGC as well */ | |
1249 | if (ret == 0) { | |
1250 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1251 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC); | |
1252 | } | |
1253 | return ret; | |
1254 | } | |
1255 | ||
1256 | /* | |
1257 | * Tweak autogain. | |
1258 | */ | |
1259 | static int ov7670_g_autogain(struct v4l2_subdev *sd, __s32 *value) | |
1260 | { | |
1261 | int ret; | |
1262 | unsigned char com8; | |
1263 | ||
1264 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1265 | *value = (com8 & COM8_AGC) != 0; | |
1266 | return ret; | |
1267 | } | |
1268 | ||
1269 | static int ov7670_s_autogain(struct v4l2_subdev *sd, int value) | |
1270 | { | |
1271 | int ret; | |
1272 | unsigned char com8; | |
1273 | ||
1274 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1275 | if (ret == 0) { | |
1276 | if (value) | |
1277 | com8 |= COM8_AGC; | |
1278 | else | |
1279 | com8 &= ~COM8_AGC; | |
1280 | ret = ov7670_write(sd, REG_COM8, com8); | |
1281 | } | |
1282 | return ret; | |
1283 | } | |
1284 | ||
364e9337 JC |
1285 | /* |
1286 | * Exposure is spread all over the place: top 6 bits in AECHH, middle | |
1287 | * 8 in AECH, and two stashed in COM1 just for the hell of it. | |
1288 | */ | |
1289 | static int ov7670_g_exp(struct v4l2_subdev *sd, __s32 *value) | |
1290 | { | |
1291 | int ret; | |
1292 | unsigned char com1, aech, aechh; | |
1293 | ||
1294 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
1295 | ov7670_read(sd, REG_AECH, &aech) + | |
1296 | ov7670_read(sd, REG_AECHH, &aechh); | |
1297 | *value = ((aechh & 0x3f) << 10) | (aech << 2) | (com1 & 0x03); | |
1298 | return ret; | |
1299 | } | |
1300 | ||
1301 | static int ov7670_s_exp(struct v4l2_subdev *sd, int value) | |
1302 | { | |
1303 | int ret; | |
1304 | unsigned char com1, com8, aech, aechh; | |
1305 | ||
1306 | ret = ov7670_read(sd, REG_COM1, &com1) + | |
1307 | ov7670_read(sd, REG_COM8, &com8); | |
1308 | ov7670_read(sd, REG_AECHH, &aechh); | |
1309 | if (ret) | |
1310 | return ret; | |
1311 | ||
1312 | com1 = (com1 & 0xfc) | (value & 0x03); | |
1313 | aech = (value >> 2) & 0xff; | |
1314 | aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f); | |
1315 | ret = ov7670_write(sd, REG_COM1, com1) + | |
1316 | ov7670_write(sd, REG_AECH, aech) + | |
1317 | ov7670_write(sd, REG_AECHH, aechh); | |
1318 | /* Have to turn off AEC as well */ | |
1319 | if (ret == 0) | |
1320 | ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC); | |
1321 | return ret; | |
1322 | } | |
1323 | ||
1324 | /* | |
1325 | * Tweak autoexposure. | |
1326 | */ | |
1327 | static int ov7670_g_autoexp(struct v4l2_subdev *sd, __s32 *value) | |
1328 | { | |
1329 | int ret; | |
1330 | unsigned char com8; | |
1331 | enum v4l2_exposure_auto_type *atype = (enum v4l2_exposure_auto_type *) value; | |
1332 | ||
1333 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1334 | if (com8 & COM8_AEC) | |
380de498 | 1335 | *atype = V4L2_EXPOSURE_AUTO; |
364e9337 | 1336 | else |
380de498 | 1337 | *atype = V4L2_EXPOSURE_MANUAL; |
364e9337 JC |
1338 | return ret; |
1339 | } | |
1340 | ||
1341 | static int ov7670_s_autoexp(struct v4l2_subdev *sd, | |
1342 | enum v4l2_exposure_auto_type value) | |
1343 | { | |
1344 | int ret; | |
1345 | unsigned char com8; | |
1346 | ||
1347 | ret = ov7670_read(sd, REG_COM8, &com8); | |
1348 | if (ret == 0) { | |
1349 | if (value == V4L2_EXPOSURE_AUTO) | |
1350 | com8 |= COM8_AEC; | |
1351 | else | |
1352 | com8 &= ~COM8_AEC; | |
1353 | ret = ov7670_write(sd, REG_COM8, com8); | |
1354 | } | |
1355 | return ret; | |
1356 | } | |
1357 | ||
81898671 JC |
1358 | |
1359 | ||
14386c2b | 1360 | static int ov7670_queryctrl(struct v4l2_subdev *sd, |
111f3356 JC |
1361 | struct v4l2_queryctrl *qc) |
1362 | { | |
ca07561a HV |
1363 | /* Fill in min, max, step and default value for these controls. */ |
1364 | switch (qc->id) { | |
1365 | case V4L2_CID_BRIGHTNESS: | |
1366 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
1367 | case V4L2_CID_CONTRAST: | |
1368 | return v4l2_ctrl_query_fill(qc, 0, 127, 1, 64); | |
1369 | case V4L2_CID_VFLIP: | |
1370 | case V4L2_CID_HFLIP: | |
1371 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
1372 | case V4L2_CID_SATURATION: | |
1373 | return v4l2_ctrl_query_fill(qc, 0, 256, 1, 128); | |
1374 | case V4L2_CID_HUE: | |
1375 | return v4l2_ctrl_query_fill(qc, -180, 180, 5, 0); | |
81898671 JC |
1376 | case V4L2_CID_GAIN: |
1377 | return v4l2_ctrl_query_fill(qc, 0, 255, 1, 128); | |
1378 | case V4L2_CID_AUTOGAIN: | |
1379 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 1); | |
364e9337 JC |
1380 | case V4L2_CID_EXPOSURE: |
1381 | return v4l2_ctrl_query_fill(qc, 0, 65535, 1, 500); | |
1382 | case V4L2_CID_EXPOSURE_AUTO: | |
1383 | return v4l2_ctrl_query_fill(qc, 0, 1, 1, 0); | |
ca07561a HV |
1384 | } |
1385 | return -EINVAL; | |
111f3356 JC |
1386 | } |
1387 | ||
14386c2b | 1388 | static int ov7670_g_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
111f3356 | 1389 | { |
ca07561a HV |
1390 | switch (ctrl->id) { |
1391 | case V4L2_CID_BRIGHTNESS: | |
1392 | return ov7670_g_brightness(sd, &ctrl->value); | |
1393 | case V4L2_CID_CONTRAST: | |
1394 | return ov7670_g_contrast(sd, &ctrl->value); | |
1395 | case V4L2_CID_SATURATION: | |
1396 | return ov7670_g_sat(sd, &ctrl->value); | |
1397 | case V4L2_CID_HUE: | |
1398 | return ov7670_g_hue(sd, &ctrl->value); | |
1399 | case V4L2_CID_VFLIP: | |
1400 | return ov7670_g_vflip(sd, &ctrl->value); | |
1401 | case V4L2_CID_HFLIP: | |
1402 | return ov7670_g_hflip(sd, &ctrl->value); | |
81898671 JC |
1403 | case V4L2_CID_GAIN: |
1404 | return ov7670_g_gain(sd, &ctrl->value); | |
1405 | case V4L2_CID_AUTOGAIN: | |
1406 | return ov7670_g_autogain(sd, &ctrl->value); | |
364e9337 JC |
1407 | case V4L2_CID_EXPOSURE: |
1408 | return ov7670_g_exp(sd, &ctrl->value); | |
1409 | case V4L2_CID_EXPOSURE_AUTO: | |
1410 | return ov7670_g_autoexp(sd, &ctrl->value); | |
ca07561a HV |
1411 | } |
1412 | return -EINVAL; | |
111f3356 JC |
1413 | } |
1414 | ||
14386c2b | 1415 | static int ov7670_s_ctrl(struct v4l2_subdev *sd, struct v4l2_control *ctrl) |
111f3356 | 1416 | { |
ca07561a HV |
1417 | switch (ctrl->id) { |
1418 | case V4L2_CID_BRIGHTNESS: | |
1419 | return ov7670_s_brightness(sd, ctrl->value); | |
1420 | case V4L2_CID_CONTRAST: | |
1421 | return ov7670_s_contrast(sd, ctrl->value); | |
1422 | case V4L2_CID_SATURATION: | |
1423 | return ov7670_s_sat(sd, ctrl->value); | |
1424 | case V4L2_CID_HUE: | |
1425 | return ov7670_s_hue(sd, ctrl->value); | |
1426 | case V4L2_CID_VFLIP: | |
1427 | return ov7670_s_vflip(sd, ctrl->value); | |
1428 | case V4L2_CID_HFLIP: | |
1429 | return ov7670_s_hflip(sd, ctrl->value); | |
81898671 JC |
1430 | case V4L2_CID_GAIN: |
1431 | return ov7670_s_gain(sd, ctrl->value); | |
1432 | case V4L2_CID_AUTOGAIN: | |
1433 | return ov7670_s_autogain(sd, ctrl->value); | |
364e9337 JC |
1434 | case V4L2_CID_EXPOSURE: |
1435 | return ov7670_s_exp(sd, ctrl->value); | |
1436 | case V4L2_CID_EXPOSURE_AUTO: | |
1437 | return ov7670_s_autoexp(sd, | |
1438 | (enum v4l2_exposure_auto_type) ctrl->value); | |
ca07561a HV |
1439 | } |
1440 | return -EINVAL; | |
111f3356 JC |
1441 | } |
1442 | ||
14386c2b HV |
1443 | static int ov7670_g_chip_ident(struct v4l2_subdev *sd, |
1444 | struct v4l2_dbg_chip_ident *chip) | |
1445 | { | |
1446 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1447 | ||
1448 | return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_OV7670, 0); | |
1449 | } | |
1450 | ||
b794aabf HV |
1451 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1452 | static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1453 | { | |
1454 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1455 | unsigned char val = 0; | |
1456 | int ret; | |
1457 | ||
1458 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1459 | return -EINVAL; | |
1460 | if (!capable(CAP_SYS_ADMIN)) | |
1461 | return -EPERM; | |
1462 | ret = ov7670_read(sd, reg->reg & 0xff, &val); | |
1463 | reg->val = val; | |
1464 | reg->size = 1; | |
1465 | return ret; | |
1466 | } | |
1467 | ||
1468 | static int ov7670_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) | |
1469 | { | |
1470 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
1471 | ||
1472 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
1473 | return -EINVAL; | |
1474 | if (!capable(CAP_SYS_ADMIN)) | |
1475 | return -EPERM; | |
1476 | ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff); | |
1477 | return 0; | |
1478 | } | |
1479 | #endif | |
1480 | ||
14386c2b | 1481 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1482 | |
14386c2b HV |
1483 | static const struct v4l2_subdev_core_ops ov7670_core_ops = { |
1484 | .g_chip_ident = ov7670_g_chip_ident, | |
1485 | .g_ctrl = ov7670_g_ctrl, | |
1486 | .s_ctrl = ov7670_s_ctrl, | |
1487 | .queryctrl = ov7670_queryctrl, | |
1488 | .reset = ov7670_reset, | |
1489 | .init = ov7670_init, | |
b794aabf HV |
1490 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1491 | .g_register = ov7670_g_register, | |
1492 | .s_register = ov7670_s_register, | |
1493 | #endif | |
14386c2b | 1494 | }; |
111f3356 | 1495 | |
14386c2b | 1496 | static const struct v4l2_subdev_video_ops ov7670_video_ops = { |
959f3bda HV |
1497 | .enum_mbus_fmt = ov7670_enum_mbus_fmt, |
1498 | .try_mbus_fmt = ov7670_try_mbus_fmt, | |
1499 | .s_mbus_fmt = ov7670_s_mbus_fmt, | |
14386c2b HV |
1500 | .s_parm = ov7670_s_parm, |
1501 | .g_parm = ov7670_g_parm, | |
e99dfcf7 | 1502 | .enum_frameintervals = ov7670_enum_frameintervals, |
b0326b7f | 1503 | .enum_framesizes = ov7670_enum_framesizes, |
14386c2b | 1504 | }; |
111f3356 | 1505 | |
14386c2b HV |
1506 | static const struct v4l2_subdev_ops ov7670_ops = { |
1507 | .core = &ov7670_core_ops, | |
1508 | .video = &ov7670_video_ops, | |
1509 | }; | |
111f3356 | 1510 | |
14386c2b | 1511 | /* ----------------------------------------------------------------------- */ |
111f3356 | 1512 | |
14386c2b HV |
1513 | static int ov7670_probe(struct i2c_client *client, |
1514 | const struct i2c_device_id *id) | |
111f3356 | 1515 | { |
14386c2b | 1516 | struct v4l2_subdev *sd; |
f9a76156 | 1517 | struct ov7670_info *info; |
3c7c9370 | 1518 | int ret; |
111f3356 | 1519 | |
14386c2b HV |
1520 | info = kzalloc(sizeof(struct ov7670_info), GFP_KERNEL); |
1521 | if (info == NULL) | |
111f3356 | 1522 | return -ENOMEM; |
14386c2b HV |
1523 | sd = &info->sd; |
1524 | v4l2_i2c_subdev_init(sd, client, &ov7670_ops); | |
1525 | ||
3c7c9370 HV |
1526 | info->clock_speed = 30; /* default: a guess */ |
1527 | if (client->dev.platform_data) { | |
1528 | struct ov7670_config *config = client->dev.platform_data; | |
1529 | ||
1530 | /* | |
1531 | * Must apply configuration before initializing device, because it | |
1532 | * selects I/O method. | |
1533 | */ | |
1534 | info->min_width = config->min_width; | |
1535 | info->min_height = config->min_height; | |
1536 | info->use_smbus = config->use_smbus; | |
1537 | ||
1538 | if (config->clock_speed) | |
1539 | info->clock_speed = config->clock_speed; | |
1540 | } | |
1541 | ||
1542 | /* Make sure it's an ov7670 */ | |
1543 | ret = ov7670_detect(sd); | |
1544 | if (ret) { | |
1545 | v4l_dbg(1, debug, client, | |
1546 | "chip found @ 0x%x (%s) is not an ov7670 chip.\n", | |
1547 | client->addr << 1, client->adapter->name); | |
1548 | kfree(info); | |
1549 | return ret; | |
1550 | } | |
1551 | v4l_info(client, "chip found @ 0x%02x (%s)\n", | |
1552 | client->addr << 1, client->adapter->name); | |
1553 | ||
1554 | info->fmt = &ov7670_formats[0]; | |
1555 | info->sat = 128; /* Review this */ | |
1556 | info->clkrc = info->clock_speed / 30; | |
111f3356 | 1557 | return 0; |
111f3356 JC |
1558 | } |
1559 | ||
1560 | ||
14386c2b | 1561 | static int ov7670_remove(struct i2c_client *client) |
111f3356 | 1562 | { |
14386c2b | 1563 | struct v4l2_subdev *sd = i2c_get_clientdata(client); |
111f3356 | 1564 | |
14386c2b HV |
1565 | v4l2_device_unregister_subdev(sd); |
1566 | kfree(to_state(sd)); | |
1567 | return 0; | |
111f3356 JC |
1568 | } |
1569 | ||
14386c2b HV |
1570 | static const struct i2c_device_id ov7670_id[] = { |
1571 | { "ov7670", 0 }, | |
1572 | { } | |
1573 | }; | |
1574 | MODULE_DEVICE_TABLE(i2c, ov7670_id); | |
1575 | ||
ef2ac770 HV |
1576 | static struct i2c_driver ov7670_driver = { |
1577 | .driver = { | |
1578 | .owner = THIS_MODULE, | |
1579 | .name = "ov7670", | |
1580 | }, | |
1581 | .probe = ov7670_probe, | |
1582 | .remove = ov7670_remove, | |
1583 | .id_table = ov7670_id, | |
111f3356 | 1584 | }; |
ef2ac770 | 1585 | |
c6e8d86f | 1586 | module_i2c_driver(ov7670_driver); |