[media] soc-camera: Add and use soc_camera_power_[on|off]() helper functions
[deliverable/linux.git] / drivers / media / i2c / soc_camera / mt9m111.c
CommitLineData
77110abb 1/*
c8cf078e 2 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
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3 *
4 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/videodev2.h>
11#include <linux/slab.h>
12#include <linux/i2c.h>
13#include <linux/log2.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
95d20109 16#include <linux/v4l2-mediabus.h>
7a707b89 17#include <linux/module.h>
77110abb 18
0c0b446d 19#include <media/soc_camera.h>
77110abb 20#include <media/v4l2-common.h>
af8425c5 21#include <media/v4l2-ctrls.h>
77110abb 22#include <media/v4l2-chip-ident.h>
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23
24/*
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25 * MT9M111, MT9M112 and MT9M131:
26 * i2c address is 0x48 or 0x5d (depending on SADDR pin)
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27 * The platform has to define i2c_board_info and call i2c_register_board_info()
28 */
29
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30/*
31 * Sensor core register addresses (0x000..0x0ff)
32 */
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33#define MT9M111_CHIP_VERSION 0x000
34#define MT9M111_ROW_START 0x001
35#define MT9M111_COLUMN_START 0x002
36#define MT9M111_WINDOW_HEIGHT 0x003
37#define MT9M111_WINDOW_WIDTH 0x004
38#define MT9M111_HORIZONTAL_BLANKING_B 0x005
39#define MT9M111_VERTICAL_BLANKING_B 0x006
40#define MT9M111_HORIZONTAL_BLANKING_A 0x007
41#define MT9M111_VERTICAL_BLANKING_A 0x008
42#define MT9M111_SHUTTER_WIDTH 0x009
43#define MT9M111_ROW_SPEED 0x00a
44#define MT9M111_EXTRA_DELAY 0x00b
45#define MT9M111_SHUTTER_DELAY 0x00c
46#define MT9M111_RESET 0x00d
47#define MT9M111_READ_MODE_B 0x020
48#define MT9M111_READ_MODE_A 0x021
49#define MT9M111_FLASH_CONTROL 0x023
50#define MT9M111_GREEN1_GAIN 0x02b
51#define MT9M111_BLUE_GAIN 0x02c
52#define MT9M111_RED_GAIN 0x02d
53#define MT9M111_GREEN2_GAIN 0x02e
54#define MT9M111_GLOBAL_GAIN 0x02f
55#define MT9M111_CONTEXT_CONTROL 0x0c8
56#define MT9M111_PAGE_MAP 0x0f0
57#define MT9M111_BYTE_WISE_ADDR 0x0f1
58
59#define MT9M111_RESET_SYNC_CHANGES (1 << 15)
60#define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
61#define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
62#define MT9M111_RESET_RESET_SOC (1 << 5)
63#define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
64#define MT9M111_RESET_CHIP_ENABLE (1 << 3)
65#define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
66#define MT9M111_RESET_RESTART_FRAME (1 << 1)
67#define MT9M111_RESET_RESET_MODE (1 << 0)
68
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69#define MT9M111_RM_FULL_POWER_RD (0 << 10)
70#define MT9M111_RM_LOW_POWER_RD (1 << 10)
71#define MT9M111_RM_COL_SKIP_4X (1 << 5)
72#define MT9M111_RM_ROW_SKIP_4X (1 << 4)
73#define MT9M111_RM_COL_SKIP_2X (1 << 3)
74#define MT9M111_RM_ROW_SKIP_2X (1 << 2)
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75#define MT9M111_RMB_MIRROR_COLS (1 << 1)
76#define MT9M111_RMB_MIRROR_ROWS (1 << 0)
77#define MT9M111_CTXT_CTRL_RESTART (1 << 15)
78#define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
79#define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
80#define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
81#define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
82#define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
83#define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
84#define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
85#define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
86#define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
c8cf078e 87
77110abb 88/*
c8cf078e 89 * Colorpipe register addresses (0x100..0x1ff)
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90 */
91#define MT9M111_OPER_MODE_CTRL 0x106
92#define MT9M111_OUTPUT_FORMAT_CTRL 0x108
93#define MT9M111_REDUCER_XZOOM_B 0x1a0
94#define MT9M111_REDUCER_XSIZE_B 0x1a1
95#define MT9M111_REDUCER_YZOOM_B 0x1a3
96#define MT9M111_REDUCER_YSIZE_B 0x1a4
97#define MT9M111_REDUCER_XZOOM_A 0x1a6
98#define MT9M111_REDUCER_XSIZE_A 0x1a7
99#define MT9M111_REDUCER_YZOOM_A 0x1a9
100#define MT9M111_REDUCER_YSIZE_A 0x1aa
101
102#define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
103#define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
104
105#define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
39bf372f 106#define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
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107#define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
108#define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
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109#define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
110#define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
111#define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
112#define MT9M111_OUTFMT_RGB (1 << 8)
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113#define MT9M111_OUTFMT_RGB565 (0 << 6)
114#define MT9M111_OUTFMT_RGB555 (1 << 6)
115#define MT9M111_OUTFMT_RGB444x (2 << 6)
116#define MT9M111_OUTFMT_RGBx444 (3 << 6)
117#define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
118#define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
119#define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
120#define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
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121#define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
122#define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
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123#define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
124#define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
c8cf078e 125
77110abb 126/*
c8cf078e 127 * Camera control register addresses (0x200..0x2ff not implemented)
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128 */
129
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130#define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
131#define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
132#define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
133#define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
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134#define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
135 (val), (mask))
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136
137#define MT9M111_MIN_DARK_ROWS 8
669470a8 138#define MT9M111_MIN_DARK_COLS 26
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139#define MT9M111_MAX_HEIGHT 1024
140#define MT9M111_MAX_WIDTH 1280
141
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142struct mt9m111_context {
143 u16 read_mode;
144 u16 blanking_h;
145 u16 blanking_v;
146 u16 reducer_xzoom;
147 u16 reducer_yzoom;
148 u16 reducer_xsize;
149 u16 reducer_ysize;
150 u16 output_fmt_ctrl2;
151 u16 control;
152};
153
154static struct mt9m111_context context_a = {
155 .read_mode = MT9M111_READ_MODE_A,
156 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
157 .blanking_v = MT9M111_VERTICAL_BLANKING_A,
158 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
159 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
160 .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
161 .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
162 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
163 .control = MT9M111_CTXT_CTRL_RESTART,
164};
165
166static struct mt9m111_context context_b = {
167 .read_mode = MT9M111_READ_MODE_B,
168 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
169 .blanking_v = MT9M111_VERTICAL_BLANKING_B,
170 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
171 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
172 .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
173 .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
174 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
175 .control = MT9M111_CTXT_CTRL_RESTART |
176 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
177 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
178 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
179 MT9M111_CTXT_CTRL_HBLANK_SEL_B,
180};
181
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182/* MT9M111 has only one fixed colorspace per pixelcode */
183struct mt9m111_datafmt {
184 enum v4l2_mbus_pixelcode code;
185 enum v4l2_colorspace colorspace;
186};
187
760697be 188static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
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189 {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
190 {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
191 {V4L2_MBUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG},
192 {V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG},
760697be 193 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
7c58e7d0 194 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
760697be 195 {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
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196 {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
197 {V4L2_MBUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
198 {V4L2_MBUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
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199 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
200 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
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201};
202
77110abb 203struct mt9m111 {
979ea1dd 204 struct v4l2_subdev subdev;
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205 struct v4l2_ctrl_handler hdl;
206 struct v4l2_ctrl *gain;
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207 int model; /* V4L2_IDENT_MT9M111 or V4L2_IDENT_MT9M112 code
208 * from v4l2-chip-ident.h */
47921932 209 struct mt9m111_context *ctx;
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210 struct v4l2_rect rect; /* cropping rectangle */
211 int width; /* output */
212 int height; /* sizes */
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213 struct mutex power_lock; /* lock to protect power_count */
214 int power_count;
760697be 215 const struct mt9m111_datafmt *fmt;
096b703f 216 int lastpage; /* PageMap cache value */
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217};
218
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219/* Find a data format by a pixel code */
220static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111,
221 enum v4l2_mbus_pixelcode code)
222{
223 int i;
224 for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++)
225 if (mt9m111_colour_fmts[i].code == code)
226 return mt9m111_colour_fmts + i;
227
228 return mt9m111->fmt;
229}
230
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231static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
232{
233 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
234}
235
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236static int reg_page_map_set(struct i2c_client *client, const u16 reg)
237{
238 int ret;
239 u16 page;
096b703f 240 struct mt9m111 *mt9m111 = to_mt9m111(client);
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241
242 page = (reg >> 8);
096b703f 243 if (page == mt9m111->lastpage)
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244 return 0;
245 if (page > 2)
246 return -EINVAL;
247
3f877045 248 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
506c629a 249 if (!ret)
096b703f 250 mt9m111->lastpage = page;
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251 return ret;
252}
253
9538e1c2 254static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
77110abb 255{
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256 int ret;
257
258 ret = reg_page_map_set(client, reg);
259 if (!ret)
3f877045 260 ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
77110abb 261
9538e1c2 262 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
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263 return ret;
264}
265
9538e1c2 266static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
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267 const u16 data)
268{
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269 int ret;
270
271 ret = reg_page_map_set(client, reg);
506c629a 272 if (!ret)
3f877045 273 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
9538e1c2 274 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
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275 return ret;
276}
277
9538e1c2 278static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
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279 const u16 data)
280{
281 int ret;
282
9538e1c2 283 ret = mt9m111_reg_read(client, reg);
77110abb 284 if (ret >= 0)
9538e1c2 285 ret = mt9m111_reg_write(client, reg, ret | data);
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286 return ret;
287}
288
9538e1c2 289static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
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290 const u16 data)
291{
292 int ret;
293
9538e1c2 294 ret = mt9m111_reg_read(client, reg);
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295 if (ret >= 0)
296 ret = mt9m111_reg_write(client, reg, ret & ~data);
297 return ret;
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298}
299
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300static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
301 const u16 data, const u16 mask)
302{
303 int ret;
304
305 ret = mt9m111_reg_read(client, reg);
306 if (ret >= 0)
307 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
308 return ret;
309}
310
2768cbbb 311static int mt9m111_set_context(struct mt9m111 *mt9m111,
47921932 312 struct mt9m111_context *ctx)
77110abb 313{
2768cbbb 314 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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315 return reg_write(CONTEXT_CONTROL, ctx->control);
316}
317
318static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
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319 struct mt9m111_context *ctx, struct v4l2_rect *rect,
320 unsigned int width, unsigned int height)
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321{
322 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
da673e60 323 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width);
47921932 324 if (!ret)
da673e60 325 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height);
47921932 326 if (!ret)
da673e60 327 ret = mt9m111_reg_write(client, ctx->reducer_xsize, width);
47921932 328 if (!ret)
da673e60 329 ret = mt9m111_reg_write(client, ctx->reducer_ysize, height);
47921932 330 return ret;
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331}
332
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333static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect,
334 int width, int height, enum v4l2_mbus_pixelcode code)
77110abb 335{
2768cbbb 336 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
47921932 337 int ret;
77110abb 338
09e231b3 339 ret = reg_write(COLUMN_START, rect->left);
506c629a 340 if (!ret)
09e231b3 341 ret = reg_write(ROW_START, rect->top);
77110abb 342
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343 if (!ret)
344 ret = reg_write(WINDOW_WIDTH, rect->width);
345 if (!ret)
346 ret = reg_write(WINDOW_HEIGHT, rect->height);
347
348 if (code != V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
349 /* IFP in use, down-scaling possible */
506c629a 350 if (!ret)
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351 ret = mt9m111_setup_rect_ctx(mt9m111, &context_b,
352 rect, width, height);
506c629a 353 if (!ret)
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354 ret = mt9m111_setup_rect_ctx(mt9m111, &context_a,
355 rect, width, height);
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356 }
357
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358 dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n",
359 __func__, code, rect->width, rect->height, rect->left, rect->top,
360 width, height, ret);
361
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362 return ret;
363}
364
2768cbbb 365static int mt9m111_enable(struct mt9m111 *mt9m111)
77110abb 366{
2768cbbb 367 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
a650bf1e 368 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
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369}
370
2768cbbb 371static int mt9m111_reset(struct mt9m111 *mt9m111)
77110abb 372{
2768cbbb 373 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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374 int ret;
375
376 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
506c629a 377 if (!ret)
77110abb 378 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
506c629a 379 if (!ret)
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380 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
381 | MT9M111_RESET_RESET_SOC);
afb13683 382
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383 return ret;
384}
385
da673e60 386static int mt9m111_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
6a6c8786 387{
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388 struct v4l2_rect rect = a->c;
389 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
390 int width, height;
391 int ret;
392
393 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
394 return -EINVAL;
395
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396 if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
397 mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
6a6c8786 398 /* Bayer format - even size lengths */
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399 rect.width = ALIGN(rect.width, 2);
400 rect.height = ALIGN(rect.height, 2);
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401 /* Let the user play with the starting pixel */
402 }
403
404 /* FIXME: the datasheet doesn't specify minimum sizes */
da673e60 405 soc_camera_limit_side(&rect.left, &rect.width,
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406 MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH);
407
da673e60 408 soc_camera_limit_side(&rect.top, &rect.height,
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409 MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT);
410
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411 width = min(mt9m111->width, rect.width);
412 height = min(mt9m111->height, rect.height);
09e231b3 413
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414 ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code);
415 if (!ret) {
6a6c8786 416 mt9m111->rect = rect;
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417 mt9m111->width = width;
418 mt9m111->height = height;
419 }
420
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421 return ret;
422}
423
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424static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
425{
2768cbbb 426 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
6a6c8786
GL
427
428 a->c = mt9m111->rect;
429 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
430
431 return 0;
432}
433
434static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
435{
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436 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
437 return -EINVAL;
438
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439 a->bounds.left = MT9M111_MIN_DARK_COLS;
440 a->bounds.top = MT9M111_MIN_DARK_ROWS;
441 a->bounds.width = MT9M111_MAX_WIDTH;
442 a->bounds.height = MT9M111_MAX_HEIGHT;
443 a->defrect = a->bounds;
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444 a->pixelaspect.numerator = 1;
445 a->pixelaspect.denominator = 1;
446
447 return 0;
448}
449
760697be
GL
450static int mt9m111_g_fmt(struct v4l2_subdev *sd,
451 struct v4l2_mbus_framefmt *mf)
6a6c8786 452{
2768cbbb 453 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
6a6c8786 454
da673e60
GL
455 mf->width = mt9m111->width;
456 mf->height = mt9m111->height;
760697be 457 mf->code = mt9m111->fmt->code;
01f5a394 458 mf->colorspace = mt9m111->fmt->colorspace;
760697be 459 mf->field = V4L2_FIELD_NONE;
6a6c8786
GL
460
461 return 0;
462}
463
2768cbbb 464static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
760697be 465 enum v4l2_mbus_pixelcode code)
77110abb 466{
7c58e7d0
MG
467 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
468 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
469 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
470 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
471 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
472 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
473 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
506c629a 474 int ret;
77110abb 475
760697be
GL
476 switch (code) {
477 case V4L2_MBUS_FMT_SBGGR8_1X8:
7c58e7d0
MG
478 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
479 MT9M111_OUTFMT_RGB;
77110abb 480 break;
760697be 481 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
7c58e7d0 482 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
77110abb 483 break;
760697be 484 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
7c58e7d0
MG
485 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
486 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
487 break;
488 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
489 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
77110abb 490 break;
760697be 491 case V4L2_MBUS_FMT_RGB565_2X8_LE:
7c58e7d0
MG
492 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
493 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
494 break;
495 case V4L2_MBUS_FMT_RGB565_2X8_BE:
496 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
497 break;
498 case V4L2_MBUS_FMT_BGR565_2X8_BE:
499 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
500 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
501 break;
502 case V4L2_MBUS_FMT_BGR565_2X8_LE:
503 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
504 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
505 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb 506 break;
ace6e979 507 case V4L2_MBUS_FMT_UYVY8_2X8:
7c58e7d0 508 data_outfmt2 = 0;
88f4b899 509 break;
ace6e979 510 case V4L2_MBUS_FMT_VYUY8_2X8:
7c58e7d0 511 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
88f4b899 512 break;
ace6e979 513 case V4L2_MBUS_FMT_YUYV8_2X8:
7c58e7d0 514 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
88f4b899 515 break;
ace6e979 516 case V4L2_MBUS_FMT_YVYU8_2X8:
7c58e7d0
MG
517 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
518 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb
RJ
519 break;
520 default:
7c58e7d0
MG
521 dev_err(&client->dev, "Pixel format not handled: %x\n", code);
522 return -EINVAL;
77110abb
RJ
523 }
524
47921932
GL
525 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
526 data_outfmt2, mask_outfmt2);
7c58e7d0 527 if (!ret)
47921932
GL
528 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
529 data_outfmt2, mask_outfmt2);
7c58e7d0 530
77110abb
RJ
531 return ret;
532}
533
760697be
GL
534static int mt9m111_try_fmt(struct v4l2_subdev *sd,
535 struct v4l2_mbus_framefmt *mf)
77110abb 536{
da673e60 537 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 538 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
760697be 539 const struct mt9m111_datafmt *fmt;
da673e60
GL
540 struct v4l2_rect *rect = &mt9m111->rect;
541 bool bayer;
542
543 fmt = mt9m111_find_datafmt(mt9m111, mf->code);
544
545 bayer = fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
546 fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE;
6a6c8786
GL
547
548 /*
549 * With Bayer format enforce even side lengths, but let the user play
550 * with the starting pixel
551 */
da673e60
GL
552 if (bayer) {
553 rect->width = ALIGN(rect->width, 2);
554 rect->height = ALIGN(rect->height, 2);
555 }
64f5905e 556
da673e60
GL
557 if (fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
558 /* IFP bypass mode, no scaling */
559 mf->width = rect->width;
560 mf->height = rect->height;
561 } else {
562 /* No upscaling */
563 if (mf->width > rect->width)
564 mf->width = rect->width;
565 if (mf->height > rect->height)
566 mf->height = rect->height;
567 }
6a6c8786 568
da673e60
GL
569 dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__,
570 mf->width, mf->height, fmt->code);
760697be 571
da673e60 572 mf->code = fmt->code;
760697be 573 mf->colorspace = fmt->colorspace;
77110abb
RJ
574
575 return 0;
576}
577
da673e60
GL
578static int mt9m111_s_fmt(struct v4l2_subdev *sd,
579 struct v4l2_mbus_framefmt *mf)
580{
581 const struct mt9m111_datafmt *fmt;
582 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
583 struct v4l2_rect *rect = &mt9m111->rect;
584 int ret;
585
586 mt9m111_try_fmt(sd, mf);
587 fmt = mt9m111_find_datafmt(mt9m111, mf->code);
588 /* try_fmt() guarantees fmt != NULL && fmt->code == mf->code */
589
590 ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code);
591 if (!ret)
592 ret = mt9m111_set_pixfmt(mt9m111, mf->code);
593 if (!ret) {
594 mt9m111->width = mf->width;
595 mt9m111->height = mf->height;
596 mt9m111->fmt = fmt;
597 }
598
599 return ret;
600}
601
979ea1dd
GL
602static int mt9m111_g_chip_ident(struct v4l2_subdev *sd,
603 struct v4l2_dbg_chip_ident *id)
77110abb 604{
c4ce6d14 605 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 606 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
77110abb 607
aecde8b5 608 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
77110abb
RJ
609 return -EINVAL;
610
40e2e092 611 if (id->match.addr != client->addr)
77110abb
RJ
612 return -ENODEV;
613
614 id->ident = mt9m111->model;
615 id->revision = 0;
616
617 return 0;
618}
619
620#ifdef CONFIG_VIDEO_ADV_DEBUG
979ea1dd
GL
621static int mt9m111_g_register(struct v4l2_subdev *sd,
622 struct v4l2_dbg_register *reg)
77110abb 623{
c4ce6d14 624 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 625 int val;
77110abb 626
aecde8b5 627 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
77110abb 628 return -EINVAL;
9538e1c2 629 if (reg->match.addr != client->addr)
77110abb
RJ
630 return -ENODEV;
631
9538e1c2 632 val = mt9m111_reg_read(client, reg->reg);
aecde8b5 633 reg->size = 2;
77110abb
RJ
634 reg->val = (u64)val;
635
636 if (reg->val > 0xffff)
637 return -EIO;
638
639 return 0;
640}
641
979ea1dd
GL
642static int mt9m111_s_register(struct v4l2_subdev *sd,
643 struct v4l2_dbg_register *reg)
77110abb 644{
c4ce6d14 645 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 646
aecde8b5 647 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
77110abb
RJ
648 return -EINVAL;
649
9538e1c2 650 if (reg->match.addr != client->addr)
77110abb
RJ
651 return -ENODEV;
652
9538e1c2 653 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
77110abb
RJ
654 return -EIO;
655
656 return 0;
657}
658#endif
659
2768cbbb 660static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
77110abb 661{
2768cbbb 662 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
663 int ret;
664
47921932
GL
665 if (flip)
666 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
667 else
668 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
77110abb
RJ
669
670 return ret;
671}
672
2768cbbb 673static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
77110abb 674{
2768cbbb 675 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
0f28b793 676 int data;
77110abb
RJ
677
678 data = reg_read(GLOBAL_GAIN);
679 if (data >= 0)
0f28b793 680 return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
681 (1 << ((data >> 9) & 1));
682 return data;
77110abb 683}
0f28b793 684
2768cbbb 685static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
77110abb 686{
2768cbbb 687 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
688 u16 val;
689
690 if (gain > 63 * 2 * 2)
691 return -EINVAL;
692
77110abb
RJ
693 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
694 val = (1 << 10) | (1 << 9) | (gain / 4);
695 else if ((gain >= 64) && (gain < 64 * 2))
506c629a 696 val = (1 << 9) | (gain / 2);
77110abb
RJ
697 else
698 val = gain;
699
700 return reg_write(GLOBAL_GAIN, val);
701}
702
2768cbbb 703static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int on)
77110abb 704{
2768cbbb 705 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
706
707 if (on)
af8425c5
HV
708 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
709 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
77110abb 710}
39bf372f 711
2768cbbb 712static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
39bf372f 713{
2768cbbb 714 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
39bf372f
RJ
715
716 if (on)
af8425c5
HV
717 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
718 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
39bf372f
RJ
719}
720
af8425c5 721static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
77110abb 722{
af8425c5
HV
723 struct mt9m111 *mt9m111 = container_of(ctrl->handler,
724 struct mt9m111, hdl);
77110abb
RJ
725
726 switch (ctrl->id) {
727 case V4L2_CID_VFLIP:
af8425c5 728 return mt9m111_set_flip(mt9m111, ctrl->val,
77110abb 729 MT9M111_RMB_MIRROR_ROWS);
77110abb 730 case V4L2_CID_HFLIP:
af8425c5 731 return mt9m111_set_flip(mt9m111, ctrl->val,
77110abb 732 MT9M111_RMB_MIRROR_COLS);
77110abb 733 case V4L2_CID_GAIN:
af8425c5 734 return mt9m111_set_global_gain(mt9m111, ctrl->val);
77110abb 735 case V4L2_CID_EXPOSURE_AUTO:
af8425c5 736 return mt9m111_set_autoexposure(mt9m111, ctrl->val);
39bf372f 737 case V4L2_CID_AUTO_WHITE_BALANCE:
af8425c5 738 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
77110abb
RJ
739 }
740
af8425c5 741 return -EINVAL;
77110abb
RJ
742}
743
14c5ea9b 744static int mt9m111_suspend(struct mt9m111 *mt9m111)
96c75399 745{
a650bf1e
GL
746 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
747 int ret;
748
af8425c5 749 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
96c75399 750
a650bf1e
GL
751 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
752 if (!ret)
753 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
754 MT9M111_RESET_OUTPUT_DISABLE |
755 MT9M111_RESET_ANALOG_STANDBY);
756 if (!ret)
757 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
758
759 return ret;
96c75399
GL
760}
761
2768cbbb 762static void mt9m111_restore_state(struct mt9m111 *mt9m111)
77110abb 763{
47921932 764 mt9m111_set_context(mt9m111, mt9m111->ctx);
2768cbbb 765 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
da673e60
GL
766 mt9m111_setup_geometry(mt9m111, &mt9m111->rect,
767 mt9m111->width, mt9m111->height, mt9m111->fmt->code);
af8425c5 768 v4l2_ctrl_handler_setup(&mt9m111->hdl);
77110abb
RJ
769}
770
14c5ea9b 771static int mt9m111_resume(struct mt9m111 *mt9m111)
77110abb 772{
a650bf1e
GL
773 int ret = mt9m111_enable(mt9m111);
774 if (!ret)
775 ret = mt9m111_reset(mt9m111);
776 if (!ret)
777 mt9m111_restore_state(mt9m111);
77110abb 778
77110abb
RJ
779 return ret;
780}
781
2768cbbb 782static int mt9m111_init(struct mt9m111 *mt9m111)
77110abb 783{
2768cbbb 784 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
785 int ret;
786
47921932
GL
787 /* Default HIGHPOWER context */
788 mt9m111->ctx = &context_b;
2768cbbb 789 ret = mt9m111_enable(mt9m111);
506c629a 790 if (!ret)
2768cbbb 791 ret = mt9m111_reset(mt9m111);
506c629a 792 if (!ret)
47921932 793 ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
506c629a 794 if (ret)
c8cf078e 795 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
506c629a 796 return ret;
77110abb
RJ
797}
798
77110abb
RJ
799/*
800 * Interface active, can use i2c. If it fails, it can indeed mean, that
801 * this wasn't our capture interface, so, we wait for the right one
802 */
14178aa5 803static int mt9m111_video_probe(struct i2c_client *client)
77110abb 804{
979ea1dd 805 struct mt9m111 *mt9m111 = to_mt9m111(client);
77110abb
RJ
806 s32 data;
807 int ret;
808
77110abb
RJ
809 data = reg_read(CHIP_VERSION);
810
811 switch (data) {
c8cf078e 812 case 0x143a: /* MT9M111 or MT9M131 */
77110abb 813 mt9m111->model = V4L2_IDENT_MT9M111;
c8cf078e
PW
814 dev_info(&client->dev,
815 "Detected a MT9M111/MT9M131 chip ID %x\n", data);
d7f83a51
MR
816 break;
817 case 0x148c: /* MT9M112 */
818 mt9m111->model = V4L2_IDENT_MT9M112;
c8cf078e 819 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
77110abb
RJ
820 break;
821 default:
85f8be68 822 dev_err(&client->dev,
c8cf078e
PW
823 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
824 data);
af8425c5 825 return -ENODEV;
77110abb
RJ
826 }
827
2768cbbb 828 ret = mt9m111_init(mt9m111);
af8425c5
HV
829 if (ret)
830 return ret;
831 return v4l2_ctrl_handler_setup(&mt9m111->hdl);
77110abb
RJ
832}
833
4ec10bac
LP
834static int mt9m111_power_on(struct mt9m111 *mt9m111)
835{
836 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
837 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
838 int ret;
839
840 ret = soc_camera_power_on(&client->dev, icl);
841 if (ret < 0)
842 return ret;
843
844 ret = mt9m111_resume(mt9m111);
845 if (ret < 0) {
846 dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret);
847 soc_camera_power_off(&client->dev, icl);
848 }
849
850 return ret;
851}
852
853static void mt9m111_power_off(struct mt9m111 *mt9m111)
854{
855 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
856 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
857
858 mt9m111_suspend(mt9m111);
859 soc_camera_power_off(&client->dev, icl);
860}
861
14c5ea9b
GL
862static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
863{
864 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
14c5ea9b
GL
865 int ret = 0;
866
867 mutex_lock(&mt9m111->power_lock);
868
869 /*
870 * If the power count is modified from 0 to != 0 or from != 0 to 0,
871 * update the power state.
872 */
873 if (mt9m111->power_count == !on) {
4ec10bac
LP
874 if (on)
875 ret = mt9m111_power_on(mt9m111);
876 else
877 mt9m111_power_off(mt9m111);
14c5ea9b
GL
878 }
879
4ec10bac
LP
880 if (!ret) {
881 /* Update the power count. */
882 mt9m111->power_count += on ? 1 : -1;
883 WARN_ON(mt9m111->power_count < 0);
884 }
14c5ea9b 885
14c5ea9b
GL
886 mutex_unlock(&mt9m111->power_lock);
887 return ret;
888}
889
af8425c5
HV
890static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
891 .s_ctrl = mt9m111_s_ctrl,
892};
893
979ea1dd 894static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
979ea1dd 895 .g_chip_ident = mt9m111_g_chip_ident,
14c5ea9b 896 .s_power = mt9m111_s_power,
979ea1dd
GL
897#ifdef CONFIG_VIDEO_ADV_DEBUG
898 .g_register = mt9m111_g_register,
899 .s_register = mt9m111_s_register,
900#endif
901};
902
3805f201 903static int mt9m111_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
760697be
GL
904 enum v4l2_mbus_pixelcode *code)
905{
3805f201 906 if (index >= ARRAY_SIZE(mt9m111_colour_fmts))
760697be
GL
907 return -EINVAL;
908
909 *code = mt9m111_colour_fmts[index].code;
910 return 0;
911}
912
0c0b446d
GL
913static int mt9m111_g_mbus_config(struct v4l2_subdev *sd,
914 struct v4l2_mbus_config *cfg)
915{
916 struct i2c_client *client = v4l2_get_subdevdata(sd);
14178aa5 917 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
0c0b446d
GL
918
919 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
920 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
921 V4L2_MBUS_DATA_ACTIVE_HIGH;
922 cfg->type = V4L2_MBUS_PARALLEL;
923 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
924
925 return 0;
926}
927
979ea1dd 928static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
760697be
GL
929 .s_mbus_fmt = mt9m111_s_fmt,
930 .g_mbus_fmt = mt9m111_g_fmt,
931 .try_mbus_fmt = mt9m111_try_fmt,
08590b96 932 .s_crop = mt9m111_s_crop,
6a6c8786
GL
933 .g_crop = mt9m111_g_crop,
934 .cropcap = mt9m111_cropcap,
760697be 935 .enum_mbus_fmt = mt9m111_enum_fmt,
0c0b446d 936 .g_mbus_config = mt9m111_g_mbus_config,
979ea1dd
GL
937};
938
939static struct v4l2_subdev_ops mt9m111_subdev_ops = {
940 .core = &mt9m111_subdev_core_ops,
941 .video = &mt9m111_subdev_video_ops,
942};
943
77110abb
RJ
944static int mt9m111_probe(struct i2c_client *client,
945 const struct i2c_device_id *did)
946{
947 struct mt9m111 *mt9m111;
77110abb 948 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
14178aa5 949 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
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950 int ret;
951
952 if (!icl) {
c8cf078e 953 dev_err(&client->dev, "mt9m111: driver needs platform data\n");
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954 return -EINVAL;
955 }
956
957 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
958 dev_warn(&adapter->dev,
959 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
960 return -EIO;
961 }
962
963 mt9m111 = kzalloc(sizeof(struct mt9m111), GFP_KERNEL);
964 if (!mt9m111)
965 return -ENOMEM;
966
979ea1dd 967 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
af8425c5
HV
968 v4l2_ctrl_handler_init(&mt9m111->hdl, 5);
969 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
970 V4L2_CID_VFLIP, 0, 1, 1, 0);
971 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
972 V4L2_CID_HFLIP, 0, 1, 1, 0);
973 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
974 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
975 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
976 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
977 v4l2_ctrl_new_std_menu(&mt9m111->hdl,
978 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
979 V4L2_EXPOSURE_AUTO);
980 mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
981 if (mt9m111->hdl.error) {
982 int err = mt9m111->hdl.error;
77110abb 983
af8425c5
HV
984 kfree(mt9m111);
985 return err;
986 }
77110abb 987
af8425c5 988 /* Second stage probe - when a capture adapter is there */
6a6c8786
GL
989 mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
990 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
991 mt9m111->rect.width = MT9M111_MAX_WIDTH;
992 mt9m111->rect.height = MT9M111_MAX_HEIGHT;
760697be 993 mt9m111->fmt = &mt9m111_colour_fmts[0];
14178aa5 994 mt9m111->lastpage = -1;
6b806e30 995 mutex_init(&mt9m111->power_lock);
6a6c8786 996
14178aa5 997 ret = mt9m111_video_probe(client);
40e2e092 998 if (ret) {
af8425c5 999 v4l2_ctrl_handler_free(&mt9m111->hdl);
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GL
1000 kfree(mt9m111);
1001 }
77110abb 1002
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RJ
1003 return ret;
1004}
1005
1006static int mt9m111_remove(struct i2c_client *client)
1007{
979ea1dd 1008 struct mt9m111 *mt9m111 = to_mt9m111(client);
40e2e092 1009
af8425c5
HV
1010 v4l2_device_unregister_subdev(&mt9m111->subdev);
1011 v4l2_ctrl_handler_free(&mt9m111->hdl);
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RJ
1012 kfree(mt9m111);
1013
1014 return 0;
1015}
1016
1017static const struct i2c_device_id mt9m111_id[] = {
1018 { "mt9m111", 0 },
1019 { }
1020};
1021MODULE_DEVICE_TABLE(i2c, mt9m111_id);
1022
1023static struct i2c_driver mt9m111_i2c_driver = {
1024 .driver = {
1025 .name = "mt9m111",
1026 },
1027 .probe = mt9m111_probe,
1028 .remove = mt9m111_remove,
1029 .id_table = mt9m111_id,
1030};
1031
c6e8d86f 1032module_i2c_driver(mt9m111_i2c_driver);
77110abb 1033
c8cf078e 1034MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
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RJ
1035MODULE_AUTHOR("Robert Jarzmik");
1036MODULE_LICENSE("GPL");
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