[media] V4L2: support asynchronous subdevice registration
[deliverable/linux.git] / drivers / media / i2c / soc_camera / mt9m111.c
CommitLineData
77110abb 1/*
c8cf078e 2 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
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3 *
4 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/videodev2.h>
11#include <linux/slab.h>
12#include <linux/i2c.h>
13#include <linux/log2.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
95d20109 16#include <linux/v4l2-mediabus.h>
7a707b89 17#include <linux/module.h>
77110abb 18
0c0b446d 19#include <media/soc_camera.h>
77110abb 20#include <media/v4l2-common.h>
af8425c5 21#include <media/v4l2-ctrls.h>
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22
23/*
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24 * MT9M111, MT9M112 and MT9M131:
25 * i2c address is 0x48 or 0x5d (depending on SADDR pin)
25a34811
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26 * The platform has to define struct i2c_board_info objects and link to them
27 * from struct soc_camera_host_desc
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28 */
29
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30/*
31 * Sensor core register addresses (0x000..0x0ff)
32 */
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33#define MT9M111_CHIP_VERSION 0x000
34#define MT9M111_ROW_START 0x001
35#define MT9M111_COLUMN_START 0x002
36#define MT9M111_WINDOW_HEIGHT 0x003
37#define MT9M111_WINDOW_WIDTH 0x004
38#define MT9M111_HORIZONTAL_BLANKING_B 0x005
39#define MT9M111_VERTICAL_BLANKING_B 0x006
40#define MT9M111_HORIZONTAL_BLANKING_A 0x007
41#define MT9M111_VERTICAL_BLANKING_A 0x008
42#define MT9M111_SHUTTER_WIDTH 0x009
43#define MT9M111_ROW_SPEED 0x00a
44#define MT9M111_EXTRA_DELAY 0x00b
45#define MT9M111_SHUTTER_DELAY 0x00c
46#define MT9M111_RESET 0x00d
47#define MT9M111_READ_MODE_B 0x020
48#define MT9M111_READ_MODE_A 0x021
49#define MT9M111_FLASH_CONTROL 0x023
50#define MT9M111_GREEN1_GAIN 0x02b
51#define MT9M111_BLUE_GAIN 0x02c
52#define MT9M111_RED_GAIN 0x02d
53#define MT9M111_GREEN2_GAIN 0x02e
54#define MT9M111_GLOBAL_GAIN 0x02f
55#define MT9M111_CONTEXT_CONTROL 0x0c8
56#define MT9M111_PAGE_MAP 0x0f0
57#define MT9M111_BYTE_WISE_ADDR 0x0f1
58
59#define MT9M111_RESET_SYNC_CHANGES (1 << 15)
60#define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
61#define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
62#define MT9M111_RESET_RESET_SOC (1 << 5)
63#define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
64#define MT9M111_RESET_CHIP_ENABLE (1 << 3)
65#define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
66#define MT9M111_RESET_RESTART_FRAME (1 << 1)
67#define MT9M111_RESET_RESET_MODE (1 << 0)
68
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69#define MT9M111_RM_FULL_POWER_RD (0 << 10)
70#define MT9M111_RM_LOW_POWER_RD (1 << 10)
71#define MT9M111_RM_COL_SKIP_4X (1 << 5)
72#define MT9M111_RM_ROW_SKIP_4X (1 << 4)
73#define MT9M111_RM_COL_SKIP_2X (1 << 3)
74#define MT9M111_RM_ROW_SKIP_2X (1 << 2)
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75#define MT9M111_RMB_MIRROR_COLS (1 << 1)
76#define MT9M111_RMB_MIRROR_ROWS (1 << 0)
77#define MT9M111_CTXT_CTRL_RESTART (1 << 15)
78#define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
79#define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
80#define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
81#define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
82#define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
83#define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
84#define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
85#define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
86#define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
c8cf078e 87
77110abb 88/*
c8cf078e 89 * Colorpipe register addresses (0x100..0x1ff)
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90 */
91#define MT9M111_OPER_MODE_CTRL 0x106
92#define MT9M111_OUTPUT_FORMAT_CTRL 0x108
93#define MT9M111_REDUCER_XZOOM_B 0x1a0
94#define MT9M111_REDUCER_XSIZE_B 0x1a1
95#define MT9M111_REDUCER_YZOOM_B 0x1a3
96#define MT9M111_REDUCER_YSIZE_B 0x1a4
97#define MT9M111_REDUCER_XZOOM_A 0x1a6
98#define MT9M111_REDUCER_XSIZE_A 0x1a7
99#define MT9M111_REDUCER_YZOOM_A 0x1a9
100#define MT9M111_REDUCER_YSIZE_A 0x1aa
101
102#define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
103#define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
104
105#define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
39bf372f 106#define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
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107#define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
108#define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
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109#define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
110#define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
111#define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
112#define MT9M111_OUTFMT_RGB (1 << 8)
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113#define MT9M111_OUTFMT_RGB565 (0 << 6)
114#define MT9M111_OUTFMT_RGB555 (1 << 6)
115#define MT9M111_OUTFMT_RGB444x (2 << 6)
116#define MT9M111_OUTFMT_RGBx444 (3 << 6)
117#define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
118#define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
119#define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
120#define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
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121#define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
122#define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
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123#define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
124#define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
c8cf078e 125
77110abb 126/*
c8cf078e 127 * Camera control register addresses (0x200..0x2ff not implemented)
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128 */
129
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130#define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
131#define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
132#define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
133#define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
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134#define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
135 (val), (mask))
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136
137#define MT9M111_MIN_DARK_ROWS 8
669470a8 138#define MT9M111_MIN_DARK_COLS 26
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139#define MT9M111_MAX_HEIGHT 1024
140#define MT9M111_MAX_WIDTH 1280
141
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142struct mt9m111_context {
143 u16 read_mode;
144 u16 blanking_h;
145 u16 blanking_v;
146 u16 reducer_xzoom;
147 u16 reducer_yzoom;
148 u16 reducer_xsize;
149 u16 reducer_ysize;
150 u16 output_fmt_ctrl2;
151 u16 control;
152};
153
154static struct mt9m111_context context_a = {
155 .read_mode = MT9M111_READ_MODE_A,
156 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
157 .blanking_v = MT9M111_VERTICAL_BLANKING_A,
158 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
159 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
160 .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
161 .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
162 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
163 .control = MT9M111_CTXT_CTRL_RESTART,
164};
165
166static struct mt9m111_context context_b = {
167 .read_mode = MT9M111_READ_MODE_B,
168 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
169 .blanking_v = MT9M111_VERTICAL_BLANKING_B,
170 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
171 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
172 .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
173 .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
174 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
175 .control = MT9M111_CTXT_CTRL_RESTART |
176 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
177 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
178 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
179 MT9M111_CTXT_CTRL_HBLANK_SEL_B,
180};
181
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182/* MT9M111 has only one fixed colorspace per pixelcode */
183struct mt9m111_datafmt {
184 enum v4l2_mbus_pixelcode code;
185 enum v4l2_colorspace colorspace;
186};
187
760697be 188static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
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189 {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
190 {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
191 {V4L2_MBUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG},
192 {V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG},
760697be 193 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
7c58e7d0 194 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
760697be 195 {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
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196 {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
197 {V4L2_MBUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
198 {V4L2_MBUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
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199 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
200 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
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201};
202
77110abb 203struct mt9m111 {
979ea1dd 204 struct v4l2_subdev subdev;
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205 struct v4l2_ctrl_handler hdl;
206 struct v4l2_ctrl *gain;
47921932 207 struct mt9m111_context *ctx;
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208 struct v4l2_rect rect; /* cropping rectangle */
209 int width; /* output */
210 int height; /* sizes */
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211 struct mutex power_lock; /* lock to protect power_count */
212 int power_count;
760697be 213 const struct mt9m111_datafmt *fmt;
096b703f 214 int lastpage; /* PageMap cache value */
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215};
216
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217/* Find a data format by a pixel code */
218static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111,
219 enum v4l2_mbus_pixelcode code)
220{
221 int i;
222 for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++)
223 if (mt9m111_colour_fmts[i].code == code)
224 return mt9m111_colour_fmts + i;
225
226 return mt9m111->fmt;
227}
228
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229static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
230{
231 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
232}
233
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234static int reg_page_map_set(struct i2c_client *client, const u16 reg)
235{
236 int ret;
237 u16 page;
096b703f 238 struct mt9m111 *mt9m111 = to_mt9m111(client);
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239
240 page = (reg >> 8);
096b703f 241 if (page == mt9m111->lastpage)
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242 return 0;
243 if (page > 2)
244 return -EINVAL;
245
3f877045 246 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
506c629a 247 if (!ret)
096b703f 248 mt9m111->lastpage = page;
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249 return ret;
250}
251
9538e1c2 252static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
77110abb 253{
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254 int ret;
255
256 ret = reg_page_map_set(client, reg);
257 if (!ret)
3f877045 258 ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
77110abb 259
9538e1c2 260 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
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261 return ret;
262}
263
9538e1c2 264static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
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265 const u16 data)
266{
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267 int ret;
268
269 ret = reg_page_map_set(client, reg);
506c629a 270 if (!ret)
3f877045 271 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
9538e1c2 272 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
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273 return ret;
274}
275
9538e1c2 276static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
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277 const u16 data)
278{
279 int ret;
280
9538e1c2 281 ret = mt9m111_reg_read(client, reg);
77110abb 282 if (ret >= 0)
9538e1c2 283 ret = mt9m111_reg_write(client, reg, ret | data);
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284 return ret;
285}
286
9538e1c2 287static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
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288 const u16 data)
289{
290 int ret;
291
9538e1c2 292 ret = mt9m111_reg_read(client, reg);
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293 if (ret >= 0)
294 ret = mt9m111_reg_write(client, reg, ret & ~data);
295 return ret;
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296}
297
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298static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
299 const u16 data, const u16 mask)
300{
301 int ret;
302
303 ret = mt9m111_reg_read(client, reg);
304 if (ret >= 0)
305 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
306 return ret;
307}
308
2768cbbb 309static int mt9m111_set_context(struct mt9m111 *mt9m111,
47921932 310 struct mt9m111_context *ctx)
77110abb 311{
2768cbbb 312 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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313 return reg_write(CONTEXT_CONTROL, ctx->control);
314}
315
316static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
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317 struct mt9m111_context *ctx, struct v4l2_rect *rect,
318 unsigned int width, unsigned int height)
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319{
320 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
da673e60 321 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width);
47921932 322 if (!ret)
da673e60 323 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height);
47921932 324 if (!ret)
da673e60 325 ret = mt9m111_reg_write(client, ctx->reducer_xsize, width);
47921932 326 if (!ret)
da673e60 327 ret = mt9m111_reg_write(client, ctx->reducer_ysize, height);
47921932 328 return ret;
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329}
330
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331static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect,
332 int width, int height, enum v4l2_mbus_pixelcode code)
77110abb 333{
2768cbbb 334 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
47921932 335 int ret;
77110abb 336
09e231b3 337 ret = reg_write(COLUMN_START, rect->left);
506c629a 338 if (!ret)
09e231b3 339 ret = reg_write(ROW_START, rect->top);
77110abb 340
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341 if (!ret)
342 ret = reg_write(WINDOW_WIDTH, rect->width);
343 if (!ret)
344 ret = reg_write(WINDOW_HEIGHT, rect->height);
345
346 if (code != V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
347 /* IFP in use, down-scaling possible */
506c629a 348 if (!ret)
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349 ret = mt9m111_setup_rect_ctx(mt9m111, &context_b,
350 rect, width, height);
506c629a 351 if (!ret)
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352 ret = mt9m111_setup_rect_ctx(mt9m111, &context_a,
353 rect, width, height);
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354 }
355
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356 dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n",
357 __func__, code, rect->width, rect->height, rect->left, rect->top,
358 width, height, ret);
359
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360 return ret;
361}
362
2768cbbb 363static int mt9m111_enable(struct mt9m111 *mt9m111)
77110abb 364{
2768cbbb 365 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
a650bf1e 366 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
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367}
368
2768cbbb 369static int mt9m111_reset(struct mt9m111 *mt9m111)
77110abb 370{
2768cbbb 371 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
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372 int ret;
373
374 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
506c629a 375 if (!ret)
77110abb 376 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
506c629a 377 if (!ret)
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378 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
379 | MT9M111_RESET_RESET_SOC);
afb13683 380
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381 return ret;
382}
383
4f996594 384static int mt9m111_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
6a6c8786 385{
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386 struct v4l2_rect rect = a->c;
387 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
388 int width, height;
389 int ret;
390
391 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
392 return -EINVAL;
393
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394 if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
395 mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
6a6c8786 396 /* Bayer format - even size lengths */
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397 rect.width = ALIGN(rect.width, 2);
398 rect.height = ALIGN(rect.height, 2);
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399 /* Let the user play with the starting pixel */
400 }
401
402 /* FIXME: the datasheet doesn't specify minimum sizes */
da673e60 403 soc_camera_limit_side(&rect.left, &rect.width,
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404 MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH);
405
da673e60 406 soc_camera_limit_side(&rect.top, &rect.height,
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407 MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT);
408
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409 width = min(mt9m111->width, rect.width);
410 height = min(mt9m111->height, rect.height);
09e231b3 411
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412 ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code);
413 if (!ret) {
6a6c8786 414 mt9m111->rect = rect;
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415 mt9m111->width = width;
416 mt9m111->height = height;
417 }
418
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419 return ret;
420}
421
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422static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
423{
2768cbbb 424 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
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425
426 a->c = mt9m111->rect;
427 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
428
429 return 0;
430}
431
432static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
433{
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434 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
435 return -EINVAL;
436
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437 a->bounds.left = MT9M111_MIN_DARK_COLS;
438 a->bounds.top = MT9M111_MIN_DARK_ROWS;
439 a->bounds.width = MT9M111_MAX_WIDTH;
440 a->bounds.height = MT9M111_MAX_HEIGHT;
441 a->defrect = a->bounds;
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442 a->pixelaspect.numerator = 1;
443 a->pixelaspect.denominator = 1;
444
445 return 0;
446}
447
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448static int mt9m111_g_fmt(struct v4l2_subdev *sd,
449 struct v4l2_mbus_framefmt *mf)
6a6c8786 450{
2768cbbb 451 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
6a6c8786 452
da673e60
GL
453 mf->width = mt9m111->width;
454 mf->height = mt9m111->height;
760697be 455 mf->code = mt9m111->fmt->code;
01f5a394 456 mf->colorspace = mt9m111->fmt->colorspace;
760697be 457 mf->field = V4L2_FIELD_NONE;
6a6c8786
GL
458
459 return 0;
460}
461
2768cbbb 462static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
760697be 463 enum v4l2_mbus_pixelcode code)
77110abb 464{
7c58e7d0
MG
465 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
466 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
467 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
468 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
469 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
470 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
471 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
506c629a 472 int ret;
77110abb 473
760697be
GL
474 switch (code) {
475 case V4L2_MBUS_FMT_SBGGR8_1X8:
7c58e7d0
MG
476 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
477 MT9M111_OUTFMT_RGB;
77110abb 478 break;
760697be 479 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
7c58e7d0 480 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
77110abb 481 break;
760697be 482 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
7c58e7d0
MG
483 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
484 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
485 break;
486 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
487 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
77110abb 488 break;
760697be 489 case V4L2_MBUS_FMT_RGB565_2X8_LE:
7c58e7d0
MG
490 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
491 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
492 break;
493 case V4L2_MBUS_FMT_RGB565_2X8_BE:
494 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
495 break;
496 case V4L2_MBUS_FMT_BGR565_2X8_BE:
497 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
498 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
499 break;
500 case V4L2_MBUS_FMT_BGR565_2X8_LE:
501 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
502 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
503 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb 504 break;
ace6e979 505 case V4L2_MBUS_FMT_UYVY8_2X8:
7c58e7d0 506 data_outfmt2 = 0;
88f4b899 507 break;
ace6e979 508 case V4L2_MBUS_FMT_VYUY8_2X8:
7c58e7d0 509 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
88f4b899 510 break;
ace6e979 511 case V4L2_MBUS_FMT_YUYV8_2X8:
7c58e7d0 512 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
88f4b899 513 break;
ace6e979 514 case V4L2_MBUS_FMT_YVYU8_2X8:
7c58e7d0
MG
515 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
516 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
77110abb
RJ
517 break;
518 default:
7c58e7d0
MG
519 dev_err(&client->dev, "Pixel format not handled: %x\n", code);
520 return -EINVAL;
77110abb
RJ
521 }
522
47921932
GL
523 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
524 data_outfmt2, mask_outfmt2);
7c58e7d0 525 if (!ret)
47921932
GL
526 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
527 data_outfmt2, mask_outfmt2);
7c58e7d0 528
77110abb
RJ
529 return ret;
530}
531
760697be
GL
532static int mt9m111_try_fmt(struct v4l2_subdev *sd,
533 struct v4l2_mbus_framefmt *mf)
77110abb 534{
da673e60 535 struct i2c_client *client = v4l2_get_subdevdata(sd);
2768cbbb 536 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
760697be 537 const struct mt9m111_datafmt *fmt;
da673e60
GL
538 struct v4l2_rect *rect = &mt9m111->rect;
539 bool bayer;
540
541 fmt = mt9m111_find_datafmt(mt9m111, mf->code);
542
543 bayer = fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
544 fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE;
6a6c8786
GL
545
546 /*
547 * With Bayer format enforce even side lengths, but let the user play
548 * with the starting pixel
549 */
da673e60
GL
550 if (bayer) {
551 rect->width = ALIGN(rect->width, 2);
552 rect->height = ALIGN(rect->height, 2);
553 }
64f5905e 554
da673e60
GL
555 if (fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
556 /* IFP bypass mode, no scaling */
557 mf->width = rect->width;
558 mf->height = rect->height;
559 } else {
560 /* No upscaling */
561 if (mf->width > rect->width)
562 mf->width = rect->width;
563 if (mf->height > rect->height)
564 mf->height = rect->height;
565 }
6a6c8786 566
da673e60
GL
567 dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__,
568 mf->width, mf->height, fmt->code);
760697be 569
da673e60 570 mf->code = fmt->code;
760697be 571 mf->colorspace = fmt->colorspace;
77110abb
RJ
572
573 return 0;
574}
575
da673e60
GL
576static int mt9m111_s_fmt(struct v4l2_subdev *sd,
577 struct v4l2_mbus_framefmt *mf)
578{
579 const struct mt9m111_datafmt *fmt;
580 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
581 struct v4l2_rect *rect = &mt9m111->rect;
582 int ret;
583
584 mt9m111_try_fmt(sd, mf);
585 fmt = mt9m111_find_datafmt(mt9m111, mf->code);
586 /* try_fmt() guarantees fmt != NULL && fmt->code == mf->code */
587
588 ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code);
589 if (!ret)
590 ret = mt9m111_set_pixfmt(mt9m111, mf->code);
591 if (!ret) {
592 mt9m111->width = mf->width;
593 mt9m111->height = mf->height;
594 mt9m111->fmt = fmt;
595 }
596
597 return ret;
598}
599
77110abb 600#ifdef CONFIG_VIDEO_ADV_DEBUG
979ea1dd
GL
601static int mt9m111_g_register(struct v4l2_subdev *sd,
602 struct v4l2_dbg_register *reg)
77110abb 603{
c4ce6d14 604 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 605 int val;
77110abb 606
6be89daa 607 if (reg->reg > 0x2ff)
77110abb 608 return -EINVAL;
77110abb 609
9538e1c2 610 val = mt9m111_reg_read(client, reg->reg);
aecde8b5 611 reg->size = 2;
77110abb
RJ
612 reg->val = (u64)val;
613
614 if (reg->val > 0xffff)
615 return -EIO;
616
617 return 0;
618}
619
979ea1dd 620static int mt9m111_s_register(struct v4l2_subdev *sd,
977ba3b1 621 const struct v4l2_dbg_register *reg)
77110abb 622{
c4ce6d14 623 struct i2c_client *client = v4l2_get_subdevdata(sd);
77110abb 624
6be89daa 625 if (reg->reg > 0x2ff)
77110abb
RJ
626 return -EINVAL;
627
9538e1c2 628 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
77110abb
RJ
629 return -EIO;
630
631 return 0;
632}
633#endif
634
2768cbbb 635static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
77110abb 636{
2768cbbb 637 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
638 int ret;
639
47921932
GL
640 if (flip)
641 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
642 else
643 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
77110abb
RJ
644
645 return ret;
646}
647
2768cbbb 648static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
77110abb 649{
2768cbbb 650 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
0f28b793 651 int data;
77110abb
RJ
652
653 data = reg_read(GLOBAL_GAIN);
654 if (data >= 0)
0f28b793 655 return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
656 (1 << ((data >> 9) & 1));
657 return data;
77110abb 658}
0f28b793 659
2768cbbb 660static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
77110abb 661{
2768cbbb 662 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
663 u16 val;
664
665 if (gain > 63 * 2 * 2)
666 return -EINVAL;
667
77110abb
RJ
668 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
669 val = (1 << 10) | (1 << 9) | (gain / 4);
670 else if ((gain >= 64) && (gain < 64 * 2))
506c629a 671 val = (1 << 9) | (gain / 2);
77110abb
RJ
672 else
673 val = gain;
674
675 return reg_write(GLOBAL_GAIN, val);
676}
677
cbaa5c54 678static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int val)
77110abb 679{
2768cbbb 680 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb 681
cbaa5c54 682 if (val == V4L2_EXPOSURE_AUTO)
af8425c5
HV
683 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
684 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
77110abb 685}
39bf372f 686
2768cbbb 687static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
39bf372f 688{
2768cbbb 689 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
39bf372f
RJ
690
691 if (on)
af8425c5
HV
692 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
693 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
39bf372f
RJ
694}
695
af8425c5 696static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
77110abb 697{
af8425c5
HV
698 struct mt9m111 *mt9m111 = container_of(ctrl->handler,
699 struct mt9m111, hdl);
77110abb
RJ
700
701 switch (ctrl->id) {
702 case V4L2_CID_VFLIP:
af8425c5 703 return mt9m111_set_flip(mt9m111, ctrl->val,
77110abb 704 MT9M111_RMB_MIRROR_ROWS);
77110abb 705 case V4L2_CID_HFLIP:
af8425c5 706 return mt9m111_set_flip(mt9m111, ctrl->val,
77110abb 707 MT9M111_RMB_MIRROR_COLS);
77110abb 708 case V4L2_CID_GAIN:
af8425c5 709 return mt9m111_set_global_gain(mt9m111, ctrl->val);
77110abb 710 case V4L2_CID_EXPOSURE_AUTO:
af8425c5 711 return mt9m111_set_autoexposure(mt9m111, ctrl->val);
39bf372f 712 case V4L2_CID_AUTO_WHITE_BALANCE:
af8425c5 713 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
77110abb
RJ
714 }
715
af8425c5 716 return -EINVAL;
77110abb
RJ
717}
718
14c5ea9b 719static int mt9m111_suspend(struct mt9m111 *mt9m111)
96c75399 720{
a650bf1e
GL
721 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
722 int ret;
723
af8425c5 724 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
96c75399 725
a650bf1e
GL
726 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
727 if (!ret)
728 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
729 MT9M111_RESET_OUTPUT_DISABLE |
730 MT9M111_RESET_ANALOG_STANDBY);
731 if (!ret)
732 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
733
734 return ret;
96c75399
GL
735}
736
2768cbbb 737static void mt9m111_restore_state(struct mt9m111 *mt9m111)
77110abb 738{
47921932 739 mt9m111_set_context(mt9m111, mt9m111->ctx);
2768cbbb 740 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
da673e60
GL
741 mt9m111_setup_geometry(mt9m111, &mt9m111->rect,
742 mt9m111->width, mt9m111->height, mt9m111->fmt->code);
af8425c5 743 v4l2_ctrl_handler_setup(&mt9m111->hdl);
77110abb
RJ
744}
745
14c5ea9b 746static int mt9m111_resume(struct mt9m111 *mt9m111)
77110abb 747{
a650bf1e
GL
748 int ret = mt9m111_enable(mt9m111);
749 if (!ret)
750 ret = mt9m111_reset(mt9m111);
751 if (!ret)
752 mt9m111_restore_state(mt9m111);
77110abb 753
77110abb
RJ
754 return ret;
755}
756
2768cbbb 757static int mt9m111_init(struct mt9m111 *mt9m111)
77110abb 758{
2768cbbb 759 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
77110abb
RJ
760 int ret;
761
2768cbbb 762 ret = mt9m111_enable(mt9m111);
506c629a 763 if (!ret)
2768cbbb 764 ret = mt9m111_reset(mt9m111);
506c629a 765 if (!ret)
47921932 766 ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
506c629a 767 if (ret)
c8cf078e 768 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
506c629a 769 return ret;
77110abb
RJ
770}
771
4ec10bac
LP
772static int mt9m111_power_on(struct mt9m111 *mt9m111)
773{
774 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
25a34811 775 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
4ec10bac
LP
776 int ret;
777
25a34811 778 ret = soc_camera_power_on(&client->dev, ssdd);
4ec10bac
LP
779 if (ret < 0)
780 return ret;
781
782 ret = mt9m111_resume(mt9m111);
783 if (ret < 0) {
784 dev_err(&client->dev, "Failed to resume the sensor: %d\n", ret);
25a34811 785 soc_camera_power_off(&client->dev, ssdd);
4ec10bac
LP
786 }
787
788 return ret;
789}
790
791static void mt9m111_power_off(struct mt9m111 *mt9m111)
792{
793 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
25a34811 794 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
4ec10bac
LP
795
796 mt9m111_suspend(mt9m111);
25a34811 797 soc_camera_power_off(&client->dev, ssdd);
4ec10bac
LP
798}
799
14c5ea9b
GL
800static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
801{
802 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
14c5ea9b
GL
803 int ret = 0;
804
805 mutex_lock(&mt9m111->power_lock);
806
807 /*
808 * If the power count is modified from 0 to != 0 or from != 0 to 0,
809 * update the power state.
810 */
811 if (mt9m111->power_count == !on) {
4ec10bac
LP
812 if (on)
813 ret = mt9m111_power_on(mt9m111);
814 else
815 mt9m111_power_off(mt9m111);
14c5ea9b
GL
816 }
817
4ec10bac
LP
818 if (!ret) {
819 /* Update the power count. */
820 mt9m111->power_count += on ? 1 : -1;
821 WARN_ON(mt9m111->power_count < 0);
822 }
14c5ea9b 823
14c5ea9b
GL
824 mutex_unlock(&mt9m111->power_lock);
825 return ret;
826}
827
af8425c5
HV
828static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
829 .s_ctrl = mt9m111_s_ctrl,
830};
831
979ea1dd 832static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
14c5ea9b 833 .s_power = mt9m111_s_power,
979ea1dd
GL
834#ifdef CONFIG_VIDEO_ADV_DEBUG
835 .g_register = mt9m111_g_register,
836 .s_register = mt9m111_s_register,
837#endif
838};
839
3805f201 840static int mt9m111_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
760697be
GL
841 enum v4l2_mbus_pixelcode *code)
842{
3805f201 843 if (index >= ARRAY_SIZE(mt9m111_colour_fmts))
760697be
GL
844 return -EINVAL;
845
846 *code = mt9m111_colour_fmts[index].code;
847 return 0;
848}
849
0c0b446d
GL
850static int mt9m111_g_mbus_config(struct v4l2_subdev *sd,
851 struct v4l2_mbus_config *cfg)
852{
853 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 854 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
0c0b446d
GL
855
856 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
857 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
858 V4L2_MBUS_DATA_ACTIVE_HIGH;
859 cfg->type = V4L2_MBUS_PARALLEL;
25a34811 860 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
0c0b446d
GL
861
862 return 0;
863}
864
979ea1dd 865static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
760697be
GL
866 .s_mbus_fmt = mt9m111_s_fmt,
867 .g_mbus_fmt = mt9m111_g_fmt,
868 .try_mbus_fmt = mt9m111_try_fmt,
08590b96 869 .s_crop = mt9m111_s_crop,
6a6c8786
GL
870 .g_crop = mt9m111_g_crop,
871 .cropcap = mt9m111_cropcap,
760697be 872 .enum_mbus_fmt = mt9m111_enum_fmt,
0c0b446d 873 .g_mbus_config = mt9m111_g_mbus_config,
979ea1dd
GL
874};
875
876static struct v4l2_subdev_ops mt9m111_subdev_ops = {
877 .core = &mt9m111_subdev_core_ops,
878 .video = &mt9m111_subdev_video_ops,
879};
880
4bbc6d52
LP
881/*
882 * Interface active, can use i2c. If it fails, it can indeed mean, that
883 * this wasn't our capture interface, so, we wait for the right one
884 */
885static int mt9m111_video_probe(struct i2c_client *client)
886{
887 struct mt9m111 *mt9m111 = to_mt9m111(client);
888 s32 data;
889 int ret;
890
891 ret = mt9m111_s_power(&mt9m111->subdev, 1);
892 if (ret < 0)
893 return ret;
894
895 data = reg_read(CHIP_VERSION);
896
897 switch (data) {
898 case 0x143a: /* MT9M111 or MT9M131 */
4bbc6d52
LP
899 dev_info(&client->dev,
900 "Detected a MT9M111/MT9M131 chip ID %x\n", data);
901 break;
902 case 0x148c: /* MT9M112 */
4bbc6d52
LP
903 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
904 break;
905 default:
906 dev_err(&client->dev,
907 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
908 data);
909 ret = -ENODEV;
910 goto done;
911 }
912
913 ret = mt9m111_init(mt9m111);
914 if (ret)
915 goto done;
916
917 ret = v4l2_ctrl_handler_setup(&mt9m111->hdl);
918
919done:
920 mt9m111_s_power(&mt9m111->subdev, 0);
921 return ret;
922}
923
77110abb
RJ
924static int mt9m111_probe(struct i2c_client *client,
925 const struct i2c_device_id *did)
926{
927 struct mt9m111 *mt9m111;
77110abb 928 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
25a34811 929 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
77110abb
RJ
930 int ret;
931
25a34811 932 if (!ssdd) {
c8cf078e 933 dev_err(&client->dev, "mt9m111: driver needs platform data\n");
77110abb
RJ
934 return -EINVAL;
935 }
936
937 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
938 dev_warn(&adapter->dev,
939 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
940 return -EIO;
941 }
942
70e176a5 943 mt9m111 = devm_kzalloc(&client->dev, sizeof(struct mt9m111), GFP_KERNEL);
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944 if (!mt9m111)
945 return -ENOMEM;
946
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947 /* Default HIGHPOWER context */
948 mt9m111->ctx = &context_b;
949
979ea1dd 950 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
af8425c5
HV
951 v4l2_ctrl_handler_init(&mt9m111->hdl, 5);
952 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
953 V4L2_CID_VFLIP, 0, 1, 1, 0);
954 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
955 V4L2_CID_HFLIP, 0, 1, 1, 0);
956 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
957 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
958 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
959 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
960 v4l2_ctrl_new_std_menu(&mt9m111->hdl,
961 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
962 V4L2_EXPOSURE_AUTO);
963 mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
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964 if (mt9m111->hdl.error)
965 return mt9m111->hdl.error;
77110abb 966
af8425c5 967 /* Second stage probe - when a capture adapter is there */
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GL
968 mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
969 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
970 mt9m111->rect.width = MT9M111_MAX_WIDTH;
971 mt9m111->rect.height = MT9M111_MAX_HEIGHT;
760697be 972 mt9m111->fmt = &mt9m111_colour_fmts[0];
14178aa5 973 mt9m111->lastpage = -1;
6b806e30 974 mutex_init(&mt9m111->power_lock);
6a6c8786 975
14178aa5 976 ret = mt9m111_video_probe(client);
70e176a5 977 if (ret)
af8425c5 978 v4l2_ctrl_handler_free(&mt9m111->hdl);
77110abb 979
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980 return ret;
981}
982
983static int mt9m111_remove(struct i2c_client *client)
984{
979ea1dd 985 struct mt9m111 *mt9m111 = to_mt9m111(client);
40e2e092 986
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987 v4l2_device_unregister_subdev(&mt9m111->subdev);
988 v4l2_ctrl_handler_free(&mt9m111->hdl);
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989
990 return 0;
991}
992
993static const struct i2c_device_id mt9m111_id[] = {
994 { "mt9m111", 0 },
995 { }
996};
997MODULE_DEVICE_TABLE(i2c, mt9m111_id);
998
999static struct i2c_driver mt9m111_i2c_driver = {
1000 .driver = {
1001 .name = "mt9m111",
1002 },
1003 .probe = mt9m111_probe,
1004 .remove = mt9m111_remove,
1005 .id_table = mt9m111_id,
1006};
1007
c6e8d86f 1008module_i2c_driver(mt9m111_i2c_driver);
77110abb 1009
c8cf078e 1010MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
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1011MODULE_AUTHOR("Robert Jarzmik");
1012MODULE_LICENSE("GPL");
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