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858424b9 KM |
1 | /* |
2 | * mt9t112 Camera Driver | |
3 | * | |
4 | * Copyright (C) 2009 Renesas Solutions Corp. | |
5 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
6 | * | |
7 | * Based on ov772x driver, mt9m111 driver, | |
8 | * | |
9 | * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
10 | * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr> | |
11 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> | |
12 | * Copyright (C) 2008 Magnus Damm | |
13 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or modify | |
16 | * it under the terms of the GNU General Public License version 2 as | |
17 | * published by the Free Software Foundation. | |
18 | */ | |
19 | ||
20 | #include <linux/delay.h> | |
21 | #include <linux/i2c.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/slab.h> | |
95d20109 | 25 | #include <linux/v4l2-mediabus.h> |
858424b9 KM |
26 | #include <linux/videodev2.h> |
27 | ||
28 | #include <media/mt9t112.h> | |
29 | #include <media/soc_camera.h> | |
9aea470b | 30 | #include <media/v4l2-clk.h> |
858424b9 | 31 | #include <media/v4l2-common.h> |
665152a4 | 32 | #include <media/v4l2-image-sizes.h> |
858424b9 KM |
33 | |
34 | /* you can check PLL/clock info */ | |
35 | /* #define EXT_CLOCK 24000000 */ | |
36 | ||
37 | /************************************************************************ | |
858424b9 | 38 | macro |
858424b9 KM |
39 | ************************************************************************/ |
40 | /* | |
41 | * frame size | |
42 | */ | |
43 | #define MAX_WIDTH 2048 | |
44 | #define MAX_HEIGHT 1536 | |
45 | ||
858424b9 KM |
46 | /* |
47 | * macro of read/write | |
48 | */ | |
49 | #define ECHECKER(ret, x) \ | |
50 | do { \ | |
51 | (ret) = (x); \ | |
52 | if ((ret) < 0) \ | |
53 | return (ret); \ | |
54 | } while (0) | |
55 | ||
56 | #define mt9t112_reg_write(ret, client, a, b) \ | |
57 | ECHECKER(ret, __mt9t112_reg_write(client, a, b)) | |
58 | #define mt9t112_mcu_write(ret, client, a, b) \ | |
59 | ECHECKER(ret, __mt9t112_mcu_write(client, a, b)) | |
60 | ||
61 | #define mt9t112_reg_mask_set(ret, client, a, b, c) \ | |
62 | ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c)) | |
63 | #define mt9t112_mcu_mask_set(ret, client, a, b, c) \ | |
64 | ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c)) | |
65 | ||
66 | #define mt9t112_reg_read(ret, client, a) \ | |
67 | ECHECKER(ret, __mt9t112_reg_read(client, a)) | |
68 | ||
69 | /* | |
70 | * Logical address | |
71 | */ | |
72 | #define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff)) | |
73 | #define VAR(id, offset) _VAR(id, offset, 0x0000) | |
74 | #define VAR8(id, offset) _VAR(id, offset, 0x8000) | |
75 | ||
76 | /************************************************************************ | |
858424b9 | 77 | struct |
858424b9 | 78 | ************************************************************************/ |
858424b9 KM |
79 | struct mt9t112_format { |
80 | enum v4l2_mbus_pixelcode code; | |
81 | enum v4l2_colorspace colorspace; | |
82 | u16 fmt; | |
83 | u16 order; | |
84 | }; | |
85 | ||
86 | struct mt9t112_priv { | |
87 | struct v4l2_subdev subdev; | |
88 | struct mt9t112_camera_info *info; | |
89 | struct i2c_client *client; | |
377c9ba7 | 90 | struct v4l2_rect frame; |
9aea470b | 91 | struct v4l2_clk *clk; |
858424b9 | 92 | const struct mt9t112_format *format; |
ec34e1d5 | 93 | int num_formats; |
858424b9 KM |
94 | u32 flags; |
95 | /* for flags */ | |
d46ebd46 GL |
96 | #define INIT_DONE (1 << 0) |
97 | #define PCLK_RISING (1 << 1) | |
858424b9 KM |
98 | }; |
99 | ||
100 | /************************************************************************ | |
858424b9 | 101 | supported format |
858424b9 KM |
102 | ************************************************************************/ |
103 | ||
104 | static const struct mt9t112_format mt9t112_cfmts[] = { | |
105 | { | |
ace6e979 | 106 | .code = V4L2_MBUS_FMT_UYVY8_2X8, |
858424b9 KM |
107 | .colorspace = V4L2_COLORSPACE_JPEG, |
108 | .fmt = 1, | |
109 | .order = 0, | |
110 | }, { | |
ace6e979 | 111 | .code = V4L2_MBUS_FMT_VYUY8_2X8, |
858424b9 KM |
112 | .colorspace = V4L2_COLORSPACE_JPEG, |
113 | .fmt = 1, | |
114 | .order = 1, | |
115 | }, { | |
ace6e979 | 116 | .code = V4L2_MBUS_FMT_YUYV8_2X8, |
858424b9 KM |
117 | .colorspace = V4L2_COLORSPACE_JPEG, |
118 | .fmt = 1, | |
119 | .order = 2, | |
120 | }, { | |
ace6e979 | 121 | .code = V4L2_MBUS_FMT_YVYU8_2X8, |
858424b9 KM |
122 | .colorspace = V4L2_COLORSPACE_JPEG, |
123 | .fmt = 1, | |
124 | .order = 3, | |
125 | }, { | |
126 | .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, | |
127 | .colorspace = V4L2_COLORSPACE_SRGB, | |
128 | .fmt = 8, | |
129 | .order = 2, | |
130 | }, { | |
131 | .code = V4L2_MBUS_FMT_RGB565_2X8_LE, | |
132 | .colorspace = V4L2_COLORSPACE_SRGB, | |
133 | .fmt = 4, | |
134 | .order = 2, | |
135 | }, | |
136 | }; | |
137 | ||
138 | /************************************************************************ | |
858424b9 | 139 | general function |
858424b9 KM |
140 | ************************************************************************/ |
141 | static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client) | |
142 | { | |
143 | return container_of(i2c_get_clientdata(client), | |
144 | struct mt9t112_priv, | |
145 | subdev); | |
146 | } | |
147 | ||
148 | static int __mt9t112_reg_read(const struct i2c_client *client, u16 command) | |
149 | { | |
150 | struct i2c_msg msg[2]; | |
151 | u8 buf[2]; | |
152 | int ret; | |
153 | ||
154 | command = swab16(command); | |
155 | ||
156 | msg[0].addr = client->addr; | |
157 | msg[0].flags = 0; | |
158 | msg[0].len = 2; | |
159 | msg[0].buf = (u8 *)&command; | |
160 | ||
161 | msg[1].addr = client->addr; | |
162 | msg[1].flags = I2C_M_RD; | |
163 | msg[1].len = 2; | |
164 | msg[1].buf = buf; | |
165 | ||
166 | /* | |
167 | * if return value of this function is < 0, | |
168 | * it mean error. | |
169 | * else, under 16bit is valid data. | |
170 | */ | |
171 | ret = i2c_transfer(client->adapter, msg, 2); | |
172 | if (ret < 0) | |
173 | return ret; | |
174 | ||
175 | memcpy(&ret, buf, 2); | |
176 | return swab16(ret); | |
177 | } | |
178 | ||
179 | static int __mt9t112_reg_write(const struct i2c_client *client, | |
180 | u16 command, u16 data) | |
181 | { | |
182 | struct i2c_msg msg; | |
183 | u8 buf[4]; | |
184 | int ret; | |
185 | ||
186 | command = swab16(command); | |
187 | data = swab16(data); | |
188 | ||
189 | memcpy(buf + 0, &command, 2); | |
190 | memcpy(buf + 2, &data, 2); | |
191 | ||
192 | msg.addr = client->addr; | |
193 | msg.flags = 0; | |
194 | msg.len = 4; | |
195 | msg.buf = buf; | |
196 | ||
197 | /* | |
198 | * i2c_transfer return message length, | |
199 | * but this function should return 0 if correct case | |
200 | */ | |
201 | ret = i2c_transfer(client->adapter, &msg, 1); | |
202 | if (ret >= 0) | |
203 | ret = 0; | |
204 | ||
205 | return ret; | |
206 | } | |
207 | ||
208 | static int __mt9t112_reg_mask_set(const struct i2c_client *client, | |
209 | u16 command, | |
210 | u16 mask, | |
211 | u16 set) | |
212 | { | |
213 | int val = __mt9t112_reg_read(client, command); | |
214 | if (val < 0) | |
215 | return val; | |
216 | ||
217 | val &= ~mask; | |
218 | val |= set & mask; | |
219 | ||
220 | return __mt9t112_reg_write(client, command, val); | |
221 | } | |
222 | ||
223 | /* mcu access */ | |
224 | static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command) | |
225 | { | |
226 | int ret; | |
227 | ||
228 | ret = __mt9t112_reg_write(client, 0x098E, command); | |
229 | if (ret < 0) | |
230 | return ret; | |
231 | ||
232 | return __mt9t112_reg_read(client, 0x0990); | |
233 | } | |
234 | ||
235 | static int __mt9t112_mcu_write(const struct i2c_client *client, | |
236 | u16 command, u16 data) | |
237 | { | |
238 | int ret; | |
239 | ||
240 | ret = __mt9t112_reg_write(client, 0x098E, command); | |
241 | if (ret < 0) | |
242 | return ret; | |
243 | ||
244 | return __mt9t112_reg_write(client, 0x0990, data); | |
245 | } | |
246 | ||
247 | static int __mt9t112_mcu_mask_set(const struct i2c_client *client, | |
248 | u16 command, | |
249 | u16 mask, | |
250 | u16 set) | |
251 | { | |
252 | int val = __mt9t112_mcu_read(client, command); | |
253 | if (val < 0) | |
254 | return val; | |
255 | ||
256 | val &= ~mask; | |
257 | val |= set & mask; | |
258 | ||
259 | return __mt9t112_mcu_write(client, command, val); | |
260 | } | |
261 | ||
262 | static int mt9t112_reset(const struct i2c_client *client) | |
263 | { | |
264 | int ret; | |
265 | ||
266 | mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001); | |
267 | msleep(1); | |
268 | mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000); | |
269 | ||
270 | return ret; | |
271 | } | |
272 | ||
273 | #ifndef EXT_CLOCK | |
274 | #define CLOCK_INFO(a, b) | |
275 | #else | |
276 | #define CLOCK_INFO(a, b) mt9t112_clock_info(a, b) | |
277 | static int mt9t112_clock_info(const struct i2c_client *client, u32 ext) | |
278 | { | |
279 | int m, n, p1, p2, p3, p4, p5, p6, p7; | |
280 | u32 vco, clk; | |
281 | char *enable; | |
282 | ||
283 | ext /= 1000; /* kbyte order */ | |
284 | ||
285 | mt9t112_reg_read(n, client, 0x0012); | |
286 | p1 = n & 0x000f; | |
287 | n = n >> 4; | |
288 | p2 = n & 0x000f; | |
289 | n = n >> 4; | |
290 | p3 = n & 0x000f; | |
291 | ||
292 | mt9t112_reg_read(n, client, 0x002a); | |
293 | p4 = n & 0x000f; | |
294 | n = n >> 4; | |
295 | p5 = n & 0x000f; | |
296 | n = n >> 4; | |
297 | p6 = n & 0x000f; | |
298 | ||
299 | mt9t112_reg_read(n, client, 0x002c); | |
300 | p7 = n & 0x000f; | |
301 | ||
302 | mt9t112_reg_read(n, client, 0x0010); | |
303 | m = n & 0x00ff; | |
304 | n = (n >> 8) & 0x003f; | |
305 | ||
306 | enable = ((6000 > ext) || (54000 < ext)) ? "X" : ""; | |
14178aa5 | 307 | dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable); |
858424b9 KM |
308 | |
309 | vco = 2 * m * ext / (n+1); | |
310 | enable = ((384000 > vco) || (768000 < vco)) ? "X" : ""; | |
14178aa5 | 311 | dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable); |
858424b9 KM |
312 | |
313 | clk = vco / (p1+1) / (p2+1); | |
314 | enable = (96000 < clk) ? "X" : ""; | |
14178aa5 | 315 | dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable); |
858424b9 KM |
316 | |
317 | clk = vco / (p3+1); | |
318 | enable = (768000 < clk) ? "X" : ""; | |
14178aa5 | 319 | dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable); |
858424b9 KM |
320 | |
321 | clk = vco / (p6+1); | |
322 | enable = (96000 < clk) ? "X" : ""; | |
14178aa5 | 323 | dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable); |
858424b9 KM |
324 | |
325 | clk = vco / (p5+1); | |
326 | enable = (54000 < clk) ? "X" : ""; | |
14178aa5 | 327 | dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable); |
858424b9 KM |
328 | |
329 | clk = vco / (p4+1); | |
330 | enable = (70000 < clk) ? "X" : ""; | |
14178aa5 | 331 | dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable); |
858424b9 KM |
332 | |
333 | clk = vco / (p7+1); | |
14178aa5 | 334 | dev_dbg(&client->dev, "External sensor : %10u K\n", clk); |
858424b9 KM |
335 | |
336 | clk = ext / (n+1); | |
337 | enable = ((2000 > clk) || (24000 < clk)) ? "X" : ""; | |
14178aa5 | 338 | dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable); |
858424b9 KM |
339 | |
340 | return 0; | |
341 | } | |
342 | #endif | |
343 | ||
377c9ba7 | 344 | static void mt9t112_frame_check(u32 *width, u32 *height, u32 *left, u32 *top) |
858424b9 | 345 | { |
377c9ba7 GL |
346 | soc_camera_limit_side(left, width, 0, 0, MAX_WIDTH); |
347 | soc_camera_limit_side(top, height, 0, 0, MAX_HEIGHT); | |
858424b9 KM |
348 | } |
349 | ||
350 | static int mt9t112_set_a_frame_size(const struct i2c_client *client, | |
351 | u16 width, | |
352 | u16 height) | |
353 | { | |
354 | int ret; | |
355 | u16 wstart = (MAX_WIDTH - width) / 2; | |
356 | u16 hstart = (MAX_HEIGHT - height) / 2; | |
357 | ||
358 | /* (Context A) Image Width/Height */ | |
359 | mt9t112_mcu_write(ret, client, VAR(26, 0), width); | |
360 | mt9t112_mcu_write(ret, client, VAR(26, 2), height); | |
361 | ||
362 | /* (Context A) Output Width/Height */ | |
363 | mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width); | |
364 | mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height); | |
365 | ||
366 | /* (Context A) Start Row/Column */ | |
367 | mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart); | |
368 | mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart); | |
369 | ||
370 | /* (Context A) End Row/Column */ | |
371 | mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart); | |
372 | mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart); | |
373 | ||
374 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); | |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
379 | static int mt9t112_set_pll_dividers(const struct i2c_client *client, | |
380 | u8 m, u8 n, | |
381 | u8 p1, u8 p2, u8 p3, | |
382 | u8 p4, u8 p5, u8 p6, | |
383 | u8 p7) | |
384 | { | |
385 | int ret; | |
386 | u16 val; | |
387 | ||
388 | /* N/M */ | |
389 | val = (n << 8) | | |
390 | (m << 0); | |
391 | mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val); | |
392 | ||
393 | /* P1/P2/P3 */ | |
394 | val = ((p3 & 0x0F) << 8) | | |
395 | ((p2 & 0x0F) << 4) | | |
396 | ((p1 & 0x0F) << 0); | |
397 | mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val); | |
398 | ||
399 | /* P4/P5/P6 */ | |
400 | val = (0x7 << 12) | | |
401 | ((p6 & 0x0F) << 8) | | |
402 | ((p5 & 0x0F) << 4) | | |
403 | ((p4 & 0x0F) << 0); | |
404 | mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val); | |
405 | ||
406 | /* P7 */ | |
407 | val = (0x1 << 12) | | |
408 | ((p7 & 0x0F) << 0); | |
409 | mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val); | |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
414 | static int mt9t112_init_pll(const struct i2c_client *client) | |
415 | { | |
416 | struct mt9t112_priv *priv = to_mt9t112(client); | |
417 | int data, i, ret; | |
418 | ||
419 | mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001); | |
420 | ||
421 | /* PLL control: BYPASS PLL = 8517 */ | |
422 | mt9t112_reg_write(ret, client, 0x0014, 0x2145); | |
423 | ||
424 | /* Replace these registers when new timing parameters are generated */ | |
425 | mt9t112_set_pll_dividers(client, | |
426 | priv->info->divider.m, | |
427 | priv->info->divider.n, | |
428 | priv->info->divider.p1, | |
429 | priv->info->divider.p2, | |
430 | priv->info->divider.p3, | |
431 | priv->info->divider.p4, | |
432 | priv->info->divider.p5, | |
433 | priv->info->divider.p6, | |
434 | priv->info->divider.p7); | |
435 | ||
436 | /* | |
437 | * TEST_BYPASS on | |
438 | * PLL_ENABLE on | |
439 | * SEL_LOCK_DET on | |
440 | * TEST_BYPASS off | |
441 | */ | |
442 | mt9t112_reg_write(ret, client, 0x0014, 0x2525); | |
443 | mt9t112_reg_write(ret, client, 0x0014, 0x2527); | |
444 | mt9t112_reg_write(ret, client, 0x0014, 0x3427); | |
445 | mt9t112_reg_write(ret, client, 0x0014, 0x3027); | |
446 | ||
447 | mdelay(10); | |
448 | ||
449 | /* | |
450 | * PLL_BYPASS off | |
451 | * Reference clock count | |
452 | * I2C Master Clock Divider | |
453 | */ | |
454 | mt9t112_reg_write(ret, client, 0x0014, 0x3046); | |
61282daf | 455 | mt9t112_reg_write(ret, client, 0x0016, 0x0400); /* JPEG initialization workaround */ |
858424b9 KM |
456 | mt9t112_reg_write(ret, client, 0x0022, 0x0190); |
457 | mt9t112_reg_write(ret, client, 0x3B84, 0x0212); | |
458 | ||
459 | /* External sensor clock is PLL bypass */ | |
460 | mt9t112_reg_write(ret, client, 0x002E, 0x0500); | |
461 | ||
462 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002); | |
463 | mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004); | |
464 | ||
465 | /* MCU disabled */ | |
466 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004); | |
467 | ||
468 | /* out of standby */ | |
469 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0); | |
470 | ||
471 | mdelay(50); | |
472 | ||
473 | /* | |
474 | * Standby Workaround | |
475 | * Disable Secondary I2C Pads | |
476 | */ | |
477 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); | |
478 | mdelay(1); | |
479 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); | |
480 | mdelay(1); | |
481 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); | |
482 | mdelay(1); | |
483 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); | |
484 | mdelay(1); | |
485 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); | |
486 | mdelay(1); | |
487 | mt9t112_reg_write(ret, client, 0x0614, 0x0001); | |
488 | mdelay(1); | |
489 | ||
490 | /* poll to verify out of standby. Must Poll this bit */ | |
491 | for (i = 0; i < 100; i++) { | |
492 | mt9t112_reg_read(data, client, 0x0018); | |
2b59125b | 493 | if (!(0x4000 & data)) |
858424b9 KM |
494 | break; |
495 | ||
496 | mdelay(10); | |
497 | } | |
498 | ||
499 | return ret; | |
500 | } | |
501 | ||
502 | static int mt9t112_init_setting(const struct i2c_client *client) | |
503 | { | |
504 | ||
505 | int ret; | |
506 | ||
507 | /* Adaptive Output Clock (A) */ | |
508 | mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000); | |
509 | ||
510 | /* Read Mode (A) */ | |
511 | mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024); | |
512 | ||
513 | /* Fine Correction (A) */ | |
514 | mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC); | |
515 | ||
516 | /* Fine IT Min (A) */ | |
517 | mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1); | |
518 | ||
519 | /* Fine IT Max Margin (A) */ | |
520 | mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF); | |
521 | ||
522 | /* Base Frame Lines (A) */ | |
523 | mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D); | |
524 | ||
525 | /* Min Line Length (A) */ | |
526 | mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a); | |
527 | ||
528 | /* Line Length (A) */ | |
529 | mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0); | |
530 | ||
531 | /* Adaptive Output Clock (B) */ | |
532 | mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000); | |
533 | ||
534 | /* Row Start (B) */ | |
535 | mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004); | |
536 | ||
537 | /* Column Start (B) */ | |
538 | mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004); | |
539 | ||
540 | /* Row End (B) */ | |
541 | mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B); | |
542 | ||
543 | /* Column End (B) */ | |
544 | mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B); | |
545 | ||
546 | /* Fine Correction (B) */ | |
547 | mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C); | |
548 | ||
549 | /* Fine IT Min (B) */ | |
550 | mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1); | |
551 | ||
552 | /* Fine IT Max Margin (B) */ | |
553 | mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF); | |
554 | ||
555 | /* Base Frame Lines (B) */ | |
556 | mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668); | |
557 | ||
558 | /* Min Line Length (B) */ | |
559 | mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0); | |
560 | ||
561 | /* Line Length (B) */ | |
562 | mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0); | |
563 | ||
564 | /* | |
565 | * Flicker Dectection registers | |
566 | * This section should be replaced whenever new Timing file is generated | |
567 | * All the following registers need to be replaced | |
568 | * Following registers are generated from Register Wizard but user can | |
569 | * modify them. For detail see auto flicker detection tuning | |
570 | */ | |
571 | ||
572 | /* FD_FDPERIOD_SELECT */ | |
573 | mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01); | |
574 | ||
575 | /* PRI_B_CONFIG_FD_ALGO_RUN */ | |
576 | mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003); | |
577 | ||
578 | /* PRI_A_CONFIG_FD_ALGO_RUN */ | |
579 | mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003); | |
580 | ||
581 | /* | |
582 | * AFD range detection tuning registers | |
583 | */ | |
584 | ||
585 | /* search_f1_50 */ | |
586 | mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25); | |
587 | ||
588 | /* search_f2_50 */ | |
589 | mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28); | |
590 | ||
591 | /* search_f1_60 */ | |
592 | mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C); | |
593 | ||
594 | /* search_f2_60 */ | |
595 | mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F); | |
596 | ||
597 | /* period_50Hz (A) */ | |
598 | mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA); | |
599 | ||
600 | /* secret register by aptina */ | |
601 | /* period_50Hz (A MSB) */ | |
602 | mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00); | |
603 | ||
604 | /* period_60Hz (A) */ | |
605 | mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B); | |
606 | ||
607 | /* secret register by aptina */ | |
608 | /* period_60Hz (A MSB) */ | |
609 | mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00); | |
610 | ||
611 | /* period_50Hz (B) */ | |
612 | mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82); | |
613 | ||
614 | /* secret register by aptina */ | |
615 | /* period_50Hz (B) MSB */ | |
616 | mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00); | |
617 | ||
618 | /* period_60Hz (B) */ | |
619 | mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D); | |
620 | ||
621 | /* secret register by aptina */ | |
622 | /* period_60Hz (B) MSB */ | |
623 | mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00); | |
624 | ||
625 | /* FD Mode */ | |
626 | mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10); | |
627 | ||
628 | /* Stat_min */ | |
629 | mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02); | |
630 | ||
631 | /* Stat_max */ | |
632 | mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03); | |
633 | ||
634 | /* Min_amplitude */ | |
635 | mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A); | |
636 | ||
637 | /* RX FIFO Watermark (A) */ | |
638 | mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014); | |
639 | ||
640 | /* RX FIFO Watermark (B) */ | |
641 | mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014); | |
642 | ||
643 | /* MCLK: 16MHz | |
644 | * PCLK: 73MHz | |
645 | * CorePixCLK: 36.5 MHz | |
646 | */ | |
647 | mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133); | |
648 | mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110); | |
649 | mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130); | |
650 | mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108); | |
651 | ||
652 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27); | |
653 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30); | |
654 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32); | |
655 | mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35); | |
656 | ||
657 | return ret; | |
658 | } | |
659 | ||
660 | static int mt9t112_auto_focus_setting(const struct i2c_client *client) | |
661 | { | |
662 | int ret; | |
663 | ||
664 | mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F); | |
665 | mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F); | |
666 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); | |
667 | ||
668 | mt9t112_reg_write(ret, client, 0x0614, 0x0000); | |
669 | ||
670 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); | |
671 | mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02); | |
672 | mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002); | |
673 | mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001); | |
674 | mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025); | |
675 | mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193); | |
676 | mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18); | |
677 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05); | |
678 | ||
679 | return ret; | |
680 | } | |
681 | ||
682 | static int mt9t112_auto_focus_trigger(const struct i2c_client *client) | |
683 | { | |
684 | int ret; | |
685 | ||
686 | mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01); | |
687 | ||
688 | return ret; | |
689 | } | |
690 | ||
691 | static int mt9t112_init_camera(const struct i2c_client *client) | |
692 | { | |
693 | int ret; | |
694 | ||
695 | ECHECKER(ret, mt9t112_reset(client)); | |
696 | ||
697 | ECHECKER(ret, mt9t112_init_pll(client)); | |
698 | ||
699 | ECHECKER(ret, mt9t112_init_setting(client)); | |
700 | ||
701 | ECHECKER(ret, mt9t112_auto_focus_setting(client)); | |
702 | ||
703 | mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0); | |
704 | ||
705 | /* Analog setting B */ | |
706 | mt9t112_reg_write(ret, client, 0x3084, 0x2409); | |
707 | mt9t112_reg_write(ret, client, 0x3092, 0x0A49); | |
708 | mt9t112_reg_write(ret, client, 0x3094, 0x4949); | |
709 | mt9t112_reg_write(ret, client, 0x3096, 0x4950); | |
710 | ||
711 | /* | |
712 | * Disable adaptive clock | |
713 | * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR | |
714 | * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR | |
715 | */ | |
716 | mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E); | |
717 | mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E); | |
718 | ||
719 | /* Configure STatus in Status_before_length Format and enable header */ | |
720 | /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ | |
721 | mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4); | |
722 | ||
723 | /* Enable JPEG in context B */ | |
724 | /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */ | |
725 | mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01); | |
726 | ||
727 | /* Disable Dac_TXLO */ | |
728 | mt9t112_reg_write(ret, client, 0x316C, 0x350F); | |
729 | ||
730 | /* Set max slew rates */ | |
731 | mt9t112_reg_write(ret, client, 0x1E, 0x777); | |
732 | ||
733 | return ret; | |
734 | } | |
735 | ||
858424b9 | 736 | /************************************************************************ |
858424b9 | 737 | v4l2_subdev_core_ops |
858424b9 | 738 | ************************************************************************/ |
858424b9 KM |
739 | |
740 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
741 | static int mt9t112_g_register(struct v4l2_subdev *sd, | |
742 | struct v4l2_dbg_register *reg) | |
743 | { | |
c4ce6d14 | 744 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
858424b9 KM |
745 | int ret; |
746 | ||
747 | reg->size = 2; | |
748 | mt9t112_reg_read(ret, client, reg->reg); | |
749 | ||
750 | reg->val = (__u64)ret; | |
751 | ||
752 | return 0; | |
753 | } | |
754 | ||
755 | static int mt9t112_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 756 | const struct v4l2_dbg_register *reg) |
858424b9 | 757 | { |
c4ce6d14 | 758 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
858424b9 KM |
759 | int ret; |
760 | ||
761 | mt9t112_reg_write(ret, client, reg->reg, reg->val); | |
762 | ||
763 | return ret; | |
764 | } | |
765 | #endif | |
766 | ||
4ec10bac LP |
767 | static int mt9t112_s_power(struct v4l2_subdev *sd, int on) |
768 | { | |
769 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 770 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
9aea470b | 771 | struct mt9t112_priv *priv = to_mt9t112(client); |
4ec10bac | 772 | |
9aea470b | 773 | return soc_camera_set_power(&client->dev, ssdd, priv->clk, on); |
4ec10bac LP |
774 | } |
775 | ||
858424b9 | 776 | static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = { |
858424b9 KM |
777 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
778 | .g_register = mt9t112_g_register, | |
779 | .s_register = mt9t112_s_register, | |
780 | #endif | |
4ec10bac | 781 | .s_power = mt9t112_s_power, |
858424b9 KM |
782 | }; |
783 | ||
784 | ||
785 | /************************************************************************ | |
858424b9 | 786 | v4l2_subdev_video_ops |
858424b9 KM |
787 | ************************************************************************/ |
788 | static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable) | |
789 | { | |
c4ce6d14 | 790 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
858424b9 KM |
791 | struct mt9t112_priv *priv = to_mt9t112(client); |
792 | int ret = 0; | |
793 | ||
794 | if (!enable) { | |
795 | /* FIXME | |
796 | * | |
797 | * If user selected large output size, | |
798 | * and used it long time, | |
799 | * mt9t112 camera will be very warm. | |
800 | * | |
801 | * But current driver can not stop mt9t112 camera. | |
802 | * So, set small size here to solve this problem. | |
803 | */ | |
804 | mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT); | |
805 | return ret; | |
806 | } | |
807 | ||
808 | if (!(priv->flags & INIT_DONE)) { | |
d46ebd46 | 809 | u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000; |
858424b9 KM |
810 | |
811 | ECHECKER(ret, mt9t112_init_camera(client)); | |
812 | ||
813 | /* Invert PCLK (Data sampled on falling edge of pixclk) */ | |
814 | mt9t112_reg_write(ret, client, 0x3C20, param); | |
815 | ||
816 | mdelay(5); | |
817 | ||
818 | priv->flags |= INIT_DONE; | |
819 | } | |
820 | ||
821 | mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt); | |
822 | mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order); | |
823 | mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06); | |
824 | ||
825 | mt9t112_set_a_frame_size(client, | |
826 | priv->frame.width, | |
827 | priv->frame.height); | |
828 | ||
829 | ECHECKER(ret, mt9t112_auto_focus_trigger(client)); | |
830 | ||
831 | dev_dbg(&client->dev, "format : %d\n", priv->format->code); | |
832 | dev_dbg(&client->dev, "size : %d x %d\n", | |
833 | priv->frame.width, | |
834 | priv->frame.height); | |
835 | ||
836 | CLOCK_INFO(client, EXT_CLOCK); | |
837 | ||
838 | return ret; | |
839 | } | |
840 | ||
377c9ba7 GL |
841 | static int mt9t112_set_params(struct mt9t112_priv *priv, |
842 | const struct v4l2_rect *rect, | |
858424b9 KM |
843 | enum v4l2_mbus_pixelcode code) |
844 | { | |
858424b9 KM |
845 | int i; |
846 | ||
858424b9 KM |
847 | /* |
848 | * get color format | |
849 | */ | |
ec34e1d5 | 850 | for (i = 0; i < priv->num_formats; i++) |
858424b9 KM |
851 | if (mt9t112_cfmts[i].code == code) |
852 | break; | |
853 | ||
ec34e1d5 | 854 | if (i == priv->num_formats) |
858424b9 KM |
855 | return -EINVAL; |
856 | ||
377c9ba7 GL |
857 | priv->frame = *rect; |
858 | ||
859 | /* | |
860 | * frame size check | |
861 | */ | |
862 | mt9t112_frame_check(&priv->frame.width, &priv->frame.height, | |
863 | &priv->frame.left, &priv->frame.top); | |
858424b9 KM |
864 | |
865 | priv->format = mt9t112_cfmts + i; | |
866 | ||
867 | return 0; | |
868 | } | |
869 | ||
870 | static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) | |
871 | { | |
872 | a->bounds.left = 0; | |
873 | a->bounds.top = 0; | |
377c9ba7 GL |
874 | a->bounds.width = MAX_WIDTH; |
875 | a->bounds.height = MAX_HEIGHT; | |
876 | a->defrect.left = 0; | |
877 | a->defrect.top = 0; | |
878 | a->defrect.width = VGA_WIDTH; | |
879 | a->defrect.height = VGA_HEIGHT; | |
858424b9 KM |
880 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
881 | a->pixelaspect.numerator = 1; | |
882 | a->pixelaspect.denominator = 1; | |
883 | ||
884 | return 0; | |
885 | } | |
886 | ||
887 | static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) | |
888 | { | |
377c9ba7 GL |
889 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
890 | struct mt9t112_priv *priv = to_mt9t112(client); | |
891 | ||
892 | a->c = priv->frame; | |
893 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
858424b9 KM |
894 | |
895 | return 0; | |
896 | } | |
897 | ||
4f996594 | 898 | static int mt9t112_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a) |
858424b9 | 899 | { |
c4ce6d14 | 900 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
377c9ba7 | 901 | struct mt9t112_priv *priv = to_mt9t112(client); |
4f996594 | 902 | const struct v4l2_rect *rect = &a->c; |
858424b9 | 903 | |
377c9ba7 | 904 | return mt9t112_set_params(priv, rect, priv->format->code); |
858424b9 KM |
905 | } |
906 | ||
907 | static int mt9t112_g_fmt(struct v4l2_subdev *sd, | |
908 | struct v4l2_mbus_framefmt *mf) | |
909 | { | |
c4ce6d14 | 910 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
858424b9 KM |
911 | struct mt9t112_priv *priv = to_mt9t112(client); |
912 | ||
858424b9 KM |
913 | mf->width = priv->frame.width; |
914 | mf->height = priv->frame.height; | |
377c9ba7 | 915 | mf->colorspace = priv->format->colorspace; |
858424b9 KM |
916 | mf->code = priv->format->code; |
917 | mf->field = V4L2_FIELD_NONE; | |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | static int mt9t112_s_fmt(struct v4l2_subdev *sd, | |
923 | struct v4l2_mbus_framefmt *mf) | |
924 | { | |
c4ce6d14 | 925 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
377c9ba7 GL |
926 | struct mt9t112_priv *priv = to_mt9t112(client); |
927 | struct v4l2_rect rect = { | |
928 | .width = mf->width, | |
929 | .height = mf->height, | |
930 | .left = priv->frame.left, | |
931 | .top = priv->frame.top, | |
932 | }; | |
933 | int ret; | |
934 | ||
935 | ret = mt9t112_set_params(priv, &rect, mf->code); | |
936 | ||
937 | if (!ret) | |
938 | mf->colorspace = priv->format->colorspace; | |
858424b9 | 939 | |
377c9ba7 | 940 | return ret; |
858424b9 KM |
941 | } |
942 | ||
943 | static int mt9t112_try_fmt(struct v4l2_subdev *sd, | |
944 | struct v4l2_mbus_framefmt *mf) | |
945 | { | |
ec34e1d5 GL |
946 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
947 | struct mt9t112_priv *priv = to_mt9t112(client); | |
377c9ba7 GL |
948 | unsigned int top, left; |
949 | int i; | |
950 | ||
ec34e1d5 | 951 | for (i = 0; i < priv->num_formats; i++) |
377c9ba7 GL |
952 | if (mt9t112_cfmts[i].code == mf->code) |
953 | break; | |
954 | ||
ec34e1d5 | 955 | if (i == priv->num_formats) { |
377c9ba7 GL |
956 | mf->code = V4L2_MBUS_FMT_UYVY8_2X8; |
957 | mf->colorspace = V4L2_COLORSPACE_JPEG; | |
958 | } else { | |
959 | mf->colorspace = mt9t112_cfmts[i].colorspace; | |
960 | } | |
961 | ||
962 | mt9t112_frame_check(&mf->width, &mf->height, &left, &top); | |
858424b9 | 963 | |
858424b9 KM |
964 | mf->field = V4L2_FIELD_NONE; |
965 | ||
966 | return 0; | |
967 | } | |
968 | ||
3805f201 | 969 | static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index, |
858424b9 KM |
970 | enum v4l2_mbus_pixelcode *code) |
971 | { | |
ec34e1d5 GL |
972 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
973 | struct mt9t112_priv *priv = to_mt9t112(client); | |
974 | ||
975 | if (index >= priv->num_formats) | |
858424b9 KM |
976 | return -EINVAL; |
977 | ||
978 | *code = mt9t112_cfmts[index].code; | |
377c9ba7 | 979 | |
858424b9 KM |
980 | return 0; |
981 | } | |
982 | ||
d46ebd46 GL |
983 | static int mt9t112_g_mbus_config(struct v4l2_subdev *sd, |
984 | struct v4l2_mbus_config *cfg) | |
985 | { | |
986 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 987 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
d46ebd46 GL |
988 | |
989 | cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH | | |
990 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH | | |
991 | V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING; | |
992 | cfg->type = V4L2_MBUS_PARALLEL; | |
25a34811 | 993 | cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); |
d46ebd46 GL |
994 | |
995 | return 0; | |
996 | } | |
997 | ||
998 | static int mt9t112_s_mbus_config(struct v4l2_subdev *sd, | |
999 | const struct v4l2_mbus_config *cfg) | |
1000 | { | |
1001 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 1002 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
d46ebd46 GL |
1003 | struct mt9t112_priv *priv = to_mt9t112(client); |
1004 | ||
25a34811 | 1005 | if (soc_camera_apply_board_flags(ssdd, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING) |
d46ebd46 GL |
1006 | priv->flags |= PCLK_RISING; |
1007 | ||
1008 | return 0; | |
1009 | } | |
1010 | ||
858424b9 KM |
1011 | static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = { |
1012 | .s_stream = mt9t112_s_stream, | |
1013 | .g_mbus_fmt = mt9t112_g_fmt, | |
1014 | .s_mbus_fmt = mt9t112_s_fmt, | |
1015 | .try_mbus_fmt = mt9t112_try_fmt, | |
1016 | .cropcap = mt9t112_cropcap, | |
1017 | .g_crop = mt9t112_g_crop, | |
1018 | .s_crop = mt9t112_s_crop, | |
1019 | .enum_mbus_fmt = mt9t112_enum_fmt, | |
d46ebd46 GL |
1020 | .g_mbus_config = mt9t112_g_mbus_config, |
1021 | .s_mbus_config = mt9t112_s_mbus_config, | |
858424b9 KM |
1022 | }; |
1023 | ||
1024 | /************************************************************************ | |
858424b9 | 1025 | i2c driver |
858424b9 KM |
1026 | ************************************************************************/ |
1027 | static struct v4l2_subdev_ops mt9t112_subdev_ops = { | |
1028 | .core = &mt9t112_subdev_core_ops, | |
1029 | .video = &mt9t112_subdev_video_ops, | |
1030 | }; | |
1031 | ||
14178aa5 | 1032 | static int mt9t112_camera_probe(struct i2c_client *client) |
858424b9 KM |
1033 | { |
1034 | struct mt9t112_priv *priv = to_mt9t112(client); | |
1035 | const char *devname; | |
1036 | int chipid; | |
4bbc6d52 LP |
1037 | int ret; |
1038 | ||
1039 | ret = mt9t112_s_power(&priv->subdev, 1); | |
1040 | if (ret < 0) | |
1041 | return ret; | |
858424b9 | 1042 | |
858424b9 KM |
1043 | /* |
1044 | * check and show chip ID | |
1045 | */ | |
1046 | mt9t112_reg_read(chipid, client, 0x0000); | |
1047 | ||
1048 | switch (chipid) { | |
1049 | case 0x2680: | |
1050 | devname = "mt9t111"; | |
ec34e1d5 | 1051 | priv->num_formats = 1; |
858424b9 KM |
1052 | break; |
1053 | case 0x2682: | |
1054 | devname = "mt9t112"; | |
ec34e1d5 | 1055 | priv->num_formats = ARRAY_SIZE(mt9t112_cfmts); |
858424b9 KM |
1056 | break; |
1057 | default: | |
1058 | dev_err(&client->dev, "Product ID error %04x\n", chipid); | |
4bbc6d52 LP |
1059 | ret = -ENODEV; |
1060 | goto done; | |
858424b9 KM |
1061 | } |
1062 | ||
1063 | dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid); | |
1064 | ||
4bbc6d52 LP |
1065 | done: |
1066 | mt9t112_s_power(&priv->subdev, 0); | |
1067 | return ret; | |
858424b9 KM |
1068 | } |
1069 | ||
1070 | static int mt9t112_probe(struct i2c_client *client, | |
1071 | const struct i2c_device_id *did) | |
1072 | { | |
377c9ba7 | 1073 | struct mt9t112_priv *priv; |
25a34811 | 1074 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
377c9ba7 GL |
1075 | struct v4l2_rect rect = { |
1076 | .width = VGA_WIDTH, | |
1077 | .height = VGA_HEIGHT, | |
1078 | .left = (MAX_WIDTH - VGA_WIDTH) / 2, | |
1079 | .top = (MAX_HEIGHT - VGA_HEIGHT) / 2, | |
1080 | }; | |
1081 | int ret; | |
858424b9 | 1082 | |
25a34811 | 1083 | if (!ssdd || !ssdd->drv_priv) { |
14178aa5 | 1084 | dev_err(&client->dev, "mt9t112: missing platform data!\n"); |
858424b9 KM |
1085 | return -EINVAL; |
1086 | } | |
1087 | ||
70e176a5 | 1088 | priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); |
858424b9 KM |
1089 | if (!priv) |
1090 | return -ENOMEM; | |
1091 | ||
25a34811 | 1092 | priv->info = ssdd->drv_priv; |
858424b9 KM |
1093 | |
1094 | v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops); | |
1095 | ||
9aea470b GL |
1096 | priv->clk = v4l2_clk_get(&client->dev, "mclk"); |
1097 | if (IS_ERR(priv->clk)) | |
1098 | return PTR_ERR(priv->clk); | |
1099 | ||
14178aa5 | 1100 | ret = mt9t112_camera_probe(client); |
858424b9 | 1101 | |
377c9ba7 | 1102 | /* Cannot fail: using the default supported pixel code */ |
9aea470b GL |
1103 | if (!ret) |
1104 | mt9t112_set_params(priv, &rect, V4L2_MBUS_FMT_UYVY8_2X8); | |
1105 | else | |
1106 | v4l2_clk_put(priv->clk); | |
377c9ba7 | 1107 | |
858424b9 KM |
1108 | return ret; |
1109 | } | |
1110 | ||
9aea470b GL |
1111 | static int mt9t112_remove(struct i2c_client *client) |
1112 | { | |
1113 | struct mt9t112_priv *priv = to_mt9t112(client); | |
1114 | ||
1115 | v4l2_clk_put(priv->clk); | |
1116 | return 0; | |
1117 | } | |
1118 | ||
858424b9 KM |
1119 | static const struct i2c_device_id mt9t112_id[] = { |
1120 | { "mt9t112", 0 }, | |
1121 | { } | |
1122 | }; | |
1123 | MODULE_DEVICE_TABLE(i2c, mt9t112_id); | |
1124 | ||
1125 | static struct i2c_driver mt9t112_i2c_driver = { | |
1126 | .driver = { | |
1127 | .name = "mt9t112", | |
1128 | }, | |
1129 | .probe = mt9t112_probe, | |
9aea470b | 1130 | .remove = mt9t112_remove, |
858424b9 KM |
1131 | .id_table = mt9t112_id, |
1132 | }; | |
1133 | ||
c6e8d86f | 1134 | module_i2c_driver(mt9t112_i2c_driver); |
858424b9 KM |
1135 | |
1136 | MODULE_DESCRIPTION("SoC Camera driver for mt9t112"); | |
1137 | MODULE_AUTHOR("Kuninori Morimoto"); | |
1138 | MODULE_LICENSE("GPL v2"); |