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[media] soc-camera: split struct soc_camera_link into host and subdevice parts
[deliverable/linux.git] / drivers / media / i2c / soc_camera / mt9t112.c
CommitLineData
858424b9
KM		 1/*
2 * mt9t112 Camera Driver
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov772x driver, mt9m111 driver,
8 *
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
11 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
12 * Copyright (C) 2008 Magnus Damm
13 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/delay.h>
21#include <linux/i2c.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/slab.h>
95d20109 25#include <linux/v4l2-mediabus.h>
858424b9
KM		 26#include <linux/videodev2.h>
27
28#include <media/mt9t112.h>
29#include <media/soc_camera.h>
858424b9
KM		 30#include <media/v4l2-chip-ident.h>
31#include <media/v4l2-common.h>
32
33/* you can check PLL/clock info */
34/* #define EXT_CLOCK 24000000 */
35
36/************************************************************************
858424b9 37 macro
858424b9
KM		 38************************************************************************/
39/*
40 * frame size
41 */
42#define MAX_WIDTH 2048
43#define MAX_HEIGHT 1536
44
45#define VGA_WIDTH 640
46#define VGA_HEIGHT 480
47
48/*
49 * macro of read/write
50 */
51#define ECHECKER(ret, x) \
52 do { \
53 (ret) = (x); \
54 if ((ret) < 0) \
55 return (ret); \
56 } while (0)
57
58#define mt9t112_reg_write(ret, client, a, b) \
59 ECHECKER(ret, __mt9t112_reg_write(client, a, b))
60#define mt9t112_mcu_write(ret, client, a, b) \
61 ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
62
63#define mt9t112_reg_mask_set(ret, client, a, b, c) \
64 ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
65#define mt9t112_mcu_mask_set(ret, client, a, b, c) \
66 ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
67
68#define mt9t112_reg_read(ret, client, a) \
69 ECHECKER(ret, __mt9t112_reg_read(client, a))
70
71/*
72 * Logical address
73 */
74#define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff))
75#define VAR(id, offset) _VAR(id, offset, 0x0000)
76#define VAR8(id, offset) _VAR(id, offset, 0x8000)
77
78/************************************************************************
858424b9 79 struct
858424b9 80************************************************************************/
858424b9
KM		 81struct mt9t112_format {
82 enum v4l2_mbus_pixelcode code;
83 enum v4l2_colorspace colorspace;
84 u16 fmt;
85 u16 order;
86};
87
88struct mt9t112_priv {
89 struct v4l2_subdev subdev;
90 struct mt9t112_camera_info *info;
91 struct i2c_client *client;
377c9ba7 92 struct v4l2_rect frame;
858424b9
KM		 93 const struct mt9t112_format *format;
94 int model;
95 u32 flags;
96/* for flags */
d46ebd46
GL		 97#define INIT_DONE (1 << 0)
98#define PCLK_RISING (1 << 1)
858424b9
KM		 99};
100
101/************************************************************************
858424b9 102 supported format
858424b9
KM		 103************************************************************************/
104
105static const struct mt9t112_format mt9t112_cfmts[] = {
106 {
ace6e979 107 .code = V4L2_MBUS_FMT_UYVY8_2X8,
858424b9
KM		 108 .colorspace = V4L2_COLORSPACE_JPEG,
109 .fmt = 1,
110 .order = 0,
111 }, {
ace6e979 112 .code = V4L2_MBUS_FMT_VYUY8_2X8,
858424b9
KM		 113 .colorspace = V4L2_COLORSPACE_JPEG,
114 .fmt = 1,
115 .order = 1,
116 }, {
ace6e979 117 .code = V4L2_MBUS_FMT_YUYV8_2X8,
858424b9
KM		 118 .colorspace = V4L2_COLORSPACE_JPEG,
119 .fmt = 1,
120 .order = 2,
121 }, {
ace6e979 122 .code = V4L2_MBUS_FMT_YVYU8_2X8,
858424b9
KM		 123 .colorspace = V4L2_COLORSPACE_JPEG,
124 .fmt = 1,
125 .order = 3,
126 }, {
127 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
128 .colorspace = V4L2_COLORSPACE_SRGB,
129 .fmt = 8,
130 .order = 2,
131 }, {
132 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
133 .colorspace = V4L2_COLORSPACE_SRGB,
134 .fmt = 4,
135 .order = 2,
136 },
137};
138
139/************************************************************************
858424b9 140 general function
858424b9
KM		 141************************************************************************/
142static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
143{
144 return container_of(i2c_get_clientdata(client),
145 struct mt9t112_priv,
146 subdev);
147}
148
149static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
150{
151 struct i2c_msg msg[2];
152 u8 buf[2];
153 int ret;
154
155 command = swab16(command);
156
157 msg[0].addr = client->addr;
158 msg[0].flags = 0;
159 msg[0].len = 2;
160 msg[0].buf = (u8 *)&command;
161
162 msg[1].addr = client->addr;
163 msg[1].flags = I2C_M_RD;
164 msg[1].len = 2;
165 msg[1].buf = buf;
166
167 /*
168 * if return value of this function is < 0,
169 * it mean error.
170 * else, under 16bit is valid data.
171 */
172 ret = i2c_transfer(client->adapter, msg, 2);
173 if (ret < 0)
174 return ret;
175
176 memcpy(&ret, buf, 2);
177 return swab16(ret);
178}
179
180static int __mt9t112_reg_write(const struct i2c_client *client,
181 u16 command, u16 data)
182{
183 struct i2c_msg msg;
184 u8 buf[4];
185 int ret;
186
187 command = swab16(command);
188 data = swab16(data);
189
190 memcpy(buf + 0, &command, 2);
191 memcpy(buf + 2, &data, 2);
192
193 msg.addr = client->addr;
194 msg.flags = 0;
195 msg.len = 4;
196 msg.buf = buf;
197
198 /*
199 * i2c_transfer return message length,
200 * but this function should return 0 if correct case
201 */
202 ret = i2c_transfer(client->adapter, &msg, 1);
203 if (ret >= 0)
204 ret = 0;
205
206 return ret;
207}
208
209static int __mt9t112_reg_mask_set(const struct i2c_client *client,
210 u16 command,
211 u16 mask,
212 u16 set)
213{
214 int val = __mt9t112_reg_read(client, command);
215 if (val < 0)
216 return val;
217
218 val &= ~mask;
219 val |= set & mask;
220
221 return __mt9t112_reg_write(client, command, val);
222}
223
224/* mcu access */
225static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
226{
227 int ret;
228
229 ret = __mt9t112_reg_write(client, 0x098E, command);
230 if (ret < 0)
231 return ret;
232
233 return __mt9t112_reg_read(client, 0x0990);
234}
235
236static int __mt9t112_mcu_write(const struct i2c_client *client,
237 u16 command, u16 data)
238{
239 int ret;
240
241 ret = __mt9t112_reg_write(client, 0x098E, command);
242 if (ret < 0)
243 return ret;
244
245 return __mt9t112_reg_write(client, 0x0990, data);
246}
247
248static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
249 u16 command,
250 u16 mask,
251 u16 set)
252{
253 int val = __mt9t112_mcu_read(client, command);
254 if (val < 0)
255 return val;
256
257 val &= ~mask;
258 val |= set & mask;
259
260 return __mt9t112_mcu_write(client, command, val);
261}
262
263static int mt9t112_reset(const struct i2c_client *client)
264{
265 int ret;
266
267 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
268 msleep(1);
269 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
270
271 return ret;
272}
273
274#ifndef EXT_CLOCK
275#define CLOCK_INFO(a, b)
276#else
277#define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
278static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
279{
280 int m, n, p1, p2, p3, p4, p5, p6, p7;
281 u32 vco, clk;
282 char *enable;
283
284 ext /= 1000; /* kbyte order */
285
286 mt9t112_reg_read(n, client, 0x0012);
287 p1 = n & 0x000f;
288 n = n >> 4;
289 p2 = n & 0x000f;
290 n = n >> 4;
291 p3 = n & 0x000f;
292
293 mt9t112_reg_read(n, client, 0x002a);
294 p4 = n & 0x000f;
295 n = n >> 4;
296 p5 = n & 0x000f;
297 n = n >> 4;
298 p6 = n & 0x000f;
299
300 mt9t112_reg_read(n, client, 0x002c);
301 p7 = n & 0x000f;
302
303 mt9t112_reg_read(n, client, 0x0010);
304 m = n & 0x00ff;
305 n = (n >> 8) & 0x003f;
306
307 enable = ((6000 > ext) || (54000 < ext)) ? "X" : "";
14178aa5 308 dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable);
858424b9
KM		 309
310 vco = 2 * m * ext / (n+1);
311 enable = ((384000 > vco) || (768000 < vco)) ? "X" : "";
14178aa5 312 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable);
858424b9
KM		 313
314 clk = vco / (p1+1) / (p2+1);
315 enable = (96000 < clk) ? "X" : "";
14178aa5 316 dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable);
858424b9
KM		 317
318 clk = vco / (p3+1);
319 enable = (768000 < clk) ? "X" : "";
14178aa5 320 dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable);
858424b9
KM		 321
322 clk = vco / (p6+1);
323 enable = (96000 < clk) ? "X" : "";
14178aa5 324 dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable);
858424b9
KM		 325
326 clk = vco / (p5+1);
327 enable = (54000 < clk) ? "X" : "";
14178aa5 328 dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable);
858424b9
KM		 329
330 clk = vco / (p4+1);
331 enable = (70000 < clk) ? "X" : "";
14178aa5 332 dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable);
858424b9
KM		 333
334 clk = vco / (p7+1);
14178aa5 335 dev_dbg(&client->dev, "External sensor : %10u K\n", clk);
858424b9
KM		 336
337 clk = ext / (n+1);
338 enable = ((2000 > clk) || (24000 < clk)) ? "X" : "";
14178aa5 339 dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable);
858424b9
KM		 340
341 return 0;
342}
343#endif
344
377c9ba7 345static void mt9t112_frame_check(u32 *width, u32 *height, u32 *left, u32 *top)
858424b9 346{
377c9ba7
GL		 347 soc_camera_limit_side(left, width, 0, 0, MAX_WIDTH);
348 soc_camera_limit_side(top, height, 0, 0, MAX_HEIGHT);
858424b9
KM		 349}
350
351static int mt9t112_set_a_frame_size(const struct i2c_client *client,
352 u16 width,
353 u16 height)
354{
355 int ret;
356 u16 wstart = (MAX_WIDTH - width) / 2;
357 u16 hstart = (MAX_HEIGHT - height) / 2;
358
359 /* (Context A) Image Width/Height */
360 mt9t112_mcu_write(ret, client, VAR(26, 0), width);
361 mt9t112_mcu_write(ret, client, VAR(26, 2), height);
362
363 /* (Context A) Output Width/Height */
364 mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
365 mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
366
367 /* (Context A) Start Row/Column */
368 mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
369 mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
370
371 /* (Context A) End Row/Column */
372 mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
373 mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart);
374
375 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
376
377 return ret;
378}
379
380static int mt9t112_set_pll_dividers(const struct i2c_client *client,
381 u8 m, u8 n,
382 u8 p1, u8 p2, u8 p3,
383 u8 p4, u8 p5, u8 p6,
384 u8 p7)
385{
386 int ret;
387 u16 val;
388
389 /* N/M */
390 val = (n << 8) |
391 (m << 0);
392 mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
393
394 /* P1/P2/P3 */
395 val = ((p3 & 0x0F) << 8) |
396 ((p2 & 0x0F) << 4) |
397 ((p1 & 0x0F) << 0);
398 mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
399
400 /* P4/P5/P6 */
401 val = (0x7 << 12) |
402 ((p6 & 0x0F) << 8) |
403 ((p5 & 0x0F) << 4) |
404 ((p4 & 0x0F) << 0);
405 mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
406
407 /* P7 */
408 val = (0x1 << 12) |
409 ((p7 & 0x0F) << 0);
410 mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
411
412 return ret;
413}
414
415static int mt9t112_init_pll(const struct i2c_client *client)
416{
417 struct mt9t112_priv *priv = to_mt9t112(client);
418 int data, i, ret;
419
420 mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
421
422 /* PLL control: BYPASS PLL = 8517 */
423 mt9t112_reg_write(ret, client, 0x0014, 0x2145);
424
425 /* Replace these registers when new timing parameters are generated */
426 mt9t112_set_pll_dividers(client,
427 priv->info->divider.m,
428 priv->info->divider.n,
429 priv->info->divider.p1,
430 priv->info->divider.p2,
431 priv->info->divider.p3,
432 priv->info->divider.p4,
433 priv->info->divider.p5,
434 priv->info->divider.p6,
435 priv->info->divider.p7);
436
437 /*
438 * TEST_BYPASS on
439 * PLL_ENABLE on
440 * SEL_LOCK_DET on
441 * TEST_BYPASS off
442 */
443 mt9t112_reg_write(ret, client, 0x0014, 0x2525);
444 mt9t112_reg_write(ret, client, 0x0014, 0x2527);
445 mt9t112_reg_write(ret, client, 0x0014, 0x3427);
446 mt9t112_reg_write(ret, client, 0x0014, 0x3027);
447
448 mdelay(10);
449
450 /*
451 * PLL_BYPASS off
452 * Reference clock count
453 * I2C Master Clock Divider
454 */
455 mt9t112_reg_write(ret, client, 0x0014, 0x3046);
61282daf 456 mt9t112_reg_write(ret, client, 0x0016, 0x0400); /* JPEG initialization workaround */
858424b9
KM		 457 mt9t112_reg_write(ret, client, 0x0022, 0x0190);
458 mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
459
460 /* External sensor clock is PLL bypass */
461 mt9t112_reg_write(ret, client, 0x002E, 0x0500);
462
463 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
464 mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
465
466 /* MCU disabled */
467 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
468
469 /* out of standby */
470 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
471
472 mdelay(50);
473
474 /*
475 * Standby Workaround
476 * Disable Secondary I2C Pads
477 */
478 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
479 mdelay(1);
480 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
481 mdelay(1);
482 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
483 mdelay(1);
484 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
485 mdelay(1);
486 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
487 mdelay(1);
488 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
489 mdelay(1);
490
491 /* poll to verify out of standby. Must Poll this bit */
492 for (i = 0; i < 100; i++) {
493 mt9t112_reg_read(data, client, 0x0018);
2b59125b 494 if (!(0x4000 & data))
858424b9
KM		 495 break;
496
497 mdelay(10);
498 }
499
500 return ret;
501}
502
503static int mt9t112_init_setting(const struct i2c_client *client)
504{
505
506 int ret;
507
508 /* Adaptive Output Clock (A) */
509 mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
510
511 /* Read Mode (A) */
512 mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
513
514 /* Fine Correction (A) */
515 mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
516
517 /* Fine IT Min (A) */
518 mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
519
520 /* Fine IT Max Margin (A) */
521 mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
522
523 /* Base Frame Lines (A) */
524 mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
525
526 /* Min Line Length (A) */
527 mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
528
529 /* Line Length (A) */
530 mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
531
532 /* Adaptive Output Clock (B) */
533 mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
534
535 /* Row Start (B) */
536 mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
537
538 /* Column Start (B) */
539 mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
540
541 /* Row End (B) */
542 mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
543
544 /* Column End (B) */
545 mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
546
547 /* Fine Correction (B) */
548 mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
549
550 /* Fine IT Min (B) */
551 mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
552
553 /* Fine IT Max Margin (B) */
554 mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
555
556 /* Base Frame Lines (B) */
557 mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
558
559 /* Min Line Length (B) */
560 mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
561
562 /* Line Length (B) */
563 mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
564
565 /*
566 * Flicker Dectection registers
567 * This section should be replaced whenever new Timing file is generated
568 * All the following registers need to be replaced
569 * Following registers are generated from Register Wizard but user can
570 * modify them. For detail see auto flicker detection tuning
571 */
572
573 /* FD_FDPERIOD_SELECT */
574 mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
575
576 /* PRI_B_CONFIG_FD_ALGO_RUN */
577 mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
578
579 /* PRI_A_CONFIG_FD_ALGO_RUN */
580 mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
581
582 /*
583 * AFD range detection tuning registers
584 */
585
586 /* search_f1_50 */
587 mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
588
589 /* search_f2_50 */
590 mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
591
592 /* search_f1_60 */
593 mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
594
595 /* search_f2_60 */
596 mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
597
598 /* period_50Hz (A) */
599 mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
600
601 /* secret register by aptina */
602 /* period_50Hz (A MSB) */
603 mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
604
605 /* period_60Hz (A) */
606 mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
607
608 /* secret register by aptina */
609 /* period_60Hz (A MSB) */
610 mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
611
612 /* period_50Hz (B) */
613 mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
614
615 /* secret register by aptina */
616 /* period_50Hz (B) MSB */
617 mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
618
619 /* period_60Hz (B) */
620 mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
621
622 /* secret register by aptina */
623 /* period_60Hz (B) MSB */
624 mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
625
626 /* FD Mode */
627 mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
628
629 /* Stat_min */
630 mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
631
632 /* Stat_max */
633 mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
634
635 /* Min_amplitude */
636 mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
637
638 /* RX FIFO Watermark (A) */
639 mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
640
641 /* RX FIFO Watermark (B) */
642 mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
643
644 /* MCLK: 16MHz
645 * PCLK: 73MHz
646 * CorePixCLK: 36.5 MHz
647 */
648 mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
649 mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
650 mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
651 mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
652
653 mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
654 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
655 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
656 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
657
658 return ret;
659}
660
661static int mt9t112_auto_focus_setting(const struct i2c_client *client)
662{
663 int ret;
664
665 mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
666 mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
667 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
668
669 mt9t112_reg_write(ret, client, 0x0614, 0x0000);
670
671 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
672 mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
673 mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002);
674 mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001);
675 mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
676 mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
677 mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18);
678 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
679
680 return ret;
681}
682
683static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
684{
685 int ret;
686
687 mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
688
689 return ret;
690}
691
692static int mt9t112_init_camera(const struct i2c_client *client)
693{
694 int ret;
695
696 ECHECKER(ret, mt9t112_reset(client));
697
698 ECHECKER(ret, mt9t112_init_pll(client));
699
700 ECHECKER(ret, mt9t112_init_setting(client));
701
702 ECHECKER(ret, mt9t112_auto_focus_setting(client));
703
704 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
705
706 /* Analog setting B */
707 mt9t112_reg_write(ret, client, 0x3084, 0x2409);
708 mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
709 mt9t112_reg_write(ret, client, 0x3094, 0x4949);
710 mt9t112_reg_write(ret, client, 0x3096, 0x4950);
711
712 /*
713 * Disable adaptive clock
714 * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
715 * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
716 */
717 mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
718 mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
719
720 /* Configure STatus in Status_before_length Format and enable header */
721 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
722 mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
723
724 /* Enable JPEG in context B */
725 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
726 mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
727
728 /* Disable Dac_TXLO */
729 mt9t112_reg_write(ret, client, 0x316C, 0x350F);
730
731 /* Set max slew rates */
732 mt9t112_reg_write(ret, client, 0x1E, 0x777);
733
734 return ret;
735}
736
858424b9 737/************************************************************************
858424b9 738 v4l2_subdev_core_ops
858424b9
KM		 739************************************************************************/
740static int mt9t112_g_chip_ident(struct v4l2_subdev *sd,
741 struct v4l2_dbg_chip_ident *id)
742{
c4ce6d14 743 struct i2c_client *client = v4l2_get_subdevdata(sd);
858424b9
KM		 744 struct mt9t112_priv *priv = to_mt9t112(client);
745
746 id->ident = priv->model;
747 id->revision = 0;
748
749 return 0;
750}
751
752#ifdef CONFIG_VIDEO_ADV_DEBUG
753static int mt9t112_g_register(struct v4l2_subdev *sd,
754 struct v4l2_dbg_register *reg)
755{
c4ce6d14 756 struct i2c_client *client = v4l2_get_subdevdata(sd);
858424b9
KM		 757 int ret;
758
759 reg->size = 2;
760 mt9t112_reg_read(ret, client, reg->reg);
761
762 reg->val = (__u64)ret;
763
764 return 0;
765}
766
767static int mt9t112_s_register(struct v4l2_subdev *sd,
768 struct v4l2_dbg_register *reg)
769{
c4ce6d14 770 struct i2c_client *client = v4l2_get_subdevdata(sd);
858424b9
KM		 771 int ret;
772
773 mt9t112_reg_write(ret, client, reg->reg, reg->val);
774
775 return ret;
776}
777#endif
778
4ec10bac
LP		 779static int mt9t112_s_power(struct v4l2_subdev *sd, int on)
780{
781 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 782 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
4ec10bac 783
25a34811 784 return soc_camera_set_power(&client->dev, ssdd, on);
4ec10bac
LP		 785}
786
858424b9
KM		 787static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
788 .g_chip_ident = mt9t112_g_chip_ident,
789#ifdef CONFIG_VIDEO_ADV_DEBUG
790 .g_register = mt9t112_g_register,
791 .s_register = mt9t112_s_register,
792#endif
4ec10bac 793 .s_power = mt9t112_s_power,
858424b9
KM		 794};
795
796
797/************************************************************************
858424b9 798 v4l2_subdev_video_ops
858424b9
KM		 799************************************************************************/
800static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
801{
c4ce6d14 802 struct i2c_client *client = v4l2_get_subdevdata(sd);
858424b9
KM		 803 struct mt9t112_priv *priv = to_mt9t112(client);
804 int ret = 0;
805
806 if (!enable) {
807 /* FIXME
808 *
809 * If user selected large output size,
810 * and used it long time,
811 * mt9t112 camera will be very warm.
812 *
813 * But current driver can not stop mt9t112 camera.
814 * So, set small size here to solve this problem.
815 */
816 mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
817 return ret;
818 }
819
820 if (!(priv->flags & INIT_DONE)) {
d46ebd46 821 u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000;
858424b9
KM		 822
823 ECHECKER(ret, mt9t112_init_camera(client));
824
825 /* Invert PCLK (Data sampled on falling edge of pixclk) */
826 mt9t112_reg_write(ret, client, 0x3C20, param);
827
828 mdelay(5);
829
830 priv->flags |= INIT_DONE;
831 }
832
833 mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
834 mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
835 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
836
837 mt9t112_set_a_frame_size(client,
838 priv->frame.width,
839 priv->frame.height);
840
841 ECHECKER(ret, mt9t112_auto_focus_trigger(client));
842
843 dev_dbg(&client->dev, "format : %d\n", priv->format->code);
844 dev_dbg(&client->dev, "size : %d x %d\n",
845 priv->frame.width,
846 priv->frame.height);
847
848 CLOCK_INFO(client, EXT_CLOCK);
849
850 return ret;
851}
852
377c9ba7
GL		 853static int mt9t112_set_params(struct mt9t112_priv *priv,
854 const struct v4l2_rect *rect,
858424b9
KM		 855 enum v4l2_mbus_pixelcode code)
856{
858424b9
KM		 857 int i;
858
858424b9
KM		 859 /*
860 * get color format
861 */
862 for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
863 if (mt9t112_cfmts[i].code == code)
864 break;
865
866 if (i == ARRAY_SIZE(mt9t112_cfmts))
867 return -EINVAL;
868
377c9ba7
GL		 869 priv->frame = *rect;
870
871 /*
872 * frame size check
873 */
874 mt9t112_frame_check(&priv->frame.width, &priv->frame.height,
875 &priv->frame.left, &priv->frame.top);
858424b9
KM		 876
877 priv->format = mt9t112_cfmts + i;
878
879 return 0;
880}
881
882static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
883{
884 a->bounds.left = 0;
885 a->bounds.top = 0;
377c9ba7
GL		 886 a->bounds.width = MAX_WIDTH;
887 a->bounds.height = MAX_HEIGHT;
888 a->defrect.left = 0;
889 a->defrect.top = 0;
890 a->defrect.width = VGA_WIDTH;
891 a->defrect.height = VGA_HEIGHT;
858424b9
KM		 892 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
893 a->pixelaspect.numerator = 1;
894 a->pixelaspect.denominator = 1;
895
896 return 0;
897}
898
899static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
900{
377c9ba7
GL		 901 struct i2c_client *client = v4l2_get_subdevdata(sd);
902 struct mt9t112_priv *priv = to_mt9t112(client);
903
904 a->c = priv->frame;
905 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
858424b9
KM		 906
907 return 0;
908}
909
4f996594 910static int mt9t112_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
858424b9 911{
c4ce6d14 912 struct i2c_client *client = v4l2_get_subdevdata(sd);
377c9ba7 913 struct mt9t112_priv *priv = to_mt9t112(client);
4f996594 914 const struct v4l2_rect *rect = &a->c;
858424b9 915
377c9ba7 916 return mt9t112_set_params(priv, rect, priv->format->code);
858424b9
KM		 917}
918
919static int mt9t112_g_fmt(struct v4l2_subdev *sd,
920 struct v4l2_mbus_framefmt *mf)
921{
c4ce6d14 922 struct i2c_client *client = v4l2_get_subdevdata(sd);
858424b9
KM		 923 struct mt9t112_priv *priv = to_mt9t112(client);
924
858424b9
KM		 925 mf->width = priv->frame.width;
926 mf->height = priv->frame.height;
377c9ba7 927 mf->colorspace = priv->format->colorspace;
858424b9
KM		 928 mf->code = priv->format->code;
929 mf->field = V4L2_FIELD_NONE;
930
931 return 0;
932}
933
934static int mt9t112_s_fmt(struct v4l2_subdev *sd,
935 struct v4l2_mbus_framefmt *mf)
936{
c4ce6d14 937 struct i2c_client *client = v4l2_get_subdevdata(sd);
377c9ba7
GL		 938 struct mt9t112_priv *priv = to_mt9t112(client);
939 struct v4l2_rect rect = {
940 .width = mf->width,
941 .height = mf->height,
942 .left = priv->frame.left,
943 .top = priv->frame.top,
944 };
945 int ret;
946
947 ret = mt9t112_set_params(priv, &rect, mf->code);
948
949 if (!ret)
950 mf->colorspace = priv->format->colorspace;
858424b9 951
377c9ba7 952 return ret;
858424b9
KM		 953}
954
955static int mt9t112_try_fmt(struct v4l2_subdev *sd,
956 struct v4l2_mbus_framefmt *mf)
957{
377c9ba7
GL		 958 unsigned int top, left;
959 int i;
960
961 for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
962 if (mt9t112_cfmts[i].code == mf->code)
963 break;
964
965 if (i == ARRAY_SIZE(mt9t112_cfmts)) {
966 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
967 mf->colorspace = V4L2_COLORSPACE_JPEG;
968 } else {
969 mf->colorspace = mt9t112_cfmts[i].colorspace;
970 }
971
972 mt9t112_frame_check(&mf->width, &mf->height, &left, &top);
858424b9 973
858424b9
KM		 974 mf->field = V4L2_FIELD_NONE;
975
976 return 0;
977}
978
3805f201 979static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
858424b9
KM		 980 enum v4l2_mbus_pixelcode *code)
981{
3805f201 982 if (index >= ARRAY_SIZE(mt9t112_cfmts))
858424b9
KM		 983 return -EINVAL;
984
985 *code = mt9t112_cfmts[index].code;
377c9ba7 986
858424b9
KM		 987 return 0;
988}
989
d46ebd46
GL		 990static int mt9t112_g_mbus_config(struct v4l2_subdev *sd,
991 struct v4l2_mbus_config *cfg)
992{
993 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 994 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
d46ebd46
GL		 995
996 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
997 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH |
998 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING;
999 cfg->type = V4L2_MBUS_PARALLEL;
25a34811 1000 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
d46ebd46
GL		 1001
1002 return 0;
1003}
1004
1005static int mt9t112_s_mbus_config(struct v4l2_subdev *sd,
1006 const struct v4l2_mbus_config *cfg)
1007{
1008 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 1009 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
d46ebd46
GL		 1010 struct mt9t112_priv *priv = to_mt9t112(client);
1011
25a34811 1012 if (soc_camera_apply_board_flags(ssdd, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING)
d46ebd46
GL		 1013 priv->flags |= PCLK_RISING;
1014
1015 return 0;
1016}
1017
858424b9
KM		 1018static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
1019 .s_stream = mt9t112_s_stream,
1020 .g_mbus_fmt = mt9t112_g_fmt,
1021 .s_mbus_fmt = mt9t112_s_fmt,
1022 .try_mbus_fmt = mt9t112_try_fmt,
1023 .cropcap = mt9t112_cropcap,
1024 .g_crop = mt9t112_g_crop,
1025 .s_crop = mt9t112_s_crop,
1026 .enum_mbus_fmt = mt9t112_enum_fmt,
d46ebd46
GL		 1027 .g_mbus_config = mt9t112_g_mbus_config,
1028 .s_mbus_config = mt9t112_s_mbus_config,
858424b9
KM		 1029};
1030
1031/************************************************************************
858424b9 1032 i2c driver
858424b9
KM		 1033************************************************************************/
1034static struct v4l2_subdev_ops mt9t112_subdev_ops = {
1035 .core = &mt9t112_subdev_core_ops,
1036 .video = &mt9t112_subdev_video_ops,
1037};
1038
14178aa5 1039static int mt9t112_camera_probe(struct i2c_client *client)
858424b9
KM		 1040{
1041 struct mt9t112_priv *priv = to_mt9t112(client);
1042 const char *devname;
1043 int chipid;
4bbc6d52
LP		 1044 int ret;
1045
1046 ret = mt9t112_s_power(&priv->subdev, 1);
1047 if (ret < 0)
1048 return ret;
858424b9 1049
858424b9
KM		 1050 /*
1051 * check and show chip ID
1052 */
1053 mt9t112_reg_read(chipid, client, 0x0000);
1054
1055 switch (chipid) {
1056 case 0x2680:
1057 devname = "mt9t111";
1058 priv->model = V4L2_IDENT_MT9T111;
1059 break;
1060 case 0x2682:
1061 devname = "mt9t112";
1062 priv->model = V4L2_IDENT_MT9T112;
1063 break;
1064 default:
1065 dev_err(&client->dev, "Product ID error %04x\n", chipid);
4bbc6d52
LP		 1066 ret = -ENODEV;
1067 goto done;
858424b9
KM		 1068 }
1069
1070 dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
1071
4bbc6d52
LP		 1072done:
1073 mt9t112_s_power(&priv->subdev, 0);
1074 return ret;
858424b9
KM		 1075}
1076
1077static int mt9t112_probe(struct i2c_client *client,
1078 const struct i2c_device_id *did)
1079{
377c9ba7 1080 struct mt9t112_priv *priv;
25a34811 1081 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
377c9ba7
GL		 1082 struct v4l2_rect rect = {
1083 .width = VGA_WIDTH,
1084 .height = VGA_HEIGHT,
1085 .left = (MAX_WIDTH - VGA_WIDTH) / 2,
1086 .top = (MAX_HEIGHT - VGA_HEIGHT) / 2,
1087 };
1088 int ret;
858424b9 1089
25a34811 1090 if (!ssdd || !ssdd->drv_priv) {
14178aa5 1091 dev_err(&client->dev, "mt9t112: missing platform data!\n");
858424b9
KM		 1092 return -EINVAL;
1093 }
1094
858424b9
KM		 1095 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1096 if (!priv)
1097 return -ENOMEM;
1098
25a34811 1099 priv->info = ssdd->drv_priv;
858424b9
KM		 1100
1101 v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
1102
14178aa5 1103 ret = mt9t112_camera_probe(client);
e4691835 1104 if (ret) {
858424b9 1105 kfree(priv);
e4691835
DC		 1106 return ret;
1107 }
858424b9 1108
377c9ba7
GL		 1109 /* Cannot fail: using the default supported pixel code */
1110 mt9t112_set_params(priv, &rect, V4L2_MBUS_FMT_UYVY8_2X8);
1111
858424b9
KM		 1112 return ret;
1113}
1114
1115static int mt9t112_remove(struct i2c_client *client)
1116{
1117 struct mt9t112_priv *priv = to_mt9t112(client);
858424b9 1118
858424b9
KM		 1119 kfree(priv);
1120 return 0;
1121}
1122
1123static const struct i2c_device_id mt9t112_id[] = {
1124 { "mt9t112", 0 },
1125 { }
1126};
1127MODULE_DEVICE_TABLE(i2c, mt9t112_id);
1128
1129static struct i2c_driver mt9t112_i2c_driver = {
1130 .driver = {
1131 .name = "mt9t112",
1132 },
1133 .probe = mt9t112_probe,
1134 .remove = mt9t112_remove,
1135 .id_table = mt9t112_id,
1136};
1137
c6e8d86f 1138module_i2c_driver(mt9t112_i2c_driver);
858424b9
KM		 1139
1140MODULE_DESCRIPTION("SoC Camera driver for mt9t112");
1141MODULE_AUTHOR("Kuninori Morimoto");
1142MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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