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7397bfbe GL |
1 | /* |
2 | * Driver for MT9V022 CMOS Image Sensor from Micron | |
3 | * | |
4 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
11 | #include <linux/videodev2.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/i2c.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/log2.h> | |
7a707b89 | 16 | #include <linux/module.h> |
7397bfbe | 17 | |
b6f50b49 | 18 | #include <media/mt9v022.h> |
e8e2c70c GL |
19 | #include <media/soc_camera.h> |
20 | #include <media/soc_mediabus.h> | |
979ea1dd | 21 | #include <media/v4l2-subdev.h> |
ab7b50ae | 22 | #include <media/v4l2-ctrls.h> |
7397bfbe | 23 | |
5d28d525 GL |
24 | /* |
25 | * mt9v022 i2c address 0x48, 0x4c, 0x58, 0x5c | |
22cf83fa | 26 | * The platform has to define struct i2c_board_info objects and link to them |
25a34811 | 27 | * from struct soc_camera_host_desc |
5d28d525 | 28 | */ |
7397bfbe GL |
29 | |
30 | static char *sensor_type; | |
31 | module_param(sensor_type, charp, S_IRUGO); | |
61a2d07d | 32 | MODULE_PARM_DESC(sensor_type, "Sensor type: \"colour\" or \"monochrome\""); |
7397bfbe GL |
33 | |
34 | /* mt9v022 selected register addresses */ | |
35 | #define MT9V022_CHIP_VERSION 0x00 | |
36 | #define MT9V022_COLUMN_START 0x01 | |
37 | #define MT9V022_ROW_START 0x02 | |
38 | #define MT9V022_WINDOW_HEIGHT 0x03 | |
39 | #define MT9V022_WINDOW_WIDTH 0x04 | |
40 | #define MT9V022_HORIZONTAL_BLANKING 0x05 | |
41 | #define MT9V022_VERTICAL_BLANKING 0x06 | |
42 | #define MT9V022_CHIP_CONTROL 0x07 | |
43 | #define MT9V022_SHUTTER_WIDTH1 0x08 | |
44 | #define MT9V022_SHUTTER_WIDTH2 0x09 | |
45 | #define MT9V022_SHUTTER_WIDTH_CTRL 0x0a | |
46 | #define MT9V022_TOTAL_SHUTTER_WIDTH 0x0b | |
47 | #define MT9V022_RESET 0x0c | |
48 | #define MT9V022_READ_MODE 0x0d | |
49 | #define MT9V022_MONITOR_MODE 0x0e | |
50 | #define MT9V022_PIXEL_OPERATION_MODE 0x0f | |
51 | #define MT9V022_LED_OUT_CONTROL 0x1b | |
52 | #define MT9V022_ADC_MODE_CONTROL 0x1c | |
d0bac768 | 53 | #define MT9V022_REG32 0x20 |
96c75399 | 54 | #define MT9V022_ANALOG_GAIN 0x35 |
7397bfbe GL |
55 | #define MT9V022_BLACK_LEVEL_CALIB_CTRL 0x47 |
56 | #define MT9V022_PIXCLK_FV_LV 0x74 | |
57 | #define MT9V022_DIGITAL_TEST_PATTERN 0x7f | |
58 | #define MT9V022_AEC_AGC_ENABLE 0xAF | |
59 | #define MT9V022_MAX_TOTAL_SHUTTER_WIDTH 0xBD | |
60 | ||
c078ac18 AG |
61 | /* mt9v024 partial list register addresses changes with respect to mt9v022 */ |
62 | #define MT9V024_PIXCLK_FV_LV 0x72 | |
63 | #define MT9V024_MAX_TOTAL_SHUTTER_WIDTH 0xAD | |
64 | ||
7397bfbe GL |
65 | /* Progressive scan, master, defaults */ |
66 | #define MT9V022_CHIP_CONTROL_DEFAULT 0x188 | |
67 | ||
6a6c8786 GL |
68 | #define MT9V022_MAX_WIDTH 752 |
69 | #define MT9V022_MAX_HEIGHT 480 | |
70 | #define MT9V022_MIN_WIDTH 48 | |
71 | #define MT9V022_MIN_HEIGHT 32 | |
72 | #define MT9V022_COLUMN_SKIP 1 | |
73 | #define MT9V022_ROW_SKIP 4 | |
74 | ||
6cc1eb70 AG |
75 | #define MT9V022_HORIZONTAL_BLANKING_MIN 43 |
76 | #define MT9V022_HORIZONTAL_BLANKING_MAX 1023 | |
77 | #define MT9V022_HORIZONTAL_BLANKING_DEF 94 | |
78 | #define MT9V022_VERTICAL_BLANKING_MIN 2 | |
79 | #define MT9V022_VERTICAL_BLANKING_MAX 3000 | |
80 | #define MT9V022_VERTICAL_BLANKING_DEF 45 | |
81 | ||
d0bac768 AG |
82 | #define is_mt9v022_rev3(id) (id == 0x1313) |
83 | #define is_mt9v024(id) (id == 0x1324) | |
c078ac18 | 84 | |
760697be GL |
85 | /* MT9V022 has only one fixed colorspace per pixelcode */ |
86 | struct mt9v022_datafmt { | |
87 | enum v4l2_mbus_pixelcode code; | |
88 | enum v4l2_colorspace colorspace; | |
89 | }; | |
90 | ||
91 | /* Find a data format by a pixel code in an array */ | |
92 | static const struct mt9v022_datafmt *mt9v022_find_datafmt( | |
93 | enum v4l2_mbus_pixelcode code, const struct mt9v022_datafmt *fmt, | |
94 | int n) | |
95 | { | |
96 | int i; | |
97 | for (i = 0; i < n; i++) | |
98 | if (fmt[i].code == code) | |
99 | return fmt + i; | |
100 | ||
101 | return NULL; | |
102 | } | |
103 | ||
104 | static const struct mt9v022_datafmt mt9v022_colour_fmts[] = { | |
5d28d525 GL |
105 | /* |
106 | * Order important: first natively supported, | |
107 | * second supported with a GPIO extender | |
108 | */ | |
760697be GL |
109 | {V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB}, |
110 | {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB}, | |
bb55de3b GL |
111 | }; |
112 | ||
760697be | 113 | static const struct mt9v022_datafmt mt9v022_monochrome_fmts[] = { |
bb55de3b | 114 | /* Order important - see above */ |
760697be | 115 | {V4L2_MBUS_FMT_Y10_1X10, V4L2_COLORSPACE_JPEG}, |
07670433 | 116 | {V4L2_MBUS_FMT_Y8_1X8, V4L2_COLORSPACE_JPEG}, |
7397bfbe GL |
117 | }; |
118 | ||
c078ac18 AG |
119 | /* only registers with different addresses on different mt9v02x sensors */ |
120 | struct mt9v02x_register { | |
121 | u8 max_total_shutter_width; | |
122 | u8 pixclk_fv_lv; | |
123 | }; | |
124 | ||
125 | static const struct mt9v02x_register mt9v022_register = { | |
126 | .max_total_shutter_width = MT9V022_MAX_TOTAL_SHUTTER_WIDTH, | |
127 | .pixclk_fv_lv = MT9V022_PIXCLK_FV_LV, | |
128 | }; | |
129 | ||
130 | static const struct mt9v02x_register mt9v024_register = { | |
131 | .max_total_shutter_width = MT9V024_MAX_TOTAL_SHUTTER_WIDTH, | |
132 | .pixclk_fv_lv = MT9V024_PIXCLK_FV_LV, | |
133 | }; | |
134 | ||
6be89daa HV |
135 | enum mt9v022_model { |
136 | MT9V022IX7ATM, | |
137 | MT9V022IX7ATC, | |
138 | }; | |
139 | ||
7397bfbe | 140 | struct mt9v022 { |
979ea1dd | 141 | struct v4l2_subdev subdev; |
ab7b50ae HV |
142 | struct v4l2_ctrl_handler hdl; |
143 | struct { | |
144 | /* exposure/auto-exposure cluster */ | |
145 | struct v4l2_ctrl *autoexposure; | |
146 | struct v4l2_ctrl *exposure; | |
147 | }; | |
148 | struct { | |
149 | /* gain/auto-gain cluster */ | |
150 | struct v4l2_ctrl *autogain; | |
151 | struct v4l2_ctrl *gain; | |
152 | }; | |
6cc1eb70 AG |
153 | struct v4l2_ctrl *hblank; |
154 | struct v4l2_ctrl *vblank; | |
6a6c8786 | 155 | struct v4l2_rect rect; /* Sensor window */ |
760697be GL |
156 | const struct mt9v022_datafmt *fmt; |
157 | const struct mt9v022_datafmt *fmts; | |
c078ac18 | 158 | const struct mt9v02x_register *reg; |
760697be | 159 | int num_fmts; |
6be89daa | 160 | enum mt9v022_model model; |
7397bfbe | 161 | u16 chip_control; |
d0bac768 | 162 | u16 chip_version; |
32536108 | 163 | unsigned short y_skip_top; /* Lines to skip at the top */ |
7397bfbe GL |
164 | }; |
165 | ||
979ea1dd GL |
166 | static struct mt9v022 *to_mt9v022(const struct i2c_client *client) |
167 | { | |
168 | return container_of(i2c_get_clientdata(client), struct mt9v022, subdev); | |
169 | } | |
170 | ||
9538e1c2 | 171 | static int reg_read(struct i2c_client *client, const u8 reg) |
7397bfbe | 172 | { |
3f877045 | 173 | return i2c_smbus_read_word_swapped(client, reg); |
7397bfbe GL |
174 | } |
175 | ||
9538e1c2 | 176 | static int reg_write(struct i2c_client *client, const u8 reg, |
7397bfbe GL |
177 | const u16 data) |
178 | { | |
3f877045 | 179 | return i2c_smbus_write_word_swapped(client, reg, data); |
7397bfbe GL |
180 | } |
181 | ||
9538e1c2 | 182 | static int reg_set(struct i2c_client *client, const u8 reg, |
7397bfbe GL |
183 | const u16 data) |
184 | { | |
185 | int ret; | |
186 | ||
9538e1c2 | 187 | ret = reg_read(client, reg); |
7397bfbe GL |
188 | if (ret < 0) |
189 | return ret; | |
9538e1c2 | 190 | return reg_write(client, reg, ret | data); |
7397bfbe GL |
191 | } |
192 | ||
9538e1c2 | 193 | static int reg_clear(struct i2c_client *client, const u8 reg, |
7397bfbe GL |
194 | const u16 data) |
195 | { | |
196 | int ret; | |
197 | ||
9538e1c2 | 198 | ret = reg_read(client, reg); |
7397bfbe GL |
199 | if (ret < 0) |
200 | return ret; | |
9538e1c2 | 201 | return reg_write(client, reg, ret & ~data); |
7397bfbe GL |
202 | } |
203 | ||
a4c56fd8 | 204 | static int mt9v022_init(struct i2c_client *client) |
7397bfbe | 205 | { |
979ea1dd | 206 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
7397bfbe GL |
207 | int ret; |
208 | ||
5d28d525 GL |
209 | /* |
210 | * Almost the default mode: master, parallel, simultaneous, and an | |
7397bfbe | 211 | * undocumented bit 0x200, which is present in table 7, but not in 8, |
5d28d525 GL |
212 | * plus snapshot mode to disable scan for now |
213 | */ | |
7397bfbe | 214 | mt9v022->chip_control |= 0x10; |
9538e1c2 | 215 | ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control); |
11211641 | 216 | if (!ret) |
9538e1c2 | 217 | ret = reg_write(client, MT9V022_READ_MODE, 0x300); |
7397bfbe GL |
218 | |
219 | /* All defaults */ | |
11211641 | 220 | if (!ret) |
7397bfbe | 221 | /* AEC, AGC on */ |
9538e1c2 | 222 | ret = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x3); |
96c75399 GL |
223 | if (!ret) |
224 | ret = reg_write(client, MT9V022_ANALOG_GAIN, 16); | |
225 | if (!ret) | |
226 | ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, 480); | |
11211641 | 227 | if (!ret) |
c078ac18 | 228 | ret = reg_write(client, mt9v022->reg->max_total_shutter_width, 480); |
11211641 | 229 | if (!ret) |
7397bfbe | 230 | /* default - auto */ |
9538e1c2 | 231 | ret = reg_clear(client, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1); |
11211641 | 232 | if (!ret) |
9538e1c2 | 233 | ret = reg_write(client, MT9V022_DIGITAL_TEST_PATTERN, 0); |
ab7b50ae HV |
234 | if (!ret) |
235 | return v4l2_ctrl_handler_setup(&mt9v022->hdl); | |
7397bfbe | 236 | |
11211641 | 237 | return ret; |
7397bfbe GL |
238 | } |
239 | ||
979ea1dd | 240 | static int mt9v022_s_stream(struct v4l2_subdev *sd, int enable) |
7397bfbe | 241 | { |
c4ce6d14 | 242 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 243 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
81034663 | 244 | |
d0bac768 | 245 | if (enable) { |
979ea1dd GL |
246 | /* Switch to master "normal" mode */ |
247 | mt9v022->chip_control &= ~0x10; | |
d0bac768 AG |
248 | if (is_mt9v022_rev3(mt9v022->chip_version) || |
249 | is_mt9v024(mt9v022->chip_version)) { | |
250 | /* | |
251 | * Unset snapshot mode specific settings: clear bit 9 | |
252 | * and bit 2 in reg. 0x20 when in normal mode. | |
253 | */ | |
254 | if (reg_clear(client, MT9V022_REG32, 0x204)) | |
255 | return -EIO; | |
256 | } | |
257 | } else { | |
979ea1dd GL |
258 | /* Switch to snapshot mode */ |
259 | mt9v022->chip_control |= 0x10; | |
d0bac768 AG |
260 | if (is_mt9v022_rev3(mt9v022->chip_version) || |
261 | is_mt9v024(mt9v022->chip_version)) { | |
262 | /* | |
263 | * Required settings for snapshot mode: set bit 9 | |
264 | * (RST enable) and bit 2 (CR enable) in reg. 0x20 | |
265 | * See TechNote TN0960 or TN-09-225. | |
266 | */ | |
267 | if (reg_set(client, MT9V022_REG32, 0x204)) | |
268 | return -EIO; | |
269 | } | |
270 | } | |
7397bfbe | 271 | |
979ea1dd | 272 | if (reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control) < 0) |
7397bfbe GL |
273 | return -EIO; |
274 | return 0; | |
275 | } | |
276 | ||
4f996594 | 277 | static int mt9v022_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a) |
ad5f2e85 | 278 | { |
c4ce6d14 | 279 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 GL |
280 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
281 | struct v4l2_rect rect = a->c; | |
bff79939 | 282 | int min_row, min_blank; |
ad5f2e85 GL |
283 | int ret; |
284 | ||
6a6c8786 | 285 | /* Bayer format - even size lengths */ |
760697be | 286 | if (mt9v022->fmts == mt9v022_colour_fmts) { |
6a6c8786 GL |
287 | rect.width = ALIGN(rect.width, 2); |
288 | rect.height = ALIGN(rect.height, 2); | |
289 | /* Let the user play with the starting pixel */ | |
290 | } | |
291 | ||
292 | soc_camera_limit_side(&rect.left, &rect.width, | |
293 | MT9V022_COLUMN_SKIP, MT9V022_MIN_WIDTH, MT9V022_MAX_WIDTH); | |
294 | ||
295 | soc_camera_limit_side(&rect.top, &rect.height, | |
296 | MT9V022_ROW_SKIP, MT9V022_MIN_HEIGHT, MT9V022_MAX_HEIGHT); | |
297 | ||
7397bfbe | 298 | /* Like in example app. Contradicts the datasheet though */ |
9538e1c2 | 299 | ret = reg_read(client, MT9V022_AEC_AGC_ENABLE); |
7397bfbe GL |
300 | if (ret >= 0) { |
301 | if (ret & 1) /* Autoexposure */ | |
c078ac18 | 302 | ret = reg_write(client, mt9v022->reg->max_total_shutter_width, |
32536108 | 303 | rect.height + mt9v022->y_skip_top + 43); |
9bb047cd AG |
304 | /* |
305 | * If autoexposure is off, there is no need to set | |
306 | * MT9V022_TOTAL_SHUTTER_WIDTH here. Autoexposure can be off | |
307 | * only if the user has set exposure manually, using the | |
308 | * V4L2_CID_EXPOSURE_AUTO with the value V4L2_EXPOSURE_MANUAL. | |
309 | * In this case the register MT9V022_TOTAL_SHUTTER_WIDTH | |
310 | * already contains the correct value. | |
311 | */ | |
7397bfbe GL |
312 | } |
313 | /* Setup frame format: defaults apart from width and height */ | |
11211641 | 314 | if (!ret) |
6a6c8786 | 315 | ret = reg_write(client, MT9V022_COLUMN_START, rect.left); |
11211641 | 316 | if (!ret) |
6a6c8786 | 317 | ret = reg_write(client, MT9V022_ROW_START, rect.top); |
bff79939 AA |
318 | /* |
319 | * mt9v022: min total row time is 660 columns, min blanking is 43 | |
320 | * mt9v024: min total row time is 690 columns, min blanking is 61 | |
321 | */ | |
322 | if (is_mt9v024(mt9v022->chip_version)) { | |
323 | min_row = 690; | |
324 | min_blank = 61; | |
325 | } else { | |
326 | min_row = 660; | |
327 | min_blank = 43; | |
328 | } | |
11211641 | 329 | if (!ret) |
6cc1eb70 | 330 | ret = v4l2_ctrl_s_ctrl(mt9v022->hblank, |
bff79939 AA |
331 | rect.width > min_row - min_blank ? |
332 | min_blank : min_row - rect.width); | |
11211641 | 333 | if (!ret) |
6cc1eb70 | 334 | ret = v4l2_ctrl_s_ctrl(mt9v022->vblank, 45); |
11211641 | 335 | if (!ret) |
6a6c8786 | 336 | ret = reg_write(client, MT9V022_WINDOW_WIDTH, rect.width); |
11211641 | 337 | if (!ret) |
9538e1c2 | 338 | ret = reg_write(client, MT9V022_WINDOW_HEIGHT, |
32536108 | 339 | rect.height + mt9v022->y_skip_top); |
7397bfbe GL |
340 | |
341 | if (ret < 0) | |
342 | return ret; | |
343 | ||
e26b3144 | 344 | dev_dbg(&client->dev, "Frame %dx%d pixel\n", rect.width, rect.height); |
6a6c8786 GL |
345 | |
346 | mt9v022->rect = rect; | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | static int mt9v022_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) | |
352 | { | |
c4ce6d14 | 353 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 GL |
354 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
355 | ||
356 | a->c = mt9v022->rect; | |
357 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static int mt9v022_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) | |
363 | { | |
364 | a->bounds.left = MT9V022_COLUMN_SKIP; | |
365 | a->bounds.top = MT9V022_ROW_SKIP; | |
366 | a->bounds.width = MT9V022_MAX_WIDTH; | |
367 | a->bounds.height = MT9V022_MAX_HEIGHT; | |
368 | a->defrect = a->bounds; | |
369 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
370 | a->pixelaspect.numerator = 1; | |
371 | a->pixelaspect.denominator = 1; | |
372 | ||
373 | return 0; | |
374 | } | |
375 | ||
760697be GL |
376 | static int mt9v022_g_fmt(struct v4l2_subdev *sd, |
377 | struct v4l2_mbus_framefmt *mf) | |
6a6c8786 | 378 | { |
c4ce6d14 | 379 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
6a6c8786 | 380 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
6a6c8786 | 381 | |
760697be GL |
382 | mf->width = mt9v022->rect.width; |
383 | mf->height = mt9v022->rect.height; | |
384 | mf->code = mt9v022->fmt->code; | |
385 | mf->colorspace = mt9v022->fmt->colorspace; | |
386 | mf->field = V4L2_FIELD_NONE; | |
7397bfbe | 387 | |
7397bfbe GL |
388 | return 0; |
389 | } | |
390 | ||
760697be GL |
391 | static int mt9v022_s_fmt(struct v4l2_subdev *sd, |
392 | struct v4l2_mbus_framefmt *mf) | |
09e231b3 | 393 | { |
c4ce6d14 | 394 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
979ea1dd | 395 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
08590b96 GL |
396 | struct v4l2_crop a = { |
397 | .c = { | |
6a6c8786 GL |
398 | .left = mt9v022->rect.left, |
399 | .top = mt9v022->rect.top, | |
760697be GL |
400 | .width = mf->width, |
401 | .height = mf->height, | |
08590b96 | 402 | }, |
09e231b3 | 403 | }; |
6a6c8786 | 404 | int ret; |
09e231b3 | 405 | |
5d28d525 GL |
406 | /* |
407 | * The caller provides a supported format, as verified per call to | |
14178aa5 | 408 | * .try_mbus_fmt(), datawidth is from our supported format list |
5d28d525 | 409 | */ |
760697be | 410 | switch (mf->code) { |
07670433 | 411 | case V4L2_MBUS_FMT_Y8_1X8: |
760697be | 412 | case V4L2_MBUS_FMT_Y10_1X10: |
6be89daa | 413 | if (mt9v022->model != MT9V022IX7ATM) |
09e231b3 GL |
414 | return -EINVAL; |
415 | break; | |
760697be GL |
416 | case V4L2_MBUS_FMT_SBGGR8_1X8: |
417 | case V4L2_MBUS_FMT_SBGGR10_1X10: | |
6be89daa | 418 | if (mt9v022->model != MT9V022IX7ATC) |
09e231b3 GL |
419 | return -EINVAL; |
420 | break; | |
09e231b3 GL |
421 | default: |
422 | return -EINVAL; | |
423 | } | |
424 | ||
425 | /* No support for scaling on this camera, just crop. */ | |
6a6c8786 GL |
426 | ret = mt9v022_s_crop(sd, &a); |
427 | if (!ret) { | |
760697be GL |
428 | mf->width = mt9v022->rect.width; |
429 | mf->height = mt9v022->rect.height; | |
430 | mt9v022->fmt = mt9v022_find_datafmt(mf->code, | |
431 | mt9v022->fmts, mt9v022->num_fmts); | |
432 | mf->colorspace = mt9v022->fmt->colorspace; | |
6a6c8786 GL |
433 | } |
434 | ||
435 | return ret; | |
09e231b3 GL |
436 | } |
437 | ||
760697be GL |
438 | static int mt9v022_try_fmt(struct v4l2_subdev *sd, |
439 | struct v4l2_mbus_framefmt *mf) | |
7397bfbe | 440 | { |
c4ce6d14 | 441 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
32536108 | 442 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
760697be GL |
443 | const struct mt9v022_datafmt *fmt; |
444 | int align = mf->code == V4L2_MBUS_FMT_SBGGR8_1X8 || | |
445 | mf->code == V4L2_MBUS_FMT_SBGGR10_1X10; | |
64f5905e | 446 | |
760697be | 447 | v4l_bound_align_image(&mf->width, MT9V022_MIN_WIDTH, |
6a6c8786 | 448 | MT9V022_MAX_WIDTH, align, |
760697be | 449 | &mf->height, MT9V022_MIN_HEIGHT + mt9v022->y_skip_top, |
32536108 | 450 | MT9V022_MAX_HEIGHT + mt9v022->y_skip_top, align, 0); |
7397bfbe | 451 | |
760697be GL |
452 | fmt = mt9v022_find_datafmt(mf->code, mt9v022->fmts, |
453 | mt9v022->num_fmts); | |
454 | if (!fmt) { | |
455 | fmt = mt9v022->fmt; | |
456 | mf->code = fmt->code; | |
457 | } | |
458 | ||
459 | mf->colorspace = fmt->colorspace; | |
460 | ||
7397bfbe GL |
461 | return 0; |
462 | } | |
463 | ||
7397bfbe | 464 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
979ea1dd GL |
465 | static int mt9v022_g_register(struct v4l2_subdev *sd, |
466 | struct v4l2_dbg_register *reg) | |
7397bfbe | 467 | { |
c4ce6d14 | 468 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
7397bfbe | 469 | |
6be89daa | 470 | if (reg->reg > 0xff) |
7397bfbe GL |
471 | return -EINVAL; |
472 | ||
aecde8b5 | 473 | reg->size = 2; |
9538e1c2 | 474 | reg->val = reg_read(client, reg->reg); |
7397bfbe GL |
475 | |
476 | if (reg->val > 0xffff) | |
477 | return -EIO; | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
979ea1dd | 482 | static int mt9v022_s_register(struct v4l2_subdev *sd, |
977ba3b1 | 483 | const struct v4l2_dbg_register *reg) |
7397bfbe | 484 | { |
c4ce6d14 | 485 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
7397bfbe | 486 | |
6be89daa | 487 | if (reg->reg > 0xff) |
7397bfbe GL |
488 | return -EINVAL; |
489 | ||
9538e1c2 | 490 | if (reg_write(client, reg->reg, reg->val) < 0) |
7397bfbe GL |
491 | return -EIO; |
492 | ||
493 | return 0; | |
494 | } | |
495 | #endif | |
496 | ||
4ec10bac LP |
497 | static int mt9v022_s_power(struct v4l2_subdev *sd, int on) |
498 | { | |
499 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 500 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
4ec10bac | 501 | |
25a34811 | 502 | return soc_camera_set_power(&client->dev, ssdd, on); |
4ec10bac LP |
503 | } |
504 | ||
ab7b50ae | 505 | static int mt9v022_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
7397bfbe | 506 | { |
ab7b50ae HV |
507 | struct mt9v022 *mt9v022 = container_of(ctrl->handler, |
508 | struct mt9v022, hdl); | |
509 | struct v4l2_subdev *sd = &mt9v022->subdev; | |
c4ce6d14 | 510 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ab7b50ae HV |
511 | struct v4l2_ctrl *gain = mt9v022->gain; |
512 | struct v4l2_ctrl *exp = mt9v022->exposure; | |
96c75399 | 513 | unsigned long range; |
7397bfbe GL |
514 | int data; |
515 | ||
516 | switch (ctrl->id) { | |
7397bfbe | 517 | case V4L2_CID_AUTOGAIN: |
96c75399 GL |
518 | data = reg_read(client, MT9V022_ANALOG_GAIN); |
519 | if (data < 0) | |
520 | return -EIO; | |
521 | ||
ab7b50ae HV |
522 | range = gain->maximum - gain->minimum; |
523 | gain->val = ((data - 16) * range + 24) / 48 + gain->minimum; | |
524 | return 0; | |
525 | case V4L2_CID_EXPOSURE_AUTO: | |
96c75399 GL |
526 | data = reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH); |
527 | if (data < 0) | |
528 | return -EIO; | |
529 | ||
ab7b50ae HV |
530 | range = exp->maximum - exp->minimum; |
531 | exp->val = ((data - 1) * range + 239) / 479 + exp->minimum; | |
532 | return 0; | |
6cc1eb70 AG |
533 | case V4L2_CID_HBLANK: |
534 | data = reg_read(client, MT9V022_HORIZONTAL_BLANKING); | |
535 | if (data < 0) | |
536 | return -EIO; | |
537 | ctrl->val = data; | |
538 | return 0; | |
539 | case V4L2_CID_VBLANK: | |
540 | data = reg_read(client, MT9V022_VERTICAL_BLANKING); | |
541 | if (data < 0) | |
542 | return -EIO; | |
543 | ctrl->val = data; | |
544 | return 0; | |
7397bfbe | 545 | } |
ab7b50ae | 546 | return -EINVAL; |
7397bfbe GL |
547 | } |
548 | ||
ab7b50ae | 549 | static int mt9v022_s_ctrl(struct v4l2_ctrl *ctrl) |
7397bfbe | 550 | { |
ab7b50ae HV |
551 | struct mt9v022 *mt9v022 = container_of(ctrl->handler, |
552 | struct mt9v022, hdl); | |
553 | struct v4l2_subdev *sd = &mt9v022->subdev; | |
c4ce6d14 | 554 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
ab7b50ae | 555 | int data; |
7397bfbe GL |
556 | |
557 | switch (ctrl->id) { | |
558 | case V4L2_CID_VFLIP: | |
ab7b50ae | 559 | if (ctrl->val) |
9538e1c2 | 560 | data = reg_set(client, MT9V022_READ_MODE, 0x10); |
7397bfbe | 561 | else |
9538e1c2 | 562 | data = reg_clear(client, MT9V022_READ_MODE, 0x10); |
7397bfbe GL |
563 | if (data < 0) |
564 | return -EIO; | |
ab7b50ae | 565 | return 0; |
7397bfbe | 566 | case V4L2_CID_HFLIP: |
ab7b50ae | 567 | if (ctrl->val) |
9538e1c2 | 568 | data = reg_set(client, MT9V022_READ_MODE, 0x20); |
7397bfbe | 569 | else |
9538e1c2 | 570 | data = reg_clear(client, MT9V022_READ_MODE, 0x20); |
7397bfbe GL |
571 | if (data < 0) |
572 | return -EIO; | |
ab7b50ae HV |
573 | return 0; |
574 | case V4L2_CID_AUTOGAIN: | |
575 | if (ctrl->val) { | |
576 | if (reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0) | |
577 | return -EIO; | |
578 | } else { | |
579 | struct v4l2_ctrl *gain = mt9v022->gain; | |
580 | /* mt9v022 has minimum == default */ | |
581 | unsigned long range = gain->maximum - gain->minimum; | |
96c75399 | 582 | /* Valid values 16 to 64, 32 to 64 must be even. */ |
ab7b50ae | 583 | unsigned long gain_val = ((gain->val - gain->minimum) * |
96c75399 | 584 | 48 + range / 2) / range + 16; |
ab7b50ae HV |
585 | |
586 | if (gain_val >= 32) | |
587 | gain_val &= ~1; | |
588 | ||
5d28d525 GL |
589 | /* |
590 | * The user wants to set gain manually, hope, she | |
591 | * knows, what she's doing... Switch AGC off. | |
592 | */ | |
9538e1c2 | 593 | if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0) |
7397bfbe GL |
594 | return -EIO; |
595 | ||
96c75399 | 596 | dev_dbg(&client->dev, "Setting gain from %d to %lu\n", |
ab7b50ae HV |
597 | reg_read(client, MT9V022_ANALOG_GAIN), gain_val); |
598 | if (reg_write(client, MT9V022_ANALOG_GAIN, gain_val) < 0) | |
7397bfbe | 599 | return -EIO; |
7397bfbe | 600 | } |
ab7b50ae HV |
601 | return 0; |
602 | case V4L2_CID_EXPOSURE_AUTO: | |
603 | if (ctrl->val == V4L2_EXPOSURE_AUTO) { | |
604 | data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x1); | |
605 | } else { | |
606 | struct v4l2_ctrl *exp = mt9v022->exposure; | |
607 | unsigned long range = exp->maximum - exp->minimum; | |
608 | unsigned long shutter = ((exp->val - exp->minimum) * | |
609 | 479 + range / 2) / range + 1; | |
610 | ||
5d28d525 GL |
611 | /* |
612 | * The user wants to set shutter width manually, hope, | |
613 | * she knows, what she's doing... Switch AEC off. | |
614 | */ | |
ab7b50ae HV |
615 | data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1); |
616 | if (data < 0) | |
7397bfbe | 617 | return -EIO; |
85f8be68 | 618 | dev_dbg(&client->dev, "Shutter width from %d to %lu\n", |
ab7b50ae HV |
619 | reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH), |
620 | shutter); | |
9538e1c2 | 621 | if (reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, |
ab7b50ae | 622 | shutter) < 0) |
7397bfbe | 623 | return -EIO; |
7397bfbe | 624 | } |
ab7b50ae | 625 | return 0; |
6cc1eb70 AG |
626 | case V4L2_CID_HBLANK: |
627 | if (reg_write(client, MT9V022_HORIZONTAL_BLANKING, | |
628 | ctrl->val) < 0) | |
629 | return -EIO; | |
630 | return 0; | |
631 | case V4L2_CID_VBLANK: | |
632 | if (reg_write(client, MT9V022_VERTICAL_BLANKING, | |
633 | ctrl->val) < 0) | |
634 | return -EIO; | |
635 | return 0; | |
7397bfbe | 636 | } |
ab7b50ae | 637 | return -EINVAL; |
7397bfbe GL |
638 | } |
639 | ||
5d28d525 GL |
640 | /* |
641 | * Interface active, can use i2c. If it fails, it can indeed mean, that | |
642 | * this wasn't our capture interface, so, we wait for the right one | |
643 | */ | |
14178aa5 | 644 | static int mt9v022_video_probe(struct i2c_client *client) |
7397bfbe | 645 | { |
979ea1dd | 646 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
25a34811 | 647 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
7397bfbe GL |
648 | s32 data; |
649 | int ret; | |
e958e27a | 650 | unsigned long flags; |
7397bfbe | 651 | |
4bbc6d52 LP |
652 | ret = mt9v022_s_power(&mt9v022->subdev, 1); |
653 | if (ret < 0) | |
654 | return ret; | |
655 | ||
7397bfbe | 656 | /* Read out the chip version register */ |
9538e1c2 | 657 | data = reg_read(client, MT9V022_CHIP_VERSION); |
7397bfbe | 658 | |
c078ac18 AG |
659 | /* must be 0x1311, 0x1313 or 0x1324 */ |
660 | if (data != 0x1311 && data != 0x1313 && data != 0x1324) { | |
7397bfbe | 661 | ret = -ENODEV; |
85f8be68 | 662 | dev_info(&client->dev, "No MT9V022 found, ID register 0x%x\n", |
7397bfbe GL |
663 | data); |
664 | goto ei2c; | |
665 | } | |
666 | ||
d0bac768 AG |
667 | mt9v022->chip_version = data; |
668 | ||
c078ac18 AG |
669 | mt9v022->reg = is_mt9v024(data) ? &mt9v024_register : |
670 | &mt9v022_register; | |
671 | ||
7397bfbe | 672 | /* Soft reset */ |
9538e1c2 | 673 | ret = reg_write(client, MT9V022_RESET, 1); |
7397bfbe GL |
674 | if (ret < 0) |
675 | goto ei2c; | |
676 | /* 15 clock cycles */ | |
677 | udelay(200); | |
9538e1c2 | 678 | if (reg_read(client, MT9V022_RESET)) { |
85f8be68 | 679 | dev_err(&client->dev, "Resetting MT9V022 failed!\n"); |
40e2e092 GL |
680 | if (ret > 0) |
681 | ret = -EIO; | |
7397bfbe GL |
682 | goto ei2c; |
683 | } | |
684 | ||
685 | /* Set monochrome or colour sensor type */ | |
686 | if (sensor_type && (!strcmp("colour", sensor_type) || | |
687 | !strcmp("color", sensor_type))) { | |
9538e1c2 | 688 | ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 4 | 0x11); |
6be89daa | 689 | mt9v022->model = MT9V022IX7ATC; |
760697be | 690 | mt9v022->fmts = mt9v022_colour_fmts; |
7397bfbe | 691 | } else { |
9538e1c2 | 692 | ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 0x11); |
6be89daa | 693 | mt9v022->model = MT9V022IX7ATM; |
760697be | 694 | mt9v022->fmts = mt9v022_monochrome_fmts; |
7397bfbe GL |
695 | } |
696 | ||
e958e27a | 697 | if (ret < 0) |
40e2e092 | 698 | goto ei2c; |
e958e27a | 699 | |
760697be | 700 | mt9v022->num_fmts = 0; |
e958e27a SH |
701 | |
702 | /* | |
703 | * This is a 10bit sensor, so by default we only allow 10bit. | |
704 | * The platform may support different bus widths due to | |
705 | * different routing of the data lines. | |
706 | */ | |
25a34811 GL |
707 | if (ssdd->query_bus_param) |
708 | flags = ssdd->query_bus_param(ssdd); | |
e958e27a SH |
709 | else |
710 | flags = SOCAM_DATAWIDTH_10; | |
711 | ||
712 | if (flags & SOCAM_DATAWIDTH_10) | |
760697be | 713 | mt9v022->num_fmts++; |
e958e27a | 714 | else |
760697be | 715 | mt9v022->fmts++; |
e958e27a SH |
716 | |
717 | if (flags & SOCAM_DATAWIDTH_8) | |
760697be | 718 | mt9v022->num_fmts++; |
e958e27a | 719 | |
760697be | 720 | mt9v022->fmt = &mt9v022->fmts[0]; |
6a6c8786 | 721 | |
85f8be68 | 722 | dev_info(&client->dev, "Detected a MT9V022 chip ID %x, %s sensor\n", |
6be89daa | 723 | data, mt9v022->model == MT9V022IX7ATM ? |
7397bfbe GL |
724 | "monochrome" : "colour"); |
725 | ||
a4c56fd8 GL |
726 | ret = mt9v022_init(client); |
727 | if (ret < 0) | |
728 | dev_err(&client->dev, "Failed to initialise the camera\n"); | |
729 | ||
7397bfbe | 730 | ei2c: |
4bbc6d52 | 731 | mt9v022_s_power(&mt9v022->subdev, 0); |
7397bfbe GL |
732 | return ret; |
733 | } | |
734 | ||
32536108 GL |
735 | static int mt9v022_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines) |
736 | { | |
c4ce6d14 | 737 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
32536108 GL |
738 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
739 | ||
740 | *lines = mt9v022->y_skip_top; | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
ab7b50ae HV |
745 | static const struct v4l2_ctrl_ops mt9v022_ctrl_ops = { |
746 | .g_volatile_ctrl = mt9v022_g_volatile_ctrl, | |
747 | .s_ctrl = mt9v022_s_ctrl, | |
748 | }; | |
749 | ||
979ea1dd | 750 | static struct v4l2_subdev_core_ops mt9v022_subdev_core_ops = { |
979ea1dd GL |
751 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
752 | .g_register = mt9v022_g_register, | |
753 | .s_register = mt9v022_s_register, | |
754 | #endif | |
4ec10bac | 755 | .s_power = mt9v022_s_power, |
979ea1dd GL |
756 | }; |
757 | ||
3805f201 | 758 | static int mt9v022_enum_fmt(struct v4l2_subdev *sd, unsigned int index, |
760697be GL |
759 | enum v4l2_mbus_pixelcode *code) |
760 | { | |
c4ce6d14 | 761 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
760697be GL |
762 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
763 | ||
3805f201 | 764 | if (index >= mt9v022->num_fmts) |
760697be GL |
765 | return -EINVAL; |
766 | ||
767 | *code = mt9v022->fmts[index].code; | |
768 | return 0; | |
769 | } | |
770 | ||
e8e2c70c GL |
771 | static int mt9v022_g_mbus_config(struct v4l2_subdev *sd, |
772 | struct v4l2_mbus_config *cfg) | |
773 | { | |
774 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 775 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
e8e2c70c GL |
776 | |
777 | cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE | | |
778 | V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING | | |
779 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
780 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
781 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
782 | cfg->type = V4L2_MBUS_PARALLEL; | |
25a34811 | 783 | cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); |
e8e2c70c GL |
784 | |
785 | return 0; | |
786 | } | |
787 | ||
788 | static int mt9v022_s_mbus_config(struct v4l2_subdev *sd, | |
789 | const struct v4l2_mbus_config *cfg) | |
790 | { | |
791 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 792 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
e8e2c70c | 793 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
25a34811 | 794 | unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg); |
443f483a | 795 | unsigned int bps = soc_mbus_get_fmtdesc(mt9v022->fmt->code)->bits_per_sample; |
e8e2c70c GL |
796 | int ret; |
797 | u16 pixclk = 0; | |
798 | ||
25a34811 GL |
799 | if (ssdd->set_bus_param) { |
800 | ret = ssdd->set_bus_param(ssdd, 1 << (bps - 1)); | |
e8e2c70c GL |
801 | if (ret) |
802 | return ret; | |
803 | } else if (bps != 10) { | |
804 | /* | |
805 | * Without board specific bus width settings we only support the | |
806 | * sensors native bus width | |
807 | */ | |
808 | return -EINVAL; | |
809 | } | |
810 | ||
811 | if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) | |
812 | pixclk |= 0x10; | |
813 | ||
814 | if (!(flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)) | |
815 | pixclk |= 0x1; | |
816 | ||
817 | if (!(flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)) | |
818 | pixclk |= 0x2; | |
819 | ||
c078ac18 | 820 | ret = reg_write(client, mt9v022->reg->pixclk_fv_lv, pixclk); |
e8e2c70c GL |
821 | if (ret < 0) |
822 | return ret; | |
823 | ||
824 | if (!(flags & V4L2_MBUS_MASTER)) | |
825 | mt9v022->chip_control &= ~0x8; | |
826 | ||
827 | ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control); | |
828 | if (ret < 0) | |
829 | return ret; | |
830 | ||
831 | dev_dbg(&client->dev, "Calculated pixclk 0x%x, chip control 0x%x\n", | |
832 | pixclk, mt9v022->chip_control); | |
833 | ||
834 | return 0; | |
835 | } | |
836 | ||
979ea1dd GL |
837 | static struct v4l2_subdev_video_ops mt9v022_subdev_video_ops = { |
838 | .s_stream = mt9v022_s_stream, | |
760697be GL |
839 | .s_mbus_fmt = mt9v022_s_fmt, |
840 | .g_mbus_fmt = mt9v022_g_fmt, | |
841 | .try_mbus_fmt = mt9v022_try_fmt, | |
08590b96 | 842 | .s_crop = mt9v022_s_crop, |
6a6c8786 GL |
843 | .g_crop = mt9v022_g_crop, |
844 | .cropcap = mt9v022_cropcap, | |
760697be | 845 | .enum_mbus_fmt = mt9v022_enum_fmt, |
e8e2c70c GL |
846 | .g_mbus_config = mt9v022_g_mbus_config, |
847 | .s_mbus_config = mt9v022_s_mbus_config, | |
979ea1dd GL |
848 | }; |
849 | ||
32536108 GL |
850 | static struct v4l2_subdev_sensor_ops mt9v022_subdev_sensor_ops = { |
851 | .g_skip_top_lines = mt9v022_g_skip_top_lines, | |
852 | }; | |
853 | ||
979ea1dd GL |
854 | static struct v4l2_subdev_ops mt9v022_subdev_ops = { |
855 | .core = &mt9v022_subdev_core_ops, | |
856 | .video = &mt9v022_subdev_video_ops, | |
32536108 | 857 | .sensor = &mt9v022_subdev_sensor_ops, |
979ea1dd GL |
858 | }; |
859 | ||
d2653e92 JD |
860 | static int mt9v022_probe(struct i2c_client *client, |
861 | const struct i2c_device_id *did) | |
7397bfbe GL |
862 | { |
863 | struct mt9v022 *mt9v022; | |
25a34811 | 864 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
7397bfbe | 865 | struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent); |
daf16bab | 866 | struct mt9v022_platform_data *pdata; |
7397bfbe GL |
867 | int ret; |
868 | ||
25a34811 | 869 | if (!ssdd) { |
7397bfbe GL |
870 | dev_err(&client->dev, "MT9V022 driver needs platform data\n"); |
871 | return -EINVAL; | |
872 | } | |
873 | ||
874 | if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) { | |
875 | dev_warn(&adapter->dev, | |
876 | "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n"); | |
877 | return -EIO; | |
878 | } | |
879 | ||
70e176a5 | 880 | mt9v022 = devm_kzalloc(&client->dev, sizeof(struct mt9v022), GFP_KERNEL); |
7397bfbe GL |
881 | if (!mt9v022) |
882 | return -ENOMEM; | |
883 | ||
25a34811 | 884 | pdata = ssdd->drv_priv; |
979ea1dd | 885 | v4l2_i2c_subdev_init(&mt9v022->subdev, client, &mt9v022_subdev_ops); |
ab7b50ae HV |
886 | v4l2_ctrl_handler_init(&mt9v022->hdl, 6); |
887 | v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
888 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
889 | v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
890 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
891 | mt9v022->autogain = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
892 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
893 | mt9v022->gain = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
894 | V4L2_CID_GAIN, 0, 127, 1, 64); | |
895 | ||
896 | /* | |
897 | * Simulated autoexposure. If enabled, we calculate shutter width | |
898 | * ourselves in the driver based on vertical blanking and frame width | |
899 | */ | |
900 | mt9v022->autoexposure = v4l2_ctrl_new_std_menu(&mt9v022->hdl, | |
901 | &mt9v022_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0, | |
902 | V4L2_EXPOSURE_AUTO); | |
903 | mt9v022->exposure = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
904 | V4L2_CID_EXPOSURE, 1, 255, 1, 255); | |
905 | ||
6cc1eb70 AG |
906 | mt9v022->hblank = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, |
907 | V4L2_CID_HBLANK, MT9V022_HORIZONTAL_BLANKING_MIN, | |
908 | MT9V022_HORIZONTAL_BLANKING_MAX, 1, | |
909 | MT9V022_HORIZONTAL_BLANKING_DEF); | |
910 | ||
911 | mt9v022->vblank = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops, | |
912 | V4L2_CID_VBLANK, MT9V022_VERTICAL_BLANKING_MIN, | |
913 | MT9V022_VERTICAL_BLANKING_MAX, 1, | |
914 | MT9V022_VERTICAL_BLANKING_DEF); | |
915 | ||
ab7b50ae HV |
916 | mt9v022->subdev.ctrl_handler = &mt9v022->hdl; |
917 | if (mt9v022->hdl.error) { | |
918 | int err = mt9v022->hdl.error; | |
919 | ||
6cc1eb70 | 920 | dev_err(&client->dev, "control initialisation err %d\n", err); |
ab7b50ae HV |
921 | return err; |
922 | } | |
923 | v4l2_ctrl_auto_cluster(2, &mt9v022->autoexposure, | |
924 | V4L2_EXPOSURE_MANUAL, true); | |
925 | v4l2_ctrl_auto_cluster(2, &mt9v022->autogain, 0, true); | |
979ea1dd | 926 | |
7397bfbe | 927 | mt9v022->chip_control = MT9V022_CHIP_CONTROL_DEFAULT; |
7397bfbe | 928 | |
96c75399 | 929 | /* |
b6f50b49 AG |
930 | * On some platforms the first read out line is corrupted. |
931 | * Workaround it by skipping if indicated by platform data. | |
96c75399 | 932 | */ |
b6f50b49 | 933 | mt9v022->y_skip_top = pdata ? pdata->y_skip_top : 0; |
6a6c8786 GL |
934 | mt9v022->rect.left = MT9V022_COLUMN_SKIP; |
935 | mt9v022->rect.top = MT9V022_ROW_SKIP; | |
936 | mt9v022->rect.width = MT9V022_MAX_WIDTH; | |
937 | mt9v022->rect.height = MT9V022_MAX_HEIGHT; | |
938 | ||
14178aa5 | 939 | ret = mt9v022_video_probe(client); |
70e176a5 | 940 | if (ret) |
ab7b50ae | 941 | v4l2_ctrl_handler_free(&mt9v022->hdl); |
7397bfbe | 942 | |
7397bfbe GL |
943 | return ret; |
944 | } | |
945 | ||
946 | static int mt9v022_remove(struct i2c_client *client) | |
947 | { | |
979ea1dd | 948 | struct mt9v022 *mt9v022 = to_mt9v022(client); |
25a34811 | 949 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
7397bfbe | 950 | |
ab7b50ae | 951 | v4l2_device_unregister_subdev(&mt9v022->subdev); |
25a34811 GL |
952 | if (ssdd->free_bus) |
953 | ssdd->free_bus(ssdd); | |
ab7b50ae | 954 | v4l2_ctrl_handler_free(&mt9v022->hdl); |
7397bfbe GL |
955 | |
956 | return 0; | |
957 | } | |
3760f736 JD |
958 | static const struct i2c_device_id mt9v022_id[] = { |
959 | { "mt9v022", 0 }, | |
960 | { } | |
961 | }; | |
962 | MODULE_DEVICE_TABLE(i2c, mt9v022_id); | |
963 | ||
7397bfbe GL |
964 | static struct i2c_driver mt9v022_i2c_driver = { |
965 | .driver = { | |
966 | .name = "mt9v022", | |
967 | }, | |
968 | .probe = mt9v022_probe, | |
969 | .remove = mt9v022_remove, | |
3760f736 | 970 | .id_table = mt9v022_id, |
7397bfbe GL |
971 | }; |
972 | ||
c6e8d86f | 973 | module_i2c_driver(mt9v022_i2c_driver); |
7397bfbe GL |
974 | |
975 | MODULE_DESCRIPTION("Micron MT9V022 Camera driver"); | |
976 | MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>"); | |
977 | MODULE_LICENSE("GPL"); |