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2f6e2404 JK |
1 | /* |
2 | * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor | |
3 | * | |
4 | * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> | |
5 | * | |
6 | * Based on OmniVision OV96xx Camera Driver | |
7 | * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com> | |
8 | * | |
9 | * Based on ov772x camera driver: | |
10 | * Copyright (C) 2008 Renesas Solutions Corp. | |
11 | * Kuninori Morimoto <morimoto.kuninori@renesas.com> | |
12 | * | |
13 | * Based on ov7670 and soc_camera_platform driver, | |
14 | * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> | |
15 | * Copyright (C) 2008 Magnus Damm | |
16 | * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de> | |
17 | * | |
18 | * Hardware specific bits initialy based on former work by Matt Callow | |
19 | * drivers/media/video/omap/sensor_ov6650.c | |
20 | * Copyright (C) 2006 Matt Callow | |
21 | * | |
22 | * This program is free software; you can redistribute it and/or modify | |
23 | * it under the terms of the GNU General Public License version 2 as | |
24 | * published by the Free Software Foundation. | |
25 | */ | |
26 | ||
27 | #include <linux/bitops.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/i2c.h> | |
30 | #include <linux/slab.h> | |
95d20109 | 31 | #include <linux/v4l2-mediabus.h> |
7a707b89 | 32 | #include <linux/module.h> |
2f6e2404 JK |
33 | |
34 | #include <media/soc_camera.h> | |
9aea470b | 35 | #include <media/v4l2-clk.h> |
afd9690c | 36 | #include <media/v4l2-ctrls.h> |
2f6e2404 | 37 | |
2f6e2404 JK |
38 | /* Register definitions */ |
39 | #define REG_GAIN 0x00 /* range 00 - 3F */ | |
40 | #define REG_BLUE 0x01 | |
41 | #define REG_RED 0x02 | |
42 | #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */ | |
43 | #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */ | |
44 | ||
45 | #define REG_BRT 0x06 | |
46 | ||
47 | #define REG_PIDH 0x0a | |
48 | #define REG_PIDL 0x0b | |
49 | ||
50 | #define REG_AECH 0x10 | |
51 | #define REG_CLKRC 0x11 /* Data Format and Internal Clock */ | |
52 | /* [7:6] Input system clock (MHz)*/ | |
53 | /* 00=8, 01=12, 10=16, 11=24 */ | |
54 | /* [5:0]: Internal Clock Pre-Scaler */ | |
55 | #define REG_COMA 0x12 /* [7] Reset */ | |
56 | #define REG_COMB 0x13 | |
57 | #define REG_COMC 0x14 | |
58 | #define REG_COMD 0x15 | |
59 | #define REG_COML 0x16 | |
60 | #define REG_HSTRT 0x17 | |
61 | #define REG_HSTOP 0x18 | |
62 | #define REG_VSTRT 0x19 | |
63 | #define REG_VSTOP 0x1a | |
64 | #define REG_PSHFT 0x1b | |
65 | #define REG_MIDH 0x1c | |
66 | #define REG_MIDL 0x1d | |
67 | #define REG_HSYNS 0x1e | |
68 | #define REG_HSYNE 0x1f | |
69 | #define REG_COME 0x20 | |
70 | #define REG_YOFF 0x21 | |
71 | #define REG_UOFF 0x22 | |
72 | #define REG_VOFF 0x23 | |
73 | #define REG_AEW 0x24 | |
74 | #define REG_AEB 0x25 | |
75 | #define REG_COMF 0x26 | |
76 | #define REG_COMG 0x27 | |
77 | #define REG_COMH 0x28 | |
78 | #define REG_COMI 0x29 | |
79 | ||
80 | #define REG_FRARL 0x2b | |
81 | #define REG_COMJ 0x2c | |
82 | #define REG_COMK 0x2d | |
83 | #define REG_AVGY 0x2e | |
84 | #define REG_REF0 0x2f | |
85 | #define REG_REF1 0x30 | |
86 | #define REG_REF2 0x31 | |
87 | #define REG_FRAJH 0x32 | |
88 | #define REG_FRAJL 0x33 | |
89 | #define REG_FACT 0x34 | |
90 | #define REG_L1AEC 0x35 | |
91 | #define REG_AVGU 0x36 | |
92 | #define REG_AVGV 0x37 | |
93 | ||
94 | #define REG_SPCB 0x60 | |
95 | #define REG_SPCC 0x61 | |
96 | #define REG_GAM1 0x62 | |
97 | #define REG_GAM2 0x63 | |
98 | #define REG_GAM3 0x64 | |
99 | #define REG_SPCD 0x65 | |
100 | ||
101 | #define REG_SPCE 0x68 | |
102 | #define REG_ADCL 0x69 | |
103 | ||
104 | #define REG_RMCO 0x6c | |
105 | #define REG_GMCO 0x6d | |
106 | #define REG_BMCO 0x6e | |
107 | ||
108 | ||
109 | /* Register bits, values, etc. */ | |
110 | #define OV6650_PIDH 0x66 /* high byte of product ID number */ | |
111 | #define OV6650_PIDL 0x50 /* low byte of product ID number */ | |
112 | #define OV6650_MIDH 0x7F /* high byte of mfg ID */ | |
113 | #define OV6650_MIDL 0xA2 /* low byte of mfg ID */ | |
114 | ||
115 | #define DEF_GAIN 0x00 | |
116 | #define DEF_BLUE 0x80 | |
117 | #define DEF_RED 0x80 | |
118 | ||
119 | #define SAT_SHIFT 4 | |
120 | #define SAT_MASK (0xf << SAT_SHIFT) | |
121 | #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK) | |
122 | ||
123 | #define HUE_EN BIT(5) | |
124 | #define HUE_MASK 0x1f | |
125 | #define DEF_HUE 0x10 | |
126 | #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK)) | |
127 | ||
128 | #define DEF_AECH 0x4D | |
129 | ||
130 | #define CLKRC_6MHz 0x00 | |
131 | #define CLKRC_12MHz 0x40 | |
132 | #define CLKRC_16MHz 0x80 | |
133 | #define CLKRC_24MHz 0xc0 | |
134 | #define CLKRC_DIV_MASK 0x3f | |
135 | #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1) | |
136 | ||
137 | #define COMA_RESET BIT(7) | |
138 | #define COMA_QCIF BIT(5) | |
139 | #define COMA_RAW_RGB BIT(4) | |
140 | #define COMA_RGB BIT(3) | |
141 | #define COMA_BW BIT(2) | |
142 | #define COMA_WORD_SWAP BIT(1) | |
143 | #define COMA_BYTE_SWAP BIT(0) | |
144 | #define DEF_COMA 0x00 | |
145 | ||
146 | #define COMB_FLIP_V BIT(7) | |
147 | #define COMB_FLIP_H BIT(5) | |
148 | #define COMB_BAND_FILTER BIT(4) | |
149 | #define COMB_AWB BIT(2) | |
150 | #define COMB_AGC BIT(1) | |
151 | #define COMB_AEC BIT(0) | |
152 | #define DEF_COMB 0x5f | |
153 | ||
154 | #define COML_ONE_CHANNEL BIT(7) | |
155 | ||
156 | #define DEF_HSTRT 0x24 | |
157 | #define DEF_HSTOP 0xd4 | |
158 | #define DEF_VSTRT 0x04 | |
159 | #define DEF_VSTOP 0x94 | |
160 | ||
161 | #define COMF_HREF_LOW BIT(4) | |
162 | ||
163 | #define COMJ_PCLK_RISING BIT(4) | |
164 | #define COMJ_VSYNC_HIGH BIT(0) | |
165 | ||
166 | /* supported resolutions */ | |
167 | #define W_QCIF (DEF_HSTOP - DEF_HSTRT) | |
168 | #define W_CIF (W_QCIF << 1) | |
169 | #define H_QCIF (DEF_VSTOP - DEF_VSTRT) | |
170 | #define H_CIF (H_QCIF << 1) | |
171 | ||
172 | #define FRAME_RATE_MAX 30 | |
173 | ||
174 | ||
175 | struct ov6650_reg { | |
176 | u8 reg; | |
177 | u8 val; | |
178 | }; | |
179 | ||
180 | struct ov6650 { | |
181 | struct v4l2_subdev subdev; | |
afd9690c HV |
182 | struct v4l2_ctrl_handler hdl; |
183 | struct { | |
184 | /* exposure/autoexposure cluster */ | |
185 | struct v4l2_ctrl *autoexposure; | |
186 | struct v4l2_ctrl *exposure; | |
187 | }; | |
188 | struct { | |
189 | /* gain/autogain cluster */ | |
190 | struct v4l2_ctrl *autogain; | |
191 | struct v4l2_ctrl *gain; | |
192 | }; | |
193 | struct { | |
194 | /* blue/red/autowhitebalance cluster */ | |
195 | struct v4l2_ctrl *autowb; | |
196 | struct v4l2_ctrl *blue; | |
197 | struct v4l2_ctrl *red; | |
198 | }; | |
9aea470b | 199 | struct v4l2_clk *clk; |
2f6e2404 JK |
200 | bool half_scale; /* scale down output by 2 */ |
201 | struct v4l2_rect rect; /* sensor cropping window */ | |
202 | unsigned long pclk_limit; /* from host */ | |
203 | unsigned long pclk_max; /* from resolution and format */ | |
204 | struct v4l2_fract tpf; /* as requested with s_parm */ | |
f5fe58fd | 205 | u32 code; |
2f6e2404 JK |
206 | enum v4l2_colorspace colorspace; |
207 | }; | |
208 | ||
209 | ||
f5fe58fd BB |
210 | static u32 ov6650_codes[] = { |
211 | MEDIA_BUS_FMT_YUYV8_2X8, | |
212 | MEDIA_BUS_FMT_UYVY8_2X8, | |
213 | MEDIA_BUS_FMT_YVYU8_2X8, | |
214 | MEDIA_BUS_FMT_VYUY8_2X8, | |
215 | MEDIA_BUS_FMT_SBGGR8_1X8, | |
216 | MEDIA_BUS_FMT_Y8_1X8, | |
2f6e2404 JK |
217 | }; |
218 | ||
2f6e2404 JK |
219 | /* read a register */ |
220 | static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val) | |
221 | { | |
222 | int ret; | |
223 | u8 data = reg; | |
224 | struct i2c_msg msg = { | |
225 | .addr = client->addr, | |
226 | .flags = 0, | |
227 | .len = 1, | |
228 | .buf = &data, | |
229 | }; | |
230 | ||
231 | ret = i2c_transfer(client->adapter, &msg, 1); | |
232 | if (ret < 0) | |
233 | goto err; | |
234 | ||
235 | msg.flags = I2C_M_RD; | |
236 | ret = i2c_transfer(client->adapter, &msg, 1); | |
237 | if (ret < 0) | |
238 | goto err; | |
239 | ||
240 | *val = data; | |
241 | return 0; | |
242 | ||
243 | err: | |
244 | dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg); | |
245 | return ret; | |
246 | } | |
247 | ||
248 | /* write a register */ | |
249 | static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val) | |
250 | { | |
251 | int ret; | |
252 | unsigned char data[2] = { reg, val }; | |
253 | struct i2c_msg msg = { | |
254 | .addr = client->addr, | |
255 | .flags = 0, | |
256 | .len = 2, | |
257 | .buf = data, | |
258 | }; | |
259 | ||
260 | ret = i2c_transfer(client->adapter, &msg, 1); | |
261 | udelay(100); | |
262 | ||
263 | if (ret < 0) { | |
264 | dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg); | |
265 | return ret; | |
266 | } | |
267 | return 0; | |
268 | } | |
269 | ||
270 | ||
271 | /* Read a register, alter its bits, write it back */ | |
272 | static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask) | |
273 | { | |
274 | u8 val; | |
275 | int ret; | |
276 | ||
277 | ret = ov6650_reg_read(client, reg, &val); | |
278 | if (ret) { | |
279 | dev_err(&client->dev, | |
280 | "[Read]-Modify-Write of register 0x%02x failed!\n", | |
281 | reg); | |
282 | return ret; | |
283 | } | |
284 | ||
285 | val &= ~mask; | |
286 | val |= set; | |
287 | ||
288 | ret = ov6650_reg_write(client, reg, val); | |
289 | if (ret) | |
290 | dev_err(&client->dev, | |
291 | "Read-Modify-[Write] of register 0x%02x failed!\n", | |
292 | reg); | |
293 | ||
294 | return ret; | |
295 | } | |
296 | ||
297 | static struct ov6650 *to_ov6650(const struct i2c_client *client) | |
298 | { | |
299 | return container_of(i2c_get_clientdata(client), struct ov6650, subdev); | |
300 | } | |
301 | ||
302 | /* Start/Stop streaming from the device */ | |
303 | static int ov6650_s_stream(struct v4l2_subdev *sd, int enable) | |
304 | { | |
305 | return 0; | |
306 | } | |
307 | ||
2f6e2404 | 308 | /* Get status of additional camera capabilities */ |
afd9690c | 309 | static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl) |
2f6e2404 | 310 | { |
afd9690c HV |
311 | struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); |
312 | struct v4l2_subdev *sd = &priv->subdev; | |
2f6e2404 | 313 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
afd9690c | 314 | uint8_t reg, reg2; |
2e56d933 | 315 | int ret; |
2f6e2404 JK |
316 | |
317 | switch (ctrl->id) { | |
318 | case V4L2_CID_AUTOGAIN: | |
afd9690c HV |
319 | ret = ov6650_reg_read(client, REG_GAIN, ®); |
320 | if (!ret) | |
321 | priv->gain->val = reg; | |
322 | return ret; | |
2f6e2404 | 323 | case V4L2_CID_AUTO_WHITE_BALANCE: |
afd9690c HV |
324 | ret = ov6650_reg_read(client, REG_BLUE, ®); |
325 | if (!ret) | |
326 | ret = ov6650_reg_read(client, REG_RED, ®2); | |
327 | if (!ret) { | |
328 | priv->blue->val = reg; | |
329 | priv->red->val = reg2; | |
2f6e2404 | 330 | } |
afd9690c | 331 | return ret; |
2f6e2404 | 332 | case V4L2_CID_EXPOSURE_AUTO: |
afd9690c HV |
333 | ret = ov6650_reg_read(client, REG_AECH, ®); |
334 | if (!ret) | |
335 | priv->exposure->val = reg; | |
336 | return ret; | |
2f6e2404 | 337 | } |
afd9690c | 338 | return -EINVAL; |
2f6e2404 JK |
339 | } |
340 | ||
341 | /* Set status of additional camera capabilities */ | |
afd9690c | 342 | static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl) |
2f6e2404 | 343 | { |
afd9690c HV |
344 | struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl); |
345 | struct v4l2_subdev *sd = &priv->subdev; | |
2f6e2404 | 346 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
2e56d933 | 347 | int ret; |
2f6e2404 JK |
348 | |
349 | switch (ctrl->id) { | |
350 | case V4L2_CID_AUTOGAIN: | |
351 | ret = ov6650_reg_rmw(client, REG_COMB, | |
afd9690c HV |
352 | ctrl->val ? COMB_AGC : 0, COMB_AGC); |
353 | if (!ret && !ctrl->val) | |
354 | ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val); | |
355 | return ret; | |
2f6e2404 JK |
356 | case V4L2_CID_AUTO_WHITE_BALANCE: |
357 | ret = ov6650_reg_rmw(client, REG_COMB, | |
afd9690c HV |
358 | ctrl->val ? COMB_AWB : 0, COMB_AWB); |
359 | if (!ret && !ctrl->val) { | |
360 | ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val); | |
361 | if (!ret) | |
362 | ret = ov6650_reg_write(client, REG_RED, | |
363 | priv->red->val); | |
364 | } | |
365 | return ret; | |
2f6e2404 | 366 | case V4L2_CID_SATURATION: |
afd9690c | 367 | return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val), |
2f6e2404 | 368 | SAT_MASK); |
2f6e2404 | 369 | case V4L2_CID_HUE: |
afd9690c | 370 | return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val), |
2f6e2404 | 371 | HUE_MASK); |
2f6e2404 | 372 | case V4L2_CID_BRIGHTNESS: |
afd9690c | 373 | return ov6650_reg_write(client, REG_BRT, ctrl->val); |
2f6e2404 | 374 | case V4L2_CID_EXPOSURE_AUTO: |
2e56d933 JK |
375 | ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val == |
376 | V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC); | |
afd9690c HV |
377 | if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL) |
378 | ret = ov6650_reg_write(client, REG_AECH, | |
379 | priv->exposure->val); | |
380 | return ret; | |
2f6e2404 | 381 | case V4L2_CID_GAMMA: |
afd9690c | 382 | return ov6650_reg_write(client, REG_GAM1, ctrl->val); |
2f6e2404 | 383 | case V4L2_CID_VFLIP: |
afd9690c HV |
384 | return ov6650_reg_rmw(client, REG_COMB, |
385 | ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V); | |
2f6e2404 | 386 | case V4L2_CID_HFLIP: |
afd9690c HV |
387 | return ov6650_reg_rmw(client, REG_COMB, |
388 | ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H); | |
2f6e2404 JK |
389 | } |
390 | ||
afd9690c | 391 | return -EINVAL; |
2f6e2404 JK |
392 | } |
393 | ||
2f6e2404 JK |
394 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
395 | static int ov6650_get_register(struct v4l2_subdev *sd, | |
396 | struct v4l2_dbg_register *reg) | |
397 | { | |
398 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
399 | int ret; | |
400 | u8 val; | |
401 | ||
402 | if (reg->reg & ~0xff) | |
403 | return -EINVAL; | |
404 | ||
405 | reg->size = 1; | |
406 | ||
407 | ret = ov6650_reg_read(client, reg->reg, &val); | |
408 | if (!ret) | |
409 | reg->val = (__u64)val; | |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
414 | static int ov6650_set_register(struct v4l2_subdev *sd, | |
977ba3b1 | 415 | const struct v4l2_dbg_register *reg) |
2f6e2404 JK |
416 | { |
417 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
418 | ||
419 | if (reg->reg & ~0xff || reg->val & ~0xff) | |
420 | return -EINVAL; | |
421 | ||
422 | return ov6650_reg_write(client, reg->reg, reg->val); | |
423 | } | |
424 | #endif | |
425 | ||
4ec10bac LP |
426 | static int ov6650_s_power(struct v4l2_subdev *sd, int on) |
427 | { | |
428 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 429 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
9aea470b | 430 | struct ov6650 *priv = to_ov6650(client); |
4ec10bac | 431 | |
9aea470b | 432 | return soc_camera_set_power(&client->dev, ssdd, priv->clk, on); |
4ec10bac LP |
433 | } |
434 | ||
2f6e2404 JK |
435 | static int ov6650_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a) |
436 | { | |
437 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
438 | struct ov6650 *priv = to_ov6650(client); | |
439 | ||
440 | a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
441 | a->c = priv->rect; | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
4f996594 | 446 | static int ov6650_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a) |
2f6e2404 JK |
447 | { |
448 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
449 | struct ov6650 *priv = to_ov6650(client); | |
4f996594 | 450 | struct v4l2_rect rect = a->c; |
2f6e2404 JK |
451 | int ret; |
452 | ||
453 | if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
454 | return -EINVAL; | |
455 | ||
4f996594 HV |
456 | rect.left = ALIGN(rect.left, 2); |
457 | rect.width = ALIGN(rect.width, 2); | |
458 | rect.top = ALIGN(rect.top, 2); | |
459 | rect.height = ALIGN(rect.height, 2); | |
460 | soc_camera_limit_side(&rect.left, &rect.width, | |
2f6e2404 | 461 | DEF_HSTRT << 1, 2, W_CIF); |
4f996594 | 462 | soc_camera_limit_side(&rect.top, &rect.height, |
2f6e2404 JK |
463 | DEF_VSTRT << 1, 2, H_CIF); |
464 | ||
4f996594 | 465 | ret = ov6650_reg_write(client, REG_HSTRT, rect.left >> 1); |
2f6e2404 | 466 | if (!ret) { |
4f996594 | 467 | priv->rect.left = rect.left; |
2f6e2404 | 468 | ret = ov6650_reg_write(client, REG_HSTOP, |
4f996594 | 469 | (rect.left + rect.width) >> 1); |
2f6e2404 JK |
470 | } |
471 | if (!ret) { | |
4f996594 HV |
472 | priv->rect.width = rect.width; |
473 | ret = ov6650_reg_write(client, REG_VSTRT, rect.top >> 1); | |
2f6e2404 JK |
474 | } |
475 | if (!ret) { | |
4f996594 | 476 | priv->rect.top = rect.top; |
2f6e2404 | 477 | ret = ov6650_reg_write(client, REG_VSTOP, |
4f996594 | 478 | (rect.top + rect.height) >> 1); |
2f6e2404 JK |
479 | } |
480 | if (!ret) | |
4f996594 | 481 | priv->rect.height = rect.height; |
2f6e2404 JK |
482 | |
483 | return ret; | |
484 | } | |
485 | ||
486 | static int ov6650_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a) | |
487 | { | |
488 | if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
489 | return -EINVAL; | |
490 | ||
491 | a->bounds.left = DEF_HSTRT << 1; | |
492 | a->bounds.top = DEF_VSTRT << 1; | |
493 | a->bounds.width = W_CIF; | |
494 | a->bounds.height = H_CIF; | |
495 | a->defrect = a->bounds; | |
496 | a->pixelaspect.numerator = 1; | |
497 | a->pixelaspect.denominator = 1; | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
da298c6d HV |
502 | static int ov6650_get_fmt(struct v4l2_subdev *sd, |
503 | struct v4l2_subdev_pad_config *cfg, | |
504 | struct v4l2_subdev_format *format) | |
2f6e2404 | 505 | { |
da298c6d | 506 | struct v4l2_mbus_framefmt *mf = &format->format; |
2f6e2404 JK |
507 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
508 | struct ov6650 *priv = to_ov6650(client); | |
509 | ||
da298c6d HV |
510 | if (format->pad) |
511 | return -EINVAL; | |
512 | ||
2f6e2404 JK |
513 | mf->width = priv->rect.width >> priv->half_scale; |
514 | mf->height = priv->rect.height >> priv->half_scale; | |
515 | mf->code = priv->code; | |
516 | mf->colorspace = priv->colorspace; | |
517 | mf->field = V4L2_FIELD_NONE; | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect) | |
523 | { | |
d889eb1e | 524 | return width > rect->width >> 1 || height > rect->height >> 1; |
2f6e2404 JK |
525 | } |
526 | ||
527 | static u8 to_clkrc(struct v4l2_fract *timeperframe, | |
528 | unsigned long pclk_limit, unsigned long pclk_max) | |
529 | { | |
530 | unsigned long pclk; | |
531 | ||
532 | if (timeperframe->numerator && timeperframe->denominator) | |
533 | pclk = pclk_max * timeperframe->denominator / | |
534 | (FRAME_RATE_MAX * timeperframe->numerator); | |
535 | else | |
536 | pclk = pclk_max; | |
537 | ||
538 | if (pclk_limit && pclk_limit < pclk) | |
539 | pclk = pclk_limit; | |
540 | ||
541 | return (pclk_max - 1) / pclk; | |
542 | } | |
543 | ||
544 | /* set the format we will capture in */ | |
545 | static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf) | |
546 | { | |
547 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
4c0b036d | 548 | struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd); |
2f6e2404 JK |
549 | struct soc_camera_sense *sense = icd->sense; |
550 | struct ov6650 *priv = to_ov6650(client); | |
551 | bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect); | |
552 | struct v4l2_crop a = { | |
553 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
554 | .c = { | |
555 | .left = priv->rect.left + (priv->rect.width >> 1) - | |
556 | (mf->width >> (1 - half_scale)), | |
557 | .top = priv->rect.top + (priv->rect.height >> 1) - | |
558 | (mf->height >> (1 - half_scale)), | |
559 | .width = mf->width << half_scale, | |
560 | .height = mf->height << half_scale, | |
561 | }, | |
562 | }; | |
f5fe58fd | 563 | u32 code = mf->code; |
2f6e2404 JK |
564 | unsigned long mclk, pclk; |
565 | u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc; | |
566 | int ret; | |
567 | ||
568 | /* select color matrix configuration for given color encoding */ | |
569 | switch (code) { | |
f5fe58fd | 570 | case MEDIA_BUS_FMT_Y8_1X8: |
2f6e2404 JK |
571 | dev_dbg(&client->dev, "pixel format GREY8_1X8\n"); |
572 | coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP; | |
573 | coma_set |= COMA_BW; | |
574 | break; | |
f5fe58fd | 575 | case MEDIA_BUS_FMT_YUYV8_2X8: |
2f6e2404 JK |
576 | dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n"); |
577 | coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP; | |
578 | coma_set |= COMA_WORD_SWAP; | |
579 | break; | |
f5fe58fd | 580 | case MEDIA_BUS_FMT_YVYU8_2X8: |
2f6e2404 JK |
581 | dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n"); |
582 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP | | |
583 | COMA_BYTE_SWAP; | |
584 | break; | |
f5fe58fd | 585 | case MEDIA_BUS_FMT_UYVY8_2X8: |
2f6e2404 JK |
586 | dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n"); |
587 | if (half_scale) { | |
588 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; | |
589 | coma_set |= COMA_BYTE_SWAP; | |
590 | } else { | |
591 | coma_mask |= COMA_RGB | COMA_BW; | |
592 | coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; | |
593 | } | |
594 | break; | |
f5fe58fd | 595 | case MEDIA_BUS_FMT_VYUY8_2X8: |
2f6e2404 JK |
596 | dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n"); |
597 | if (half_scale) { | |
598 | coma_mask |= COMA_RGB | COMA_BW; | |
599 | coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP; | |
600 | } else { | |
601 | coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP; | |
602 | coma_set |= COMA_BYTE_SWAP; | |
603 | } | |
604 | break; | |
f5fe58fd | 605 | case MEDIA_BUS_FMT_SBGGR8_1X8: |
2f6e2404 JK |
606 | dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n"); |
607 | coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP; | |
608 | coma_set |= COMA_RAW_RGB | COMA_RGB; | |
609 | break; | |
2f6e2404 JK |
610 | default: |
611 | dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code); | |
612 | return -EINVAL; | |
613 | } | |
614 | priv->code = code; | |
615 | ||
f5fe58fd BB |
616 | if (code == MEDIA_BUS_FMT_Y8_1X8 || |
617 | code == MEDIA_BUS_FMT_SBGGR8_1X8) { | |
2f6e2404 JK |
618 | coml_mask = COML_ONE_CHANNEL; |
619 | coml_set = 0; | |
620 | priv->pclk_max = 4000000; | |
621 | } else { | |
622 | coml_mask = 0; | |
623 | coml_set = COML_ONE_CHANNEL; | |
624 | priv->pclk_max = 8000000; | |
625 | } | |
626 | ||
f5fe58fd | 627 | if (code == MEDIA_BUS_FMT_SBGGR8_1X8) |
2f6e2404 JK |
628 | priv->colorspace = V4L2_COLORSPACE_SRGB; |
629 | else if (code != 0) | |
630 | priv->colorspace = V4L2_COLORSPACE_JPEG; | |
631 | ||
632 | if (half_scale) { | |
633 | dev_dbg(&client->dev, "max resolution: QCIF\n"); | |
634 | coma_set |= COMA_QCIF; | |
635 | priv->pclk_max /= 2; | |
636 | } else { | |
637 | dev_dbg(&client->dev, "max resolution: CIF\n"); | |
638 | coma_mask |= COMA_QCIF; | |
639 | } | |
640 | priv->half_scale = half_scale; | |
641 | ||
642 | if (sense) { | |
643 | if (sense->master_clock == 8000000) { | |
644 | dev_dbg(&client->dev, "8MHz input clock\n"); | |
645 | clkrc = CLKRC_6MHz; | |
646 | } else if (sense->master_clock == 12000000) { | |
647 | dev_dbg(&client->dev, "12MHz input clock\n"); | |
648 | clkrc = CLKRC_12MHz; | |
649 | } else if (sense->master_clock == 16000000) { | |
650 | dev_dbg(&client->dev, "16MHz input clock\n"); | |
651 | clkrc = CLKRC_16MHz; | |
652 | } else if (sense->master_clock == 24000000) { | |
653 | dev_dbg(&client->dev, "24MHz input clock\n"); | |
654 | clkrc = CLKRC_24MHz; | |
655 | } else { | |
656 | dev_err(&client->dev, | |
6d73d072 | 657 | "unsupported input clock, check platform data\n"); |
2f6e2404 JK |
658 | return -EINVAL; |
659 | } | |
660 | mclk = sense->master_clock; | |
661 | priv->pclk_limit = sense->pixel_clock_max; | |
662 | } else { | |
663 | clkrc = CLKRC_24MHz; | |
664 | mclk = 24000000; | |
665 | priv->pclk_limit = 0; | |
666 | dev_dbg(&client->dev, "using default 24MHz input clock\n"); | |
667 | } | |
668 | ||
669 | clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max); | |
670 | ||
671 | pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc); | |
672 | dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n", | |
673 | mclk / pclk, 10 * mclk % pclk / pclk); | |
674 | ||
675 | ret = ov6650_s_crop(sd, &a); | |
676 | if (!ret) | |
677 | ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask); | |
678 | if (!ret) | |
679 | ret = ov6650_reg_write(client, REG_CLKRC, clkrc); | |
680 | if (!ret) | |
681 | ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask); | |
682 | ||
683 | if (!ret) { | |
684 | mf->colorspace = priv->colorspace; | |
685 | mf->width = priv->rect.width >> half_scale; | |
686 | mf->height = priv->rect.height >> half_scale; | |
687 | } | |
2f6e2404 JK |
688 | return ret; |
689 | } | |
690 | ||
717fd5b4 HV |
691 | static int ov6650_set_fmt(struct v4l2_subdev *sd, |
692 | struct v4l2_subdev_pad_config *cfg, | |
693 | struct v4l2_subdev_format *format) | |
2f6e2404 | 694 | { |
717fd5b4 | 695 | struct v4l2_mbus_framefmt *mf = &format->format; |
2f6e2404 JK |
696 | struct i2c_client *client = v4l2_get_subdevdata(sd); |
697 | struct ov6650 *priv = to_ov6650(client); | |
698 | ||
717fd5b4 HV |
699 | if (format->pad) |
700 | return -EINVAL; | |
701 | ||
2f6e2404 JK |
702 | if (is_unscaled_ok(mf->width, mf->height, &priv->rect)) |
703 | v4l_bound_align_image(&mf->width, 2, W_CIF, 1, | |
704 | &mf->height, 2, H_CIF, 1, 0); | |
705 | ||
706 | mf->field = V4L2_FIELD_NONE; | |
707 | ||
708 | switch (mf->code) { | |
f5fe58fd BB |
709 | case MEDIA_BUS_FMT_Y10_1X10: |
710 | mf->code = MEDIA_BUS_FMT_Y8_1X8; | |
711 | case MEDIA_BUS_FMT_Y8_1X8: | |
712 | case MEDIA_BUS_FMT_YVYU8_2X8: | |
713 | case MEDIA_BUS_FMT_YUYV8_2X8: | |
714 | case MEDIA_BUS_FMT_VYUY8_2X8: | |
715 | case MEDIA_BUS_FMT_UYVY8_2X8: | |
2f6e2404 JK |
716 | mf->colorspace = V4L2_COLORSPACE_JPEG; |
717 | break; | |
718 | default: | |
f5fe58fd BB |
719 | mf->code = MEDIA_BUS_FMT_SBGGR8_1X8; |
720 | case MEDIA_BUS_FMT_SBGGR8_1X8: | |
2f6e2404 JK |
721 | mf->colorspace = V4L2_COLORSPACE_SRGB; |
722 | break; | |
723 | } | |
724 | ||
717fd5b4 HV |
725 | if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) |
726 | return ov6650_s_fmt(sd, mf); | |
727 | cfg->try_fmt = *mf; | |
728 | ||
2f6e2404 JK |
729 | return 0; |
730 | } | |
731 | ||
ebcff5fc HV |
732 | static int ov6650_enum_mbus_code(struct v4l2_subdev *sd, |
733 | struct v4l2_subdev_pad_config *cfg, | |
734 | struct v4l2_subdev_mbus_code_enum *code) | |
2f6e2404 | 735 | { |
ebcff5fc | 736 | if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes)) |
2f6e2404 JK |
737 | return -EINVAL; |
738 | ||
ebcff5fc | 739 | code->code = ov6650_codes[code->index]; |
2f6e2404 JK |
740 | return 0; |
741 | } | |
742 | ||
743 | static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) | |
744 | { | |
745 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
746 | struct ov6650 *priv = to_ov6650(client); | |
747 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
748 | ||
749 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
750 | return -EINVAL; | |
751 | ||
752 | memset(cp, 0, sizeof(*cp)); | |
753 | cp->capability = V4L2_CAP_TIMEPERFRAME; | |
754 | cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf, | |
755 | priv->pclk_limit, priv->pclk_max)); | |
756 | cp->timeperframe.denominator = FRAME_RATE_MAX; | |
757 | ||
758 | dev_dbg(&client->dev, "Frame interval: %u/%u s\n", | |
759 | cp->timeperframe.numerator, cp->timeperframe.denominator); | |
760 | ||
761 | return 0; | |
762 | } | |
763 | ||
764 | static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms) | |
765 | { | |
766 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
767 | struct ov6650 *priv = to_ov6650(client); | |
768 | struct v4l2_captureparm *cp = &parms->parm.capture; | |
769 | struct v4l2_fract *tpf = &cp->timeperframe; | |
770 | int div, ret; | |
771 | u8 clkrc; | |
772 | ||
773 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
774 | return -EINVAL; | |
775 | ||
776 | if (cp->extendedmode != 0) | |
777 | return -EINVAL; | |
778 | ||
779 | if (tpf->numerator == 0 || tpf->denominator == 0) | |
780 | div = 1; /* Reset to full rate */ | |
781 | else | |
782 | div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator; | |
783 | ||
784 | if (div == 0) | |
785 | div = 1; | |
786 | else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK)) | |
787 | div = GET_CLKRC_DIV(CLKRC_DIV_MASK); | |
788 | ||
789 | /* | |
790 | * Keep result to be used as tpf limit | |
791 | * for subseqent clock divider calculations | |
792 | */ | |
793 | priv->tpf.numerator = div; | |
794 | priv->tpf.denominator = FRAME_RATE_MAX; | |
795 | ||
796 | clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max); | |
797 | ||
798 | ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK); | |
799 | if (!ret) { | |
800 | tpf->numerator = GET_CLKRC_DIV(clkrc); | |
801 | tpf->denominator = FRAME_RATE_MAX; | |
802 | } | |
803 | ||
804 | return ret; | |
805 | } | |
806 | ||
807 | /* Soft reset the camera. This has nothing to do with the RESET pin! */ | |
808 | static int ov6650_reset(struct i2c_client *client) | |
809 | { | |
810 | int ret; | |
811 | ||
812 | dev_dbg(&client->dev, "reset\n"); | |
813 | ||
814 | ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0); | |
815 | if (ret) | |
816 | dev_err(&client->dev, | |
25985edc | 817 | "An error occurred while entering soft reset!\n"); |
2f6e2404 JK |
818 | |
819 | return ret; | |
820 | } | |
821 | ||
822 | /* program default register values */ | |
823 | static int ov6650_prog_dflt(struct i2c_client *client) | |
824 | { | |
825 | int ret; | |
826 | ||
827 | dev_dbg(&client->dev, "initializing\n"); | |
828 | ||
829 | ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */ | |
830 | if (!ret) | |
831 | ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER); | |
832 | ||
833 | return ret; | |
834 | } | |
835 | ||
14178aa5 | 836 | static int ov6650_video_probe(struct i2c_client *client) |
2f6e2404 | 837 | { |
4bbc6d52 | 838 | struct ov6650 *priv = to_ov6650(client); |
2f6e2404 | 839 | u8 pidh, pidl, midh, midl; |
4bbc6d52 LP |
840 | int ret; |
841 | ||
842 | ret = ov6650_s_power(&priv->subdev, 1); | |
843 | if (ret < 0) | |
844 | return ret; | |
2f6e2404 JK |
845 | |
846 | /* | |
847 | * check and show product ID and manufacturer ID | |
848 | */ | |
849 | ret = ov6650_reg_read(client, REG_PIDH, &pidh); | |
850 | if (!ret) | |
851 | ret = ov6650_reg_read(client, REG_PIDL, &pidl); | |
852 | if (!ret) | |
853 | ret = ov6650_reg_read(client, REG_MIDH, &midh); | |
854 | if (!ret) | |
855 | ret = ov6650_reg_read(client, REG_MIDL, &midl); | |
856 | ||
857 | if (ret) | |
4bbc6d52 | 858 | goto done; |
2f6e2404 JK |
859 | |
860 | if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) { | |
861 | dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n", | |
862 | pidh, pidl); | |
4bbc6d52 LP |
863 | ret = -ENODEV; |
864 | goto done; | |
2f6e2404 JK |
865 | } |
866 | ||
867 | dev_info(&client->dev, | |
868 | "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n", | |
869 | pidh, pidl, midh, midl); | |
870 | ||
871 | ret = ov6650_reset(client); | |
872 | if (!ret) | |
873 | ret = ov6650_prog_dflt(client); | |
4bbc6d52 LP |
874 | if (!ret) |
875 | ret = v4l2_ctrl_handler_setup(&priv->hdl); | |
2f6e2404 | 876 | |
4bbc6d52 LP |
877 | done: |
878 | ov6650_s_power(&priv->subdev, 0); | |
2f6e2404 JK |
879 | return ret; |
880 | } | |
881 | ||
afd9690c HV |
882 | static const struct v4l2_ctrl_ops ov6550_ctrl_ops = { |
883 | .g_volatile_ctrl = ov6550_g_volatile_ctrl, | |
884 | .s_ctrl = ov6550_s_ctrl, | |
2f6e2404 JK |
885 | }; |
886 | ||
887 | static struct v4l2_subdev_core_ops ov6650_core_ops = { | |
2f6e2404 JK |
888 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
889 | .g_register = ov6650_get_register, | |
890 | .s_register = ov6650_set_register, | |
891 | #endif | |
4ec10bac | 892 | .s_power = ov6650_s_power, |
2f6e2404 JK |
893 | }; |
894 | ||
db669e79 | 895 | /* Request bus settings on camera side */ |
59ca25b7 GL |
896 | static int ov6650_g_mbus_config(struct v4l2_subdev *sd, |
897 | struct v4l2_mbus_config *cfg) | |
898 | { | |
899 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 | 900 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
59ca25b7 GL |
901 | |
902 | cfg->flags = V4L2_MBUS_MASTER | | |
903 | V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING | | |
904 | V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW | | |
905 | V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW | | |
906 | V4L2_MBUS_DATA_ACTIVE_HIGH; | |
907 | cfg->type = V4L2_MBUS_PARALLEL; | |
25a34811 | 908 | cfg->flags = soc_camera_apply_board_flags(ssdd, cfg); |
59ca25b7 GL |
909 | |
910 | return 0; | |
911 | } | |
912 | ||
db669e79 | 913 | /* Alter bus settings on camera side */ |
59ca25b7 GL |
914 | static int ov6650_s_mbus_config(struct v4l2_subdev *sd, |
915 | const struct v4l2_mbus_config *cfg) | |
916 | { | |
917 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
25a34811 GL |
918 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
919 | unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg); | |
59ca25b7 GL |
920 | int ret; |
921 | ||
922 | if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING) | |
923 | ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0); | |
924 | else | |
925 | ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING); | |
926 | if (ret) | |
927 | return ret; | |
928 | ||
929 | if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW) | |
930 | ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0); | |
931 | else | |
932 | ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW); | |
933 | if (ret) | |
934 | return ret; | |
935 | ||
936 | if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) | |
937 | ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0); | |
938 | else | |
939 | ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH); | |
940 | ||
941 | return ret; | |
942 | } | |
943 | ||
2f6e2404 JK |
944 | static struct v4l2_subdev_video_ops ov6650_video_ops = { |
945 | .s_stream = ov6650_s_stream, | |
2f6e2404 JK |
946 | .cropcap = ov6650_cropcap, |
947 | .g_crop = ov6650_g_crop, | |
948 | .s_crop = ov6650_s_crop, | |
949 | .g_parm = ov6650_g_parm, | |
950 | .s_parm = ov6650_s_parm, | |
59ca25b7 GL |
951 | .g_mbus_config = ov6650_g_mbus_config, |
952 | .s_mbus_config = ov6650_s_mbus_config, | |
2f6e2404 JK |
953 | }; |
954 | ||
ebcff5fc HV |
955 | static const struct v4l2_subdev_pad_ops ov6650_pad_ops = { |
956 | .enum_mbus_code = ov6650_enum_mbus_code, | |
da298c6d | 957 | .get_fmt = ov6650_get_fmt, |
717fd5b4 | 958 | .set_fmt = ov6650_set_fmt, |
ebcff5fc HV |
959 | }; |
960 | ||
2f6e2404 JK |
961 | static struct v4l2_subdev_ops ov6650_subdev_ops = { |
962 | .core = &ov6650_core_ops, | |
963 | .video = &ov6650_video_ops, | |
ebcff5fc | 964 | .pad = &ov6650_pad_ops, |
2f6e2404 JK |
965 | }; |
966 | ||
967 | /* | |
968 | * i2c_driver function | |
969 | */ | |
970 | static int ov6650_probe(struct i2c_client *client, | |
971 | const struct i2c_device_id *did) | |
972 | { | |
973 | struct ov6650 *priv; | |
25a34811 | 974 | struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client); |
2f6e2404 JK |
975 | int ret; |
976 | ||
25a34811 | 977 | if (!ssdd) { |
2f6e2404 JK |
978 | dev_err(&client->dev, "Missing platform_data for driver\n"); |
979 | return -EINVAL; | |
980 | } | |
981 | ||
70e176a5 | 982 | priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL); |
2f6e2404 JK |
983 | if (!priv) { |
984 | dev_err(&client->dev, | |
985 | "Failed to allocate memory for private data!\n"); | |
986 | return -ENOMEM; | |
987 | } | |
988 | ||
989 | v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops); | |
afd9690c HV |
990 | v4l2_ctrl_handler_init(&priv->hdl, 13); |
991 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
992 | V4L2_CID_VFLIP, 0, 1, 1, 0); | |
993 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
994 | V4L2_CID_HFLIP, 0, 1, 1, 0); | |
995 | priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
996 | V4L2_CID_AUTOGAIN, 0, 1, 1, 1); | |
997 | priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
998 | V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN); | |
999 | priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1000 | V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1); | |
1001 | priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1002 | V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE); | |
1003 | priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1004 | V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED); | |
1005 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1006 | V4L2_CID_SATURATION, 0, 0xf, 1, 0x8); | |
1007 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1008 | V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE); | |
1009 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1010 | V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80); | |
1011 | priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl, | |
2e56d933 JK |
1012 | &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, |
1013 | V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO); | |
afd9690c HV |
1014 | priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, |
1015 | V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH); | |
1016 | v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops, | |
1017 | V4L2_CID_GAMMA, 0, 0xff, 1, 0x12); | |
1018 | ||
1019 | priv->subdev.ctrl_handler = &priv->hdl; | |
70e176a5 GL |
1020 | if (priv->hdl.error) |
1021 | return priv->hdl.error; | |
2f6e2404 | 1022 | |
afd9690c HV |
1023 | v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true); |
1024 | v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true); | |
1025 | v4l2_ctrl_auto_cluster(2, &priv->autoexposure, | |
1026 | V4L2_EXPOSURE_MANUAL, true); | |
2f6e2404 JK |
1027 | |
1028 | priv->rect.left = DEF_HSTRT << 1; | |
1029 | priv->rect.top = DEF_VSTRT << 1; | |
1030 | priv->rect.width = W_CIF; | |
1031 | priv->rect.height = H_CIF; | |
1032 | priv->half_scale = false; | |
f5fe58fd | 1033 | priv->code = MEDIA_BUS_FMT_YUYV8_2X8; |
2f6e2404 JK |
1034 | priv->colorspace = V4L2_COLORSPACE_JPEG; |
1035 | ||
9aea470b GL |
1036 | priv->clk = v4l2_clk_get(&client->dev, "mclk"); |
1037 | if (IS_ERR(priv->clk)) { | |
1038 | ret = PTR_ERR(priv->clk); | |
1039 | goto eclkget; | |
1040 | } | |
1041 | ||
14178aa5 | 1042 | ret = ov6650_video_probe(client); |
9aea470b GL |
1043 | if (ret) { |
1044 | v4l2_clk_put(priv->clk); | |
1045 | eclkget: | |
afd9690c | 1046 | v4l2_ctrl_handler_free(&priv->hdl); |
9aea470b | 1047 | } |
2f6e2404 JK |
1048 | |
1049 | return ret; | |
1050 | } | |
1051 | ||
1052 | static int ov6650_remove(struct i2c_client *client) | |
1053 | { | |
1054 | struct ov6650 *priv = to_ov6650(client); | |
1055 | ||
9aea470b | 1056 | v4l2_clk_put(priv->clk); |
afd9690c HV |
1057 | v4l2_device_unregister_subdev(&priv->subdev); |
1058 | v4l2_ctrl_handler_free(&priv->hdl); | |
2f6e2404 JK |
1059 | return 0; |
1060 | } | |
1061 | ||
1062 | static const struct i2c_device_id ov6650_id[] = { | |
1063 | { "ov6650", 0 }, | |
1064 | { } | |
1065 | }; | |
1066 | MODULE_DEVICE_TABLE(i2c, ov6650_id); | |
1067 | ||
1068 | static struct i2c_driver ov6650_i2c_driver = { | |
1069 | .driver = { | |
1070 | .name = "ov6650", | |
1071 | }, | |
1072 | .probe = ov6650_probe, | |
1073 | .remove = ov6650_remove, | |
1074 | .id_table = ov6650_id, | |
1075 | }; | |
1076 | ||
c6e8d86f | 1077 | module_i2c_driver(ov6650_i2c_driver); |
2f6e2404 JK |
1078 | |
1079 | MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650"); | |
1080 | MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>"); | |
1081 | MODULE_LICENSE("GPL v2"); |