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[media] V4L2: support asynchronous subdevice registration
[deliverable/linux.git] / drivers / media / i2c / soc_camera / ov9740.c
CommitLineData
9bd060e4
AC		 1/*
2 * OmniVision OV9740 Camera Driver
3 *
4 * Copyright (C) 2011 NVIDIA Corporation
5 *
6 * Based on ov9640 camera driver.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/i2c.h>
16#include <linux/slab.h>
95d20109 17#include <linux/v4l2-mediabus.h>
e534c9ea 18
9bd060e4 19#include <media/soc_camera.h>
34e181c5 20#include <media/v4l2-ctrls.h>
9bd060e4
AC		 21
22#define to_ov9740(sd) container_of(sd, struct ov9740_priv, subdev)
23
24/* General Status Registers */
25#define OV9740_MODEL_ID_HI 0x0000
26#define OV9740_MODEL_ID_LO 0x0001
27#define OV9740_REVISION_NUMBER 0x0002
28#define OV9740_MANUFACTURER_ID 0x0003
29#define OV9740_SMIA_VERSION 0x0004
30
31/* General Setup Registers */
32#define OV9740_MODE_SELECT 0x0100
33#define OV9740_IMAGE_ORT 0x0101
34#define OV9740_SOFTWARE_RESET 0x0103
35#define OV9740_GRP_PARAM_HOLD 0x0104
36#define OV9740_MSK_CORRUP_FM 0x0105
37
38/* Timing Setting */
39#define OV9740_FRM_LENGTH_LN_HI 0x0340 /* VTS */
40#define OV9740_FRM_LENGTH_LN_LO 0x0341 /* VTS */
41#define OV9740_LN_LENGTH_PCK_HI 0x0342 /* HTS */
42#define OV9740_LN_LENGTH_PCK_LO 0x0343 /* HTS */
43#define OV9740_X_ADDR_START_HI 0x0344
44#define OV9740_X_ADDR_START_LO 0x0345
45#define OV9740_Y_ADDR_START_HI 0x0346
46#define OV9740_Y_ADDR_START_LO 0x0347
47#define OV9740_X_ADDR_END_HI 0x0348
48#define OV9740_X_ADDR_END_LO 0x0349
c6aac9fc
AC		 49#define OV9740_Y_ADDR_END_HI 0x034a
50#define OV9740_Y_ADDR_END_LO 0x034b
51#define OV9740_X_OUTPUT_SIZE_HI 0x034c
52#define OV9740_X_OUTPUT_SIZE_LO 0x034d
53#define OV9740_Y_OUTPUT_SIZE_HI 0x034e
54#define OV9740_Y_OUTPUT_SIZE_LO 0x034f
9bd060e4
AC		 55
56/* IO Control Registers */
57#define OV9740_IO_CREL00 0x3002
58#define OV9740_IO_CREL01 0x3004
59#define OV9740_IO_CREL02 0x3005
60#define OV9740_IO_OUTPUT_SEL01 0x3026
61#define OV9740_IO_OUTPUT_SEL02 0x3027
62
63/* AWB Registers */
64#define OV9740_AWB_MANUAL_CTRL 0x3406
65
66/* Analog Control Registers */
67#define OV9740_ANALOG_CTRL01 0x3601
68#define OV9740_ANALOG_CTRL02 0x3602
69#define OV9740_ANALOG_CTRL03 0x3603
70#define OV9740_ANALOG_CTRL04 0x3604
71#define OV9740_ANALOG_CTRL10 0x3610
72#define OV9740_ANALOG_CTRL12 0x3612
c4fdce56 73#define OV9740_ANALOG_CTRL15 0x3615
9bd060e4
AC		 74#define OV9740_ANALOG_CTRL20 0x3620
75#define OV9740_ANALOG_CTRL21 0x3621
76#define OV9740_ANALOG_CTRL22 0x3622
77#define OV9740_ANALOG_CTRL30 0x3630
78#define OV9740_ANALOG_CTRL31 0x3631
79#define OV9740_ANALOG_CTRL32 0x3632
80#define OV9740_ANALOG_CTRL33 0x3633
81
82/* Sensor Control */
83#define OV9740_SENSOR_CTRL03 0x3703
84#define OV9740_SENSOR_CTRL04 0x3704
85#define OV9740_SENSOR_CTRL05 0x3705
86#define OV9740_SENSOR_CTRL07 0x3707
87
88/* Timing Control */
89#define OV9740_TIMING_CTRL17 0x3817
90#define OV9740_TIMING_CTRL19 0x3819
91#define OV9740_TIMING_CTRL33 0x3833
92#define OV9740_TIMING_CTRL35 0x3835
93
94/* Banding Filter */
c6aac9fc
AC		 95#define OV9740_AEC_MAXEXPO_60_H 0x3a02
96#define OV9740_AEC_MAXEXPO_60_L 0x3a03
97#define OV9740_AEC_B50_STEP_HI 0x3a08
98#define OV9740_AEC_B50_STEP_LO 0x3a09
99#define OV9740_AEC_B60_STEP_HI 0x3a0a
100#define OV9740_AEC_B60_STEP_LO 0x3a0b
101#define OV9740_AEC_CTRL0D 0x3a0d
102#define OV9740_AEC_CTRL0E 0x3a0e
103#define OV9740_AEC_MAXEXPO_50_H 0x3a14
104#define OV9740_AEC_MAXEXPO_50_L 0x3a15
9bd060e4
AC		 105
106/* AEC/AGC Control */
107#define OV9740_AEC_ENABLE 0x3503
c6aac9fc
AC		 108#define OV9740_GAIN_CEILING_01 0x3a18
109#define OV9740_GAIN_CEILING_02 0x3a19
110#define OV9740_AEC_HI_THRESHOLD 0x3a11
111#define OV9740_AEC_3A1A 0x3a1a
112#define OV9740_AEC_CTRL1B_WPT2 0x3a1b
113#define OV9740_AEC_CTRL0F_WPT 0x3a0f
114#define OV9740_AEC_CTRL10_BPT 0x3a10
115#define OV9740_AEC_CTRL1E_BPT2 0x3a1e
116#define OV9740_AEC_LO_THRESHOLD 0x3a1f
9bd060e4
AC		 117
118/* BLC Control */
119#define OV9740_BLC_AUTO_ENABLE 0x4002
120#define OV9740_BLC_MODE 0x4005
121
122/* VFIFO */
123#define OV9740_VFIFO_READ_START_HI 0x4608
124#define OV9740_VFIFO_READ_START_LO 0x4609
125
126/* DVP Control */
127#define OV9740_DVP_VSYNC_CTRL02 0x4702
128#define OV9740_DVP_VSYNC_MODE 0x4704
129#define OV9740_DVP_VSYNC_CTRL06 0x4706
130
131/* PLL Setting */
132#define OV9740_PLL_MODE_CTRL01 0x3104
133#define OV9740_PRE_PLL_CLK_DIV 0x0305
134#define OV9740_PLL_MULTIPLIER 0x0307
135#define OV9740_VT_SYS_CLK_DIV 0x0303
136#define OV9740_VT_PIX_CLK_DIV 0x0301
137#define OV9740_PLL_CTRL3010 0x3010
c6aac9fc 138#define OV9740_VFIFO_CTRL00 0x460e
9bd060e4
AC		 139
140/* ISP Control */
141#define OV9740_ISP_CTRL00 0x5000
142#define OV9740_ISP_CTRL01 0x5001
143#define OV9740_ISP_CTRL03 0x5003
144#define OV9740_ISP_CTRL05 0x5005
145#define OV9740_ISP_CTRL12 0x5012
146#define OV9740_ISP_CTRL19 0x5019
c6aac9fc
AC		 147#define OV9740_ISP_CTRL1A 0x501a
148#define OV9740_ISP_CTRL1E 0x501e
149#define OV9740_ISP_CTRL1F 0x501f
9bd060e4
AC		 150#define OV9740_ISP_CTRL20 0x5020
151#define OV9740_ISP_CTRL21 0x5021
152
153/* AWB */
154#define OV9740_AWB_CTRL00 0x5180
155#define OV9740_AWB_CTRL01 0x5181
156#define OV9740_AWB_CTRL02 0x5182
157#define OV9740_AWB_CTRL03 0x5183
158#define OV9740_AWB_ADV_CTRL01 0x5184
159#define OV9740_AWB_ADV_CTRL02 0x5185
160#define OV9740_AWB_ADV_CTRL03 0x5186
161#define OV9740_AWB_ADV_CTRL04 0x5187
162#define OV9740_AWB_ADV_CTRL05 0x5188
163#define OV9740_AWB_ADV_CTRL06 0x5189
c6aac9fc
AC		 164#define OV9740_AWB_ADV_CTRL07 0x518a
165#define OV9740_AWB_ADV_CTRL08 0x518b
166#define OV9740_AWB_ADV_CTRL09 0x518c
167#define OV9740_AWB_ADV_CTRL10 0x518d
168#define OV9740_AWB_ADV_CTRL11 0x518e
169#define OV9740_AWB_CTRL0F 0x518f
9bd060e4
AC		 170#define OV9740_AWB_CTRL10 0x5190
171#define OV9740_AWB_CTRL11 0x5191
172#define OV9740_AWB_CTRL12 0x5192
173#define OV9740_AWB_CTRL13 0x5193
174#define OV9740_AWB_CTRL14 0x5194
175
176/* MIPI Control */
177#define OV9740_MIPI_CTRL00 0x4800
178#define OV9740_MIPI_3837 0x3837
179#define OV9740_MIPI_CTRL01 0x4801
180#define OV9740_MIPI_CTRL03 0x4803
181#define OV9740_MIPI_CTRL05 0x4805
182#define OV9740_VFIFO_RD_CTRL 0x4601
183#define OV9740_MIPI_CTRL_3012 0x3012
184#define OV9740_SC_CMMM_MIPI_CTR 0x3014
185
970aa9e0
AC		 186#define OV9740_MAX_WIDTH 1280
187#define OV9740_MAX_HEIGHT 720
9bd060e4
AC		 188
189/* Misc. structures */
190struct ov9740_reg {
191 u16 reg;
192 u8 val;
193};
194
195struct ov9740_priv {
196 struct v4l2_subdev subdev;
34e181c5 197 struct v4l2_ctrl_handler hdl;
9bd060e4 198
9bd060e4
AC		 199 u16 model;
200 u8 revision;
201 u8 manid;
202 u8 smiaver;
203
204 bool flag_vflip;
205 bool flag_hflip;
95904d4b
AC		 206
207 /* For suspend/resume. */
208 struct v4l2_mbus_framefmt current_mf;
209 bool current_enable;
9bd060e4
AC		 210};
211
212static const struct ov9740_reg ov9740_defaults[] = {
c4fdce56
AC		 213 /* Software Reset */
214 { OV9740_SOFTWARE_RESET, 0x01 },
215
9bd060e4
AC		 216 /* Banding Filter */
217 { OV9740_AEC_B50_STEP_HI, 0x00 },
218 { OV9740_AEC_B50_STEP_LO, 0xe8 },
219 { OV9740_AEC_CTRL0E, 0x03 },
220 { OV9740_AEC_MAXEXPO_50_H, 0x15 },
221 { OV9740_AEC_MAXEXPO_50_L, 0xc6 },
222 { OV9740_AEC_B60_STEP_HI, 0x00 },
223 { OV9740_AEC_B60_STEP_LO, 0xc0 },
224 { OV9740_AEC_CTRL0D, 0x04 },
225 { OV9740_AEC_MAXEXPO_60_H, 0x18 },
226 { OV9740_AEC_MAXEXPO_60_L, 0x20 },
227
228 /* LC */
229 { 0x5842, 0x02 }, { 0x5843, 0x5e }, { 0x5844, 0x04 }, { 0x5845, 0x32 },
230 { 0x5846, 0x03 }, { 0x5847, 0x29 }, { 0x5848, 0x02 }, { 0x5849, 0xcc },
231
232 /* Un-documented OV9740 registers */
233 { 0x5800, 0x29 }, { 0x5801, 0x25 }, { 0x5802, 0x20 }, { 0x5803, 0x21 },
234 { 0x5804, 0x26 }, { 0x5805, 0x2e }, { 0x5806, 0x11 }, { 0x5807, 0x0c },
c6aac9fc
AC		 235 { 0x5808, 0x09 }, { 0x5809, 0x0a }, { 0x580a, 0x0e }, { 0x580b, 0x16 },
236 { 0x580c, 0x06 }, { 0x580d, 0x02 }, { 0x580e, 0x00 }, { 0x580f, 0x00 },
9bd060e4
AC		 237 { 0x5810, 0x04 }, { 0x5811, 0x0a }, { 0x5812, 0x05 }, { 0x5813, 0x02 },
238 { 0x5814, 0x00 }, { 0x5815, 0x00 }, { 0x5816, 0x03 }, { 0x5817, 0x09 },
c6aac9fc
AC		 239 { 0x5818, 0x0f }, { 0x5819, 0x0a }, { 0x581a, 0x07 }, { 0x581b, 0x08 },
240 { 0x581c, 0x0b }, { 0x581d, 0x14 }, { 0x581e, 0x28 }, { 0x581f, 0x23 },
9bd060e4
AC		 241 { 0x5820, 0x1d }, { 0x5821, 0x1e }, { 0x5822, 0x24 }, { 0x5823, 0x2a },
242 { 0x5824, 0x4f }, { 0x5825, 0x6f }, { 0x5826, 0x5f }, { 0x5827, 0x7f },
c6aac9fc
AC		 243 { 0x5828, 0x9f }, { 0x5829, 0x5f }, { 0x582a, 0x8f }, { 0x582b, 0x9e },
244 { 0x582c, 0x8f }, { 0x582d, 0x9f }, { 0x582e, 0x4f }, { 0x582f, 0x87 },
9bd060e4
AC		 245 { 0x5830, 0x86 }, { 0x5831, 0x97 }, { 0x5832, 0xae }, { 0x5833, 0x3f },
246 { 0x5834, 0x8e }, { 0x5835, 0x7c }, { 0x5836, 0x7e }, { 0x5837, 0xaf },
c6aac9fc
AC		 247 { 0x5838, 0x8f }, { 0x5839, 0x8f }, { 0x583a, 0x9f }, { 0x583b, 0x7f },
248 { 0x583c, 0x5f },
9bd060e4
AC		 249
250 /* Y Gamma */
251 { 0x5480, 0x07 }, { 0x5481, 0x18 }, { 0x5482, 0x2c }, { 0x5483, 0x4e },
252 { 0x5484, 0x5e }, { 0x5485, 0x6b }, { 0x5486, 0x77 }, { 0x5487, 0x82 },
c6aac9fc
AC		 253 { 0x5488, 0x8c }, { 0x5489, 0x95 }, { 0x548a, 0xa4 }, { 0x548b, 0xb1 },
254 { 0x548c, 0xc6 }, { 0x548d, 0xd8 }, { 0x548e, 0xe9 },
9bd060e4
AC		 255
256 /* UV Gamma */
257 { 0x5490, 0x0f }, { 0x5491, 0xff }, { 0x5492, 0x0d }, { 0x5493, 0x05 },
258 { 0x5494, 0x07 }, { 0x5495, 0x1a }, { 0x5496, 0x04 }, { 0x5497, 0x01 },
c6aac9fc
AC		 259 { 0x5498, 0x03 }, { 0x5499, 0x53 }, { 0x549a, 0x02 }, { 0x549b, 0xeb },
260 { 0x549c, 0x02 }, { 0x549d, 0xa0 }, { 0x549e, 0x02 }, { 0x549f, 0x67 },
261 { 0x54a0, 0x02 }, { 0x54a1, 0x3b }, { 0x54a2, 0x02 }, { 0x54a3, 0x18 },
262 { 0x54a4, 0x01 }, { 0x54a5, 0xe7 }, { 0x54a6, 0x01 }, { 0x54a7, 0xc3 },
263 { 0x54a8, 0x01 }, { 0x54a9, 0x94 }, { 0x54aa, 0x01 }, { 0x54ab, 0x72 },
264 { 0x54ac, 0x01 }, { 0x54ad, 0x57 },
9bd060e4
AC		 265
266 /* AWB */
267 { OV9740_AWB_CTRL00, 0xf0 },
268 { OV9740_AWB_CTRL01, 0x00 },
269 { OV9740_AWB_CTRL02, 0x41 },
270 { OV9740_AWB_CTRL03, 0x42 },
271 { OV9740_AWB_ADV_CTRL01, 0x8a },
272 { OV9740_AWB_ADV_CTRL02, 0x61 },
273 { OV9740_AWB_ADV_CTRL03, 0xce },
274 { OV9740_AWB_ADV_CTRL04, 0xa8 },
275 { OV9740_AWB_ADV_CTRL05, 0x17 },
276 { OV9740_AWB_ADV_CTRL06, 0x1f },
277 { OV9740_AWB_ADV_CTRL07, 0x27 },
278 { OV9740_AWB_ADV_CTRL08, 0x41 },
279 { OV9740_AWB_ADV_CTRL09, 0x34 },
280 { OV9740_AWB_ADV_CTRL10, 0xf0 },
281 { OV9740_AWB_ADV_CTRL11, 0x10 },
282 { OV9740_AWB_CTRL0F, 0xff },
283 { OV9740_AWB_CTRL10, 0x00 },
284 { OV9740_AWB_CTRL11, 0xff },
285 { OV9740_AWB_CTRL12, 0x00 },
286 { OV9740_AWB_CTRL13, 0xff },
287 { OV9740_AWB_CTRL14, 0x00 },
288
289 /* CIP */
c6aac9fc 290 { 0x530d, 0x12 },
9bd060e4
AC		 291
292 /* CMX */
293 { 0x5380, 0x01 }, { 0x5381, 0x00 }, { 0x5382, 0x00 }, { 0x5383, 0x17 },
294 { 0x5384, 0x00 }, { 0x5385, 0x01 }, { 0x5386, 0x00 }, { 0x5387, 0x00 },
c6aac9fc
AC		 295 { 0x5388, 0x00 }, { 0x5389, 0xe0 }, { 0x538a, 0x00 }, { 0x538b, 0x20 },
296 { 0x538c, 0x00 }, { 0x538d, 0x00 }, { 0x538e, 0x00 }, { 0x538f, 0x16 },
9bd060e4
AC		 297 { 0x5390, 0x00 }, { 0x5391, 0x9c }, { 0x5392, 0x00 }, { 0x5393, 0xa0 },
298 { 0x5394, 0x18 },
299
300 /* 50/60 Detection */
c6aac9fc 301 { 0x3c0a, 0x9c }, { 0x3c0b, 0x3f },
9bd060e4
AC		 302
303 /* Output Select */
304 { OV9740_IO_OUTPUT_SEL01, 0x00 },
305 { OV9740_IO_OUTPUT_SEL02, 0x00 },
306 { OV9740_IO_CREL00, 0x00 },
307 { OV9740_IO_CREL01, 0x00 },
308 { OV9740_IO_CREL02, 0x00 },
309
310 /* AWB Control */
311 { OV9740_AWB_MANUAL_CTRL, 0x00 },
312
313 /* Analog Control */
314 { OV9740_ANALOG_CTRL03, 0xaa },
315 { OV9740_ANALOG_CTRL32, 0x2f },
316 { OV9740_ANALOG_CTRL20, 0x66 },
317 { OV9740_ANALOG_CTRL21, 0xc0 },
318 { OV9740_ANALOG_CTRL31, 0x52 },
319 { OV9740_ANALOG_CTRL33, 0x50 },
320 { OV9740_ANALOG_CTRL30, 0xca },
321 { OV9740_ANALOG_CTRL04, 0x0c },
322 { OV9740_ANALOG_CTRL01, 0x40 },
323 { OV9740_ANALOG_CTRL02, 0x16 },
324 { OV9740_ANALOG_CTRL10, 0xa1 },
325 { OV9740_ANALOG_CTRL12, 0x24 },
326 { OV9740_ANALOG_CTRL22, 0x9f },
c4fdce56 327 { OV9740_ANALOG_CTRL15, 0xf0 },
9bd060e4
AC		 328
329 /* Sensor Control */
330 { OV9740_SENSOR_CTRL03, 0x42 },
331 { OV9740_SENSOR_CTRL04, 0x10 },
332 { OV9740_SENSOR_CTRL05, 0x45 },
333 { OV9740_SENSOR_CTRL07, 0x14 },
334
335 /* Timing Control */
336 { OV9740_TIMING_CTRL33, 0x04 },
337 { OV9740_TIMING_CTRL35, 0x02 },
338 { OV9740_TIMING_CTRL19, 0x6e },
339 { OV9740_TIMING_CTRL17, 0x94 },
340
341 /* AEC/AGC Control */
342 { OV9740_AEC_ENABLE, 0x10 },
343 { OV9740_GAIN_CEILING_01, 0x00 },
344 { OV9740_GAIN_CEILING_02, 0x7f },
345 { OV9740_AEC_HI_THRESHOLD, 0xa0 },
346 { OV9740_AEC_3A1A, 0x05 },
347 { OV9740_AEC_CTRL1B_WPT2, 0x50 },
348 { OV9740_AEC_CTRL0F_WPT, 0x50 },
349 { OV9740_AEC_CTRL10_BPT, 0x4c },
350 { OV9740_AEC_CTRL1E_BPT2, 0x4c },
351 { OV9740_AEC_LO_THRESHOLD, 0x26 },
352
353 /* BLC Control */
354 { OV9740_BLC_AUTO_ENABLE, 0x45 },
355 { OV9740_BLC_MODE, 0x18 },
356
357 /* DVP Control */
358 { OV9740_DVP_VSYNC_CTRL02, 0x04 },
359 { OV9740_DVP_VSYNC_MODE, 0x00 },
360 { OV9740_DVP_VSYNC_CTRL06, 0x08 },
361
362 /* PLL Setting */
363 { OV9740_PLL_MODE_CTRL01, 0x20 },
364 { OV9740_PRE_PLL_CLK_DIV, 0x03 },
365 { OV9740_PLL_MULTIPLIER, 0x4c },
366 { OV9740_VT_SYS_CLK_DIV, 0x01 },
367 { OV9740_VT_PIX_CLK_DIV, 0x08 },
368 { OV9740_PLL_CTRL3010, 0x01 },
369 { OV9740_VFIFO_CTRL00, 0x82 },
370
371 /* Timing Setting */
372 /* VTS */
373 { OV9740_FRM_LENGTH_LN_HI, 0x03 },
374 { OV9740_FRM_LENGTH_LN_LO, 0x07 },
375 /* HTS */
376 { OV9740_LN_LENGTH_PCK_HI, 0x06 },
377 { OV9740_LN_LENGTH_PCK_LO, 0x62 },
378
379 /* MIPI Control */
c4fdce56 380 { OV9740_MIPI_CTRL00, 0x44 }, /* 0x64 for discontinuous clk */
9bd060e4
AC		 381 { OV9740_MIPI_3837, 0x01 },
382 { OV9740_MIPI_CTRL01, 0x0f },
383 { OV9740_MIPI_CTRL03, 0x05 },
384 { OV9740_MIPI_CTRL05, 0x10 },
385 { OV9740_VFIFO_RD_CTRL, 0x16 },
386 { OV9740_MIPI_CTRL_3012, 0x70 },
387 { OV9740_SC_CMMM_MIPI_CTR, 0x01 },
c4fdce56
AC		 388
389 /* YUYV order */
390 { OV9740_ISP_CTRL19, 0x02 },
9bd060e4
AC		 391};
392
9bd060e4
AC		 393static enum v4l2_mbus_pixelcode ov9740_codes[] = {
394 V4L2_MBUS_FMT_YUYV8_2X8,
395};
396
9bd060e4
AC		 397/* read a register */
398static int ov9740_reg_read(struct i2c_client *client, u16 reg, u8 *val)
399{
400 int ret;
401 struct i2c_msg msg[] = {
402 {
403 .addr = client->addr,
404 .flags = 0,
405 .len = 2,
406 .buf = (u8 *)&reg,
407 },
408 {
409 .addr = client->addr,
410 .flags = I2C_M_RD,
411 .len = 1,
412 .buf = val,
413 },
414 };
415
416 reg = swab16(reg);
417
418 ret = i2c_transfer(client->adapter, msg, 2);
419 if (ret < 0) {
420 dev_err(&client->dev, "Failed reading register 0x%04x!\n", reg);
421 return ret;
422 }
423
424 return 0;
425}
426
427/* write a register */
428static int ov9740_reg_write(struct i2c_client *client, u16 reg, u8 val)
429{
430 struct i2c_msg msg;
431 struct {
432 u16 reg;
433 u8 val;
434 } __packed buf;
435 int ret;
436
437 reg = swab16(reg);
438
439 buf.reg = reg;
440 buf.val = val;
441
442 msg.addr = client->addr;
443 msg.flags = 0;
444 msg.len = 3;
445 msg.buf = (u8 *)&buf;
446
447 ret = i2c_transfer(client->adapter, &msg, 1);
448 if (ret < 0) {
449 dev_err(&client->dev, "Failed writing register 0x%04x!\n", reg);
450 return ret;
451 }
452
453 return 0;
454}
455
456
457/* Read a register, alter its bits, write it back */
458static int ov9740_reg_rmw(struct i2c_client *client, u16 reg, u8 set, u8 unset)
459{
460 u8 val;
461 int ret;
462
463 ret = ov9740_reg_read(client, reg, &val);
464 if (ret < 0) {
465 dev_err(&client->dev,
5fec8b90
AC		 466 "[Read]-Modify-Write of register 0x%04x failed!\n",
467 reg);
9bd060e4
AC		 468 return ret;
469 }
470
471 val |= set;
472 val &= ~unset;
473
474 ret = ov9740_reg_write(client, reg, val);
475 if (ret < 0) {
476 dev_err(&client->dev,
5fec8b90
AC		 477 "Read-Modify-[Write] of register 0x%04x failed!\n",
478 reg);
9bd060e4
AC		 479 return ret;
480 }
481
482 return 0;
483}
484
485static int ov9740_reg_write_array(struct i2c_client *client,
486 const struct ov9740_reg *regarray,
487 int regarraylen)
488{
489 int i;
490 int ret;
491
492 for (i = 0; i < regarraylen; i++) {
493 ret = ov9740_reg_write(client,
494 regarray[i].reg, regarray[i].val);
495 if (ret < 0)
496 return ret;
497 }
498
499 return 0;
500}
501
502/* Start/Stop streaming from the device */
503static int ov9740_s_stream(struct v4l2_subdev *sd, int enable)
504{
505 struct i2c_client *client = v4l2_get_subdevdata(sd);
506 struct ov9740_priv *priv = to_ov9740(sd);
507 int ret;
508
509 /* Program orientation register. */
510 if (priv->flag_vflip)
511 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x2, 0);
512 else
513 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x2);
514 if (ret < 0)
515 return ret;
516
517 if (priv->flag_hflip)
518 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x1, 0);
519 else
520 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x1);
521 if (ret < 0)
522 return ret;
523
524 if (enable) {
525 dev_dbg(&client->dev, "Enabling Streaming\n");
526 /* Start Streaming */
527 ret = ov9740_reg_write(client, OV9740_MODE_SELECT, 0x01);
528
529 } else {
530 dev_dbg(&client->dev, "Disabling Streaming\n");
531 /* Software Reset */
532 ret = ov9740_reg_write(client, OV9740_SOFTWARE_RESET, 0x01);
533 if (!ret)
534 /* Setting Streaming to Standby */
535 ret = ov9740_reg_write(client, OV9740_MODE_SELECT,
536 0x00);
537 }
538
95904d4b
AC		 539 priv->current_enable = enable;
540
9bd060e4
AC		 541 return ret;
542}
543
9bd060e4
AC		 544/* select nearest higher resolution for capture */
545static void ov9740_res_roundup(u32 *width, u32 *height)
546{
970aa9e0
AC		 547 /* Width must be a multiple of 4 pixels. */
548 *width = ALIGN(*width, 4);
9bd060e4 549
970aa9e0
AC		 550 /* Max resolution is 1280x720 (720p). */
551 if (*width > OV9740_MAX_WIDTH)
552 *width = OV9740_MAX_WIDTH;
9bd060e4 553
970aa9e0
AC		 554 if (*height > OV9740_MAX_HEIGHT)
555 *height = OV9740_MAX_HEIGHT;
9bd060e4
AC		 556}
557
558/* Setup registers according to resolution and color encoding */
970aa9e0 559static int ov9740_set_res(struct i2c_client *client, u32 width, u32 height)
9bd060e4 560{
970aa9e0
AC		 561 u32 x_start;
562 u32 y_start;
563 u32 x_end;
564 u32 y_end;
565 bool scaling = 0;
566 u32 scale_input_x;
567 u32 scale_input_y;
9bd060e4
AC		 568 int ret;
569
970aa9e0
AC		 570 if ((width != OV9740_MAX_WIDTH) || (height != OV9740_MAX_HEIGHT))
571 scaling = 1;
572
573 /*
574 * Try to use as much of the sensor area as possible when supporting
575 * smaller resolutions. Depending on the aspect ratio of the
576 * chosen resolution, we can either use the full width of the sensor,
577 * or the full height of the sensor (or both if the aspect ratio is
578 * the same as 1280x720.
579 */
580 if ((OV9740_MAX_WIDTH * height) > (OV9740_MAX_HEIGHT * width)) {
581 scale_input_x = (OV9740_MAX_HEIGHT * width) / height;
582 scale_input_y = OV9740_MAX_HEIGHT;
9bd060e4 583 } else {
970aa9e0
AC		 584 scale_input_x = OV9740_MAX_WIDTH;
585 scale_input_y = (OV9740_MAX_WIDTH * height) / width;
9bd060e4
AC		 586 }
587
970aa9e0
AC		 588 /* These describe the area of the sensor to use. */
589 x_start = (OV9740_MAX_WIDTH - scale_input_x) / 2;
590 y_start = (OV9740_MAX_HEIGHT - scale_input_y) / 2;
591 x_end = x_start + scale_input_x - 1;
592 y_end = y_start + scale_input_y - 1;
593
594 ret = ov9740_reg_write(client, OV9740_X_ADDR_START_HI, x_start >> 8);
595 if (ret)
596 goto done;
597 ret = ov9740_reg_write(client, OV9740_X_ADDR_START_LO, x_start & 0xff);
598 if (ret)
599 goto done;
600 ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_HI, y_start >> 8);
601 if (ret)
602 goto done;
603 ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_LO, y_start & 0xff);
604 if (ret)
605 goto done;
606
607 ret = ov9740_reg_write(client, OV9740_X_ADDR_END_HI, x_end >> 8);
608 if (ret)
609 goto done;
610 ret = ov9740_reg_write(client, OV9740_X_ADDR_END_LO, x_end & 0xff);
611 if (ret)
612 goto done;
613 ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_HI, y_end >> 8);
614 if (ret)
615 goto done;
616 ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_LO, y_end & 0xff);
617 if (ret)
618 goto done;
619
620 ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_HI, width >> 8);
621 if (ret)
622 goto done;
623 ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_LO, width & 0xff);
624 if (ret)
625 goto done;
626 ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_HI, height >> 8);
627 if (ret)
628 goto done;
629 ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_LO, height & 0xff);
630 if (ret)
631 goto done;
632
633 ret = ov9740_reg_write(client, OV9740_ISP_CTRL1E, scale_input_x >> 8);
634 if (ret)
635 goto done;
636 ret = ov9740_reg_write(client, OV9740_ISP_CTRL1F, scale_input_x & 0xff);
637 if (ret)
638 goto done;
639 ret = ov9740_reg_write(client, OV9740_ISP_CTRL20, scale_input_y >> 8);
640 if (ret)
641 goto done;
642 ret = ov9740_reg_write(client, OV9740_ISP_CTRL21, scale_input_y & 0xff);
643 if (ret)
644 goto done;
645
646 ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_HI,
647 (scale_input_x - width) >> 8);
648 if (ret)
649 goto done;
650 ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_LO,
651 (scale_input_x - width) & 0xff);
652 if (ret)
653 goto done;
654
655 ret = ov9740_reg_write(client, OV9740_ISP_CTRL00, 0xff);
656 if (ret)
657 goto done;
658 ret = ov9740_reg_write(client, OV9740_ISP_CTRL01, 0xef |
659 (scaling << 4));
660 if (ret)
661 goto done;
662 ret = ov9740_reg_write(client, OV9740_ISP_CTRL03, 0xff);
663
664done:
9bd060e4
AC		 665 return ret;
666}
667
668/* set the format we will capture in */
669static int ov9740_s_fmt(struct v4l2_subdev *sd,
670 struct v4l2_mbus_framefmt *mf)
671{
672 struct i2c_client *client = v4l2_get_subdevdata(sd);
95904d4b 673 struct ov9740_priv *priv = to_ov9740(sd);
9bd060e4
AC		 674 enum v4l2_colorspace cspace;
675 enum v4l2_mbus_pixelcode code = mf->code;
676 int ret;
677
678 ov9740_res_roundup(&mf->width, &mf->height);
679
680 switch (code) {
681 case V4L2_MBUS_FMT_YUYV8_2X8:
682 cspace = V4L2_COLORSPACE_SRGB;
683 break;
684 default:
685 return -EINVAL;
686 }
687
688 ret = ov9740_reg_write_array(client, ov9740_defaults,
689 ARRAY_SIZE(ov9740_defaults));
690 if (ret < 0)
691 return ret;
692
970aa9e0 693 ret = ov9740_set_res(client, mf->width, mf->height);
9bd060e4
AC		 694 if (ret < 0)
695 return ret;
696
697 mf->code = code;
698 mf->colorspace = cspace;
699
95904d4b
AC		 700 memcpy(&priv->current_mf, mf, sizeof(struct v4l2_mbus_framefmt));
701
9bd060e4
AC		 702 return ret;
703}
704
705static int ov9740_try_fmt(struct v4l2_subdev *sd,
706 struct v4l2_mbus_framefmt *mf)
707{
708 ov9740_res_roundup(&mf->width, &mf->height);
709
710 mf->field = V4L2_FIELD_NONE;
711 mf->code = V4L2_MBUS_FMT_YUYV8_2X8;
712 mf->colorspace = V4L2_COLORSPACE_SRGB;
713
714 return 0;
715}
716
717static int ov9740_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
718 enum v4l2_mbus_pixelcode *code)
719{
720 if (index >= ARRAY_SIZE(ov9740_codes))
721 return -EINVAL;
722
723 *code = ov9740_codes[index];
724
725 return 0;
726}
727
728static int ov9740_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
729{
730 a->bounds.left = 0;
731 a->bounds.top = 0;
970aa9e0
AC		 732 a->bounds.width = OV9740_MAX_WIDTH;
733 a->bounds.height = OV9740_MAX_HEIGHT;
9bd060e4
AC		 734 a->defrect = a->bounds;
735 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
736 a->pixelaspect.numerator = 1;
737 a->pixelaspect.denominator = 1;
738
739 return 0;
740}
741
742static int ov9740_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
743{
744 a->c.left = 0;
745 a->c.top = 0;
970aa9e0
AC		 746 a->c.width = OV9740_MAX_WIDTH;
747 a->c.height = OV9740_MAX_HEIGHT;
9bd060e4
AC		 748 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
749
750 return 0;
751}
752
e29c9bfb 753/* Set status of additional camera capabilities */
34e181c5 754static int ov9740_s_ctrl(struct v4l2_ctrl *ctrl)
e29c9bfb 755{
34e181c5
HV		 756 struct ov9740_priv *priv =
757 container_of(ctrl->handler, struct ov9740_priv, hdl);
e29c9bfb
AC		 758
759 switch (ctrl->id) {
760 case V4L2_CID_VFLIP:
34e181c5 761 priv->flag_vflip = ctrl->val;
e29c9bfb
AC		 762 break;
763 case V4L2_CID_HFLIP:
34e181c5 764 priv->flag_hflip = ctrl->val;
e29c9bfb
AC		 765 break;
766 default:
767 return -EINVAL;
768 }
769
770 return 0;
771}
772
95904d4b
AC		 773static int ov9740_s_power(struct v4l2_subdev *sd, int on)
774{
4ec10bac 775 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 776 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
95904d4b 777 struct ov9740_priv *priv = to_ov9740(sd);
4ec10bac 778 int ret;
95904d4b
AC		 779
780 if (on) {
25a34811 781 ret = soc_camera_power_on(&client->dev, ssdd);
4ec10bac
LP		 782 if (ret < 0)
783 return ret;
784
785 if (priv->current_enable) {
786 ov9740_s_fmt(sd, &priv->current_mf);
787 ov9740_s_stream(sd, 1);
788 }
95904d4b 789 } else {
4ec10bac
LP		 790 if (priv->current_enable) {
791 ov9740_s_stream(sd, 0);
792 priv->current_enable = true;
793 }
794
25a34811 795 soc_camera_power_off(&client->dev, ssdd);
95904d4b
AC		 796 }
797
798 return 0;
799}
800
e29c9bfb
AC		 801#ifdef CONFIG_VIDEO_ADV_DEBUG
802static int ov9740_get_register(struct v4l2_subdev *sd,
803 struct v4l2_dbg_register *reg)
804{
805 struct i2c_client *client = v4l2_get_subdevdata(sd);
806 int ret;
807 u8 val;
808
809 if (reg->reg & ~0xffff)
810 return -EINVAL;
811
812 reg->size = 2;
813
814 ret = ov9740_reg_read(client, reg->reg, &val);
815 if (ret)
816 return ret;
817
818 reg->val = (__u64)val;
819
820 return ret;
821}
822
823static int ov9740_set_register(struct v4l2_subdev *sd,
977ba3b1 824 const struct v4l2_dbg_register *reg)
e29c9bfb
AC		 825{
826 struct i2c_client *client = v4l2_get_subdevdata(sd);
827
828 if (reg->reg & ~0xffff || reg->val & ~0xff)
829 return -EINVAL;
830
831 return ov9740_reg_write(client, reg->reg, reg->val);
832}
833#endif
834
14178aa5 835static int ov9740_video_probe(struct i2c_client *client)
9bd060e4
AC		 836{
837 struct v4l2_subdev *sd = i2c_get_clientdata(client);
838 struct ov9740_priv *priv = to_ov9740(sd);
839 u8 modelhi, modello;
840 int ret;
841
4bbc6d52
LP		 842 ret = ov9740_s_power(&priv->subdev, 1);
843 if (ret < 0)
844 return ret;
845
9bd060e4
AC		 846 /*
847 * check and show product ID and manufacturer ID
848 */
849 ret = ov9740_reg_read(client, OV9740_MODEL_ID_HI, &modelhi);
850 if (ret < 0)
4bbc6d52 851 goto done;
9bd060e4
AC		 852
853 ret = ov9740_reg_read(client, OV9740_MODEL_ID_LO, &modello);
854 if (ret < 0)
4bbc6d52 855 goto done;
9bd060e4
AC		 856
857 priv->model = (modelhi << 8) | modello;
858
859 ret = ov9740_reg_read(client, OV9740_REVISION_NUMBER, &priv->revision);
860 if (ret < 0)
4bbc6d52 861 goto done;
9bd060e4
AC		 862
863 ret = ov9740_reg_read(client, OV9740_MANUFACTURER_ID, &priv->manid);
864 if (ret < 0)
4bbc6d52 865 goto done;
9bd060e4
AC		 866
867 ret = ov9740_reg_read(client, OV9740_SMIA_VERSION, &priv->smiaver);
868 if (ret < 0)
4bbc6d52 869 goto done;
9bd060e4
AC		 870
871 if (priv->model != 0x9740) {
872 ret = -ENODEV;
4bbc6d52 873 goto done;
9bd060e4
AC		 874 }
875
9bd060e4
AC		 876 dev_info(&client->dev, "ov9740 Model ID 0x%04x, Revision 0x%02x, "
877 "Manufacturer 0x%02x, SMIA Version 0x%02x\n",
878 priv->model, priv->revision, priv->manid, priv->smiaver);
879
4bbc6d52
LP		 880 ret = v4l2_ctrl_handler_setup(&priv->hdl);
881
882done:
883 ov9740_s_power(&priv->subdev, 0);
9bd060e4
AC		 884 return ret;
885}
886
3d780ad7 887/* Request bus settings on camera side */
e534c9ea
GL		 888static int ov9740_g_mbus_config(struct v4l2_subdev *sd,
889 struct v4l2_mbus_config *cfg)
890{
891 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 892 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
e534c9ea
GL		 893
894 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
895 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
896 V4L2_MBUS_DATA_ACTIVE_HIGH;
897 cfg->type = V4L2_MBUS_PARALLEL;
25a34811 898 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
e534c9ea
GL		 899
900 return 0;
901}
902
e29c9bfb 903static struct v4l2_subdev_video_ops ov9740_video_ops = {
e534c9ea
GL		 904 .s_stream = ov9740_s_stream,
905 .s_mbus_fmt = ov9740_s_fmt,
906 .try_mbus_fmt = ov9740_try_fmt,
907 .enum_mbus_fmt = ov9740_enum_fmt,
908 .cropcap = ov9740_cropcap,
909 .g_crop = ov9740_g_crop,
910 .g_mbus_config = ov9740_g_mbus_config,
e29c9bfb
AC		 911};
912
9bd060e4 913static struct v4l2_subdev_core_ops ov9740_core_ops = {
95904d4b 914 .s_power = ov9740_s_power,
9bd060e4
AC		 915#ifdef CONFIG_VIDEO_ADV_DEBUG
916 .g_register = ov9740_get_register,
917 .s_register = ov9740_set_register,
918#endif
9bd060e4
AC		 919};
920
9bd060e4
AC		 921static struct v4l2_subdev_ops ov9740_subdev_ops = {
922 .core = &ov9740_core_ops,
923 .video = &ov9740_video_ops,
924};
925
34e181c5
HV		 926static const struct v4l2_ctrl_ops ov9740_ctrl_ops = {
927 .s_ctrl = ov9740_s_ctrl,
928};
929
9bd060e4
AC		 930/*
931 * i2c_driver function
932 */
933static int ov9740_probe(struct i2c_client *client,
934 const struct i2c_device_id *did)
935{
936 struct ov9740_priv *priv;
25a34811 937 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
9bd060e4
AC		 938 int ret;
939
25a34811 940 if (!ssdd) {
9bd060e4
AC		 941 dev_err(&client->dev, "Missing platform_data for driver\n");
942 return -EINVAL;
943 }
944
70e176a5 945 priv = devm_kzalloc(&client->dev, sizeof(struct ov9740_priv), GFP_KERNEL);
9bd060e4
AC		 946 if (!priv) {
947 dev_err(&client->dev, "Failed to allocate private data!\n");
948 return -ENOMEM;
949 }
950
951 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9740_subdev_ops);
34e181c5
HV		 952 v4l2_ctrl_handler_init(&priv->hdl, 13);
953 v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
954 V4L2_CID_VFLIP, 0, 1, 1, 0);
955 v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
956 V4L2_CID_HFLIP, 0, 1, 1, 0);
957 priv->subdev.ctrl_handler = &priv->hdl;
70e176a5
GL		 958 if (priv->hdl.error)
959 return priv->hdl.error;
9bd060e4 960
14178aa5 961 ret = ov9740_video_probe(client);
70e176a5 962 if (ret < 0)
34e181c5 963 v4l2_ctrl_handler_free(&priv->hdl);
9bd060e4
AC		 964
965 return ret;
966}
967
968static int ov9740_remove(struct i2c_client *client)
969{
970 struct ov9740_priv *priv = i2c_get_clientdata(client);
971
34e181c5
HV		 972 v4l2_device_unregister_subdev(&priv->subdev);
973 v4l2_ctrl_handler_free(&priv->hdl);
9bd060e4
AC		 974 return 0;
975}
976
977static const struct i2c_device_id ov9740_id[] = {
978 { "ov9740", 0 },
979 { }
980};
981MODULE_DEVICE_TABLE(i2c, ov9740_id);
982
983static struct i2c_driver ov9740_i2c_driver = {
984 .driver = {
985 .name = "ov9740",
986 },
987 .probe = ov9740_probe,
988 .remove = ov9740_remove,
989 .id_table = ov9740_id,
990};
991
c6e8d86f 992module_i2c_driver(ov9740_i2c_driver);
9bd060e4
AC		 993
994MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV9740");
995MODULE_AUTHOR("Andrew Chew <achew@nvidia.com>");
996MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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