[media] V4L2: support asynchronous subdevice registration
[deliverable/linux.git] / drivers / media / i2c / soc_camera / tw9910.c
CommitLineData
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1/*
2 * tw9910 Video Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov772x driver,
8 *
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
11 * Copyright (C) 2008 Magnus Damm
12 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/i2c.h>
22#include <linux/slab.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
95d20109 25#include <linux/v4l2-mediabus.h>
ed922a89 26#include <linux/videodev2.h>
0d3263f9 27
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28#include <media/soc_camera.h>
29#include <media/tw9910.h>
0d3263f9 30#include <media/v4l2-subdev.h>
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31
32#define GET_ID(val) ((val & 0xF8) >> 3)
6d74e5f3 33#define GET_REV(val) (val & 0x07)
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34
35/*
36 * register offset
37 */
38#define ID 0x00 /* Product ID Code Register */
39#define STATUS1 0x01 /* Chip Status Register I */
40#define INFORM 0x02 /* Input Format */
41#define OPFORM 0x03 /* Output Format Control Register */
42#define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
43#define OUTCTR1 0x05 /* Output Control I */
44#define ACNTL1 0x06 /* Analog Control Register 1 */
45#define CROP_HI 0x07 /* Cropping Register, High */
46#define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
47#define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
48#define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
49#define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
50#define CNTRL1 0x0C /* Control Register I */
51#define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
52#define SCALE_HI 0x0E /* Scaling Register, High */
53#define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
54#define BRIGHT 0x10 /* BRIGHTNESS Control Register */
55#define CONTRAST 0x11 /* CONTRAST Control Register */
56#define SHARPNESS 0x12 /* SHARPNESS Control Register I */
57#define SAT_U 0x13 /* Chroma (U) Gain Register */
58#define SAT_V 0x14 /* Chroma (V) Gain Register */
59#define HUE 0x15 /* Hue Control Register */
60#define CORING1 0x17
61#define CORING2 0x18 /* Coring and IF compensation */
62#define VBICNTL 0x19 /* VBI Control Register */
63#define ACNTL2 0x1A /* Analog Control 2 */
64#define OUTCTR2 0x1B /* Output Control 2 */
65#define SDT 0x1C /* Standard Selection */
66#define SDTR 0x1D /* Standard Recognition */
67#define TEST 0x1F /* Test Control Register */
68#define CLMPG 0x20 /* Clamping Gain */
69#define IAGC 0x21 /* Individual AGC Gain */
70#define AGCGAIN 0x22 /* AGC Gain */
71#define PEAKWT 0x23 /* White Peak Threshold */
72#define CLMPL 0x24 /* Clamp level */
73#define SYNCT 0x25 /* Sync Amplitude */
74#define MISSCNT 0x26 /* Sync Miss Count Register */
75#define PCLAMP 0x27 /* Clamp Position Register */
76#define VCNTL1 0x28 /* Vertical Control I */
77#define VCNTL2 0x29 /* Vertical Control II */
78#define CKILL 0x2A /* Color Killer Level Control */
79#define COMB 0x2B /* Comb Filter Control */
80#define LDLY 0x2C /* Luma Delay and H Filter Control */
81#define MISC1 0x2D /* Miscellaneous Control I */
82#define LOOP 0x2E /* LOOP Control Register */
83#define MISC2 0x2F /* Miscellaneous Control II */
84#define MVSN 0x30 /* Macrovision Detection */
85#define STATUS2 0x31 /* Chip STATUS II */
86#define HFREF 0x32 /* H monitor */
87#define CLMD 0x33 /* CLAMP MODE */
88#define IDCNTL 0x34 /* ID Detection Control */
89#define CLCNTL1 0x35 /* Clamp Control I */
90#define ANAPLLCTL 0x4C
91#define VBIMIN 0x4D
92#define HSLOWCTL 0x4E
93#define WSS3 0x4F
94#define FILLDATA 0x50
95#define SDID 0x51
96#define DID 0x52
97#define WSS1 0x53
98#define WSS2 0x54
99#define VVBI 0x55
100#define LCTL6 0x56
101#define LCTL7 0x57
102#define LCTL8 0x58
103#define LCTL9 0x59
104#define LCTL10 0x5A
105#define LCTL11 0x5B
106#define LCTL12 0x5C
107#define LCTL13 0x5D
108#define LCTL14 0x5E
109#define LCTL15 0x5F
110#define LCTL16 0x60
111#define LCTL17 0x61
112#define LCTL18 0x62
113#define LCTL19 0x63
114#define LCTL20 0x64
115#define LCTL21 0x65
116#define LCTL22 0x66
117#define LCTL23 0x67
118#define LCTL24 0x68
119#define LCTL25 0x69
120#define LCTL26 0x6A
faa58261 121#define HSBEGIN 0x6B
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122#define HSEND 0x6C
123#define OVSDLY 0x6D
124#define OVSEND 0x6E
125#define VBIDELAY 0x6F
126
127/*
128 * register detail
129 */
130
131/* INFORM */
132#define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
133#define FC27_FF 0x00 /* 0 : Square pixel mode. */
134 /* Must use 24.54MHz for 60Hz field rate */
135 /* source or 29.5MHz for 50Hz field rate */
136#define IFSEL_S 0x10 /* 01 : S-video decoding */
137#define IFSEL_C 0x00 /* 00 : Composite video decoding */
138 /* Y input video selection */
139#define YSEL_M0 0x00 /* 00 : Mux0 selected */
140#define YSEL_M1 0x04 /* 01 : Mux1 selected */
141#define YSEL_M2 0x08 /* 10 : Mux2 selected */
142#define YSEL_M3 0x10 /* 11 : Mux3 selected */
143
144/* OPFORM */
145#define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
146 /* 1 : ITU-R-656 compatible data sequence format */
147#define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
148 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
149#define LLCMODE 0x20 /* 1 : LLC output mode. */
150 /* 0 : free-run output mode */
151#define AINC 0x10 /* Serial interface auto-indexing control */
152 /* 0 : auto-increment */
153 /* 1 : non-auto */
154#define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
155 /* 0 : Vertical out ctrl by HACTIVE and DVALID */
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156#define OEN_TRI_SEL_MASK 0x07
157#define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
158#define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
159#define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
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160
161/* OUTCTR1 */
162#define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
163#define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
164 /* VS pin output control */
165#define VSSL_VSYNC 0x00 /* 0 : VSYNC */
166#define VSSL_VACT 0x10 /* 1 : VACT */
167#define VSSL_FIELD 0x20 /* 2 : FIELD */
168#define VSSL_VVALID 0x30 /* 3 : VVALID */
169#define VSSL_ZERO 0x70 /* 7 : 0 */
170#define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
171#define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
172 /* HS pin output control */
173#define HSSL_HACT 0x00 /* 0 : HACT */
174#define HSSL_HSYNC 0x01 /* 1 : HSYNC */
175#define HSSL_DVALID 0x02 /* 2 : DVALID */
176#define HSSL_HLOCK 0x03 /* 3 : HLOCK */
177#define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
178#define HSSL_ZERO 0x07 /* 7 : 0 */
179
180/* ACNTL1 */
181#define SRESET 0x80 /* resets the device to its default state
182 * but all register content remain unchanged.
183 * This bit is self-resetting.
184 */
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185#define ACNTL1_PDN_MASK 0x0e
186#define CLK_PDN 0x08 /* system clock power down */
187#define Y_PDN 0x04 /* Luma ADC power down */
188#define C_PDN 0x02 /* Chroma ADC power down */
189
190/* ACNTL2 */
191#define ACNTL2_PDN_MASK 0x40
192#define PLL_PDN 0x40 /* PLL power down */
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193
194/* VBICNTL */
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195
196/* RTSEL : control the real time signal output from the MPOUT pin */
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197#define RTSEL_MASK 0x07
198#define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
199#define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
200#define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
201#define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
202#define RTSEL_MONO 0x04 /* 0100 = MONO */
203#define RTSEL_DET50 0x05 /* 0101 = DET50 */
204#define RTSEL_FIELD 0x06 /* 0110 = FIELD */
205#define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
206
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207/* HSYNC start and end are constant for now */
208#define HSYNC_START 0x0260
209#define HSYNC_END 0x0300
210
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211/*
212 * structure
213 */
214
215struct regval_list {
216 unsigned char reg_num;
217 unsigned char value;
218};
219
220struct tw9910_scale_ctrl {
221 char *name;
222 unsigned short width;
223 unsigned short height;
224 u16 hscale;
225 u16 vscale;
226};
227
ed922a89 228struct tw9910_priv {
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229 struct v4l2_subdev subdev;
230 struct tw9910_video_info *info;
231 const struct tw9910_scale_ctrl *scale;
2f0babb7 232 v4l2_std_id norm;
906b1018 233 u32 revision;
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234};
235
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236static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
237 {
238 .name = "NTSC SQ",
239 .width = 640,
240 .height = 480,
241 .hscale = 0x0100,
242 .vscale = 0x0100,
243 },
244 {
245 .name = "NTSC CCIR601",
246 .width = 720,
247 .height = 480,
248 .hscale = 0x0100,
249 .vscale = 0x0100,
250 },
251 {
252 .name = "NTSC SQ (CIF)",
253 .width = 320,
254 .height = 240,
255 .hscale = 0x0200,
256 .vscale = 0x0200,
257 },
258 {
259 .name = "NTSC CCIR601 (CIF)",
260 .width = 360,
261 .height = 240,
262 .hscale = 0x0200,
263 .vscale = 0x0200,
264 },
265 {
266 .name = "NTSC SQ (QCIF)",
267 .width = 160,
268 .height = 120,
269 .hscale = 0x0400,
270 .vscale = 0x0400,
271 },
272 {
273 .name = "NTSC CCIR601 (QCIF)",
274 .width = 180,
275 .height = 120,
276 .hscale = 0x0400,
277 .vscale = 0x0400,
278 },
279};
280
281static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
282 {
283 .name = "PAL SQ",
284 .width = 768,
285 .height = 576,
286 .hscale = 0x0100,
287 .vscale = 0x0100,
288 },
289 {
290 .name = "PAL CCIR601",
291 .width = 720,
292 .height = 576,
293 .hscale = 0x0100,
294 .vscale = 0x0100,
295 },
296 {
297 .name = "PAL SQ (CIF)",
298 .width = 384,
299 .height = 288,
300 .hscale = 0x0200,
301 .vscale = 0x0200,
302 },
303 {
304 .name = "PAL CCIR601 (CIF)",
305 .width = 360,
306 .height = 288,
307 .hscale = 0x0200,
308 .vscale = 0x0200,
309 },
310 {
311 .name = "PAL SQ (QCIF)",
312 .width = 192,
313 .height = 144,
314 .hscale = 0x0400,
315 .vscale = 0x0400,
316 },
317 {
318 .name = "PAL CCIR601 (QCIF)",
319 .width = 180,
320 .height = 144,
321 .hscale = 0x0400,
322 .vscale = 0x0400,
323 },
324};
325
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326/*
327 * general function
328 */
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329static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
330{
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331 return container_of(i2c_get_clientdata(client), struct tw9910_priv,
332 subdev);
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333}
334
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335static int tw9910_mask_set(struct i2c_client *client, u8 command,
336 u8 mask, u8 set)
337{
338 s32 val = i2c_smbus_read_byte_data(client, command);
339 if (val < 0)
340 return val;
341
342 val &= ~mask;
343 val |= set & mask;
344
345 return i2c_smbus_write_byte_data(client, command, val);
346}
347
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348static int tw9910_set_scale(struct i2c_client *client,
349 const struct tw9910_scale_ctrl *scale)
350{
351 int ret;
352
353 ret = i2c_smbus_write_byte_data(client, SCALE_HI,
354 (scale->vscale & 0x0F00) >> 4 |
355 (scale->hscale & 0x0F00) >> 8);
356 if (ret < 0)
357 return ret;
358
359 ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
360 scale->hscale & 0x00FF);
361 if (ret < 0)
362 return ret;
363
364 ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
365 scale->vscale & 0x00FF);
366
367 return ret;
368}
369
2ad90b71 370static int tw9910_set_hsync(struct i2c_client *client)
ed922a89 371{
faa58261 372 struct tw9910_priv *priv = to_tw9910(client);
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373 int ret;
374
375 /* bit 10 - 3 */
faa58261 376 ret = i2c_smbus_write_byte_data(client, HSBEGIN,
2ad90b71 377 (HSYNC_START & 0x07F8) >> 3);
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378 if (ret < 0)
379 return ret;
380
381 /* bit 10 - 3 */
382 ret = i2c_smbus_write_byte_data(client, HSEND,
2ad90b71 383 (HSYNC_END & 0x07F8) >> 3);
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384 if (ret < 0)
385 return ret;
386
faa58261 387 /* So far only revisions 0 and 1 have been seen */
ed922a89 388 /* bit 2 - 0 */
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389 if (1 == priv->revision)
390 ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
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391 (HSYNC_START & 0x0007) << 4 |
392 (HSYNC_END & 0x0007));
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393
394 return ret;
395}
396
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397static void tw9910_reset(struct i2c_client *client)
398{
607e5ad8 399 tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
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400 msleep(1);
401}
402
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403static int tw9910_power(struct i2c_client *client, int enable)
404{
405 int ret;
406 u8 acntl1;
407 u8 acntl2;
408
409 if (enable) {
410 acntl1 = 0;
411 acntl2 = 0;
412 } else {
413 acntl1 = CLK_PDN | Y_PDN | C_PDN;
414 acntl2 = PLL_PDN;
415 }
416
417 ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
418 if (ret < 0)
419 return ret;
420
421 return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
422}
423
2f0babb7 424static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm,
2ad90b71 425 u32 width, u32 height)
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426{
427 const struct tw9910_scale_ctrl *scale;
428 const struct tw9910_scale_ctrl *ret = NULL;
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429 __u32 diff = 0xffffffff, tmp;
430 int size, i;
431
432 if (norm & V4L2_STD_NTSC) {
433 scale = tw9910_ntsc_scales;
434 size = ARRAY_SIZE(tw9910_ntsc_scales);
435 } else if (norm & V4L2_STD_PAL) {
436 scale = tw9910_pal_scales;
437 size = ARRAY_SIZE(tw9910_pal_scales);
438 } else {
439 return NULL;
440 }
441
442 for (i = 0; i < size; i++) {
443 tmp = abs(width - scale[i].width) +
444 abs(height - scale[i].height);
445 if (tmp < diff) {
446 diff = tmp;
447 ret = scale + i;
448 }
449 }
450
451 return ret;
452}
453
454/*
5476ea8d 455 * subdevice operations
ed922a89 456 */
979ea1dd 457static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
ed922a89 458{
c4ce6d14 459 struct i2c_client *client = v4l2_get_subdevdata(sd);
979ea1dd 460 struct tw9910_priv *priv = to_tw9910(client);
06f292e4 461 u8 val;
607e5ad8 462 int ret;
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463
464 if (!enable) {
465 switch (priv->revision) {
466 case 0:
467 val = OEN_TRI_SEL_ALL_OFF_r0;
468 break;
469 case 1:
470 val = OEN_TRI_SEL_ALL_OFF_r1;
471 break;
472 default:
473 dev_err(&client->dev, "un-supported revision\n");
474 return -EINVAL;
475 }
476 } else {
477 val = OEN_TRI_SEL_ALL_ON;
ed922a89 478
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479 if (!priv->scale) {
480 dev_err(&client->dev, "norm select error\n");
481 return -EPERM;
482 }
ed922a89 483
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484 dev_dbg(&client->dev, "%s %dx%d\n",
485 priv->scale->name,
486 priv->scale->width,
487 priv->scale->height);
488 }
ed922a89 489
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490 ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
491 if (ret < 0)
492 return ret;
493
494 return tw9910_power(client, enable);
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495}
496
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497static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
498{
499 struct i2c_client *client = v4l2_get_subdevdata(sd);
500 struct tw9910_priv *priv = to_tw9910(client);
501
502 *norm = priv->norm;
503
504 return 0;
505}
506
979ea1dd 507static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
ed922a89 508{
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509 struct i2c_client *client = v4l2_get_subdevdata(sd);
510 struct tw9910_priv *priv = to_tw9910(client);
ed922a89 511
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512 if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL)))
513 return -EINVAL;
ed922a89 514
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515 priv->norm = norm;
516
517 return 0;
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518}
519
ed922a89 520#ifdef CONFIG_VIDEO_ADV_DEBUG
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521static int tw9910_g_register(struct v4l2_subdev *sd,
522 struct v4l2_dbg_register *reg)
ed922a89 523{
c4ce6d14 524 struct i2c_client *client = v4l2_get_subdevdata(sd);
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525 int ret;
526
527 if (reg->reg > 0xff)
528 return -EINVAL;
529
15c4fee3 530 reg->size = 1;
40e2e092 531 ret = i2c_smbus_read_byte_data(client, reg->reg);
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532 if (ret < 0)
533 return ret;
534
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GL
535 /*
536 * ret = int
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537 * reg->val = __u64
538 */
539 reg->val = (__u64)ret;
540
541 return 0;
542}
543
979ea1dd 544static int tw9910_s_register(struct v4l2_subdev *sd,
977ba3b1 545 const struct v4l2_dbg_register *reg)
ed922a89 546{
c4ce6d14 547 struct i2c_client *client = v4l2_get_subdevdata(sd);
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548
549 if (reg->reg > 0xff ||
550 reg->val > 0xff)
551 return -EINVAL;
552
40e2e092 553 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
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554}
555#endif
556
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LP
557static int tw9910_s_power(struct v4l2_subdev *sd, int on)
558{
559 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 560 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
4ec10bac 561
25a34811 562 return soc_camera_set_power(&client->dev, ssdd, on);
4ec10bac
LP
563}
564
2ad90b71 565static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
ed922a89 566{
c4ce6d14 567 struct i2c_client *client = v4l2_get_subdevdata(sd);
979ea1dd 568 struct tw9910_priv *priv = to_tw9910(client);
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GL
569 int ret = -EINVAL;
570 u8 val;
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571
572 /*
573 * select suitable norm
574 */
2f0babb7 575 priv->scale = tw9910_select_norm(priv->norm, *width, *height);
ed922a89 576 if (!priv->scale)
6d756112 577 goto tw9910_set_fmt_error;
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578
579 /*
580 * reset hardware
581 */
40e2e092 582 tw9910_reset(client);
6d756112 583
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584 /*
585 * set bus width
586 */
587 val = 0x00;
588 if (SOCAM_DATAWIDTH_16 == priv->info->buswidth)
589 val = LEN;
590
40e2e092 591 ret = tw9910_mask_set(client, OPFORM, LEN, val);
ed922a89 592 if (ret < 0)
6d756112 593 goto tw9910_set_fmt_error;
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594
595 /*
596 * select MPOUT behavior
597 */
598 switch (priv->info->mpout) {
599 case TW9910_MPO_VLOSS:
600 val = RTSEL_VLOSS; break;
601 case TW9910_MPO_HLOCK:
602 val = RTSEL_HLOCK; break;
603 case TW9910_MPO_SLOCK:
604 val = RTSEL_SLOCK; break;
605 case TW9910_MPO_VLOCK:
606 val = RTSEL_VLOCK; break;
607 case TW9910_MPO_MONO:
608 val = RTSEL_MONO; break;
609 case TW9910_MPO_DET50:
610 val = RTSEL_DET50; break;
611 case TW9910_MPO_FIELD:
612 val = RTSEL_FIELD; break;
613 case TW9910_MPO_RTCO:
614 val = RTSEL_RTCO; break;
615 default:
616 val = 0;
617 }
618
40e2e092 619 ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
ed922a89 620 if (ret < 0)
6d756112 621 goto tw9910_set_fmt_error;
ed922a89
KM
622
623 /*
624 * set scale
625 */
40e2e092 626 ret = tw9910_set_scale(client, priv->scale);
ed922a89 627 if (ret < 0)
6d756112 628 goto tw9910_set_fmt_error;
ed922a89 629
ed922a89
KM
630 /*
631 * set hsync
632 */
2ad90b71 633 ret = tw9910_set_hsync(client);
6d756112
KM
634 if (ret < 0)
635 goto tw9910_set_fmt_error;
636
2ad90b71
GL
637 *width = priv->scale->width;
638 *height = priv->scale->height;
123ab622 639
6d756112
KM
640 return ret;
641
642tw9910_set_fmt_error:
643
40e2e092 644 tw9910_reset(client);
6d756112 645 priv->scale = NULL;
ed922a89
KM
646
647 return ret;
648}
649
6a6c8786
GL
650static int tw9910_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
651{
c4ce6d14 652 struct i2c_client *client = v4l2_get_subdevdata(sd);
2f0babb7 653 struct tw9910_priv *priv = to_tw9910(client);
6a6c8786
GL
654
655 a->c.left = 0;
656 a->c.top = 0;
2f0babb7 657 if (priv->norm & V4L2_STD_NTSC) {
2ad90b71
GL
658 a->c.width = 640;
659 a->c.height = 480;
660 } else {
661 a->c.width = 768;
662 a->c.height = 576;
663 }
6a6c8786
GL
664 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
665
666 return 0;
667}
668
669static int tw9910_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
670{
2ad90b71 671 struct i2c_client *client = v4l2_get_subdevdata(sd);
2f0babb7 672 struct tw9910_priv *priv = to_tw9910(client);
2ad90b71 673
6a6c8786
GL
674 a->bounds.left = 0;
675 a->bounds.top = 0;
2f0babb7 676 if (priv->norm & V4L2_STD_NTSC) {
2ad90b71
GL
677 a->bounds.width = 640;
678 a->bounds.height = 480;
679 } else {
680 a->bounds.width = 768;
681 a->bounds.height = 576;
682 }
683 a->defrect = a->bounds;
6a6c8786
GL
684 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
685 a->pixelaspect.numerator = 1;
686 a->pixelaspect.denominator = 1;
687
688 return 0;
689}
690
760697be
GL
691static int tw9910_g_fmt(struct v4l2_subdev *sd,
692 struct v4l2_mbus_framefmt *mf)
6a6c8786 693{
c4ce6d14 694 struct i2c_client *client = v4l2_get_subdevdata(sd);
6a6c8786 695 struct tw9910_priv *priv = to_tw9910(client);
6a6c8786
GL
696
697 if (!priv->scale) {
7bf6afbb
LP
698 priv->scale = tw9910_select_norm(priv->norm, 640, 480);
699 if (!priv->scale)
700 return -EINVAL;
6a6c8786
GL
701 }
702
760697be
GL
703 mf->width = priv->scale->width;
704 mf->height = priv->scale->height;
ace6e979 705 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
760697be 706 mf->colorspace = V4L2_COLORSPACE_JPEG;
34cae30b 707 mf->field = V4L2_FIELD_INTERLACED_BT;
6a6c8786
GL
708
709 return 0;
710}
711
760697be
GL
712static int tw9910_s_fmt(struct v4l2_subdev *sd,
713 struct v4l2_mbus_framefmt *mf)
09e231b3 714{
2ad90b71 715 u32 width = mf->width, height = mf->height;
760697be
GL
716 int ret;
717
718 WARN_ON(mf->field != V4L2_FIELD_ANY &&
34cae30b 719 mf->field != V4L2_FIELD_INTERLACED_BT);
09e231b3
GL
720
721 /*
722 * check color format
723 */
ace6e979 724 if (mf->code != V4L2_MBUS_FMT_UYVY8_2X8)
09e231b3
GL
725 return -EINVAL;
726
760697be
GL
727 mf->colorspace = V4L2_COLORSPACE_JPEG;
728
2ad90b71 729 ret = tw9910_set_frame(sd, &width, &height);
123ab622 730 if (!ret) {
2ad90b71
GL
731 mf->width = width;
732 mf->height = height;
123ab622
GL
733 }
734 return ret;
09e231b3
GL
735}
736
760697be
GL
737static int tw9910_try_fmt(struct v4l2_subdev *sd,
738 struct v4l2_mbus_framefmt *mf)
ed922a89 739{
c4ce6d14 740 struct i2c_client *client = v4l2_get_subdevdata(sd);
2f0babb7 741 struct tw9910_priv *priv = to_tw9910(client);
ed922a89
KM
742 const struct tw9910_scale_ctrl *scale;
743
760697be 744 if (V4L2_FIELD_ANY == mf->field) {
34cae30b
KM
745 mf->field = V4L2_FIELD_INTERLACED_BT;
746 } else if (V4L2_FIELD_INTERLACED_BT != mf->field) {
760697be 747 dev_err(&client->dev, "Field type %d invalid.\n", mf->field);
ed922a89
KM
748 return -EINVAL;
749 }
750
ace6e979 751 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
760697be
GL
752 mf->colorspace = V4L2_COLORSPACE_JPEG;
753
ed922a89
KM
754 /*
755 * select suitable norm
756 */
2f0babb7 757 scale = tw9910_select_norm(priv->norm, mf->width, mf->height);
ed922a89
KM
758 if (!scale)
759 return -EINVAL;
760
760697be
GL
761 mf->width = scale->width;
762 mf->height = scale->height;
ed922a89
KM
763
764 return 0;
765}
766
2f0babb7 767static int tw9910_video_probe(struct i2c_client *client)
ed922a89 768{
979ea1dd 769 struct tw9910_priv *priv = to_tw9910(client);
88a67c51 770 s32 id;
4bbc6d52 771 int ret;
ed922a89 772
ed922a89
KM
773 /*
774 * tw9910 only use 8 or 16 bit bus width
775 */
776 if (SOCAM_DATAWIDTH_16 != priv->info->buswidth &&
777 SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
85f8be68 778 dev_err(&client->dev, "bus width error\n");
ed922a89
KM
779 return -ENODEV;
780 }
781
4bbc6d52
LP
782 ret = tw9910_s_power(&priv->subdev, 1);
783 if (ret < 0)
784 return ret;
785
ed922a89
KM
786 /*
787 * check and show Product ID
4a4bc5e4 788 * So far only revisions 0 and 1 have been seen
ed922a89 789 */
88a67c51
KM
790 id = i2c_smbus_read_byte_data(client, ID);
791 priv->revision = GET_REV(id);
792 id = GET_ID(id);
40e2e092 793
88a67c51 794 if (0x0B != id ||
6d74e5f3 795 0x01 < priv->revision) {
85f8be68 796 dev_err(&client->dev,
6d74e5f3 797 "Product ID error %x:%x\n",
88a67c51 798 id, priv->revision);
4bbc6d52
LP
799 ret = -ENODEV;
800 goto done;
ed922a89
KM
801 }
802
85f8be68 803 dev_info(&client->dev,
88a67c51 804 "tw9910 Product ID %0x:%0x\n", id, priv->revision);
ed922a89 805
2f0babb7 806 priv->norm = V4L2_STD_NTSC;
ed922a89 807
4bbc6d52
LP
808done:
809 tw9910_s_power(&priv->subdev, 0);
810 return ret;
ed922a89
KM
811}
812
979ea1dd 813static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
979ea1dd 814 .s_std = tw9910_s_std,
2f0babb7 815 .g_std = tw9910_g_std,
ed922a89 816#ifdef CONFIG_VIDEO_ADV_DEBUG
979ea1dd
GL
817 .g_register = tw9910_g_register,
818 .s_register = tw9910_s_register,
ed922a89 819#endif
4ec10bac 820 .s_power = tw9910_s_power,
ed922a89
KM
821};
822
3805f201 823static int tw9910_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
760697be
GL
824 enum v4l2_mbus_pixelcode *code)
825{
826 if (index)
827 return -EINVAL;
828
ace6e979 829 *code = V4L2_MBUS_FMT_UYVY8_2X8;
760697be
GL
830 return 0;
831}
832
0d3263f9
GL
833static int tw9910_g_mbus_config(struct v4l2_subdev *sd,
834 struct v4l2_mbus_config *cfg)
835{
836 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 837 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
0d3263f9
GL
838
839 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
840 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
841 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
842 V4L2_MBUS_DATA_ACTIVE_HIGH;
843 cfg->type = V4L2_MBUS_PARALLEL;
25a34811 844 cfg->flags = soc_camera_apply_board_flags(ssdd, cfg);
0d3263f9
GL
845
846 return 0;
847}
848
849static int tw9910_s_mbus_config(struct v4l2_subdev *sd,
850 const struct v4l2_mbus_config *cfg)
851{
852 struct i2c_client *client = v4l2_get_subdevdata(sd);
25a34811 853 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
0d3263f9 854 u8 val = VSSL_VVALID | HSSL_DVALID;
25a34811 855 unsigned long flags = soc_camera_apply_board_flags(ssdd, cfg);
0d3263f9
GL
856
857 /*
858 * set OUTCTR1
859 *
860 * We use VVALID and DVALID signals to control VSYNC and HSYNC
861 * outputs, in this mode their polarity is inverted.
862 */
863 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
864 val |= HSP_HI;
865
866 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
867 val |= VSP_HI;
868
869 return i2c_smbus_write_byte_data(client, OUTCTR1, val);
870}
871
979ea1dd
GL
872static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
873 .s_stream = tw9910_s_stream,
760697be
GL
874 .g_mbus_fmt = tw9910_g_fmt,
875 .s_mbus_fmt = tw9910_s_fmt,
876 .try_mbus_fmt = tw9910_try_fmt,
6a6c8786
GL
877 .cropcap = tw9910_cropcap,
878 .g_crop = tw9910_g_crop,
760697be 879 .enum_mbus_fmt = tw9910_enum_fmt,
0d3263f9
GL
880 .g_mbus_config = tw9910_g_mbus_config,
881 .s_mbus_config = tw9910_s_mbus_config,
979ea1dd
GL
882};
883
884static struct v4l2_subdev_ops tw9910_subdev_ops = {
885 .core = &tw9910_subdev_core_ops,
886 .video = &tw9910_subdev_video_ops,
887};
888
ed922a89
KM
889/*
890 * i2c_driver function
891 */
892
893static int tw9910_probe(struct i2c_client *client,
894 const struct i2c_device_id *did)
895
896{
14178aa5
GL
897 struct tw9910_priv *priv;
898 struct tw9910_video_info *info;
14178aa5 899 struct i2c_adapter *adapter =
40e2e092 900 to_i2c_adapter(client->dev.parent);
25a34811 901 struct soc_camera_subdev_desc *ssdd = soc_camera_i2c_to_desc(client);
ed922a89 902
25a34811 903 if (!ssdd || !ssdd->drv_priv) {
14178aa5 904 dev_err(&client->dev, "TW9910: missing platform data!\n");
ed922a89 905 return -EINVAL;
40e2e092 906 }
ed922a89 907
25a34811 908 info = ssdd->drv_priv;
40e2e092
GL
909
910 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
ed922a89
KM
911 dev_err(&client->dev,
912 "I2C-Adapter doesn't support "
913 "I2C_FUNC_SMBUS_BYTE_DATA\n");
914 return -EIO;
915 }
916
70e176a5 917 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
ed922a89
KM
918 if (!priv)
919 return -ENOMEM;
920
921 priv->info = info;
979ea1dd
GL
922
923 v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
ed922a89 924
70e176a5 925 return tw9910_video_probe(client);
ed922a89
KM
926}
927
ed922a89
KM
928static const struct i2c_device_id tw9910_id[] = {
929 { "tw9910", 0 },
930 { }
931};
932MODULE_DEVICE_TABLE(i2c, tw9910_id);
933
934static struct i2c_driver tw9910_i2c_driver = {
935 .driver = {
936 .name = "tw9910",
937 },
938 .probe = tw9910_probe,
ed922a89
KM
939 .id_table = tw9910_id,
940};
941
c6e8d86f 942module_i2c_driver(tw9910_i2c_driver);
ed922a89
KM
943
944MODULE_DESCRIPTION("SoC Camera driver for tw9910");
945MODULE_AUTHOR("Kuninori Morimoto");
946MODULE_LICENSE("GPL v2");
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