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Merge tag 'pci-v4.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
[deliverable/linux.git] / drivers / media / i2c / tvaudio.c
CommitLineData
1da177e4 1/*
b4ab114c 2 * Driver for simple i2c audio chips.
1da177e4
LT		 3 *
4 * Copyright (c) 2000 Gerd Knorr
5 * based on code by:
6 * Eric Sandeen (eric_sandeen@bigfoot.com)
7 * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
8 * Greg Alexander (galexand@acm.org)
9 *
6a3ca5f5
HV		 10 * For the TDA9875 part:
11 * Copyright (c) 2000 Guillaume Delvit based on Gerd Knorr source
12 * and Eric Sandeen
13 *
b4ab114c
MCC		 14 * Copyright(c) 2005-2008 Mauro Carvalho Chehab
15 * - Some cleanups, code fixes, etc
16 * - Convert it to V4L2 API
17 *
1da177e4
LT		 18 * This code is placed under the terms of the GNU General Public License
19 *
20 * OPTIONS:
21 * debug - set to 1 if you'd like to see debug messages
22 *
23 */
24
1da177e4 25#include <linux/module.h>
1da177e4
LT		 26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/delay.h>
31#include <linux/errno.h>
32#include <linux/slab.h>
7f6adeaf 33#include <linux/videodev2.h>
1da177e4 34#include <linux/i2c.h>
1da177e4 35#include <linux/init.h>
bc282879 36#include <linux/kthread.h>
7dfb7103 37#include <linux/freezer.h>
1da177e4 38
b5dcee22 39#include <media/i2c/tvaudio.h>
64f70e7e 40#include <media/v4l2-device.h>
c9114031 41#include <media/v4l2-ctrls.h>
1da177e4 42
7c9b5048 43#include <media/i2c-addr.h>
1da177e4
LT		 44
45/* ---------------------------------------------------------------------- */
46/* insmod args */
47
ff699e6b 48static int debug; /* insmod parameter */
1da177e4
LT		 49module_param(debug, int, 0644);
50
51MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
52MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
53MODULE_LICENSE("GPL");
54
55#define UNSET (-1U)
18fc59e2 56
1da177e4
LT		 57/* ---------------------------------------------------------------------- */
58/* our structs */
59
4c6c390e 60#define MAXREGS 256
1da177e4
LT		 61
62struct CHIPSTATE;
63typedef int (*getvalue)(int);
64typedef int (*checkit)(struct CHIPSTATE*);
65typedef int (*initialize)(struct CHIPSTATE*);
7bcfdf0f
DG		 66typedef int (*getrxsubchans)(struct CHIPSTATE *);
67typedef void (*setaudmode)(struct CHIPSTATE*, int mode);
1da177e4
LT		 68
69/* i2c command */
70typedef struct AUDIOCMD {
71 int count; /* # of bytes to send */
72 unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
73} audiocmd;
74
75/* chip description */
76struct CHIPDESC {
77 char *name; /* chip name */
1da177e4
LT		 78 int addr_lo, addr_hi; /* i2c address range */
79 int registers; /* # of registers */
80
81 int *insmodopt;
82 checkit checkit;
83 initialize initialize;
84 int flags;
85#define CHIP_HAS_VOLUME 1
86#define CHIP_HAS_BASSTREBLE 2
87#define CHIP_HAS_INPUTSEL 4
dd03e970 88#define CHIP_NEED_CHECKMODE 8
1da177e4
LT		 89
90 /* various i2c command sequences */
91 audiocmd init;
92
93 /* which register has which value */
c9114031 94 int leftreg, rightreg, treblereg, bassreg;
1da177e4 95
a346caac
HV		 96 /* initialize with (defaults to 65535/32768/32768 */
97 int volinit, trebleinit, bassinit;
1da177e4
LT		 98
99 /* functions to convert the values (v4l -> chip) */
c9114031 100 getvalue volfunc, treblefunc, bassfunc;
1da177e4
LT		 101
102 /* get/set mode */
7bcfdf0f
DG		 103 getrxsubchans getrxsubchans;
104 setaudmode setaudmode;
1da177e4 105
1da177e4
LT		 106 /* input switch register + values for v4l inputs */
107 int inputreg;
8bf2f8e7 108 int inputmap[4];
1da177e4
LT		 109 int inputmute;
110 int inputmask;
111};
1da177e4
LT		 112
113/* current state of the chip */
114struct CHIPSTATE {
64f70e7e 115 struct v4l2_subdev sd;
c9114031
HV		 116 struct v4l2_ctrl_handler hdl;
117 struct {
118 /* volume/balance cluster */
119 struct v4l2_ctrl *volume;
120 struct v4l2_ctrl *balance;
121 };
1da177e4 122
81cb5c4f
MCC		 123 /* chip-specific description - should point to
124 an entry at CHIPDESC table */
125 struct CHIPDESC *desc;
1da177e4
LT		 126
127 /* shadow register set */
128 audiocmd shadow;
129
130 /* current settings */
c9114031 131 u16 muted;
1da177e4 132 int prevmode;
8a854284 133 int radio;
8bf2f8e7 134 int input;
1da177e4
LT		 135
136 /* thread */
bc282879 137 struct task_struct *thread;
1da177e4 138 struct timer_list wt;
8a4b275f 139 int audmode;
1da177e4
LT		 140};
141
64f70e7e
HV		 142static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
143{
144 return container_of(sd, struct CHIPSTATE, sd);
145}
146
c9114031
HV		 147static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
148{
149 return &container_of(ctrl->handler, struct CHIPSTATE, hdl)->sd;
150}
151
1da177e4 152
1da177e4
LT		 153/* ---------------------------------------------------------------------- */
154/* i2c I/O functions */
155
156static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
157{
64f70e7e
HV		 158 struct v4l2_subdev *sd = &chip->sd;
159 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 160 unsigned char buffer[2];
161
49426437 162 if (subaddr < 0) {
64f70e7e 163 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
1da177e4
LT		 164 chip->shadow.bytes[1] = val;
165 buffer[0] = val;
64f70e7e
HV		 166 if (1 != i2c_master_send(c, buffer, 1)) {
167 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
1da177e4
LT		 168 return -1;
169 }
170 } else {
49426437 171 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 172 v4l2_info(sd,
49426437
MCC		 173 "Tried to access a non-existent register: %d\n",
174 subaddr);
175 return -EINVAL;
176 }
177
64f70e7e
HV		 178 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
179 subaddr, val);
1da177e4
LT		 180 chip->shadow.bytes[subaddr+1] = val;
181 buffer[0] = subaddr;
182 buffer[1] = val;
64f70e7e
HV		 183 if (2 != i2c_master_send(c, buffer, 2)) {
184 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
185 subaddr, val);
1da177e4
LT		 186 return -1;
187 }
188 }
189 return 0;
190}
191
49426437
MCC		 192static int chip_write_masked(struct CHIPSTATE *chip,
193 int subaddr, int val, int mask)
1da177e4 194{
64f70e7e
HV		 195 struct v4l2_subdev *sd = &chip->sd;
196
1da177e4 197 if (mask != 0) {
49426437 198 if (subaddr < 0) {
1da177e4
LT		 199 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
200 } else {
49426437 201 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 202 v4l2_info(sd,
49426437
MCC		 203 "Tried to access a non-existent register: %d\n",
204 subaddr);
205 return -EINVAL;
206 }
207
1da177e4
LT		 208 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
209 }
210 }
211 return chip_write(chip, subaddr, val);
212}
213
214static int chip_read(struct CHIPSTATE *chip)
215{
64f70e7e
HV		 216 struct v4l2_subdev *sd = &chip->sd;
217 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 218 unsigned char buffer;
219
64f70e7e
HV		 220 if (1 != i2c_master_recv(c, &buffer, 1)) {
221 v4l2_warn(sd, "I/O error (read)\n");
1da177e4
LT		 222 return -1;
223 }
64f70e7e 224 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
1da177e4
LT		 225 return buffer;
226}
227
228static int chip_read2(struct CHIPSTATE *chip, int subaddr)
229{
64f70e7e
HV		 230 struct v4l2_subdev *sd = &chip->sd;
231 struct i2c_client *c = v4l2_get_subdevdata(sd);
18fc59e2
MCC		 232 unsigned char write[1];
233 unsigned char read[1];
234 struct i2c_msg msgs[2] = {
752d283a
S		 235 {
236 .addr = c->addr,
237 .len = 1,
238 .buf = write
239 },
240 {
241 .addr = c->addr,
242 .flags = I2C_M_RD,
243 .len = 1,
244 .buf = read
245 }
18fc59e2 246 };
64f70e7e 247
18fc59e2 248 write[0] = subaddr;
1da177e4 249
64f70e7e
HV		 250 if (2 != i2c_transfer(c->adapter, msgs, 2)) {
251 v4l2_warn(sd, "I/O error (read2)\n");
1da177e4
LT		 252 return -1;
253 }
64f70e7e
HV		 254 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
255 subaddr, read[0]);
1da177e4
LT		 256 return read[0];
257}
258
259static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
260{
64f70e7e
HV		 261 struct v4l2_subdev *sd = &chip->sd;
262 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 263 int i;
264
265 if (0 == cmd->count)
266 return 0;
267
49426437 268 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 269 v4l2_info(sd,
49426437
MCC		 270 "Tried to access a non-existent register range: %d to %d\n",
271 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
272 return -EINVAL;
273 }
274
5a13e40b 275 /* FIXME: it seems that the shadow bytes are wrong below !*/
49426437 276
1da177e4 277 /* update our shadow register set; print bytes if (debug > 0) */
64f70e7e
HV		 278 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
279 name, cmd->bytes[0]);
1da177e4 280 for (i = 1; i < cmd->count; i++) {
18fc59e2 281 if (debug)
64f70e7e 282 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
1da177e4
LT		 283 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
284 }
18fc59e2 285 if (debug)
64f70e7e 286 printk(KERN_CONT "\n");
1da177e4
LT		 287
288 /* send data to the chip */
64f70e7e
HV		 289 if (cmd->count != i2c_master_send(c, cmd->bytes, cmd->count)) {
290 v4l2_warn(sd, "I/O error (%s)\n", name);
1da177e4
LT		 291 return -1;
292 }
293 return 0;
294}
295
296/* ---------------------------------------------------------------------- */
297/* kernel thread for doing i2c stuff asyncronly
298 * right now it is used only to check the audio mode (mono/stereo/whatever)
299 * some time after switching to another TV channel, then turn on stereo
300 * if available, ...
301 */
302
303static void chip_thread_wake(unsigned long data)
304{
18fc59e2 305 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
bc282879 306 wake_up_process(chip->thread);
1da177e4
LT		 307}
308
309static int chip_thread(void *data)
310{
18fc59e2 311 struct CHIPSTATE *chip = data;
81cb5c4f 312 struct CHIPDESC *desc = chip->desc;
64f70e7e 313 struct v4l2_subdev *sd = &chip->sd;
e21adca8 314 int mode, selected;
1da177e4 315
64f70e7e 316 v4l2_dbg(1, debug, sd, "thread started\n");
83144186 317 set_freezable();
1da177e4 318 for (;;) {
bc282879
CLG		 319 set_current_state(TASK_INTERRUPTIBLE);
320 if (!kthread_should_stop())
1da177e4 321 schedule();
bc282879 322 set_current_state(TASK_RUNNING);
5e50e7a9 323 try_to_freeze();
bc282879 324 if (kthread_should_stop())
1da177e4 325 break;
64f70e7e 326 v4l2_dbg(1, debug, sd, "thread wakeup\n");
1da177e4 327
e21adca8
DG		 328 /* don't do anything for radio */
329 if (chip->radio)
1da177e4
LT		 330 continue;
331
332 /* have a look what's going on */
7bcfdf0f 333 mode = desc->getrxsubchans(chip);
dd03e970
MCC		 334 if (mode == chip->prevmode)
335 continue;
336
337 /* chip detected a new audio mode - set it */
64f70e7e 338 v4l2_dbg(1, debug, sd, "thread checkmode\n");
dd03e970
MCC		 339
340 chip->prevmode = mode;
341
e21adca8
DG		 342 selected = V4L2_TUNER_MODE_MONO;
343 switch (chip->audmode) {
344 case V4L2_TUNER_MODE_MONO:
345 if (mode & V4L2_TUNER_SUB_LANG1)
346 selected = V4L2_TUNER_MODE_LANG1;
347 break;
348 case V4L2_TUNER_MODE_STEREO:
349 case V4L2_TUNER_MODE_LANG1:
350 if (mode & V4L2_TUNER_SUB_LANG1)
351 selected = V4L2_TUNER_MODE_LANG1;
352 else if (mode & V4L2_TUNER_SUB_STEREO)
353 selected = V4L2_TUNER_MODE_STEREO;
354 break;
355 case V4L2_TUNER_MODE_LANG2:
356 if (mode & V4L2_TUNER_SUB_LANG2)
357 selected = V4L2_TUNER_MODE_LANG2;
358 else if (mode & V4L2_TUNER_SUB_STEREO)
359 selected = V4L2_TUNER_MODE_STEREO;
360 break;
9e019e07
DG		 361 case V4L2_TUNER_MODE_LANG1_LANG2:
362 if (mode & V4L2_TUNER_SUB_LANG2)
363 selected = V4L2_TUNER_MODE_LANG1_LANG2;
364 else if (mode & V4L2_TUNER_SUB_STEREO)
365 selected = V4L2_TUNER_MODE_STEREO;
e21adca8 366 }
7bcfdf0f 367 desc->setaudmode(chip, selected);
1da177e4
LT		 368
369 /* schedule next check */
09df5cbe 370 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4
LT		 371 }
372
64f70e7e 373 v4l2_dbg(1, debug, sd, "thread exiting\n");
1da177e4
LT		 374 return 0;
375}
376
1da177e4
LT		 377/* ---------------------------------------------------------------------- */
378/* audio chip descriptions - defines+functions for tda9840 */
379
380#define TDA9840_SW 0x00
381#define TDA9840_LVADJ 0x02
382#define TDA9840_STADJ 0x03
383#define TDA9840_TEST 0x04
384
385#define TDA9840_MONO 0x10
386#define TDA9840_STEREO 0x2a
387#define TDA9840_DUALA 0x12
388#define TDA9840_DUALB 0x1e
389#define TDA9840_DUALAB 0x1a
390#define TDA9840_DUALBA 0x16
391#define TDA9840_EXTERNAL 0x7a
392
393#define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
394#define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
395#define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
396
397#define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
398#define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
399
7bcfdf0f 400static int tda9840_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 401{
64f70e7e 402 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 403 int val, mode;
404
405 val = chip_read(chip);
3322a59e 406 mode = V4L2_TUNER_SUB_MONO;
1da177e4 407 if (val & TDA9840_DS_DUAL)
3322a59e 408 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4 409 if (val & TDA9840_ST_STEREO)
1884e298 410 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 411
7bcfdf0f
DG		 412 v4l2_dbg(1, debug, sd,
413 "tda9840_getrxsubchans(): raw chip read: %d, return: %d\n",
18fc59e2 414 val, mode);
1da177e4
LT		 415 return mode;
416}
417
7bcfdf0f 418static void tda9840_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4
LT		 419{
420 int update = 1;
421 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
422
423 switch (mode) {
dc3d75da 424 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 425 t |= TDA9840_MONO;
426 break;
dc3d75da 427 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 428 t |= TDA9840_STEREO;
429 break;
dc3d75da 430 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 431 t |= TDA9840_DUALA;
432 break;
dc3d75da 433 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 434 t |= TDA9840_DUALB;
435 break;
9e019e07
DG		 436 case V4L2_TUNER_MODE_LANG1_LANG2:
437 t |= TDA9840_DUALAB;
438 break;
1da177e4
LT		 439 default:
440 update = 0;
441 }
442
443 if (update)
444 chip_write(chip, TDA9840_SW, t);
445}
446
94f9e56e
HV		 447static int tda9840_checkit(struct CHIPSTATE *chip)
448{
449 int rc;
450 rc = chip_read(chip);
451 /* lower 5 bits should be 0 */
452 return ((rc & 0x1f) == 0) ? 1 : 0;
453}
454
1da177e4
LT		 455/* ---------------------------------------------------------------------- */
456/* audio chip descriptions - defines+functions for tda985x */
457
458/* subaddresses for TDA9855 */
459#define TDA9855_VR 0x00 /* Volume, right */
460#define TDA9855_VL 0x01 /* Volume, left */
461#define TDA9855_BA 0x02 /* Bass */
462#define TDA9855_TR 0x03 /* Treble */
463#define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
464
465/* subaddresses for TDA9850 */
466#define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
467
468/* subaddesses for both chips */
469#define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
470#define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
471#define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
472#define TDA985x_A1 0x08 /* Alignment 1 for both chips */
473#define TDA985x_A2 0x09 /* Alignment 2 for both chips */
474#define TDA985x_A3 0x0a /* Alignment 3 for both chips */
475
476/* Masks for bits in TDA9855 subaddresses */
477/* 0x00 - VR in TDA9855 */
478/* 0x01 - VL in TDA9855 */
479/* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
480 * in 1dB steps - mute is 0x27 */
481
482
483/* 0x02 - BA in TDA9855 */
484/* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
485 * in .5dB steps - 0 is 0x0E */
486
487
488/* 0x03 - TR in TDA9855 */
489/* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
490 * in 3dB steps - 0 is 0x7 */
491
492/* Masks for bits in both chips' subaddresses */
493/* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
494/* Unique to TDA9855: */
495/* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
496 * in 3dB steps - mute is 0x0 */
497
498/* Unique to TDA9850: */
499/* lower 4 bits control stereo noise threshold, over which stereo turns off
500 * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
501
502
503/* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
504/* Unique to TDA9855: */
505#define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
506#define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
507#define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
508#define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
509 /* Bits 0 to 3 select various combinations
4ac97914
MCC		 510 * of line in and line out, only the
511 * interesting ones are defined */
1da177e4
LT		 512#define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
513#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
514
515/* Unique to TDA9850: */
516/* lower 4 bits contol SAP noise threshold, over which SAP turns off
517 * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
518
519
520/* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
521/* Common to TDA9855 and TDA9850: */
522#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
9e019e07 523#define TDA985x_MONOSAP 2<<6 /* Selects Mono on left, SAP on right */
1da177e4
LT		 524#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
525#define TDA985x_MONO 0 /* Forces Mono output */
526#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
527
528/* Unique to TDA9855: */
529#define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
530#define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
531#define TDA9855_LINEAR 0 /* Linear Stereo */
532#define TDA9855_PSEUDO 1 /* Pseudo Stereo */
533#define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
534#define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
535#define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
536
537/* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
538/* Common to both TDA9855 and TDA9850: */
539/* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
540 * in .5dB steps - 0dB is 0x7 */
541
542/* 0x08, 0x09 - A1 and A2 (read/write) */
543/* Common to both TDA9855 and TDA9850: */
544/* lower 5 bites are wideband and spectral expander alignment
545 * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
546#define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
547#define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
548#define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
549
550/* 0x0a - A3 */
551/* Common to both TDA9855 and TDA9850: */
552/* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
553 * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
554#define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
555
556static int tda9855_volume(int val) { return val/0x2e8+0x27; }
557static int tda9855_bass(int val) { return val/0xccc+0x06; }
558static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
559
7bcfdf0f 560static int tda985x_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 561{
3322a59e 562 int mode, val;
1da177e4 563
1da177e4
LT		 564 /* Add mono mode regardless of SAP and stereo */
565 /* Allows forced mono */
3322a59e
DG		 566 mode = V4L2_TUNER_SUB_MONO;
567 val = chip_read(chip);
568 if (val & TDA985x_STP)
1884e298 569 mode = V4L2_TUNER_SUB_STEREO;
3322a59e
DG		 570 if (val & TDA985x_SAPP)
571 mode |= V4L2_TUNER_SUB_SAP;
572 return mode;
1da177e4
LT		 573}
574
7bcfdf0f 575static void tda985x_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4
LT		 576{
577 int update = 1;
578 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
579
580 switch (mode) {
dc3d75da 581 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 582 c6 |= TDA985x_MONO;
583 break;
dc3d75da 584 case V4L2_TUNER_MODE_STEREO:
00fb1850 585 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 586 c6 |= TDA985x_STEREO;
587 break;
00fb1850 588 case V4L2_TUNER_MODE_SAP:
1da177e4
LT		 589 c6 |= TDA985x_SAP;
590 break;
9e019e07
DG		 591 case V4L2_TUNER_MODE_LANG1_LANG2:
592 c6 |= TDA985x_MONOSAP;
593 break;
1da177e4
LT		 594 default:
595 update = 0;
596 }
597 if (update)
598 chip_write(chip,TDA985x_C6,c6);
599}
600
601
602/* ---------------------------------------------------------------------- */
603/* audio chip descriptions - defines+functions for tda9873h */
604
605/* Subaddresses for TDA9873H */
606
607#define TDA9873_SW 0x00 /* Switching */
608#define TDA9873_AD 0x01 /* Adjust */
609#define TDA9873_PT 0x02 /* Port */
610
611/* Subaddress 0x00: Switching Data
612 * B7..B0:
613 *
614 * B1, B0: Input source selection
615 * 0, 0 internal
616 * 1, 0 external stereo
617 * 0, 1 external mono
618 */
619#define TDA9873_INP_MASK 3
620#define TDA9873_INTERNAL 0
621#define TDA9873_EXT_STEREO 2
622#define TDA9873_EXT_MONO 1
623
624/* B3, B2: output signal select
625 * B4 : transmission mode
626 * 0, 0, 1 Mono
627 * 1, 0, 0 Stereo
628 * 1, 1, 1 Stereo (reversed channel)
629 * 0, 0, 0 Dual AB
630 * 0, 0, 1 Dual AA
631 * 0, 1, 0 Dual BB
632 * 0, 1, 1 Dual BA
633 */
634
635#define TDA9873_TR_MASK (7 << 2)
636#define TDA9873_TR_MONO 4
637#define TDA9873_TR_STEREO 1 << 4
d59a14e2 638#define TDA9873_TR_REVERSE ((1 << 3) | (1 << 2))
1da177e4
LT		 639#define TDA9873_TR_DUALA 1 << 2
640#define TDA9873_TR_DUALB 1 << 3
9e019e07 641#define TDA9873_TR_DUALAB 0
1da177e4
LT		 642
643/* output level controls
644 * B5: output level switch (0 = reduced gain, 1 = normal gain)
645 * B6: mute (1 = muted)
646 * B7: auto-mute (1 = auto-mute enabled)
647 */
648
649#define TDA9873_GAIN_NORMAL 1 << 5
650#define TDA9873_MUTE 1 << 6
651#define TDA9873_AUTOMUTE 1 << 7
652
653/* Subaddress 0x01: Adjust/standard */
654
655/* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
656 * Recommended value is +0 dB
657 */
658
659#define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
660
661/* Bits C6..C4 control FM stantard
662 * C6, C5, C4
663 * 0, 0, 0 B/G (PAL FM)
664 * 0, 0, 1 M
665 * 0, 1, 0 D/K(1)
666 * 0, 1, 1 D/K(2)
667 * 1, 0, 0 D/K(3)
668 * 1, 0, 1 I
669 */
670#define TDA9873_BG 0
671#define TDA9873_M 1
672#define TDA9873_DK1 2
673#define TDA9873_DK2 3
674#define TDA9873_DK3 4
675#define TDA9873_I 5
676
677/* C7 controls identification response time (1=fast/0=normal)
678 */
679#define TDA9873_IDR_NORM 0
680#define TDA9873_IDR_FAST 1 << 7
681
682
683/* Subaddress 0x02: Port data */
684
685/* E1, E0 free programmable ports P1/P2
686 0, 0 both ports low
687 0, 1 P1 high
688 1, 0 P2 high
689 1, 1 both ports high
690*/
691
692#define TDA9873_PORTS 3
693
694/* E2: test port */
695#define TDA9873_TST_PORT 1 << 2
696
697/* E5..E3 control mono output channel (together with transmission mode bit B4)
698 *
699 * E5 E4 E3 B4 OUTM
700 * 0 0 0 0 mono
701 * 0 0 1 0 DUAL B
702 * 0 1 0 1 mono (from stereo decoder)
703 */
704#define TDA9873_MOUT_MONO 0
705#define TDA9873_MOUT_FMONO 0
706#define TDA9873_MOUT_DUALA 0
707#define TDA9873_MOUT_DUALB 1 << 3
708#define TDA9873_MOUT_ST 1 << 4
d59a14e2 709#define TDA9873_MOUT_EXTM ((1 << 4) | (1 << 3))
1da177e4 710#define TDA9873_MOUT_EXTL 1 << 5
d59a14e2
DG		 711#define TDA9873_MOUT_EXTR ((1 << 5) | (1 << 3))
712#define TDA9873_MOUT_EXTLR ((1 << 5) | (1 << 4))
713#define TDA9873_MOUT_MUTE ((1 << 5) | (1 << 4) | (1 << 3))
1da177e4
LT		 714
715/* Status bits: (chip read) */
716#define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
717#define TDA9873_STEREO 2 /* Stereo sound is identified */
718#define TDA9873_DUAL 4 /* Dual sound is identified */
719
7bcfdf0f 720static int tda9873_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 721{
64f70e7e 722 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 723 int val,mode;
724
725 val = chip_read(chip);
3322a59e 726 mode = V4L2_TUNER_SUB_MONO;
1da177e4 727 if (val & TDA9873_STEREO)
1884e298 728 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 729 if (val & TDA9873_DUAL)
3322a59e 730 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
7bcfdf0f
DG		 731 v4l2_dbg(1, debug, sd,
732 "tda9873_getrxsubchans(): raw chip read: %d, return: %d\n",
18fc59e2 733 val, mode);
1da177e4
LT		 734 return mode;
735}
736
7bcfdf0f 737static void tda9873_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4 738{
64f70e7e 739 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 740 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
741 /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
742
743 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
7bcfdf0f
DG		 744 v4l2_dbg(1, debug, sd,
745 "tda9873_setaudmode(): external input\n");
1da177e4
LT		 746 return;
747 }
748
7bcfdf0f
DG		 749 v4l2_dbg(1, debug, sd,
750 "tda9873_setaudmode(): chip->shadow.bytes[%d] = %d\n",
751 TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
752 v4l2_dbg(1, debug, sd, "tda9873_setaudmode(): sw_data = %d\n",
753 sw_data);
1da177e4
LT		 754
755 switch (mode) {
dc3d75da 756 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 757 sw_data |= TDA9873_TR_MONO;
758 break;
dc3d75da 759 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 760 sw_data |= TDA9873_TR_STEREO;
761 break;
dc3d75da 762 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 763 sw_data |= TDA9873_TR_DUALA;
764 break;
dc3d75da 765 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 766 sw_data |= TDA9873_TR_DUALB;
767 break;
9e019e07
DG		 768 case V4L2_TUNER_MODE_LANG1_LANG2:
769 sw_data |= TDA9873_TR_DUALAB;
770 break;
1da177e4 771 default:
1da177e4
LT		 772 return;
773 }
774
775 chip_write(chip, TDA9873_SW, sw_data);
7bcfdf0f
DG		 776 v4l2_dbg(1, debug, sd,
777 "tda9873_setaudmode(): req. mode %d; chip_write: %d\n",
1da177e4
LT		 778 mode, sw_data);
779}
780
781static int tda9873_checkit(struct CHIPSTATE *chip)
782{
783 int rc;
784
785 if (-1 == (rc = chip_read2(chip,254)))
786 return 0;
787 return (rc & ~0x1f) == 0x80;
788}
789
790
791/* ---------------------------------------------------------------------- */
792/* audio chip description - defines+functions for tda9874h and tda9874a */
793/* Dariusz Kowalewski <darekk@automex.pl> */
794
795/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
796#define TDA9874A_AGCGR 0x00 /* AGC gain */
797#define TDA9874A_GCONR 0x01 /* general config */
798#define TDA9874A_MSR 0x02 /* monitor select */
799#define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
800#define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
801#define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
802#define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
803#define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
804#define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
805#define TDA9874A_DCR 0x09 /* demodulator config */
806#define TDA9874A_FMER 0x0a /* FM de-emphasis */
807#define TDA9874A_FMMR 0x0b /* FM dematrix */
808#define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
809#define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
810#define TDA9874A_NCONR 0x0e /* NICAM config */
811#define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
812#define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
813#define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
814#define TDA9874A_AMCONR 0x12 /* audio mute control */
815#define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
816#define TDA9874A_AOSR 0x14 /* analog output select */
817#define TDA9874A_DAICONR 0x15 /* digital audio interface config */
818#define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
819#define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
820#define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
821#define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
822
823/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
824#define TDA9874A_DSR 0x00 /* device status */
825#define TDA9874A_NSR 0x01 /* NICAM status */
826#define TDA9874A_NECR 0x02 /* NICAM error count */
827#define TDA9874A_DR1 0x03 /* add. data LSB */
828#define TDA9874A_DR2 0x04 /* add. data MSB */
829#define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
830#define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
831#define TDA9874A_SIFLR 0x07 /* SIF level */
832#define TDA9874A_TR2 252 /* test reg. 2 */
833#define TDA9874A_TR1 253 /* test reg. 1 */
834#define TDA9874A_DIC 254 /* device id. code */
835#define TDA9874A_SIC 255 /* software id. code */
836
837
838static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
839static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
840static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
841static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
842static int tda9874a_dic = -1; /* device id. code */
843
844/* insmod options for tda9874a */
845static unsigned int tda9874a_SIF = UNSET;
846static unsigned int tda9874a_AMSEL = UNSET;
847static unsigned int tda9874a_STD = UNSET;
848module_param(tda9874a_SIF, int, 0444);
849module_param(tda9874a_AMSEL, int, 0444);
850module_param(tda9874a_STD, int, 0444);
851
852/*
853 * initialization table for tda9874 decoder:
854 * - carrier 1 freq. registers (3 bytes)
855 * - carrier 2 freq. registers (3 bytes)
856 * - demudulator config register
857 * - FM de-emphasis register (slow identification mode)
858 * Note: frequency registers must be written in single i2c transfer.
859 */
860static struct tda9874a_MODES {
861 char *name;
862 audiocmd cmd;
863} tda9874a_modelist[9] = {
04e6f990 864 { "A2, B/G", /* default */
1da177e4
LT		 865 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
866 { "A2, M (Korea)",
867 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
868 { "A2, D/K (1)",
869 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
870 { "A2, D/K (2)",
871 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
872 { "A2, D/K (3)",
873 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
874 { "NICAM, I",
875 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
876 { "NICAM, B/G",
877 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
04e6f990 878 { "NICAM, D/K",
1da177e4
LT		 879 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
880 { "NICAM, L",
881 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
882};
883
884static int tda9874a_setup(struct CHIPSTATE *chip)
885{
64f70e7e
HV		 886 struct v4l2_subdev *sd = &chip->sd;
887
1da177e4
LT		 888 chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
889 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
890 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
891 if(tda9874a_dic == 0x11) {
892 chip_write(chip, TDA9874A_FMMR, 0x80);
893 } else { /* dic == 0x07 */
894 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
895 chip_write(chip, TDA9874A_FMMR, 0x00);
896 }
897 chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
898 chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
899 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
900 chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
901 /* Note: If signal quality is poor you may want to change NICAM */
902 /* error limit registers (NLELR and NUELR) to some greater values. */
903 /* Then the sound would remain stereo, but won't be so clear. */
904 chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
905 chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
906
907 if(tda9874a_dic == 0x11) {
908 chip_write(chip, TDA9874A_AMCONR, 0xf9);
909 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
910 chip_write(chip, TDA9874A_AOSR, 0x80);
911 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
912 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
913 } else { /* dic == 0x07 */
914 chip_write(chip, TDA9874A_AMCONR, 0xfb);
915 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
18fc59e2 916 chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
1da177e4 917 }
64f70e7e 918 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
1da177e4
LT		 919 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
920 return 1;
921}
922
7bcfdf0f 923static int tda9874a_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 924{
64f70e7e 925 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 926 int dsr,nsr,mode;
927 int necr; /* just for debugging */
928
3322a59e 929 mode = V4L2_TUNER_SUB_MONO;
1da177e4
LT		 930
931 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
932 return mode;
933 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
934 return mode;
935 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
936 return mode;
937
938 /* need to store dsr/nsr somewhere */
939 chip->shadow.bytes[MAXREGS-2] = dsr;
940 chip->shadow.bytes[MAXREGS-1] = nsr;
941
942 if(tda9874a_mode) {
943 /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
944 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
945 * that sound has (temporarily) switched from NICAM to
946 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
947 * error count. So in fact there is no stereo in this case :-(
dc3d75da 948 * But changing the mode to V4L2_TUNER_MODE_MONO would switch
1da177e4
LT		 949 * external 4052 multiplexer in audio_hook().
950 */
1da177e4 951 if(nsr & 0x02) /* NSR.S/MB=1 */
1884e298 952 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 953 if(nsr & 0x01) /* NSR.D/SB=1 */
3322a59e 954 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4
LT		 955 } else {
956 if(dsr & 0x02) /* DSR.IDSTE=1 */
1884e298 957 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 958 if(dsr & 0x04) /* DSR.IDDUA=1 */
3322a59e 959 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4
LT		 960 }
961
7bcfdf0f
DG		 962 v4l2_dbg(1, debug, sd,
963 "tda9874a_getrxsubchans(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1da177e4
LT		 964 dsr, nsr, necr, mode);
965 return mode;
966}
967
7bcfdf0f 968static void tda9874a_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4 969{
64f70e7e
HV		 970 struct v4l2_subdev *sd = &chip->sd;
971
1da177e4
LT		 972 /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
973 /* If auto-muting is disabled, we can hear a signal of degrading quality. */
64f70e7e 974 if (tda9874a_mode) {
1da177e4
LT		 975 if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
976 tda9874a_NCONR &= 0xfe; /* enable */
977 else
978 tda9874a_NCONR |= 0x01; /* disable */
979 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
980 }
981
982 /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
983 * and has auto-select function for audio output (AOSR register).
984 * Old TDA9874H doesn't support these features.
985 * TDA9874A also has additional mono output pin (OUTM), which
986 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
987 */
988 if(tda9874a_dic == 0x11) {
989 int aosr = 0x80;
990 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
991
992 switch(mode) {
dc3d75da
MCC		 993 case V4L2_TUNER_MODE_MONO:
994 case V4L2_TUNER_MODE_STEREO:
1da177e4 995 break;
dc3d75da 996 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 997 aosr = 0x80; /* auto-select, dual A/A */
998 mdacosr = (tda9874a_mode) ? 0x82:0x80;
999 break;
dc3d75da 1000 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1001 aosr = 0xa0; /* auto-select, dual B/B */
1002 mdacosr = (tda9874a_mode) ? 0x83:0x81;
1003 break;
9e019e07
DG		 1004 case V4L2_TUNER_MODE_LANG1_LANG2:
1005 aosr = 0x00; /* always route L to L and R to R */
1006 mdacosr = (tda9874a_mode) ? 0x82:0x80;
1007 break;
1da177e4 1008 default:
1da177e4
LT		 1009 return;
1010 }
1011 chip_write(chip, TDA9874A_AOSR, aosr);
1012 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
1013
7bcfdf0f
DG		 1014 v4l2_dbg(1, debug, sd,
1015 "tda9874a_setaudmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1da177e4
LT		 1016 mode, aosr, mdacosr);
1017
1018 } else { /* dic == 0x07 */
1019 int fmmr,aosr;
1020
1021 switch(mode) {
dc3d75da 1022 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1023 fmmr = 0x00; /* mono */
1024 aosr = 0x10; /* A/A */
1025 break;
dc3d75da 1026 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1027 if(tda9874a_mode) {
1028 fmmr = 0x00;
1029 aosr = 0x00; /* handled by NICAM auto-mute */
1030 } else {
1031 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
1032 aosr = 0x00;
1033 }
1034 break;
dc3d75da 1035 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1036 fmmr = 0x02; /* dual */
1037 aosr = 0x10; /* dual A/A */
1038 break;
dc3d75da 1039 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1040 fmmr = 0x02; /* dual */
1041 aosr = 0x20; /* dual B/B */
1042 break;
9e019e07
DG		 1043 case V4L2_TUNER_MODE_LANG1_LANG2:
1044 fmmr = 0x02; /* dual */
1045 aosr = 0x00; /* dual A/B */
1046 break;
1da177e4 1047 default:
1da177e4
LT		 1048 return;
1049 }
1050 chip_write(chip, TDA9874A_FMMR, fmmr);
1051 chip_write(chip, TDA9874A_AOSR, aosr);
1052
7bcfdf0f
DG		 1053 v4l2_dbg(1, debug, sd,
1054 "tda9874a_setaudmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1da177e4
LT		 1055 mode, fmmr, aosr);
1056 }
1057}
1058
1059static int tda9874a_checkit(struct CHIPSTATE *chip)
1060{
64f70e7e 1061 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1062 int dic,sic; /* device id. and software id. codes */
1063
1064 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
1065 return 0;
1066 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
1067 return 0;
1068
64f70e7e 1069 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1da177e4
LT		 1070
1071 if((dic == 0x11)||(dic == 0x07)) {
64f70e7e 1072 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1da177e4
LT		 1073 tda9874a_dic = dic; /* remember device id. */
1074 return 1;
1075 }
1076 return 0; /* not found */
1077}
1078
1079static int tda9874a_initialize(struct CHIPSTATE *chip)
1080{
1081 if (tda9874a_SIF > 2)
1082 tda9874a_SIF = 1;
04e6f990 1083 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1da177e4
LT		 1084 tda9874a_STD = 0;
1085 if(tda9874a_AMSEL > 1)
1086 tda9874a_AMSEL = 0;
1087
1088 if(tda9874a_SIF == 1)
1089 tda9874a_GCONR = 0xc0; /* sound IF input 1 */
1090 else
1091 tda9874a_GCONR = 0xc1; /* sound IF input 2 */
1092
1093 tda9874a_ESP = tda9874a_STD;
1094 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1095
1096 if(tda9874a_AMSEL == 0)
1097 tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
1098 else
1099 tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
1100
1101 tda9874a_setup(chip);
1102 return 0;
1103}
1104
411674fd
HV		 1105/* ---------------------------------------------------------------------- */
1106/* audio chip description - defines+functions for tda9875 */
1107/* The TDA9875 is made by Philips Semiconductor
1108 * http://www.semiconductors.philips.com
1109 * TDA9875: I2C-bus controlled DSP audio processor, FM demodulator
1110 *
1111 */
1112
1113/* subaddresses for TDA9875 */
1114#define TDA9875_MUT 0x12 /*General mute (value --> 0b11001100*/
1115#define TDA9875_CFG 0x01 /* Config register (value --> 0b00000000 */
1116#define TDA9875_DACOS 0x13 /*DAC i/o select (ADC) 0b0000100*/
1117#define TDA9875_LOSR 0x16 /*Line output select regirter 0b0100 0001*/
1118
1119#define TDA9875_CH1V 0x0c /*Channel 1 volume (mute)*/
1120#define TDA9875_CH2V 0x0d /*Channel 2 volume (mute)*/
1121#define TDA9875_SC1 0x14 /*SCART 1 in (mono)*/
1122#define TDA9875_SC2 0x15 /*SCART 2 in (mono)*/
1123
1124#define TDA9875_ADCIS 0x17 /*ADC input select (mono) 0b0110 000*/
1125#define TDA9875_AER 0x19 /*Audio effect (AVL+Pseudo) 0b0000 0110*/
1126#define TDA9875_MCS 0x18 /*Main channel select (DAC) 0b0000100*/
1127#define TDA9875_MVL 0x1a /* Main volume gauche */
1128#define TDA9875_MVR 0x1b /* Main volume droite */
1129#define TDA9875_MBA 0x1d /* Main Basse */
1130#define TDA9875_MTR 0x1e /* Main treble */
25985edc
LDM		 1131#define TDA9875_ACS 0x1f /* Auxiliary channel select (FM) 0b0000000*/
1132#define TDA9875_AVL 0x20 /* Auxiliary volume gauche */
1133#define TDA9875_AVR 0x21 /* Auxiliary volume droite */
1134#define TDA9875_ABA 0x22 /* Auxiliary Basse */
1135#define TDA9875_ATR 0x23 /* Auxiliary treble */
411674fd
HV		 1136
1137#define TDA9875_MSR 0x02 /* Monitor select register */
1138#define TDA9875_C1MSB 0x03 /* Carrier 1 (FM) frequency register MSB */
1139#define TDA9875_C1MIB 0x04 /* Carrier 1 (FM) frequency register (16-8]b */
1140#define TDA9875_C1LSB 0x05 /* Carrier 1 (FM) frequency register LSB */
1141#define TDA9875_C2MSB 0x06 /* Carrier 2 (nicam) frequency register MSB */
1142#define TDA9875_C2MIB 0x07 /* Carrier 2 (nicam) frequency register (16-8]b */
1143#define TDA9875_C2LSB 0x08 /* Carrier 2 (nicam) frequency register LSB */
1144#define TDA9875_DCR 0x09 /* Demodulateur configuration regirter*/
1145#define TDA9875_DEEM 0x0a /* FM de-emphasis regirter*/
1146#define TDA9875_FMAT 0x0b /* FM Matrix regirter*/
1147
1148/* values */
1149#define TDA9875_MUTE_ON 0xff /* general mute */
1150#define TDA9875_MUTE_OFF 0xcc /* general no mute */
1151
1152static int tda9875_initialize(struct CHIPSTATE *chip)
1153{
1154 chip_write(chip, TDA9875_CFG, 0xd0); /*reg de config 0 (reset)*/
1155 chip_write(chip, TDA9875_MSR, 0x03); /* Monitor 0b00000XXX*/
1156 chip_write(chip, TDA9875_C1MSB, 0x00); /*Car1(FM) MSB XMHz*/
1157 chip_write(chip, TDA9875_C1MIB, 0x00); /*Car1(FM) MIB XMHz*/
1158 chip_write(chip, TDA9875_C1LSB, 0x00); /*Car1(FM) LSB XMHz*/
1159 chip_write(chip, TDA9875_C2MSB, 0x00); /*Car2(NICAM) MSB XMHz*/
1160 chip_write(chip, TDA9875_C2MIB, 0x00); /*Car2(NICAM) MIB XMHz*/
1161 chip_write(chip, TDA9875_C2LSB, 0x00); /*Car2(NICAM) LSB XMHz*/
1162 chip_write(chip, TDA9875_DCR, 0x00); /*Demod config 0x00*/
1163 chip_write(chip, TDA9875_DEEM, 0x44); /*DE-Emph 0b0100 0100*/
1164 chip_write(chip, TDA9875_FMAT, 0x00); /*FM Matrix reg 0x00*/
1165 chip_write(chip, TDA9875_SC1, 0x00); /* SCART 1 (SC1)*/
1166 chip_write(chip, TDA9875_SC2, 0x01); /* SCART 2 (sc2)*/
1167
1168 chip_write(chip, TDA9875_CH1V, 0x10); /* Channel volume 1 mute*/
1169 chip_write(chip, TDA9875_CH2V, 0x10); /* Channel volume 2 mute */
1170 chip_write(chip, TDA9875_DACOS, 0x02); /* sig DAC i/o(in:nicam)*/
1171 chip_write(chip, TDA9875_ADCIS, 0x6f); /* sig ADC input(in:mono)*/
1172 chip_write(chip, TDA9875_LOSR, 0x00); /* line out (in:mono)*/
1173 chip_write(chip, TDA9875_AER, 0x00); /*06 Effect (AVL+PSEUDO) */
1174 chip_write(chip, TDA9875_MCS, 0x44); /* Main ch select (DAC) */
1175 chip_write(chip, TDA9875_MVL, 0x03); /* Vol Main left 10dB */
1176 chip_write(chip, TDA9875_MVR, 0x03); /* Vol Main right 10dB*/
1177 chip_write(chip, TDA9875_MBA, 0x00); /* Main Bass Main 0dB*/
1178 chip_write(chip, TDA9875_MTR, 0x00); /* Main Treble Main 0dB*/
1179 chip_write(chip, TDA9875_ACS, 0x44); /* Aux chan select (dac)*/
1180 chip_write(chip, TDA9875_AVL, 0x00); /* Vol Aux left 0dB*/
1181 chip_write(chip, TDA9875_AVR, 0x00); /* Vol Aux right 0dB*/
1182 chip_write(chip, TDA9875_ABA, 0x00); /* Aux Bass Main 0dB*/
1183 chip_write(chip, TDA9875_ATR, 0x00); /* Aux Aigus Main 0dB*/
1184
1185 chip_write(chip, TDA9875_MUT, 0xcc); /* General mute */
1186 return 0;
1187}
1188
1189static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1190static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1191static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1192
1193/* ----------------------------------------------------------------------- */
1194
1195
1196/* *********************** *
1197 * i2c interface functions *
1198 * *********************** */
1199
1200static int tda9875_checkit(struct CHIPSTATE *chip)
1201{
1202 struct v4l2_subdev *sd = &chip->sd;
1203 int dic, rev;
1204
1205 dic = chip_read2(chip, 254);
1206 rev = chip_read2(chip, 255);
1207
1208 if (dic == 0 || dic == 2) { /* tda9875 and tda9875A */
1209 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1210 dic == 0 ? "" : "A", rev);
1211 return 1;
1212 }
1213 return 0;
1214}
1da177e4
LT		 1215
1216/* ---------------------------------------------------------------------- */
1217/* audio chip descriptions - defines+functions for tea6420 */
1218
1219#define TEA6300_VL 0x00 /* volume left */
1220#define TEA6300_VR 0x01 /* volume right */
1221#define TEA6300_BA 0x02 /* bass */
1222#define TEA6300_TR 0x03 /* treble */
1223#define TEA6300_FA 0x04 /* fader control */
1224#define TEA6300_S 0x05 /* switch register */
f2421ca3 1225 /* values for those registers: */
1da177e4
LT		 1226#define TEA6300_S_SA 0x01 /* stereo A input */
1227#define TEA6300_S_SB 0x02 /* stereo B */
1228#define TEA6300_S_SC 0x04 /* stereo C */
1229#define TEA6300_S_GMU 0x80 /* general mute */
1230
1231#define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
1232#define TEA6320_FFR 0x01 /* fader front right (0-5) */
1233#define TEA6320_FFL 0x02 /* fader front left (0-5) */
1234#define TEA6320_FRR 0x03 /* fader rear right (0-5) */
1235#define TEA6320_FRL 0x04 /* fader rear left (0-5) */
1236#define TEA6320_BA 0x05 /* bass (0-4) */
1237#define TEA6320_TR 0x06 /* treble (0-4) */
1238#define TEA6320_S 0x07 /* switch register */
f2421ca3 1239 /* values for those registers: */
1da177e4
LT		 1240#define TEA6320_S_SA 0x07 /* stereo A input */
1241#define TEA6320_S_SB 0x06 /* stereo B */
1242#define TEA6320_S_SC 0x05 /* stereo C */
1243#define TEA6320_S_SD 0x04 /* stereo D */
1244#define TEA6320_S_GMU 0x80 /* general mute */
1245
1246#define TEA6420_S_SA 0x00 /* stereo A input */
1247#define TEA6420_S_SB 0x01 /* stereo B */
1248#define TEA6420_S_SC 0x02 /* stereo C */
1249#define TEA6420_S_SD 0x03 /* stereo D */
1250#define TEA6420_S_SE 0x04 /* stereo E */
1251#define TEA6420_S_GMU 0x05 /* general mute */
1252
1253static int tea6300_shift10(int val) { return val >> 10; }
1254static int tea6300_shift12(int val) { return val >> 12; }
1255
1256/* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
1257/* 0x0c mirror those immediately higher) */
1258static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1259static int tea6320_shift11(int val) { return val >> 11; }
1260static int tea6320_initialize(struct CHIPSTATE * chip)
1261{
1262 chip_write(chip, TEA6320_FFR, 0x3f);
1263 chip_write(chip, TEA6320_FFL, 0x3f);
1264 chip_write(chip, TEA6320_FRR, 0x3f);
1265 chip_write(chip, TEA6320_FRL, 0x3f);
1266
1267 return 0;
1268}
1269
1270
1271/* ---------------------------------------------------------------------- */
1272/* audio chip descriptions - defines+functions for tda8425 */
1273
1274#define TDA8425_VL 0x00 /* volume left */
1275#define TDA8425_VR 0x01 /* volume right */
1276#define TDA8425_BA 0x02 /* bass */
1277#define TDA8425_TR 0x03 /* treble */
1278#define TDA8425_S1 0x08 /* switch functions */
f2421ca3 1279 /* values for those registers: */
1da177e4
LT		 1280#define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
1281#define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
1282#define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
1283#define TDA8425_S1_MU 0x20 /* mute bit */
1284#define TDA8425_S1_STEREO 0x18 /* stereo bits */
1285#define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
1286#define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
1287#define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
1288#define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
1289#define TDA8425_S1_ML 0x06 /* language selector */
1290#define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
1291#define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
1292#define TDA8425_S1_ML_STEREO 0x06 /* stereo */
1293#define TDA8425_S1_IS 0x01 /* channel selector */
1294
1295
1296static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1297static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1298
7bcfdf0f 1299static void tda8425_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4
LT		 1300{
1301 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1302
f952848d
DG		 1303 switch (mode) {
1304 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1305 s1 |= TDA8425_S1_ML_SOUND_A;
1306 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d
DG		 1307 break;
1308 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1309 s1 |= TDA8425_S1_ML_SOUND_B;
1310 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d 1311 break;
9e019e07
DG		 1312 case V4L2_TUNER_MODE_LANG1_LANG2:
1313 s1 |= TDA8425_S1_ML_STEREO;
1314 s1 |= TDA8425_S1_STEREO_LINEAR;
1315 break;
f952848d 1316 case V4L2_TUNER_MODE_MONO:
1da177e4 1317 s1 |= TDA8425_S1_ML_STEREO;
f952848d
DG		 1318 s1 |= TDA8425_S1_STEREO_MONO;
1319 break;
1320 case V4L2_TUNER_MODE_STEREO:
1321 s1 |= TDA8425_S1_ML_STEREO;
1322 s1 |= TDA8425_S1_STEREO_SPATIAL;
1323 break;
1324 default:
1325 return;
1da177e4
LT		 1326 }
1327 chip_write(chip,TDA8425_S1,s1);
1328}
1329
1330
1331/* ---------------------------------------------------------------------- */
1332/* audio chip descriptions - defines+functions for pic16c54 (PV951) */
1333
1334/* the registers of 16C54, I2C sub address. */
1335#define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
1336#define PIC16C54_REG_MISC 0x02
1337
1338/* bit definition of the RESET register, I2C data. */
1339#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
f2421ca3 1340 /* code of remote controller */
1da177e4
LT		 1341#define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
1342#define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
1343#define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
1344#define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
1345#define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
1346#define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
1347#define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
1348
1349/* ---------------------------------------------------------------------- */
1350/* audio chip descriptions - defines+functions for TA8874Z */
1351
18fc59e2 1352/* write 1st byte */
1da177e4
LT		 1353#define TA8874Z_LED_STE 0x80
1354#define TA8874Z_LED_BIL 0x40
1355#define TA8874Z_LED_EXT 0x20
1356#define TA8874Z_MONO_SET 0x10
1357#define TA8874Z_MUTE 0x08
1358#define TA8874Z_F_MONO 0x04
1359#define TA8874Z_MODE_SUB 0x02
1360#define TA8874Z_MODE_MAIN 0x01
1361
18fc59e2
MCC		 1362/* write 2nd byte */
1363/*#define TA8874Z_TI 0x80 */ /* test mode */
1da177e4
LT		 1364#define TA8874Z_SEPARATION 0x3f
1365#define TA8874Z_SEPARATION_DEFAULT 0x10
1366
18fc59e2 1367/* read */
1da177e4
LT		 1368#define TA8874Z_B1 0x80
1369#define TA8874Z_B0 0x40
1370#define TA8874Z_CHAG_FLAG 0x20
1371
18fc59e2
MCC		 1372/*
1373 * B1 B0
1374 * mono L H
1375 * stereo L L
1376 * BIL H L
1377 */
7bcfdf0f 1378static int ta8874z_getrxsubchans(struct CHIPSTATE *chip)
1da177e4
LT		 1379{
1380 int val, mode;
1381
1382 val = chip_read(chip);
3322a59e 1383 mode = V4L2_TUNER_SUB_MONO;
1da177e4 1384 if (val & TA8874Z_B1){
3322a59e 1385 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4 1386 }else if (!(val & TA8874Z_B0)){
1884e298 1387 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 1388 }
7bcfdf0f
DG		 1389 /* v4l2_dbg(1, debug, &chip->sd,
1390 "ta8874z_getrxsubchans(): raw chip read: 0x%02x, return: 0x%02x\n",
1391 val, mode); */
1da177e4
LT		 1392 return mode;
1393}
1394
1395static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1396static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1397static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1398static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
9e019e07 1399static audiocmd ta8874z_both = {2, { TA8874Z_MODE_MAIN | TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1da177e4 1400
7bcfdf0f 1401static void ta8874z_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4 1402{
64f70e7e 1403 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1404 int update = 1;
1405 audiocmd *t = NULL;
64f70e7e 1406
7bcfdf0f 1407 v4l2_dbg(1, debug, sd, "ta8874z_setaudmode(): mode: 0x%02x\n", mode);
1da177e4
LT		 1408
1409 switch(mode){
dc3d75da 1410 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1411 t = &ta8874z_mono;
1412 break;
dc3d75da 1413 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1414 t = &ta8874z_stereo;
1415 break;
dc3d75da 1416 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1417 t = &ta8874z_main;
1418 break;
dc3d75da 1419 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1420 t = &ta8874z_sub;
1421 break;
9e019e07
DG		 1422 case V4L2_TUNER_MODE_LANG1_LANG2:
1423 t = &ta8874z_both;
1424 break;
1da177e4
LT		 1425 default:
1426 update = 0;
1427 }
1428
1429 if(update)
1430 chip_cmd(chip, "TA8874Z", t);
1431}
1432
1433static int ta8874z_checkit(struct CHIPSTATE *chip)
1434{
1435 int rc;
1436 rc = chip_read(chip);
1437 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1438}
1439
1440/* ---------------------------------------------------------------------- */
1441/* audio chip descriptions - struct CHIPDESC */
1442
1443/* insmod options to enable/disable individual audio chips */
52c1da39
AB		 1444static int tda8425 = 1;
1445static int tda9840 = 1;
1446static int tda9850 = 1;
1447static int tda9855 = 1;
1448static int tda9873 = 1;
1449static int tda9874a = 1;
411674fd 1450static int tda9875 = 1;
ff699e6b
DSL		 1451static int tea6300; /* default 0 - address clash with msp34xx */
1452static int tea6320; /* default 0 - address clash with msp34xx */
52c1da39
AB		 1453static int tea6420 = 1;
1454static int pic16c54 = 1;
ff699e6b 1455static int ta8874z; /* default 0 - address clash with tda9840 */
1da177e4
LT		 1456
1457module_param(tda8425, int, 0444);
1458module_param(tda9840, int, 0444);
1459module_param(tda9850, int, 0444);
1460module_param(tda9855, int, 0444);
1461module_param(tda9873, int, 0444);
1462module_param(tda9874a, int, 0444);
411674fd 1463module_param(tda9875, int, 0444);
1da177e4
LT		 1464module_param(tea6300, int, 0444);
1465module_param(tea6320, int, 0444);
1466module_param(tea6420, int, 0444);
1467module_param(pic16c54, int, 0444);
1468module_param(ta8874z, int, 0444);
1469
1470static struct CHIPDESC chiplist[] = {
1471 {
1472 .name = "tda9840",
1da177e4 1473 .insmodopt = &tda9840,
09df1c16
MCC		 1474 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1475 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1476 .registers = 5,
dd03e970 1477 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1478
af1a9951 1479 /* callbacks */
94f9e56e 1480 .checkit = tda9840_checkit,
7bcfdf0f
DG		 1481 .getrxsubchans = tda9840_getrxsubchans,
1482 .setaudmode = tda9840_setaudmode,
1da177e4 1483
4ac97914 1484 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1da177e4
LT		 1485 /* ,TDA9840_SW, TDA9840_MONO */} }
1486 },
1487 {
1488 .name = "tda9873h",
1da177e4 1489 .insmodopt = &tda9873,
09df1c16
MCC		 1490 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1491 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4 1492 .registers = 3,
dd03e970 1493 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1da177e4 1494
af1a9951
MCC		 1495 /* callbacks */
1496 .checkit = tda9873_checkit,
7bcfdf0f
DG		 1497 .getrxsubchans = tda9873_getrxsubchans,
1498 .setaudmode = tda9873_setaudmode,
1da177e4
LT		 1499
1500 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1501 .inputreg = TDA9873_SW,
1502 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
8bf2f8e7 1503 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1da177e4
LT		 1504 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1505
1506 },
1507 {
1508 .name = "tda9874h/a",
1da177e4 1509 .insmodopt = &tda9874a,
09df1c16
MCC		 1510 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1511 .addr_hi = I2C_ADDR_TDA9874 >> 1,
dd03e970 1512 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1513
af1a9951
MCC		 1514 /* callbacks */
1515 .initialize = tda9874a_initialize,
1516 .checkit = tda9874a_checkit,
7bcfdf0f
DG		 1517 .getrxsubchans = tda9874a_getrxsubchans,
1518 .setaudmode = tda9874a_setaudmode,
1da177e4 1519 },
411674fd
HV		 1520 {
1521 .name = "tda9875",
1522 .insmodopt = &tda9875,
1523 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1524 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1525 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1526
1527 /* callbacks */
1528 .initialize = tda9875_initialize,
1529 .checkit = tda9875_checkit,
1530 .volfunc = tda9875_volume,
1531 .bassfunc = tda9875_bass,
1532 .treblefunc = tda9875_treble,
1533 .leftreg = TDA9875_MVL,
1534 .rightreg = TDA9875_MVR,
1535 .bassreg = TDA9875_MBA,
1536 .treblereg = TDA9875_MTR,
a346caac 1537 .volinit = 58880,
411674fd 1538 },
1da177e4
LT		 1539 {
1540 .name = "tda9850",
1da177e4 1541 .insmodopt = &tda9850,
09df1c16
MCC		 1542 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1543 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1544 .registers = 11,
1545
7bcfdf0f
DG		 1546 .getrxsubchans = tda985x_getrxsubchans,
1547 .setaudmode = tda985x_setaudmode,
1da177e4
LT		 1548
1549 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1550 },
1551 {
1552 .name = "tda9855",
1da177e4 1553 .insmodopt = &tda9855,
09df1c16
MCC		 1554 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1555 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1556 .registers = 11,
1557 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1558
1559 .leftreg = TDA9855_VL,
1560 .rightreg = TDA9855_VR,
1561 .bassreg = TDA9855_BA,
1562 .treblereg = TDA9855_TR,
af1a9951
MCC		 1563
1564 /* callbacks */
1da177e4
LT		 1565 .volfunc = tda9855_volume,
1566 .bassfunc = tda9855_bass,
1567 .treblefunc = tda9855_treble,
7bcfdf0f
DG		 1568 .getrxsubchans = tda985x_getrxsubchans,
1569 .setaudmode = tda985x_setaudmode,
1da177e4
LT		 1570
1571 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1572 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1573 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1574 0x07, 0x10, 0x10, 0x03 }}
1575 },
1576 {
1577 .name = "tea6300",
1da177e4 1578 .insmodopt = &tea6300,
09df1c16
MCC		 1579 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1580 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1581 .registers = 6,
1582 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1583
1584 .leftreg = TEA6300_VR,
1585 .rightreg = TEA6300_VL,
1586 .bassreg = TEA6300_BA,
1587 .treblereg = TEA6300_TR,
af1a9951
MCC		 1588
1589 /* callbacks */
1da177e4
LT		 1590 .volfunc = tea6300_shift10,
1591 .bassfunc = tea6300_shift12,
1592 .treblefunc = tea6300_shift12,
1593
1594 .inputreg = TEA6300_S,
1595 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1596 .inputmute = TEA6300_S_GMU,
1597 },
1598 {
1599 .name = "tea6320",
1da177e4 1600 .insmodopt = &tea6320,
09df1c16
MCC		 1601 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1602 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1603 .registers = 8,
1604 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1605
1606 .leftreg = TEA6320_V,
1607 .rightreg = TEA6320_V,
1608 .bassreg = TEA6320_BA,
1609 .treblereg = TEA6320_TR,
af1a9951
MCC		 1610
1611 /* callbacks */
1612 .initialize = tea6320_initialize,
1da177e4
LT		 1613 .volfunc = tea6320_volume,
1614 .bassfunc = tea6320_shift11,
1615 .treblefunc = tea6320_shift11,
1616
1617 .inputreg = TEA6320_S,
1618 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1619 .inputmute = TEA6300_S_GMU,
1620 },
1621 {
1622 .name = "tea6420",
1da177e4 1623 .insmodopt = &tea6420,
09df1c16
MCC		 1624 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1625 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1da177e4
LT		 1626 .registers = 1,
1627 .flags = CHIP_HAS_INPUTSEL,
1628
1629 .inputreg = -1,
1630 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
71df09bc
HV		 1631 .inputmute = TEA6420_S_GMU,
1632 .inputmask = 0x07,
1da177e4
LT		 1633 },
1634 {
1635 .name = "tda8425",
1da177e4 1636 .insmodopt = &tda8425,
09df1c16
MCC		 1637 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1638 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1da177e4
LT		 1639 .registers = 9,
1640 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1641
1642 .leftreg = TDA8425_VL,
1643 .rightreg = TDA8425_VR,
1644 .bassreg = TDA8425_BA,
1645 .treblereg = TDA8425_TR,
af1a9951
MCC		 1646
1647 /* callbacks */
1da177e4
LT		 1648 .volfunc = tda8425_shift10,
1649 .bassfunc = tda8425_shift12,
1650 .treblefunc = tda8425_shift12,
7bcfdf0f 1651 .setaudmode = tda8425_setaudmode,
1da177e4
LT		 1652
1653 .inputreg = TDA8425_S1,
1654 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1655 .inputmute = TDA8425_S1_OFF,
1656
1da177e4
LT		 1657 },
1658 {
1659 .name = "pic16c54 (PV951)",
1da177e4 1660 .insmodopt = &pic16c54,
09df1c16
MCC		 1661 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1662 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1da177e4
LT		 1663 .registers = 2,
1664 .flags = CHIP_HAS_INPUTSEL,
1665
1666 .inputreg = PIC16C54_REG_MISC,
1667 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1668 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1669 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
8bf2f8e7 1670 PIC16C54_MISC_SND_MUTE},
1da177e4
LT		 1671 .inputmute = PIC16C54_MISC_SND_MUTE,
1672 },
1673 {
1674 .name = "ta8874z",
1da177e4
LT		 1675 .checkit = ta8874z_checkit,
1676 .insmodopt = &ta8874z,
09df1c16
MCC		 1677 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1678 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4
LT		 1679 .registers = 2,
1680
af1a9951 1681 /* callbacks */
7bcfdf0f
DG		 1682 .getrxsubchans = ta8874z_getrxsubchans,
1683 .setaudmode = ta8874z_setaudmode,
1da177e4 1684
4ac97914 1685 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1da177e4
LT		 1686 },
1687 { .name = NULL } /* EOF */
1688};
1689
1690
1691/* ---------------------------------------------------------------------- */
1da177e4 1692
c9114031 1693static int tvaudio_s_ctrl(struct v4l2_ctrl *ctrl)
8bf2f8e7 1694{
c9114031 1695 struct v4l2_subdev *sd = to_sd(ctrl);
64f70e7e 1696 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1697 struct CHIPDESC *desc = chip->desc;
8bf2f8e7
HV		 1698
1699 switch (ctrl->id) {
1700 case V4L2_CID_AUDIO_MUTE:
c9114031 1701 chip->muted = ctrl->val;
8bf2f8e7
HV		 1702 if (chip->muted)
1703 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1704 else
1705 chip_write_masked(chip,desc->inputreg,
1706 desc->inputmap[chip->input],desc->inputmask);
dc3d75da 1707 return 0;
c9114031 1708 case V4L2_CID_AUDIO_VOLUME: {
a346caac
HV		 1709 u32 volume, balance;
1710 u32 left, right;
88af8304 1711
c9114031
HV		 1712 volume = chip->volume->val;
1713 balance = chip->balance->val;
a346caac
HV		 1714 left = (min(65536U - balance, 32768U) * volume) / 32768U;
1715 right = (min(balance, 32768U) * volume) / 32768U;
dc3d75da 1716
a346caac
HV		 1717 chip_write(chip, desc->leftreg, desc->volfunc(left));
1718 chip_write(chip, desc->rightreg, desc->volfunc(right));
dc3d75da
MCC		 1719 return 0;
1720 }
1721 case V4L2_CID_AUDIO_BASS:
c9114031 1722 chip_write(chip, desc->bassreg, desc->bassfunc(ctrl->val));
dc3d75da
MCC		 1723 return 0;
1724 case V4L2_CID_AUDIO_TREBLE:
c9114031 1725 chip_write(chip, desc->treblereg, desc->treblefunc(ctrl->val));
dc3d75da
MCC		 1726 return 0;
1727 }
1728 return -EINVAL;
8bf2f8e7
HV		 1729}
1730
1731
1da177e4
LT		 1732/* ---------------------------------------------------------------------- */
1733/* video4linux interface */
1734
64f70e7e 1735static int tvaudio_s_radio(struct v4l2_subdev *sd)
1da177e4 1736{
64f70e7e 1737 struct CHIPSTATE *chip = to_state(sd);
1da177e4 1738
64f70e7e 1739 chip->radio = 1;
64f70e7e
HV		 1740 /* del_timer(&chip->wt); */
1741 return 0;
1742}
1743
5325b427
HV		 1744static int tvaudio_s_routing(struct v4l2_subdev *sd,
1745 u32 input, u32 output, u32 config)
64f70e7e
HV		 1746{
1747 struct CHIPSTATE *chip = to_state(sd);
1748 struct CHIPDESC *desc = chip->desc;
1da177e4 1749
5fa7b9f3
HV		 1750 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1751 return 0;
5325b427 1752 if (input >= 4)
64f70e7e
HV		 1753 return -EINVAL;
1754 /* There are four inputs: tuner, radio, extern and intern. */
5325b427 1755 chip->input = input;
64f70e7e
HV		 1756 if (chip->muted)
1757 return 0;
1758 chip_write_masked(chip, desc->inputreg,
1759 desc->inputmap[chip->input], desc->inputmask);
1760 return 0;
1761}
1762
2f73c7c5 1763static int tvaudio_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
64f70e7e
HV		 1764{
1765 struct CHIPSTATE *chip = to_state(sd);
1766 struct CHIPDESC *desc = chip->desc;
64f70e7e 1767
7bcfdf0f 1768 if (!desc->setaudmode)
5fa7b9f3 1769 return 0;
64f70e7e
HV		 1770 if (chip->radio)
1771 return 0;
5fa7b9f3 1772
64f70e7e
HV		 1773 switch (vt->audmode) {
1774 case V4L2_TUNER_MODE_MONO:
1775 case V4L2_TUNER_MODE_STEREO:
1776 case V4L2_TUNER_MODE_LANG1:
1777 case V4L2_TUNER_MODE_LANG2:
64f70e7e 1778 case V4L2_TUNER_MODE_LANG1_LANG2:
64f70e7e
HV		 1779 break;
1780 default:
1781 return -EINVAL;
1782 }
1783 chip->audmode = vt->audmode;
1784
e21adca8
DG		 1785 if (chip->thread)
1786 wake_up_process(chip->thread);
1787 else
7bcfdf0f 1788 desc->setaudmode(chip, vt->audmode);
e21adca8 1789
64f70e7e
HV		 1790 return 0;
1791}
8bf2f8e7 1792
64f70e7e
HV		 1793static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1794{
1795 struct CHIPSTATE *chip = to_state(sd);
1796 struct CHIPDESC *desc = chip->desc;
2474ed44 1797
7bcfdf0f 1798 if (!desc->getrxsubchans)
5fa7b9f3 1799 return 0;
64f70e7e
HV		 1800 if (chip->radio)
1801 return 0;
5fa7b9f3 1802
64f70e7e 1803 vt->audmode = chip->audmode;
7bcfdf0f 1804 vt->rxsubchans = desc->getrxsubchans(chip);
3d4b8035 1805 vt->capability |= V4L2_TUNER_CAP_STEREO |
64f70e7e
HV		 1806 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1807
64f70e7e
HV		 1808 return 0;
1809}
1810
1811static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1812{
1813 struct CHIPSTATE *chip = to_state(sd);
1814
1815 chip->radio = 0;
1816 return 0;
1817}
1818
b530a447 1819static int tvaudio_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *freq)
64f70e7e
HV		 1820{
1821 struct CHIPSTATE *chip = to_state(sd);
1822 struct CHIPDESC *desc = chip->desc;
1823
7bcfdf0f 1824 /* For chips that provide getrxsubchans and setaudmode, and doesn't
64f70e7e
HV		 1825 automatically follows the stereo carrier, a kthread is
1826 created to set the audio standard. In this case, when then
1827 the video channel is changed, tvaudio starts on MONO mode.
1828 After waiting for 2 seconds, the kernel thread is called,
1829 to follow whatever audio standard is pointed by the
1830 audio carrier.
1831 */
1832 if (chip->thread) {
7bcfdf0f 1833 desc->setaudmode(chip, V4L2_TUNER_MODE_MONO);
e21adca8 1834 chip->prevmode = -1; /* reset previous mode */
64f70e7e 1835 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
2474ed44 1836 }
64f70e7e
HV		 1837 return 0;
1838}
2474ed44 1839
c9114031
HV		 1840static int tvaudio_log_status(struct v4l2_subdev *sd)
1841{
1842 struct CHIPSTATE *chip = to_state(sd);
1843 struct CHIPDESC *desc = chip->desc;
1844
1845 v4l2_info(sd, "Chip: %s\n", desc->name);
1846 v4l2_ctrl_handler_log_status(&chip->hdl, sd->name);
1847 return 0;
1848}
1849
64f70e7e
HV		 1850/* ----------------------------------------------------------------------- */
1851
c9114031
HV		 1852static const struct v4l2_ctrl_ops tvaudio_ctrl_ops = {
1853 .s_ctrl = tvaudio_s_ctrl,
1854};
1855
64f70e7e 1856static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
c9114031 1857 .log_status = tvaudio_log_status,
64f70e7e
HV		 1858};
1859
1860static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1861 .s_radio = tvaudio_s_radio,
1862 .s_frequency = tvaudio_s_frequency,
64f70e7e 1863 .s_tuner = tvaudio_s_tuner,
e6a1a08f 1864 .g_tuner = tvaudio_g_tuner,
64f70e7e
HV		 1865};
1866
1867static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1868 .s_routing = tvaudio_s_routing,
1869};
1870
8774bed9
LP		 1871static const struct v4l2_subdev_video_ops tvaudio_video_ops = {
1872 .s_std = tvaudio_s_std,
1873};
1874
64f70e7e
HV		 1875static const struct v4l2_subdev_ops tvaudio_ops = {
1876 .core = &tvaudio_core_ops,
1877 .tuner = &tvaudio_tuner_ops,
1878 .audio = &tvaudio_audio_ops,
8774bed9 1879 .video = &tvaudio_video_ops,
64f70e7e
HV		 1880};
1881
1882/* ----------------------------------------------------------------------- */
1883
1884
1885/* i2c registration */
1886
1887static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1888{
1889 struct CHIPSTATE *chip;
1890 struct CHIPDESC *desc;
1891 struct v4l2_subdev *sd;
1892
1893 if (debug) {
1894 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1895 printk(KERN_INFO "tvaudio: known chips: ");
1896 for (desc = chiplist; desc->name != NULL; desc++)
1897 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1898 printk("\n");
2474ed44 1899 }
1da177e4 1900
c02b211d 1901 chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
64f70e7e
HV		 1902 if (!chip)
1903 return -ENOMEM;
1904 sd = &chip->sd;
1905 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
8a854284 1906
64f70e7e
HV		 1907 /* find description for the chip */
1908 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1909 for (desc = chiplist; desc->name != NULL; desc++) {
1910 if (0 == *(desc->insmodopt))
1911 continue;
1912 if (client->addr < desc->addr_lo ||
1913 client->addr > desc->addr_hi)
1914 continue;
1915 if (desc->checkit && !desc->checkit(chip))
1916 continue;
1da177e4
LT		 1917 break;
1918 }
64f70e7e
HV		 1919 if (desc->name == NULL) {
1920 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
64f70e7e
HV		 1921 return -EIO;
1922 }
1923 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1924 if (desc->flags) {
1925 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1926 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1927 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1928 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1929 }
8a854284 1930
64f70e7e
HV		 1931 /* fill required data structures */
1932 if (!id)
1933 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1934 chip->desc = desc;
1935 chip->shadow.count = desc->registers+1;
1936 chip->prevmode = -1;
1937 chip->audmode = V4L2_TUNER_MODE_LANG1;
8a854284 1938
64f70e7e
HV		 1939 /* initialization */
1940 if (desc->initialize != NULL)
1941 desc->initialize(chip);
1942 else
1943 chip_cmd(chip, "init", &desc->init);
8a854284 1944
c9114031
HV		 1945 v4l2_ctrl_handler_init(&chip->hdl, 5);
1946 if (desc->flags & CHIP_HAS_INPUTSEL)
1947 v4l2_ctrl_new_std(&chip->hdl, &tvaudio_ctrl_ops,
1948 V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
64f70e7e
HV		 1949 if (desc->flags & CHIP_HAS_VOLUME) {
1950 if (!desc->volfunc) {
1951 /* This shouldn't be happen. Warn user, but keep working
1952 without volume controls
1953 */
1954 v4l2_info(sd, "volume callback undefined!\n");
1955 desc->flags &= ~CHIP_HAS_VOLUME;
1956 } else {
c9114031
HV		 1957 chip->volume = v4l2_ctrl_new_std(&chip->hdl,
1958 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
1959 0, 65535, 65535 / 100,
1960 desc->volinit ? desc->volinit : 65535);
1961 chip->balance = v4l2_ctrl_new_std(&chip->hdl,
1962 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BALANCE,
1963 0, 65535, 65535 / 100, 32768);
1964 v4l2_ctrl_cluster(2, &chip->volume);
64f70e7e 1965 }
8a854284 1966 }
64f70e7e
HV		 1967 if (desc->flags & CHIP_HAS_BASSTREBLE) {
1968 if (!desc->bassfunc || !desc->treblefunc) {
1969 /* This shouldn't be happen. Warn user, but keep working
1970 without bass/treble controls
1971 */
1972 v4l2_info(sd, "bass/treble callbacks undefined!\n");
1973 desc->flags &= ~CHIP_HAS_BASSTREBLE;
1974 } else {
c9114031
HV		 1975 v4l2_ctrl_new_std(&chip->hdl,
1976 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BASS,
1977 0, 65535, 65535 / 100,
1978 desc->bassinit ? desc->bassinit : 32768);
1979 v4l2_ctrl_new_std(&chip->hdl,
1980 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_TREBLE,
1981 0, 65535, 65535 / 100,
1982 desc->trebleinit ? desc->trebleinit : 32768);
1da177e4 1983 }
64f70e7e 1984 }
74cab31c 1985
c9114031
HV		 1986 sd->ctrl_handler = &chip->hdl;
1987 if (chip->hdl.error) {
1988 int err = chip->hdl.error;
1989
1990 v4l2_ctrl_handler_free(&chip->hdl);
c9114031
HV		 1991 return err;
1992 }
1993 /* set controls to the default values */
1994 v4l2_ctrl_handler_setup(&chip->hdl);
1995
64f70e7e 1996 chip->thread = NULL;
e4129a9c 1997 init_timer(&chip->wt);
64f70e7e 1998 if (desc->flags & CHIP_NEED_CHECKMODE) {
7bcfdf0f 1999 if (!desc->getrxsubchans || !desc->setaudmode) {
64f70e7e
HV		 2000 /* This shouldn't be happen. Warn user, but keep working
2001 without kthread
2002 */
2003 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2004 return 0;
2005 }
2006 /* start async thread */
64f70e7e
HV		 2007 chip->wt.function = chip_thread_wake;
2008 chip->wt.data = (unsigned long)chip;
f170168b
KC		 2009 chip->thread = kthread_run(chip_thread, chip, "%s",
2010 client->name);
64f70e7e
HV		 2011 if (IS_ERR(chip->thread)) {
2012 v4l2_warn(sd, "failed to create kthread\n");
2013 chip->thread = NULL;
2014 }
1da177e4
LT		 2015 }
2016 return 0;
2017}
2018
64f70e7e
HV		 2019static int tvaudio_remove(struct i2c_client *client)
2020{
2021 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2022 struct CHIPSTATE *chip = to_state(sd);
2023
2024 del_timer_sync(&chip->wt);
2025 if (chip->thread) {
2026 /* shutdown async thread */
2027 kthread_stop(chip->thread);
2028 chip->thread = NULL;
2029 }
2030
2031 v4l2_device_unregister_subdev(sd);
c9114031 2032 v4l2_ctrl_handler_free(&chip->hdl);
64f70e7e
HV		 2033 return 0;
2034}
2035
ae429083
JD		 2036/* This driver supports many devices and the idea is to let the driver
2037 detect which device is present. So rather than listing all supported
2038 devices here, we pretend to support a single, fake device type. */
64f70e7e 2039static const struct i2c_device_id tvaudio_id[] = {
ae429083
JD		 2040 { "tvaudio", 0 },
2041 { }
2042};
64f70e7e 2043MODULE_DEVICE_TABLE(i2c, tvaudio_id);
ae429083 2044
7a004d13
HV		 2045static struct i2c_driver tvaudio_driver = {
2046 .driver = {
7a004d13
HV		 2047 .name = "tvaudio",
2048 },
2049 .probe = tvaudio_probe,
2050 .remove = tvaudio_remove,
2051 .id_table = tvaudio_id,
08e14054 2052};
7a004d13 2053
c6e8d86f 2054module_i2c_driver(tvaudio_driver);
Linux kernel - Deliverables
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