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[media] bttv: there may be multiple tvaudio/tda7432 devices
[deliverable/linux.git] / drivers / media / i2c / tvaudio.c
CommitLineData
1da177e4 1/*
b4ab114c 2 * Driver for simple i2c audio chips.
1da177e4
LT		 3 *
4 * Copyright (c) 2000 Gerd Knorr
5 * based on code by:
6 * Eric Sandeen (eric_sandeen@bigfoot.com)
7 * Steve VanDeBogart (vandebo@uclink.berkeley.edu)
8 * Greg Alexander (galexand@acm.org)
9 *
6a3ca5f5
HV		 10 * For the TDA9875 part:
11 * Copyright (c) 2000 Guillaume Delvit based on Gerd Knorr source
12 * and Eric Sandeen
13 *
b4ab114c
MCC		 14 * Copyright(c) 2005-2008 Mauro Carvalho Chehab
15 * - Some cleanups, code fixes, etc
16 * - Convert it to V4L2 API
17 *
1da177e4
LT		 18 * This code is placed under the terms of the GNU General Public License
19 *
20 * OPTIONS:
21 * debug - set to 1 if you'd like to see debug messages
22 *
23 */
24
1da177e4 25#include <linux/module.h>
1da177e4
LT		 26#include <linux/kernel.h>
27#include <linux/sched.h>
28#include <linux/string.h>
29#include <linux/timer.h>
30#include <linux/delay.h>
31#include <linux/errno.h>
32#include <linux/slab.h>
7f6adeaf 33#include <linux/videodev2.h>
1da177e4 34#include <linux/i2c.h>
1da177e4 35#include <linux/init.h>
bc282879 36#include <linux/kthread.h>
7dfb7103 37#include <linux/freezer.h>
1da177e4 38
8bf2f8e7 39#include <media/tvaudio.h>
64f70e7e 40#include <media/v4l2-device.h>
74cab31c 41#include <media/v4l2-chip-ident.h>
c9114031 42#include <media/v4l2-ctrls.h>
1da177e4 43
7c9b5048 44#include <media/i2c-addr.h>
1da177e4
LT		 45
46/* ---------------------------------------------------------------------- */
47/* insmod args */
48
ff699e6b 49static int debug; /* insmod parameter */
1da177e4
LT		 50module_param(debug, int, 0644);
51
52MODULE_DESCRIPTION("device driver for various i2c TV sound decoder / audiomux chips");
53MODULE_AUTHOR("Eric Sandeen, Steve VanDeBogart, Greg Alexander, Gerd Knorr");
54MODULE_LICENSE("GPL");
55
56#define UNSET (-1U)
18fc59e2 57
1da177e4
LT		 58/* ---------------------------------------------------------------------- */
59/* our structs */
60
4c6c390e 61#define MAXREGS 256
1da177e4
LT		 62
63struct CHIPSTATE;
64typedef int (*getvalue)(int);
65typedef int (*checkit)(struct CHIPSTATE*);
66typedef int (*initialize)(struct CHIPSTATE*);
7bcfdf0f
DG		 67typedef int (*getrxsubchans)(struct CHIPSTATE *);
68typedef void (*setaudmode)(struct CHIPSTATE*, int mode);
1da177e4
LT		 69
70/* i2c command */
71typedef struct AUDIOCMD {
72 int count; /* # of bytes to send */
73 unsigned char bytes[MAXREGS+1]; /* addr, data, data, ... */
74} audiocmd;
75
76/* chip description */
77struct CHIPDESC {
78 char *name; /* chip name */
1da177e4
LT		 79 int addr_lo, addr_hi; /* i2c address range */
80 int registers; /* # of registers */
81
82 int *insmodopt;
83 checkit checkit;
84 initialize initialize;
85 int flags;
86#define CHIP_HAS_VOLUME 1
87#define CHIP_HAS_BASSTREBLE 2
88#define CHIP_HAS_INPUTSEL 4
dd03e970 89#define CHIP_NEED_CHECKMODE 8
1da177e4
LT		 90
91 /* various i2c command sequences */
92 audiocmd init;
93
94 /* which register has which value */
c9114031 95 int leftreg, rightreg, treblereg, bassreg;
1da177e4 96
a346caac
HV		 97 /* initialize with (defaults to 65535/32768/32768 */
98 int volinit, trebleinit, bassinit;
1da177e4
LT		 99
100 /* functions to convert the values (v4l -> chip) */
c9114031 101 getvalue volfunc, treblefunc, bassfunc;
1da177e4
LT		 102
103 /* get/set mode */
7bcfdf0f
DG		 104 getrxsubchans getrxsubchans;
105 setaudmode setaudmode;
1da177e4 106
1da177e4
LT		 107 /* input switch register + values for v4l inputs */
108 int inputreg;
8bf2f8e7 109 int inputmap[4];
1da177e4
LT		 110 int inputmute;
111 int inputmask;
112};
1da177e4
LT		 113
114/* current state of the chip */
115struct CHIPSTATE {
64f70e7e 116 struct v4l2_subdev sd;
c9114031
HV		 117 struct v4l2_ctrl_handler hdl;
118 struct {
119 /* volume/balance cluster */
120 struct v4l2_ctrl *volume;
121 struct v4l2_ctrl *balance;
122 };
1da177e4 123
81cb5c4f
MCC		 124 /* chip-specific description - should point to
125 an entry at CHIPDESC table */
126 struct CHIPDESC *desc;
1da177e4
LT		 127
128 /* shadow register set */
129 audiocmd shadow;
130
131 /* current settings */
c9114031 132 u16 muted;
1da177e4 133 int prevmode;
8a854284 134 int radio;
8bf2f8e7 135 int input;
1da177e4
LT		 136
137 /* thread */
bc282879 138 struct task_struct *thread;
1da177e4 139 struct timer_list wt;
8a4b275f 140 int audmode;
1da177e4
LT		 141};
142
64f70e7e
HV		 143static inline struct CHIPSTATE *to_state(struct v4l2_subdev *sd)
144{
145 return container_of(sd, struct CHIPSTATE, sd);
146}
147
c9114031
HV		 148static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
149{
150 return &container_of(ctrl->handler, struct CHIPSTATE, hdl)->sd;
151}
152
1da177e4 153
1da177e4
LT		 154/* ---------------------------------------------------------------------- */
155/* i2c I/O functions */
156
157static int chip_write(struct CHIPSTATE *chip, int subaddr, int val)
158{
64f70e7e
HV		 159 struct v4l2_subdev *sd = &chip->sd;
160 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 161 unsigned char buffer[2];
162
49426437 163 if (subaddr < 0) {
64f70e7e 164 v4l2_dbg(1, debug, sd, "chip_write: 0x%x\n", val);
1da177e4
LT		 165 chip->shadow.bytes[1] = val;
166 buffer[0] = val;
64f70e7e
HV		 167 if (1 != i2c_master_send(c, buffer, 1)) {
168 v4l2_warn(sd, "I/O error (write 0x%x)\n", val);
1da177e4
LT		 169 return -1;
170 }
171 } else {
49426437 172 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 173 v4l2_info(sd,
49426437
MCC		 174 "Tried to access a non-existent register: %d\n",
175 subaddr);
176 return -EINVAL;
177 }
178
64f70e7e
HV		 179 v4l2_dbg(1, debug, sd, "chip_write: reg%d=0x%x\n",
180 subaddr, val);
1da177e4
LT		 181 chip->shadow.bytes[subaddr+1] = val;
182 buffer[0] = subaddr;
183 buffer[1] = val;
64f70e7e
HV		 184 if (2 != i2c_master_send(c, buffer, 2)) {
185 v4l2_warn(sd, "I/O error (write reg%d=0x%x)\n",
186 subaddr, val);
1da177e4
LT		 187 return -1;
188 }
189 }
190 return 0;
191}
192
49426437
MCC		 193static int chip_write_masked(struct CHIPSTATE *chip,
194 int subaddr, int val, int mask)
1da177e4 195{
64f70e7e
HV		 196 struct v4l2_subdev *sd = &chip->sd;
197
1da177e4 198 if (mask != 0) {
49426437 199 if (subaddr < 0) {
1da177e4
LT		 200 val = (chip->shadow.bytes[1] & ~mask) | (val & mask);
201 } else {
49426437 202 if (subaddr + 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 203 v4l2_info(sd,
49426437
MCC		 204 "Tried to access a non-existent register: %d\n",
205 subaddr);
206 return -EINVAL;
207 }
208
1da177e4
LT		 209 val = (chip->shadow.bytes[subaddr+1] & ~mask) | (val & mask);
210 }
211 }
212 return chip_write(chip, subaddr, val);
213}
214
215static int chip_read(struct CHIPSTATE *chip)
216{
64f70e7e
HV		 217 struct v4l2_subdev *sd = &chip->sd;
218 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 219 unsigned char buffer;
220
64f70e7e
HV		 221 if (1 != i2c_master_recv(c, &buffer, 1)) {
222 v4l2_warn(sd, "I/O error (read)\n");
1da177e4
LT		 223 return -1;
224 }
64f70e7e 225 v4l2_dbg(1, debug, sd, "chip_read: 0x%x\n", buffer);
1da177e4
LT		 226 return buffer;
227}
228
229static int chip_read2(struct CHIPSTATE *chip, int subaddr)
230{
64f70e7e
HV		 231 struct v4l2_subdev *sd = &chip->sd;
232 struct i2c_client *c = v4l2_get_subdevdata(sd);
18fc59e2
MCC		 233 unsigned char write[1];
234 unsigned char read[1];
235 struct i2c_msg msgs[2] = {
752d283a
S		 236 {
237 .addr = c->addr,
238 .len = 1,
239 .buf = write
240 },
241 {
242 .addr = c->addr,
243 .flags = I2C_M_RD,
244 .len = 1,
245 .buf = read
246 }
18fc59e2 247 };
64f70e7e 248
18fc59e2 249 write[0] = subaddr;
1da177e4 250
64f70e7e
HV		 251 if (2 != i2c_transfer(c->adapter, msgs, 2)) {
252 v4l2_warn(sd, "I/O error (read2)\n");
1da177e4
LT		 253 return -1;
254 }
64f70e7e
HV		 255 v4l2_dbg(1, debug, sd, "chip_read2: reg%d=0x%x\n",
256 subaddr, read[0]);
1da177e4
LT		 257 return read[0];
258}
259
260static int chip_cmd(struct CHIPSTATE *chip, char *name, audiocmd *cmd)
261{
64f70e7e
HV		 262 struct v4l2_subdev *sd = &chip->sd;
263 struct i2c_client *c = v4l2_get_subdevdata(sd);
1da177e4
LT		 264 int i;
265
266 if (0 == cmd->count)
267 return 0;
268
49426437 269 if (cmd->count + cmd->bytes[0] - 1 >= ARRAY_SIZE(chip->shadow.bytes)) {
64f70e7e 270 v4l2_info(sd,
49426437
MCC		 271 "Tried to access a non-existent register range: %d to %d\n",
272 cmd->bytes[0] + 1, cmd->bytes[0] + cmd->count - 1);
273 return -EINVAL;
274 }
275
276 /* FIXME: it seems that the shadow bytes are wrong bellow !*/
277
1da177e4 278 /* update our shadow register set; print bytes if (debug > 0) */
64f70e7e
HV		 279 v4l2_dbg(1, debug, sd, "chip_cmd(%s): reg=%d, data:",
280 name, cmd->bytes[0]);
1da177e4 281 for (i = 1; i < cmd->count; i++) {
18fc59e2 282 if (debug)
64f70e7e 283 printk(KERN_CONT " 0x%x", cmd->bytes[i]);
1da177e4
LT		 284 chip->shadow.bytes[i+cmd->bytes[0]] = cmd->bytes[i];
285 }
18fc59e2 286 if (debug)
64f70e7e 287 printk(KERN_CONT "\n");
1da177e4
LT		 288
289 /* send data to the chip */
64f70e7e
HV		 290 if (cmd->count != i2c_master_send(c, cmd->bytes, cmd->count)) {
291 v4l2_warn(sd, "I/O error (%s)\n", name);
1da177e4
LT		 292 return -1;
293 }
294 return 0;
295}
296
297/* ---------------------------------------------------------------------- */
298/* kernel thread for doing i2c stuff asyncronly
299 * right now it is used only to check the audio mode (mono/stereo/whatever)
300 * some time after switching to another TV channel, then turn on stereo
301 * if available, ...
302 */
303
304static void chip_thread_wake(unsigned long data)
305{
18fc59e2 306 struct CHIPSTATE *chip = (struct CHIPSTATE*)data;
bc282879 307 wake_up_process(chip->thread);
1da177e4
LT		 308}
309
310static int chip_thread(void *data)
311{
18fc59e2 312 struct CHIPSTATE *chip = data;
81cb5c4f 313 struct CHIPDESC *desc = chip->desc;
64f70e7e 314 struct v4l2_subdev *sd = &chip->sd;
e21adca8 315 int mode, selected;
1da177e4 316
64f70e7e 317 v4l2_dbg(1, debug, sd, "thread started\n");
83144186 318 set_freezable();
1da177e4 319 for (;;) {
bc282879
CLG		 320 set_current_state(TASK_INTERRUPTIBLE);
321 if (!kthread_should_stop())
1da177e4 322 schedule();
bc282879 323 set_current_state(TASK_RUNNING);
5e50e7a9 324 try_to_freeze();
bc282879 325 if (kthread_should_stop())
1da177e4 326 break;
64f70e7e 327 v4l2_dbg(1, debug, sd, "thread wakeup\n");
1da177e4 328
e21adca8
DG		 329 /* don't do anything for radio */
330 if (chip->radio)
1da177e4
LT		 331 continue;
332
333 /* have a look what's going on */
7bcfdf0f 334 mode = desc->getrxsubchans(chip);
dd03e970
MCC		 335 if (mode == chip->prevmode)
336 continue;
337
338 /* chip detected a new audio mode - set it */
64f70e7e 339 v4l2_dbg(1, debug, sd, "thread checkmode\n");
dd03e970
MCC		 340
341 chip->prevmode = mode;
342
e21adca8
DG		 343 selected = V4L2_TUNER_MODE_MONO;
344 switch (chip->audmode) {
345 case V4L2_TUNER_MODE_MONO:
346 if (mode & V4L2_TUNER_SUB_LANG1)
347 selected = V4L2_TUNER_MODE_LANG1;
348 break;
349 case V4L2_TUNER_MODE_STEREO:
350 case V4L2_TUNER_MODE_LANG1:
351 if (mode & V4L2_TUNER_SUB_LANG1)
352 selected = V4L2_TUNER_MODE_LANG1;
353 else if (mode & V4L2_TUNER_SUB_STEREO)
354 selected = V4L2_TUNER_MODE_STEREO;
355 break;
356 case V4L2_TUNER_MODE_LANG2:
357 if (mode & V4L2_TUNER_SUB_LANG2)
358 selected = V4L2_TUNER_MODE_LANG2;
359 else if (mode & V4L2_TUNER_SUB_STEREO)
360 selected = V4L2_TUNER_MODE_STEREO;
361 break;
9e019e07
DG		 362 case V4L2_TUNER_MODE_LANG1_LANG2:
363 if (mode & V4L2_TUNER_SUB_LANG2)
364 selected = V4L2_TUNER_MODE_LANG1_LANG2;
365 else if (mode & V4L2_TUNER_SUB_STEREO)
366 selected = V4L2_TUNER_MODE_STEREO;
e21adca8 367 }
7bcfdf0f 368 desc->setaudmode(chip, selected);
1da177e4
LT		 369
370 /* schedule next check */
09df5cbe 371 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
1da177e4
LT		 372 }
373
64f70e7e 374 v4l2_dbg(1, debug, sd, "thread exiting\n");
1da177e4
LT		 375 return 0;
376}
377
1da177e4
LT		 378/* ---------------------------------------------------------------------- */
379/* audio chip descriptions - defines+functions for tda9840 */
380
381#define TDA9840_SW 0x00
382#define TDA9840_LVADJ 0x02
383#define TDA9840_STADJ 0x03
384#define TDA9840_TEST 0x04
385
386#define TDA9840_MONO 0x10
387#define TDA9840_STEREO 0x2a
388#define TDA9840_DUALA 0x12
389#define TDA9840_DUALB 0x1e
390#define TDA9840_DUALAB 0x1a
391#define TDA9840_DUALBA 0x16
392#define TDA9840_EXTERNAL 0x7a
393
394#define TDA9840_DS_DUAL 0x20 /* Dual sound identified */
395#define TDA9840_ST_STEREO 0x40 /* Stereo sound identified */
396#define TDA9840_PONRES 0x80 /* Power-on reset detected if = 1 */
397
398#define TDA9840_TEST_INT1SN 0x1 /* Integration time 0.5s when set */
399#define TDA9840_TEST_INTFU 0x02 /* Disables integrator function */
400
7bcfdf0f 401static int tda9840_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 402{
64f70e7e 403 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 404 int val, mode;
405
406 val = chip_read(chip);
3322a59e 407 mode = V4L2_TUNER_SUB_MONO;
1da177e4 408 if (val & TDA9840_DS_DUAL)
3322a59e 409 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4 410 if (val & TDA9840_ST_STEREO)
1884e298 411 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 412
7bcfdf0f
DG		 413 v4l2_dbg(1, debug, sd,
414 "tda9840_getrxsubchans(): raw chip read: %d, return: %d\n",
18fc59e2 415 val, mode);
1da177e4
LT		 416 return mode;
417}
418
7bcfdf0f 419static void tda9840_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4
LT		 420{
421 int update = 1;
422 int t = chip->shadow.bytes[TDA9840_SW + 1] & ~0x7e;
423
424 switch (mode) {
dc3d75da 425 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 426 t |= TDA9840_MONO;
427 break;
dc3d75da 428 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 429 t |= TDA9840_STEREO;
430 break;
dc3d75da 431 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 432 t |= TDA9840_DUALA;
433 break;
dc3d75da 434 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 435 t |= TDA9840_DUALB;
436 break;
9e019e07
DG		 437 case V4L2_TUNER_MODE_LANG1_LANG2:
438 t |= TDA9840_DUALAB;
439 break;
1da177e4
LT		 440 default:
441 update = 0;
442 }
443
444 if (update)
445 chip_write(chip, TDA9840_SW, t);
446}
447
94f9e56e
HV		 448static int tda9840_checkit(struct CHIPSTATE *chip)
449{
450 int rc;
451 rc = chip_read(chip);
452 /* lower 5 bits should be 0 */
453 return ((rc & 0x1f) == 0) ? 1 : 0;
454}
455
1da177e4
LT		 456/* ---------------------------------------------------------------------- */
457/* audio chip descriptions - defines+functions for tda985x */
458
459/* subaddresses for TDA9855 */
460#define TDA9855_VR 0x00 /* Volume, right */
461#define TDA9855_VL 0x01 /* Volume, left */
462#define TDA9855_BA 0x02 /* Bass */
463#define TDA9855_TR 0x03 /* Treble */
464#define TDA9855_SW 0x04 /* Subwoofer - not connected on DTV2000 */
465
466/* subaddresses for TDA9850 */
467#define TDA9850_C4 0x04 /* Control 1 for TDA9850 */
468
469/* subaddesses for both chips */
470#define TDA985x_C5 0x05 /* Control 2 for TDA9850, Control 1 for TDA9855 */
471#define TDA985x_C6 0x06 /* Control 3 for TDA9850, Control 2 for TDA9855 */
472#define TDA985x_C7 0x07 /* Control 4 for TDA9850, Control 3 for TDA9855 */
473#define TDA985x_A1 0x08 /* Alignment 1 for both chips */
474#define TDA985x_A2 0x09 /* Alignment 2 for both chips */
475#define TDA985x_A3 0x0a /* Alignment 3 for both chips */
476
477/* Masks for bits in TDA9855 subaddresses */
478/* 0x00 - VR in TDA9855 */
479/* 0x01 - VL in TDA9855 */
480/* lower 7 bits control gain from -71dB (0x28) to 16dB (0x7f)
481 * in 1dB steps - mute is 0x27 */
482
483
484/* 0x02 - BA in TDA9855 */
485/* lower 5 bits control bass gain from -12dB (0x06) to 16.5dB (0x19)
486 * in .5dB steps - 0 is 0x0E */
487
488
489/* 0x03 - TR in TDA9855 */
490/* 4 bits << 1 control treble gain from -12dB (0x3) to 12dB (0xb)
491 * in 3dB steps - 0 is 0x7 */
492
493/* Masks for bits in both chips' subaddresses */
494/* 0x04 - SW in TDA9855, C4/Control 1 in TDA9850 */
495/* Unique to TDA9855: */
496/* 4 bits << 2 control subwoofer/surround gain from -14db (0x1) to 14db (0xf)
497 * in 3dB steps - mute is 0x0 */
498
499/* Unique to TDA9850: */
500/* lower 4 bits control stereo noise threshold, over which stereo turns off
501 * set to values of 0x00 through 0x0f for Ster1 through Ster16 */
502
503
504/* 0x05 - C5 - Control 1 in TDA9855 , Control 2 in TDA9850*/
505/* Unique to TDA9855: */
506#define TDA9855_MUTE 1<<7 /* GMU, Mute at outputs */
507#define TDA9855_AVL 1<<6 /* AVL, Automatic Volume Level */
508#define TDA9855_LOUD 1<<5 /* Loudness, 1==off */
509#define TDA9855_SUR 1<<3 /* Surround / Subwoofer 1==.5(L-R) 0==.5(L+R) */
510 /* Bits 0 to 3 select various combinations
4ac97914
MCC		 511 * of line in and line out, only the
512 * interesting ones are defined */
1da177e4
LT		 513#define TDA9855_EXT 1<<2 /* Selects inputs LIR and LIL. Pins 41 & 12 */
514#define TDA9855_INT 0 /* Selects inputs LOR and LOL. (internal) */
515
516/* Unique to TDA9850: */
517/* lower 4 bits contol SAP noise threshold, over which SAP turns off
518 * set to values of 0x00 through 0x0f for SAP1 through SAP16 */
519
520
521/* 0x06 - C6 - Control 2 in TDA9855, Control 3 in TDA9850 */
522/* Common to TDA9855 and TDA9850: */
523#define TDA985x_SAP 3<<6 /* Selects SAP output, mute if not received */
9e019e07 524#define TDA985x_MONOSAP 2<<6 /* Selects Mono on left, SAP on right */
1da177e4
LT		 525#define TDA985x_STEREO 1<<6 /* Selects Stereo ouput, mono if not received */
526#define TDA985x_MONO 0 /* Forces Mono output */
527#define TDA985x_LMU 1<<3 /* Mute (LOR/LOL for 9855, OUTL/OUTR for 9850) */
528
529/* Unique to TDA9855: */
530#define TDA9855_TZCM 1<<5 /* If set, don't mute till zero crossing */
531#define TDA9855_VZCM 1<<4 /* If set, don't change volume till zero crossing*/
532#define TDA9855_LINEAR 0 /* Linear Stereo */
533#define TDA9855_PSEUDO 1 /* Pseudo Stereo */
534#define TDA9855_SPAT_30 2 /* Spatial Stereo, 30% anti-phase crosstalk */
535#define TDA9855_SPAT_50 3 /* Spatial Stereo, 52% anti-phase crosstalk */
536#define TDA9855_E_MONO 7 /* Forced mono - mono select elseware, so useless*/
537
538/* 0x07 - C7 - Control 3 in TDA9855, Control 4 in TDA9850 */
539/* Common to both TDA9855 and TDA9850: */
540/* lower 4 bits control input gain from -3.5dB (0x0) to 4dB (0xF)
541 * in .5dB steps - 0dB is 0x7 */
542
543/* 0x08, 0x09 - A1 and A2 (read/write) */
544/* Common to both TDA9855 and TDA9850: */
545/* lower 5 bites are wideband and spectral expander alignment
546 * from 0x00 to 0x1f - nominal at 0x0f and 0x10 (read/write) */
547#define TDA985x_STP 1<<5 /* Stereo Pilot/detect (read-only) */
548#define TDA985x_SAPP 1<<6 /* SAP Pilot/detect (read-only) */
549#define TDA985x_STS 1<<7 /* Stereo trigger 1= <35mV 0= <30mV (write-only)*/
550
551/* 0x0a - A3 */
552/* Common to both TDA9855 and TDA9850: */
553/* lower 3 bits control timing current for alignment: -30% (0x0), -20% (0x1),
554 * -10% (0x2), nominal (0x3), +10% (0x6), +20% (0x5), +30% (0x4) */
555#define TDA985x_ADJ 1<<7 /* Stereo adjust on/off (wideband and spectral */
556
557static int tda9855_volume(int val) { return val/0x2e8+0x27; }
558static int tda9855_bass(int val) { return val/0xccc+0x06; }
559static int tda9855_treble(int val) { return (val/0x1c71+0x3)<<1; }
560
7bcfdf0f 561static int tda985x_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 562{
3322a59e 563 int mode, val;
1da177e4 564
1da177e4
LT		 565 /* Add mono mode regardless of SAP and stereo */
566 /* Allows forced mono */
3322a59e
DG		 567 mode = V4L2_TUNER_SUB_MONO;
568 val = chip_read(chip);
569 if (val & TDA985x_STP)
1884e298 570 mode = V4L2_TUNER_SUB_STEREO;
3322a59e
DG		 571 if (val & TDA985x_SAPP)
572 mode |= V4L2_TUNER_SUB_SAP;
573 return mode;
1da177e4
LT		 574}
575
7bcfdf0f 576static void tda985x_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4
LT		 577{
578 int update = 1;
579 int c6 = chip->shadow.bytes[TDA985x_C6+1] & 0x3f;
580
581 switch (mode) {
dc3d75da 582 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 583 c6 |= TDA985x_MONO;
584 break;
dc3d75da 585 case V4L2_TUNER_MODE_STEREO:
00fb1850 586 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 587 c6 |= TDA985x_STEREO;
588 break;
00fb1850 589 case V4L2_TUNER_MODE_SAP:
1da177e4
LT		 590 c6 |= TDA985x_SAP;
591 break;
9e019e07
DG		 592 case V4L2_TUNER_MODE_LANG1_LANG2:
593 c6 |= TDA985x_MONOSAP;
594 break;
1da177e4
LT		 595 default:
596 update = 0;
597 }
598 if (update)
599 chip_write(chip,TDA985x_C6,c6);
600}
601
602
603/* ---------------------------------------------------------------------- */
604/* audio chip descriptions - defines+functions for tda9873h */
605
606/* Subaddresses for TDA9873H */
607
608#define TDA9873_SW 0x00 /* Switching */
609#define TDA9873_AD 0x01 /* Adjust */
610#define TDA9873_PT 0x02 /* Port */
611
612/* Subaddress 0x00: Switching Data
613 * B7..B0:
614 *
615 * B1, B0: Input source selection
616 * 0, 0 internal
617 * 1, 0 external stereo
618 * 0, 1 external mono
619 */
620#define TDA9873_INP_MASK 3
621#define TDA9873_INTERNAL 0
622#define TDA9873_EXT_STEREO 2
623#define TDA9873_EXT_MONO 1
624
625/* B3, B2: output signal select
626 * B4 : transmission mode
627 * 0, 0, 1 Mono
628 * 1, 0, 0 Stereo
629 * 1, 1, 1 Stereo (reversed channel)
630 * 0, 0, 0 Dual AB
631 * 0, 0, 1 Dual AA
632 * 0, 1, 0 Dual BB
633 * 0, 1, 1 Dual BA
634 */
635
636#define TDA9873_TR_MASK (7 << 2)
637#define TDA9873_TR_MONO 4
638#define TDA9873_TR_STEREO 1 << 4
d59a14e2 639#define TDA9873_TR_REVERSE ((1 << 3) | (1 << 2))
1da177e4
LT		 640#define TDA9873_TR_DUALA 1 << 2
641#define TDA9873_TR_DUALB 1 << 3
9e019e07 642#define TDA9873_TR_DUALAB 0
1da177e4
LT		 643
644/* output level controls
645 * B5: output level switch (0 = reduced gain, 1 = normal gain)
646 * B6: mute (1 = muted)
647 * B7: auto-mute (1 = auto-mute enabled)
648 */
649
650#define TDA9873_GAIN_NORMAL 1 << 5
651#define TDA9873_MUTE 1 << 6
652#define TDA9873_AUTOMUTE 1 << 7
653
654/* Subaddress 0x01: Adjust/standard */
655
656/* Lower 4 bits (C3..C0) control stereo adjustment on R channel (-0.6 - +0.7 dB)
657 * Recommended value is +0 dB
658 */
659
660#define TDA9873_STEREO_ADJ 0x06 /* 0dB gain */
661
662/* Bits C6..C4 control FM stantard
663 * C6, C5, C4
664 * 0, 0, 0 B/G (PAL FM)
665 * 0, 0, 1 M
666 * 0, 1, 0 D/K(1)
667 * 0, 1, 1 D/K(2)
668 * 1, 0, 0 D/K(3)
669 * 1, 0, 1 I
670 */
671#define TDA9873_BG 0
672#define TDA9873_M 1
673#define TDA9873_DK1 2
674#define TDA9873_DK2 3
675#define TDA9873_DK3 4
676#define TDA9873_I 5
677
678/* C7 controls identification response time (1=fast/0=normal)
679 */
680#define TDA9873_IDR_NORM 0
681#define TDA9873_IDR_FAST 1 << 7
682
683
684/* Subaddress 0x02: Port data */
685
686/* E1, E0 free programmable ports P1/P2
687 0, 0 both ports low
688 0, 1 P1 high
689 1, 0 P2 high
690 1, 1 both ports high
691*/
692
693#define TDA9873_PORTS 3
694
695/* E2: test port */
696#define TDA9873_TST_PORT 1 << 2
697
698/* E5..E3 control mono output channel (together with transmission mode bit B4)
699 *
700 * E5 E4 E3 B4 OUTM
701 * 0 0 0 0 mono
702 * 0 0 1 0 DUAL B
703 * 0 1 0 1 mono (from stereo decoder)
704 */
705#define TDA9873_MOUT_MONO 0
706#define TDA9873_MOUT_FMONO 0
707#define TDA9873_MOUT_DUALA 0
708#define TDA9873_MOUT_DUALB 1 << 3
709#define TDA9873_MOUT_ST 1 << 4
d59a14e2 710#define TDA9873_MOUT_EXTM ((1 << 4) | (1 << 3))
1da177e4 711#define TDA9873_MOUT_EXTL 1 << 5
d59a14e2
DG		 712#define TDA9873_MOUT_EXTR ((1 << 5) | (1 << 3))
713#define TDA9873_MOUT_EXTLR ((1 << 5) | (1 << 4))
714#define TDA9873_MOUT_MUTE ((1 << 5) | (1 << 4) | (1 << 3))
1da177e4
LT		 715
716/* Status bits: (chip read) */
717#define TDA9873_PONR 0 /* Power-on reset detected if = 1 */
718#define TDA9873_STEREO 2 /* Stereo sound is identified */
719#define TDA9873_DUAL 4 /* Dual sound is identified */
720
7bcfdf0f 721static int tda9873_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 722{
64f70e7e 723 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 724 int val,mode;
725
726 val = chip_read(chip);
3322a59e 727 mode = V4L2_TUNER_SUB_MONO;
1da177e4 728 if (val & TDA9873_STEREO)
1884e298 729 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 730 if (val & TDA9873_DUAL)
3322a59e 731 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
7bcfdf0f
DG		 732 v4l2_dbg(1, debug, sd,
733 "tda9873_getrxsubchans(): raw chip read: %d, return: %d\n",
18fc59e2 734 val, mode);
1da177e4
LT		 735 return mode;
736}
737
7bcfdf0f 738static void tda9873_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4 739{
64f70e7e 740 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 741 int sw_data = chip->shadow.bytes[TDA9873_SW+1] & ~ TDA9873_TR_MASK;
742 /* int adj_data = chip->shadow.bytes[TDA9873_AD+1] ; */
743
744 if ((sw_data & TDA9873_INP_MASK) != TDA9873_INTERNAL) {
7bcfdf0f
DG		 745 v4l2_dbg(1, debug, sd,
746 "tda9873_setaudmode(): external input\n");
1da177e4
LT		 747 return;
748 }
749
7bcfdf0f
DG		 750 v4l2_dbg(1, debug, sd,
751 "tda9873_setaudmode(): chip->shadow.bytes[%d] = %d\n",
752 TDA9873_SW+1, chip->shadow.bytes[TDA9873_SW+1]);
753 v4l2_dbg(1, debug, sd, "tda9873_setaudmode(): sw_data = %d\n",
754 sw_data);
1da177e4
LT		 755
756 switch (mode) {
dc3d75da 757 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 758 sw_data |= TDA9873_TR_MONO;
759 break;
dc3d75da 760 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 761 sw_data |= TDA9873_TR_STEREO;
762 break;
dc3d75da 763 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 764 sw_data |= TDA9873_TR_DUALA;
765 break;
dc3d75da 766 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 767 sw_data |= TDA9873_TR_DUALB;
768 break;
9e019e07
DG		 769 case V4L2_TUNER_MODE_LANG1_LANG2:
770 sw_data |= TDA9873_TR_DUALAB;
771 break;
1da177e4 772 default:
1da177e4
LT		 773 return;
774 }
775
776 chip_write(chip, TDA9873_SW, sw_data);
7bcfdf0f
DG		 777 v4l2_dbg(1, debug, sd,
778 "tda9873_setaudmode(): req. mode %d; chip_write: %d\n",
1da177e4
LT		 779 mode, sw_data);
780}
781
782static int tda9873_checkit(struct CHIPSTATE *chip)
783{
784 int rc;
785
786 if (-1 == (rc = chip_read2(chip,254)))
787 return 0;
788 return (rc & ~0x1f) == 0x80;
789}
790
791
792/* ---------------------------------------------------------------------- */
793/* audio chip description - defines+functions for tda9874h and tda9874a */
794/* Dariusz Kowalewski <darekk@automex.pl> */
795
796/* Subaddresses for TDA9874H and TDA9874A (slave rx) */
797#define TDA9874A_AGCGR 0x00 /* AGC gain */
798#define TDA9874A_GCONR 0x01 /* general config */
799#define TDA9874A_MSR 0x02 /* monitor select */
800#define TDA9874A_C1FRA 0x03 /* carrier 1 freq. */
801#define TDA9874A_C1FRB 0x04 /* carrier 1 freq. */
802#define TDA9874A_C1FRC 0x05 /* carrier 1 freq. */
803#define TDA9874A_C2FRA 0x06 /* carrier 2 freq. */
804#define TDA9874A_C2FRB 0x07 /* carrier 2 freq. */
805#define TDA9874A_C2FRC 0x08 /* carrier 2 freq. */
806#define TDA9874A_DCR 0x09 /* demodulator config */
807#define TDA9874A_FMER 0x0a /* FM de-emphasis */
808#define TDA9874A_FMMR 0x0b /* FM dematrix */
809#define TDA9874A_C1OLAR 0x0c /* ch.1 output level adj. */
810#define TDA9874A_C2OLAR 0x0d /* ch.2 output level adj. */
811#define TDA9874A_NCONR 0x0e /* NICAM config */
812#define TDA9874A_NOLAR 0x0f /* NICAM output level adj. */
813#define TDA9874A_NLELR 0x10 /* NICAM lower error limit */
814#define TDA9874A_NUELR 0x11 /* NICAM upper error limit */
815#define TDA9874A_AMCONR 0x12 /* audio mute control */
816#define TDA9874A_SDACOSR 0x13 /* stereo DAC output select */
817#define TDA9874A_AOSR 0x14 /* analog output select */
818#define TDA9874A_DAICONR 0x15 /* digital audio interface config */
819#define TDA9874A_I2SOSR 0x16 /* I2S-bus output select */
820#define TDA9874A_I2SOLAR 0x17 /* I2S-bus output level adj. */
821#define TDA9874A_MDACOSR 0x18 /* mono DAC output select (tda9874a) */
822#define TDA9874A_ESP 0xFF /* easy standard progr. (tda9874a) */
823
824/* Subaddresses for TDA9874H and TDA9874A (slave tx) */
825#define TDA9874A_DSR 0x00 /* device status */
826#define TDA9874A_NSR 0x01 /* NICAM status */
827#define TDA9874A_NECR 0x02 /* NICAM error count */
828#define TDA9874A_DR1 0x03 /* add. data LSB */
829#define TDA9874A_DR2 0x04 /* add. data MSB */
830#define TDA9874A_LLRA 0x05 /* monitor level read-out LSB */
831#define TDA9874A_LLRB 0x06 /* monitor level read-out MSB */
832#define TDA9874A_SIFLR 0x07 /* SIF level */
833#define TDA9874A_TR2 252 /* test reg. 2 */
834#define TDA9874A_TR1 253 /* test reg. 1 */
835#define TDA9874A_DIC 254 /* device id. code */
836#define TDA9874A_SIC 255 /* software id. code */
837
838
839static int tda9874a_mode = 1; /* 0: A2, 1: NICAM */
840static int tda9874a_GCONR = 0xc0; /* default config. input pin: SIFSEL=0 */
841static int tda9874a_NCONR = 0x01; /* default NICAM config.: AMSEL=0,AMUTE=1 */
842static int tda9874a_ESP = 0x07; /* default standard: NICAM D/K */
843static int tda9874a_dic = -1; /* device id. code */
844
845/* insmod options for tda9874a */
846static unsigned int tda9874a_SIF = UNSET;
847static unsigned int tda9874a_AMSEL = UNSET;
848static unsigned int tda9874a_STD = UNSET;
849module_param(tda9874a_SIF, int, 0444);
850module_param(tda9874a_AMSEL, int, 0444);
851module_param(tda9874a_STD, int, 0444);
852
853/*
854 * initialization table for tda9874 decoder:
855 * - carrier 1 freq. registers (3 bytes)
856 * - carrier 2 freq. registers (3 bytes)
857 * - demudulator config register
858 * - FM de-emphasis register (slow identification mode)
859 * Note: frequency registers must be written in single i2c transfer.
860 */
861static struct tda9874a_MODES {
862 char *name;
863 audiocmd cmd;
864} tda9874a_modelist[9] = {
04e6f990 865 { "A2, B/G", /* default */
1da177e4
LT		 866 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x77,0xA0,0x00, 0x00,0x00 }} },
867 { "A2, M (Korea)",
868 { 9, { TDA9874A_C1FRA, 0x5D,0xC0,0x00, 0x62,0x6A,0xAA, 0x20,0x22 }} },
869 { "A2, D/K (1)",
870 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x82,0x60,0x00, 0x00,0x00 }} },
871 { "A2, D/K (2)",
872 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x8C,0x75,0x55, 0x00,0x00 }} },
873 { "A2, D/K (3)",
874 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x77,0xA0,0x00, 0x00,0x00 }} },
875 { "NICAM, I",
876 { 9, { TDA9874A_C1FRA, 0x7D,0x00,0x00, 0x88,0x8A,0xAA, 0x08,0x33 }} },
877 { "NICAM, B/G",
878 { 9, { TDA9874A_C1FRA, 0x72,0x95,0x55, 0x79,0xEA,0xAA, 0x08,0x33 }} },
04e6f990 879 { "NICAM, D/K",
1da177e4
LT		 880 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x08,0x33 }} },
881 { "NICAM, L",
882 { 9, { TDA9874A_C1FRA, 0x87,0x6A,0xAA, 0x79,0xEA,0xAA, 0x09,0x33 }} }
883};
884
885static int tda9874a_setup(struct CHIPSTATE *chip)
886{
64f70e7e
HV		 887 struct v4l2_subdev *sd = &chip->sd;
888
1da177e4
LT		 889 chip_write(chip, TDA9874A_AGCGR, 0x00); /* 0 dB */
890 chip_write(chip, TDA9874A_GCONR, tda9874a_GCONR);
891 chip_write(chip, TDA9874A_MSR, (tda9874a_mode) ? 0x03:0x02);
892 if(tda9874a_dic == 0x11) {
893 chip_write(chip, TDA9874A_FMMR, 0x80);
894 } else { /* dic == 0x07 */
895 chip_cmd(chip,"tda9874_modelist",&tda9874a_modelist[tda9874a_STD].cmd);
896 chip_write(chip, TDA9874A_FMMR, 0x00);
897 }
898 chip_write(chip, TDA9874A_C1OLAR, 0x00); /* 0 dB */
899 chip_write(chip, TDA9874A_C2OLAR, 0x00); /* 0 dB */
900 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
901 chip_write(chip, TDA9874A_NOLAR, 0x00); /* 0 dB */
902 /* Note: If signal quality is poor you may want to change NICAM */
903 /* error limit registers (NLELR and NUELR) to some greater values. */
904 /* Then the sound would remain stereo, but won't be so clear. */
905 chip_write(chip, TDA9874A_NLELR, 0x14); /* default */
906 chip_write(chip, TDA9874A_NUELR, 0x50); /* default */
907
908 if(tda9874a_dic == 0x11) {
909 chip_write(chip, TDA9874A_AMCONR, 0xf9);
910 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
911 chip_write(chip, TDA9874A_AOSR, 0x80);
912 chip_write(chip, TDA9874A_MDACOSR, (tda9874a_mode) ? 0x82:0x80);
913 chip_write(chip, TDA9874A_ESP, tda9874a_ESP);
914 } else { /* dic == 0x07 */
915 chip_write(chip, TDA9874A_AMCONR, 0xfb);
916 chip_write(chip, TDA9874A_SDACOSR, (tda9874a_mode) ? 0x81:0x80);
18fc59e2 917 chip_write(chip, TDA9874A_AOSR, 0x00); /* or 0x10 */
1da177e4 918 }
64f70e7e 919 v4l2_dbg(1, debug, sd, "tda9874a_setup(): %s [0x%02X].\n",
1da177e4
LT		 920 tda9874a_modelist[tda9874a_STD].name,tda9874a_STD);
921 return 1;
922}
923
7bcfdf0f 924static int tda9874a_getrxsubchans(struct CHIPSTATE *chip)
1da177e4 925{
64f70e7e 926 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 927 int dsr,nsr,mode;
928 int necr; /* just for debugging */
929
3322a59e 930 mode = V4L2_TUNER_SUB_MONO;
1da177e4
LT		 931
932 if(-1 == (dsr = chip_read2(chip,TDA9874A_DSR)))
933 return mode;
934 if(-1 == (nsr = chip_read2(chip,TDA9874A_NSR)))
935 return mode;
936 if(-1 == (necr = chip_read2(chip,TDA9874A_NECR)))
937 return mode;
938
939 /* need to store dsr/nsr somewhere */
940 chip->shadow.bytes[MAXREGS-2] = dsr;
941 chip->shadow.bytes[MAXREGS-1] = nsr;
942
943 if(tda9874a_mode) {
944 /* Note: DSR.RSSF and DSR.AMSTAT bits are also checked.
945 * If NICAM auto-muting is enabled, DSR.AMSTAT=1 indicates
946 * that sound has (temporarily) switched from NICAM to
947 * mono FM (or AM) on 1st sound carrier due to high NICAM bit
948 * error count. So in fact there is no stereo in this case :-(
dc3d75da 949 * But changing the mode to V4L2_TUNER_MODE_MONO would switch
1da177e4
LT		 950 * external 4052 multiplexer in audio_hook().
951 */
1da177e4 952 if(nsr & 0x02) /* NSR.S/MB=1 */
1884e298 953 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 954 if(nsr & 0x01) /* NSR.D/SB=1 */
3322a59e 955 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4
LT		 956 } else {
957 if(dsr & 0x02) /* DSR.IDSTE=1 */
1884e298 958 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 959 if(dsr & 0x04) /* DSR.IDDUA=1 */
3322a59e 960 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4
LT		 961 }
962
7bcfdf0f
DG		 963 v4l2_dbg(1, debug, sd,
964 "tda9874a_getrxsubchans(): DSR=0x%X, NSR=0x%X, NECR=0x%X, return: %d.\n",
1da177e4
LT		 965 dsr, nsr, necr, mode);
966 return mode;
967}
968
7bcfdf0f 969static void tda9874a_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4 970{
64f70e7e
HV		 971 struct v4l2_subdev *sd = &chip->sd;
972
1da177e4
LT		 973 /* Disable/enable NICAM auto-muting (based on DSR.RSSF status bit). */
974 /* If auto-muting is disabled, we can hear a signal of degrading quality. */
64f70e7e 975 if (tda9874a_mode) {
1da177e4
LT		 976 if(chip->shadow.bytes[MAXREGS-2] & 0x20) /* DSR.RSSF=1 */
977 tda9874a_NCONR &= 0xfe; /* enable */
978 else
979 tda9874a_NCONR |= 0x01; /* disable */
980 chip_write(chip, TDA9874A_NCONR, tda9874a_NCONR);
981 }
982
983 /* Note: TDA9874A supports automatic FM dematrixing (FMMR register)
984 * and has auto-select function for audio output (AOSR register).
985 * Old TDA9874H doesn't support these features.
986 * TDA9874A also has additional mono output pin (OUTM), which
987 * on same (all?) tv-cards is not used, anyway (as well as MONOIN).
988 */
989 if(tda9874a_dic == 0x11) {
990 int aosr = 0x80;
991 int mdacosr = (tda9874a_mode) ? 0x82:0x80;
992
993 switch(mode) {
dc3d75da
MCC		 994 case V4L2_TUNER_MODE_MONO:
995 case V4L2_TUNER_MODE_STEREO:
1da177e4 996 break;
dc3d75da 997 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 998 aosr = 0x80; /* auto-select, dual A/A */
999 mdacosr = (tda9874a_mode) ? 0x82:0x80;
1000 break;
dc3d75da 1001 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1002 aosr = 0xa0; /* auto-select, dual B/B */
1003 mdacosr = (tda9874a_mode) ? 0x83:0x81;
1004 break;
9e019e07
DG		 1005 case V4L2_TUNER_MODE_LANG1_LANG2:
1006 aosr = 0x00; /* always route L to L and R to R */
1007 mdacosr = (tda9874a_mode) ? 0x82:0x80;
1008 break;
1da177e4 1009 default:
1da177e4
LT		 1010 return;
1011 }
1012 chip_write(chip, TDA9874A_AOSR, aosr);
1013 chip_write(chip, TDA9874A_MDACOSR, mdacosr);
1014
7bcfdf0f
DG		 1015 v4l2_dbg(1, debug, sd,
1016 "tda9874a_setaudmode(): req. mode %d; AOSR=0x%X, MDACOSR=0x%X.\n",
1da177e4
LT		 1017 mode, aosr, mdacosr);
1018
1019 } else { /* dic == 0x07 */
1020 int fmmr,aosr;
1021
1022 switch(mode) {
dc3d75da 1023 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1024 fmmr = 0x00; /* mono */
1025 aosr = 0x10; /* A/A */
1026 break;
dc3d75da 1027 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1028 if(tda9874a_mode) {
1029 fmmr = 0x00;
1030 aosr = 0x00; /* handled by NICAM auto-mute */
1031 } else {
1032 fmmr = (tda9874a_ESP == 1) ? 0x05 : 0x04; /* stereo */
1033 aosr = 0x00;
1034 }
1035 break;
dc3d75da 1036 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1037 fmmr = 0x02; /* dual */
1038 aosr = 0x10; /* dual A/A */
1039 break;
dc3d75da 1040 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1041 fmmr = 0x02; /* dual */
1042 aosr = 0x20; /* dual B/B */
1043 break;
9e019e07
DG		 1044 case V4L2_TUNER_MODE_LANG1_LANG2:
1045 fmmr = 0x02; /* dual */
1046 aosr = 0x00; /* dual A/B */
1047 break;
1da177e4 1048 default:
1da177e4
LT		 1049 return;
1050 }
1051 chip_write(chip, TDA9874A_FMMR, fmmr);
1052 chip_write(chip, TDA9874A_AOSR, aosr);
1053
7bcfdf0f
DG		 1054 v4l2_dbg(1, debug, sd,
1055 "tda9874a_setaudmode(): req. mode %d; FMMR=0x%X, AOSR=0x%X.\n",
1da177e4
LT		 1056 mode, fmmr, aosr);
1057 }
1058}
1059
1060static int tda9874a_checkit(struct CHIPSTATE *chip)
1061{
64f70e7e 1062 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1063 int dic,sic; /* device id. and software id. codes */
1064
1065 if(-1 == (dic = chip_read2(chip,TDA9874A_DIC)))
1066 return 0;
1067 if(-1 == (sic = chip_read2(chip,TDA9874A_SIC)))
1068 return 0;
1069
64f70e7e 1070 v4l2_dbg(1, debug, sd, "tda9874a_checkit(): DIC=0x%X, SIC=0x%X.\n", dic, sic);
1da177e4
LT		 1071
1072 if((dic == 0x11)||(dic == 0x07)) {
64f70e7e 1073 v4l2_info(sd, "found tda9874%s.\n", (dic == 0x11) ? "a" : "h");
1da177e4
LT		 1074 tda9874a_dic = dic; /* remember device id. */
1075 return 1;
1076 }
1077 return 0; /* not found */
1078}
1079
1080static int tda9874a_initialize(struct CHIPSTATE *chip)
1081{
1082 if (tda9874a_SIF > 2)
1083 tda9874a_SIF = 1;
04e6f990 1084 if (tda9874a_STD >= ARRAY_SIZE(tda9874a_modelist))
1da177e4
LT		 1085 tda9874a_STD = 0;
1086 if(tda9874a_AMSEL > 1)
1087 tda9874a_AMSEL = 0;
1088
1089 if(tda9874a_SIF == 1)
1090 tda9874a_GCONR = 0xc0; /* sound IF input 1 */
1091 else
1092 tda9874a_GCONR = 0xc1; /* sound IF input 2 */
1093
1094 tda9874a_ESP = tda9874a_STD;
1095 tda9874a_mode = (tda9874a_STD < 5) ? 0 : 1;
1096
1097 if(tda9874a_AMSEL == 0)
1098 tda9874a_NCONR = 0x01; /* auto-mute: analog mono input */
1099 else
1100 tda9874a_NCONR = 0x05; /* auto-mute: 1st carrier FM or AM */
1101
1102 tda9874a_setup(chip);
1103 return 0;
1104}
1105
411674fd
HV		 1106/* ---------------------------------------------------------------------- */
1107/* audio chip description - defines+functions for tda9875 */
1108/* The TDA9875 is made by Philips Semiconductor
1109 * http://www.semiconductors.philips.com
1110 * TDA9875: I2C-bus controlled DSP audio processor, FM demodulator
1111 *
1112 */
1113
1114/* subaddresses for TDA9875 */
1115#define TDA9875_MUT 0x12 /*General mute (value --> 0b11001100*/
1116#define TDA9875_CFG 0x01 /* Config register (value --> 0b00000000 */
1117#define TDA9875_DACOS 0x13 /*DAC i/o select (ADC) 0b0000100*/
1118#define TDA9875_LOSR 0x16 /*Line output select regirter 0b0100 0001*/
1119
1120#define TDA9875_CH1V 0x0c /*Channel 1 volume (mute)*/
1121#define TDA9875_CH2V 0x0d /*Channel 2 volume (mute)*/
1122#define TDA9875_SC1 0x14 /*SCART 1 in (mono)*/
1123#define TDA9875_SC2 0x15 /*SCART 2 in (mono)*/
1124
1125#define TDA9875_ADCIS 0x17 /*ADC input select (mono) 0b0110 000*/
1126#define TDA9875_AER 0x19 /*Audio effect (AVL+Pseudo) 0b0000 0110*/
1127#define TDA9875_MCS 0x18 /*Main channel select (DAC) 0b0000100*/
1128#define TDA9875_MVL 0x1a /* Main volume gauche */
1129#define TDA9875_MVR 0x1b /* Main volume droite */
1130#define TDA9875_MBA 0x1d /* Main Basse */
1131#define TDA9875_MTR 0x1e /* Main treble */
25985edc
LDM		 1132#define TDA9875_ACS 0x1f /* Auxiliary channel select (FM) 0b0000000*/
1133#define TDA9875_AVL 0x20 /* Auxiliary volume gauche */
1134#define TDA9875_AVR 0x21 /* Auxiliary volume droite */
1135#define TDA9875_ABA 0x22 /* Auxiliary Basse */
1136#define TDA9875_ATR 0x23 /* Auxiliary treble */
411674fd
HV		 1137
1138#define TDA9875_MSR 0x02 /* Monitor select register */
1139#define TDA9875_C1MSB 0x03 /* Carrier 1 (FM) frequency register MSB */
1140#define TDA9875_C1MIB 0x04 /* Carrier 1 (FM) frequency register (16-8]b */
1141#define TDA9875_C1LSB 0x05 /* Carrier 1 (FM) frequency register LSB */
1142#define TDA9875_C2MSB 0x06 /* Carrier 2 (nicam) frequency register MSB */
1143#define TDA9875_C2MIB 0x07 /* Carrier 2 (nicam) frequency register (16-8]b */
1144#define TDA9875_C2LSB 0x08 /* Carrier 2 (nicam) frequency register LSB */
1145#define TDA9875_DCR 0x09 /* Demodulateur configuration regirter*/
1146#define TDA9875_DEEM 0x0a /* FM de-emphasis regirter*/
1147#define TDA9875_FMAT 0x0b /* FM Matrix regirter*/
1148
1149/* values */
1150#define TDA9875_MUTE_ON 0xff /* general mute */
1151#define TDA9875_MUTE_OFF 0xcc /* general no mute */
1152
1153static int tda9875_initialize(struct CHIPSTATE *chip)
1154{
1155 chip_write(chip, TDA9875_CFG, 0xd0); /*reg de config 0 (reset)*/
1156 chip_write(chip, TDA9875_MSR, 0x03); /* Monitor 0b00000XXX*/
1157 chip_write(chip, TDA9875_C1MSB, 0x00); /*Car1(FM) MSB XMHz*/
1158 chip_write(chip, TDA9875_C1MIB, 0x00); /*Car1(FM) MIB XMHz*/
1159 chip_write(chip, TDA9875_C1LSB, 0x00); /*Car1(FM) LSB XMHz*/
1160 chip_write(chip, TDA9875_C2MSB, 0x00); /*Car2(NICAM) MSB XMHz*/
1161 chip_write(chip, TDA9875_C2MIB, 0x00); /*Car2(NICAM) MIB XMHz*/
1162 chip_write(chip, TDA9875_C2LSB, 0x00); /*Car2(NICAM) LSB XMHz*/
1163 chip_write(chip, TDA9875_DCR, 0x00); /*Demod config 0x00*/
1164 chip_write(chip, TDA9875_DEEM, 0x44); /*DE-Emph 0b0100 0100*/
1165 chip_write(chip, TDA9875_FMAT, 0x00); /*FM Matrix reg 0x00*/
1166 chip_write(chip, TDA9875_SC1, 0x00); /* SCART 1 (SC1)*/
1167 chip_write(chip, TDA9875_SC2, 0x01); /* SCART 2 (sc2)*/
1168
1169 chip_write(chip, TDA9875_CH1V, 0x10); /* Channel volume 1 mute*/
1170 chip_write(chip, TDA9875_CH2V, 0x10); /* Channel volume 2 mute */
1171 chip_write(chip, TDA9875_DACOS, 0x02); /* sig DAC i/o(in:nicam)*/
1172 chip_write(chip, TDA9875_ADCIS, 0x6f); /* sig ADC input(in:mono)*/
1173 chip_write(chip, TDA9875_LOSR, 0x00); /* line out (in:mono)*/
1174 chip_write(chip, TDA9875_AER, 0x00); /*06 Effect (AVL+PSEUDO) */
1175 chip_write(chip, TDA9875_MCS, 0x44); /* Main ch select (DAC) */
1176 chip_write(chip, TDA9875_MVL, 0x03); /* Vol Main left 10dB */
1177 chip_write(chip, TDA9875_MVR, 0x03); /* Vol Main right 10dB*/
1178 chip_write(chip, TDA9875_MBA, 0x00); /* Main Bass Main 0dB*/
1179 chip_write(chip, TDA9875_MTR, 0x00); /* Main Treble Main 0dB*/
1180 chip_write(chip, TDA9875_ACS, 0x44); /* Aux chan select (dac)*/
1181 chip_write(chip, TDA9875_AVL, 0x00); /* Vol Aux left 0dB*/
1182 chip_write(chip, TDA9875_AVR, 0x00); /* Vol Aux right 0dB*/
1183 chip_write(chip, TDA9875_ABA, 0x00); /* Aux Bass Main 0dB*/
1184 chip_write(chip, TDA9875_ATR, 0x00); /* Aux Aigus Main 0dB*/
1185
1186 chip_write(chip, TDA9875_MUT, 0xcc); /* General mute */
1187 return 0;
1188}
1189
1190static int tda9875_volume(int val) { return (unsigned char)(val / 602 - 84); }
1191static int tda9875_bass(int val) { return (unsigned char)(max(-12, val / 2115 - 15)); }
1192static int tda9875_treble(int val) { return (unsigned char)(val / 2622 - 12); }
1193
1194/* ----------------------------------------------------------------------- */
1195
1196
1197/* *********************** *
1198 * i2c interface functions *
1199 * *********************** */
1200
1201static int tda9875_checkit(struct CHIPSTATE *chip)
1202{
1203 struct v4l2_subdev *sd = &chip->sd;
1204 int dic, rev;
1205
1206 dic = chip_read2(chip, 254);
1207 rev = chip_read2(chip, 255);
1208
1209 if (dic == 0 || dic == 2) { /* tda9875 and tda9875A */
1210 v4l2_info(sd, "found tda9875%s rev. %d.\n",
1211 dic == 0 ? "" : "A", rev);
1212 return 1;
1213 }
1214 return 0;
1215}
1da177e4
LT		 1216
1217/* ---------------------------------------------------------------------- */
1218/* audio chip descriptions - defines+functions for tea6420 */
1219
1220#define TEA6300_VL 0x00 /* volume left */
1221#define TEA6300_VR 0x01 /* volume right */
1222#define TEA6300_BA 0x02 /* bass */
1223#define TEA6300_TR 0x03 /* treble */
1224#define TEA6300_FA 0x04 /* fader control */
1225#define TEA6300_S 0x05 /* switch register */
f2421ca3 1226 /* values for those registers: */
1da177e4
LT		 1227#define TEA6300_S_SA 0x01 /* stereo A input */
1228#define TEA6300_S_SB 0x02 /* stereo B */
1229#define TEA6300_S_SC 0x04 /* stereo C */
1230#define TEA6300_S_GMU 0x80 /* general mute */
1231
1232#define TEA6320_V 0x00 /* volume (0-5)/loudness off (6)/zero crossing mute(7) */
1233#define TEA6320_FFR 0x01 /* fader front right (0-5) */
1234#define TEA6320_FFL 0x02 /* fader front left (0-5) */
1235#define TEA6320_FRR 0x03 /* fader rear right (0-5) */
1236#define TEA6320_FRL 0x04 /* fader rear left (0-5) */
1237#define TEA6320_BA 0x05 /* bass (0-4) */
1238#define TEA6320_TR 0x06 /* treble (0-4) */
1239#define TEA6320_S 0x07 /* switch register */
f2421ca3 1240 /* values for those registers: */
1da177e4
LT		 1241#define TEA6320_S_SA 0x07 /* stereo A input */
1242#define TEA6320_S_SB 0x06 /* stereo B */
1243#define TEA6320_S_SC 0x05 /* stereo C */
1244#define TEA6320_S_SD 0x04 /* stereo D */
1245#define TEA6320_S_GMU 0x80 /* general mute */
1246
1247#define TEA6420_S_SA 0x00 /* stereo A input */
1248#define TEA6420_S_SB 0x01 /* stereo B */
1249#define TEA6420_S_SC 0x02 /* stereo C */
1250#define TEA6420_S_SD 0x03 /* stereo D */
1251#define TEA6420_S_SE 0x04 /* stereo E */
1252#define TEA6420_S_GMU 0x05 /* general mute */
1253
1254static int tea6300_shift10(int val) { return val >> 10; }
1255static int tea6300_shift12(int val) { return val >> 12; }
1256
1257/* Assumes 16bit input (values 0x3f to 0x0c are unique, values less than */
1258/* 0x0c mirror those immediately higher) */
1259static int tea6320_volume(int val) { return (val / (65535/(63-12)) + 12) & 0x3f; }
1260static int tea6320_shift11(int val) { return val >> 11; }
1261static int tea6320_initialize(struct CHIPSTATE * chip)
1262{
1263 chip_write(chip, TEA6320_FFR, 0x3f);
1264 chip_write(chip, TEA6320_FFL, 0x3f);
1265 chip_write(chip, TEA6320_FRR, 0x3f);
1266 chip_write(chip, TEA6320_FRL, 0x3f);
1267
1268 return 0;
1269}
1270
1271
1272/* ---------------------------------------------------------------------- */
1273/* audio chip descriptions - defines+functions for tda8425 */
1274
1275#define TDA8425_VL 0x00 /* volume left */
1276#define TDA8425_VR 0x01 /* volume right */
1277#define TDA8425_BA 0x02 /* bass */
1278#define TDA8425_TR 0x03 /* treble */
1279#define TDA8425_S1 0x08 /* switch functions */
f2421ca3 1280 /* values for those registers: */
1da177e4
LT		 1281#define TDA8425_S1_OFF 0xEE /* audio off (mute on) */
1282#define TDA8425_S1_CH1 0xCE /* audio channel 1 (mute off) - "linear stereo" mode */
1283#define TDA8425_S1_CH2 0xCF /* audio channel 2 (mute off) - "linear stereo" mode */
1284#define TDA8425_S1_MU 0x20 /* mute bit */
1285#define TDA8425_S1_STEREO 0x18 /* stereo bits */
1286#define TDA8425_S1_STEREO_SPATIAL 0x18 /* spatial stereo */
1287#define TDA8425_S1_STEREO_LINEAR 0x08 /* linear stereo */
1288#define TDA8425_S1_STEREO_PSEUDO 0x10 /* pseudo stereo */
1289#define TDA8425_S1_STEREO_MONO 0x00 /* forced mono */
1290#define TDA8425_S1_ML 0x06 /* language selector */
1291#define TDA8425_S1_ML_SOUND_A 0x02 /* sound a */
1292#define TDA8425_S1_ML_SOUND_B 0x04 /* sound b */
1293#define TDA8425_S1_ML_STEREO 0x06 /* stereo */
1294#define TDA8425_S1_IS 0x01 /* channel selector */
1295
1296
1297static int tda8425_shift10(int val) { return (val >> 10) | 0xc0; }
1298static int tda8425_shift12(int val) { return (val >> 12) | 0xf0; }
1299
7bcfdf0f 1300static void tda8425_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4
LT		 1301{
1302 int s1 = chip->shadow.bytes[TDA8425_S1+1] & 0xe1;
1303
f952848d
DG		 1304 switch (mode) {
1305 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1306 s1 |= TDA8425_S1_ML_SOUND_A;
1307 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d
DG		 1308 break;
1309 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1310 s1 |= TDA8425_S1_ML_SOUND_B;
1311 s1 |= TDA8425_S1_STEREO_PSEUDO;
f952848d 1312 break;
9e019e07
DG		 1313 case V4L2_TUNER_MODE_LANG1_LANG2:
1314 s1 |= TDA8425_S1_ML_STEREO;
1315 s1 |= TDA8425_S1_STEREO_LINEAR;
1316 break;
f952848d 1317 case V4L2_TUNER_MODE_MONO:
1da177e4 1318 s1 |= TDA8425_S1_ML_STEREO;
f952848d
DG		 1319 s1 |= TDA8425_S1_STEREO_MONO;
1320 break;
1321 case V4L2_TUNER_MODE_STEREO:
1322 s1 |= TDA8425_S1_ML_STEREO;
1323 s1 |= TDA8425_S1_STEREO_SPATIAL;
1324 break;
1325 default:
1326 return;
1da177e4
LT		 1327 }
1328 chip_write(chip,TDA8425_S1,s1);
1329}
1330
1331
1332/* ---------------------------------------------------------------------- */
1333/* audio chip descriptions - defines+functions for pic16c54 (PV951) */
1334
1335/* the registers of 16C54, I2C sub address. */
1336#define PIC16C54_REG_KEY_CODE 0x01 /* Not use. */
1337#define PIC16C54_REG_MISC 0x02
1338
1339/* bit definition of the RESET register, I2C data. */
1340#define PIC16C54_MISC_RESET_REMOTE_CTL 0x01 /* bit 0, Reset to receive the key */
f2421ca3 1341 /* code of remote controller */
1da177e4
LT		 1342#define PIC16C54_MISC_MTS_MAIN 0x02 /* bit 1 */
1343#define PIC16C54_MISC_MTS_SAP 0x04 /* bit 2 */
1344#define PIC16C54_MISC_MTS_BOTH 0x08 /* bit 3 */
1345#define PIC16C54_MISC_SND_MUTE 0x10 /* bit 4, Mute Audio(Line-in and Tuner) */
1346#define PIC16C54_MISC_SND_NOTMUTE 0x20 /* bit 5 */
1347#define PIC16C54_MISC_SWITCH_TUNER 0x40 /* bit 6 , Switch to Line-in */
1348#define PIC16C54_MISC_SWITCH_LINE 0x80 /* bit 7 , Switch to Tuner */
1349
1350/* ---------------------------------------------------------------------- */
1351/* audio chip descriptions - defines+functions for TA8874Z */
1352
18fc59e2 1353/* write 1st byte */
1da177e4
LT		 1354#define TA8874Z_LED_STE 0x80
1355#define TA8874Z_LED_BIL 0x40
1356#define TA8874Z_LED_EXT 0x20
1357#define TA8874Z_MONO_SET 0x10
1358#define TA8874Z_MUTE 0x08
1359#define TA8874Z_F_MONO 0x04
1360#define TA8874Z_MODE_SUB 0x02
1361#define TA8874Z_MODE_MAIN 0x01
1362
18fc59e2
MCC		 1363/* write 2nd byte */
1364/*#define TA8874Z_TI 0x80 */ /* test mode */
1da177e4
LT		 1365#define TA8874Z_SEPARATION 0x3f
1366#define TA8874Z_SEPARATION_DEFAULT 0x10
1367
18fc59e2 1368/* read */
1da177e4
LT		 1369#define TA8874Z_B1 0x80
1370#define TA8874Z_B0 0x40
1371#define TA8874Z_CHAG_FLAG 0x20
1372
18fc59e2
MCC		 1373/*
1374 * B1 B0
1375 * mono L H
1376 * stereo L L
1377 * BIL H L
1378 */
7bcfdf0f 1379static int ta8874z_getrxsubchans(struct CHIPSTATE *chip)
1da177e4
LT		 1380{
1381 int val, mode;
1382
1383 val = chip_read(chip);
3322a59e 1384 mode = V4L2_TUNER_SUB_MONO;
1da177e4 1385 if (val & TA8874Z_B1){
3322a59e 1386 mode |= V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1da177e4 1387 }else if (!(val & TA8874Z_B0)){
1884e298 1388 mode = V4L2_TUNER_SUB_STEREO;
1da177e4 1389 }
7bcfdf0f
DG		 1390 /* v4l2_dbg(1, debug, &chip->sd,
1391 "ta8874z_getrxsubchans(): raw chip read: 0x%02x, return: 0x%02x\n",
1392 val, mode); */
1da177e4
LT		 1393 return mode;
1394}
1395
1396static audiocmd ta8874z_stereo = { 2, {0, TA8874Z_SEPARATION_DEFAULT}};
1397static audiocmd ta8874z_mono = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}};
1398static audiocmd ta8874z_main = {2, { 0, TA8874Z_SEPARATION_DEFAULT}};
1399static audiocmd ta8874z_sub = {2, { TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
9e019e07 1400static audiocmd ta8874z_both = {2, { TA8874Z_MODE_MAIN | TA8874Z_MODE_SUB, TA8874Z_SEPARATION_DEFAULT}};
1da177e4 1401
7bcfdf0f 1402static void ta8874z_setaudmode(struct CHIPSTATE *chip, int mode)
1da177e4 1403{
64f70e7e 1404 struct v4l2_subdev *sd = &chip->sd;
1da177e4
LT		 1405 int update = 1;
1406 audiocmd *t = NULL;
64f70e7e 1407
7bcfdf0f 1408 v4l2_dbg(1, debug, sd, "ta8874z_setaudmode(): mode: 0x%02x\n", mode);
1da177e4
LT		 1409
1410 switch(mode){
dc3d75da 1411 case V4L2_TUNER_MODE_MONO:
1da177e4
LT		 1412 t = &ta8874z_mono;
1413 break;
dc3d75da 1414 case V4L2_TUNER_MODE_STEREO:
1da177e4
LT		 1415 t = &ta8874z_stereo;
1416 break;
dc3d75da 1417 case V4L2_TUNER_MODE_LANG1:
1da177e4
LT		 1418 t = &ta8874z_main;
1419 break;
dc3d75da 1420 case V4L2_TUNER_MODE_LANG2:
1da177e4
LT		 1421 t = &ta8874z_sub;
1422 break;
9e019e07
DG		 1423 case V4L2_TUNER_MODE_LANG1_LANG2:
1424 t = &ta8874z_both;
1425 break;
1da177e4
LT		 1426 default:
1427 update = 0;
1428 }
1429
1430 if(update)
1431 chip_cmd(chip, "TA8874Z", t);
1432}
1433
1434static int ta8874z_checkit(struct CHIPSTATE *chip)
1435{
1436 int rc;
1437 rc = chip_read(chip);
1438 return ((rc & 0x1f) == 0x1f) ? 1 : 0;
1439}
1440
1441/* ---------------------------------------------------------------------- */
1442/* audio chip descriptions - struct CHIPDESC */
1443
1444/* insmod options to enable/disable individual audio chips */
52c1da39
AB		 1445static int tda8425 = 1;
1446static int tda9840 = 1;
1447static int tda9850 = 1;
1448static int tda9855 = 1;
1449static int tda9873 = 1;
1450static int tda9874a = 1;
411674fd 1451static int tda9875 = 1;
ff699e6b
DSL		 1452static int tea6300; /* default 0 - address clash with msp34xx */
1453static int tea6320; /* default 0 - address clash with msp34xx */
52c1da39
AB		 1454static int tea6420 = 1;
1455static int pic16c54 = 1;
ff699e6b 1456static int ta8874z; /* default 0 - address clash with tda9840 */
1da177e4
LT		 1457
1458module_param(tda8425, int, 0444);
1459module_param(tda9840, int, 0444);
1460module_param(tda9850, int, 0444);
1461module_param(tda9855, int, 0444);
1462module_param(tda9873, int, 0444);
1463module_param(tda9874a, int, 0444);
411674fd 1464module_param(tda9875, int, 0444);
1da177e4
LT		 1465module_param(tea6300, int, 0444);
1466module_param(tea6320, int, 0444);
1467module_param(tea6420, int, 0444);
1468module_param(pic16c54, int, 0444);
1469module_param(ta8874z, int, 0444);
1470
1471static struct CHIPDESC chiplist[] = {
1472 {
1473 .name = "tda9840",
1da177e4 1474 .insmodopt = &tda9840,
09df1c16
MCC		 1475 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1476 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4 1477 .registers = 5,
dd03e970 1478 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1479
af1a9951 1480 /* callbacks */
94f9e56e 1481 .checkit = tda9840_checkit,
7bcfdf0f
DG		 1482 .getrxsubchans = tda9840_getrxsubchans,
1483 .setaudmode = tda9840_setaudmode,
1da177e4 1484
4ac97914 1485 .init = { 2, { TDA9840_TEST, TDA9840_TEST_INT1SN
1da177e4
LT		 1486 /* ,TDA9840_SW, TDA9840_MONO */} }
1487 },
1488 {
1489 .name = "tda9873h",
1da177e4 1490 .insmodopt = &tda9873,
09df1c16
MCC		 1491 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1492 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4 1493 .registers = 3,
dd03e970 1494 .flags = CHIP_HAS_INPUTSEL | CHIP_NEED_CHECKMODE,
1da177e4 1495
af1a9951
MCC		 1496 /* callbacks */
1497 .checkit = tda9873_checkit,
7bcfdf0f
DG		 1498 .getrxsubchans = tda9873_getrxsubchans,
1499 .setaudmode = tda9873_setaudmode,
1da177e4
LT		 1500
1501 .init = { 4, { TDA9873_SW, 0xa4, 0x06, 0x03 } },
1502 .inputreg = TDA9873_SW,
1503 .inputmute = TDA9873_MUTE | TDA9873_AUTOMUTE,
8bf2f8e7 1504 .inputmap = {0xa0, 0xa2, 0xa0, 0xa0},
1da177e4
LT		 1505 .inputmask = TDA9873_INP_MASK|TDA9873_MUTE|TDA9873_AUTOMUTE,
1506
1507 },
1508 {
1509 .name = "tda9874h/a",
1da177e4 1510 .insmodopt = &tda9874a,
09df1c16
MCC		 1511 .addr_lo = I2C_ADDR_TDA9874 >> 1,
1512 .addr_hi = I2C_ADDR_TDA9874 >> 1,
dd03e970 1513 .flags = CHIP_NEED_CHECKMODE,
1da177e4 1514
af1a9951
MCC		 1515 /* callbacks */
1516 .initialize = tda9874a_initialize,
1517 .checkit = tda9874a_checkit,
7bcfdf0f
DG		 1518 .getrxsubchans = tda9874a_getrxsubchans,
1519 .setaudmode = tda9874a_setaudmode,
1da177e4 1520 },
411674fd
HV		 1521 {
1522 .name = "tda9875",
1523 .insmodopt = &tda9875,
1524 .addr_lo = I2C_ADDR_TDA9875 >> 1,
1525 .addr_hi = I2C_ADDR_TDA9875 >> 1,
1526 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1527
1528 /* callbacks */
1529 .initialize = tda9875_initialize,
1530 .checkit = tda9875_checkit,
1531 .volfunc = tda9875_volume,
1532 .bassfunc = tda9875_bass,
1533 .treblefunc = tda9875_treble,
1534 .leftreg = TDA9875_MVL,
1535 .rightreg = TDA9875_MVR,
1536 .bassreg = TDA9875_MBA,
1537 .treblereg = TDA9875_MTR,
a346caac 1538 .volinit = 58880,
411674fd 1539 },
1da177e4
LT		 1540 {
1541 .name = "tda9850",
1da177e4 1542 .insmodopt = &tda9850,
09df1c16
MCC		 1543 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1544 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1545 .registers = 11,
1546
7bcfdf0f
DG		 1547 .getrxsubchans = tda985x_getrxsubchans,
1548 .setaudmode = tda985x_setaudmode,
1da177e4
LT		 1549
1550 .init = { 8, { TDA9850_C4, 0x08, 0x08, TDA985x_STEREO, 0x07, 0x10, 0x10, 0x03 } }
1551 },
1552 {
1553 .name = "tda9855",
1da177e4 1554 .insmodopt = &tda9855,
09df1c16
MCC		 1555 .addr_lo = I2C_ADDR_TDA985x_L >> 1,
1556 .addr_hi = I2C_ADDR_TDA985x_H >> 1,
1da177e4
LT		 1557 .registers = 11,
1558 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE,
1559
1560 .leftreg = TDA9855_VL,
1561 .rightreg = TDA9855_VR,
1562 .bassreg = TDA9855_BA,
1563 .treblereg = TDA9855_TR,
af1a9951
MCC		 1564
1565 /* callbacks */
1da177e4
LT		 1566 .volfunc = tda9855_volume,
1567 .bassfunc = tda9855_bass,
1568 .treblefunc = tda9855_treble,
7bcfdf0f
DG		 1569 .getrxsubchans = tda985x_getrxsubchans,
1570 .setaudmode = tda985x_setaudmode,
1da177e4
LT		 1571
1572 .init = { 12, { 0, 0x6f, 0x6f, 0x0e, 0x07<<1, 0x8<<2,
1573 TDA9855_MUTE | TDA9855_AVL | TDA9855_LOUD | TDA9855_INT,
1574 TDA985x_STEREO | TDA9855_LINEAR | TDA9855_TZCM | TDA9855_VZCM,
1575 0x07, 0x10, 0x10, 0x03 }}
1576 },
1577 {
1578 .name = "tea6300",
1da177e4 1579 .insmodopt = &tea6300,
09df1c16
MCC		 1580 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1581 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1582 .registers = 6,
1583 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1584
1585 .leftreg = TEA6300_VR,
1586 .rightreg = TEA6300_VL,
1587 .bassreg = TEA6300_BA,
1588 .treblereg = TEA6300_TR,
af1a9951
MCC		 1589
1590 /* callbacks */
1da177e4
LT		 1591 .volfunc = tea6300_shift10,
1592 .bassfunc = tea6300_shift12,
1593 .treblefunc = tea6300_shift12,
1594
1595 .inputreg = TEA6300_S,
1596 .inputmap = { TEA6300_S_SA, TEA6300_S_SB, TEA6300_S_SC },
1597 .inputmute = TEA6300_S_GMU,
1598 },
1599 {
1600 .name = "tea6320",
1da177e4 1601 .insmodopt = &tea6320,
09df1c16
MCC		 1602 .addr_lo = I2C_ADDR_TEA6300 >> 1,
1603 .addr_hi = I2C_ADDR_TEA6300 >> 1,
1da177e4
LT		 1604 .registers = 8,
1605 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1606
1607 .leftreg = TEA6320_V,
1608 .rightreg = TEA6320_V,
1609 .bassreg = TEA6320_BA,
1610 .treblereg = TEA6320_TR,
af1a9951
MCC		 1611
1612 /* callbacks */
1613 .initialize = tea6320_initialize,
1da177e4
LT		 1614 .volfunc = tea6320_volume,
1615 .bassfunc = tea6320_shift11,
1616 .treblefunc = tea6320_shift11,
1617
1618 .inputreg = TEA6320_S,
1619 .inputmap = { TEA6320_S_SA, TEA6420_S_SB, TEA6300_S_SC, TEA6320_S_SD },
1620 .inputmute = TEA6300_S_GMU,
1621 },
1622 {
1623 .name = "tea6420",
1da177e4 1624 .insmodopt = &tea6420,
09df1c16
MCC		 1625 .addr_lo = I2C_ADDR_TEA6420 >> 1,
1626 .addr_hi = I2C_ADDR_TEA6420 >> 1,
1da177e4
LT		 1627 .registers = 1,
1628 .flags = CHIP_HAS_INPUTSEL,
1629
1630 .inputreg = -1,
1631 .inputmap = { TEA6420_S_SA, TEA6420_S_SB, TEA6420_S_SC },
71df09bc
HV		 1632 .inputmute = TEA6420_S_GMU,
1633 .inputmask = 0x07,
1da177e4
LT		 1634 },
1635 {
1636 .name = "tda8425",
1da177e4 1637 .insmodopt = &tda8425,
09df1c16
MCC		 1638 .addr_lo = I2C_ADDR_TDA8425 >> 1,
1639 .addr_hi = I2C_ADDR_TDA8425 >> 1,
1da177e4
LT		 1640 .registers = 9,
1641 .flags = CHIP_HAS_VOLUME | CHIP_HAS_BASSTREBLE | CHIP_HAS_INPUTSEL,
1642
1643 .leftreg = TDA8425_VL,
1644 .rightreg = TDA8425_VR,
1645 .bassreg = TDA8425_BA,
1646 .treblereg = TDA8425_TR,
af1a9951
MCC		 1647
1648 /* callbacks */
1da177e4
LT		 1649 .volfunc = tda8425_shift10,
1650 .bassfunc = tda8425_shift12,
1651 .treblefunc = tda8425_shift12,
7bcfdf0f 1652 .setaudmode = tda8425_setaudmode,
1da177e4
LT		 1653
1654 .inputreg = TDA8425_S1,
1655 .inputmap = { TDA8425_S1_CH1, TDA8425_S1_CH1, TDA8425_S1_CH1 },
1656 .inputmute = TDA8425_S1_OFF,
1657
1da177e4
LT		 1658 },
1659 {
1660 .name = "pic16c54 (PV951)",
1da177e4 1661 .insmodopt = &pic16c54,
09df1c16
MCC		 1662 .addr_lo = I2C_ADDR_PIC16C54 >> 1,
1663 .addr_hi = I2C_ADDR_PIC16C54>> 1,
1da177e4
LT		 1664 .registers = 2,
1665 .flags = CHIP_HAS_INPUTSEL,
1666
1667 .inputreg = PIC16C54_REG_MISC,
1668 .inputmap = {PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_TUNER,
1669 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
1670 PIC16C54_MISC_SND_NOTMUTE|PIC16C54_MISC_SWITCH_LINE,
8bf2f8e7 1671 PIC16C54_MISC_SND_MUTE},
1da177e4
LT		 1672 .inputmute = PIC16C54_MISC_SND_MUTE,
1673 },
1674 {
1675 .name = "ta8874z",
1da177e4
LT		 1676 .checkit = ta8874z_checkit,
1677 .insmodopt = &ta8874z,
09df1c16
MCC		 1678 .addr_lo = I2C_ADDR_TDA9840 >> 1,
1679 .addr_hi = I2C_ADDR_TDA9840 >> 1,
1da177e4
LT		 1680 .registers = 2,
1681
af1a9951 1682 /* callbacks */
7bcfdf0f
DG		 1683 .getrxsubchans = ta8874z_getrxsubchans,
1684 .setaudmode = ta8874z_setaudmode,
1da177e4 1685
4ac97914 1686 .init = {2, { TA8874Z_MONO_SET, TA8874Z_SEPARATION_DEFAULT}},
1da177e4
LT		 1687 },
1688 { .name = NULL } /* EOF */
1689};
1690
1691
1692/* ---------------------------------------------------------------------- */
1da177e4 1693
c9114031 1694static int tvaudio_s_ctrl(struct v4l2_ctrl *ctrl)
8bf2f8e7 1695{
c9114031 1696 struct v4l2_subdev *sd = to_sd(ctrl);
64f70e7e 1697 struct CHIPSTATE *chip = to_state(sd);
81cb5c4f 1698 struct CHIPDESC *desc = chip->desc;
8bf2f8e7
HV		 1699
1700 switch (ctrl->id) {
1701 case V4L2_CID_AUDIO_MUTE:
c9114031 1702 chip->muted = ctrl->val;
8bf2f8e7
HV		 1703 if (chip->muted)
1704 chip_write_masked(chip,desc->inputreg,desc->inputmute,desc->inputmask);
1705 else
1706 chip_write_masked(chip,desc->inputreg,
1707 desc->inputmap[chip->input],desc->inputmask);
dc3d75da 1708 return 0;
c9114031 1709 case V4L2_CID_AUDIO_VOLUME: {
a346caac
HV		 1710 u32 volume, balance;
1711 u32 left, right;
88af8304 1712
c9114031
HV		 1713 volume = chip->volume->val;
1714 balance = chip->balance->val;
a346caac
HV		 1715 left = (min(65536U - balance, 32768U) * volume) / 32768U;
1716 right = (min(balance, 32768U) * volume) / 32768U;
dc3d75da 1717
a346caac
HV		 1718 chip_write(chip, desc->leftreg, desc->volfunc(left));
1719 chip_write(chip, desc->rightreg, desc->volfunc(right));
dc3d75da
MCC		 1720 return 0;
1721 }
1722 case V4L2_CID_AUDIO_BASS:
c9114031 1723 chip_write(chip, desc->bassreg, desc->bassfunc(ctrl->val));
dc3d75da
MCC		 1724 return 0;
1725 case V4L2_CID_AUDIO_TREBLE:
c9114031 1726 chip_write(chip, desc->treblereg, desc->treblefunc(ctrl->val));
dc3d75da
MCC		 1727 return 0;
1728 }
1729 return -EINVAL;
8bf2f8e7
HV		 1730}
1731
1732
1da177e4
LT		 1733/* ---------------------------------------------------------------------- */
1734/* video4linux interface */
1735
64f70e7e 1736static int tvaudio_s_radio(struct v4l2_subdev *sd)
1da177e4 1737{
64f70e7e 1738 struct CHIPSTATE *chip = to_state(sd);
1da177e4 1739
64f70e7e 1740 chip->radio = 1;
64f70e7e
HV		 1741 /* del_timer(&chip->wt); */
1742 return 0;
1743}
1744
5325b427
HV		 1745static int tvaudio_s_routing(struct v4l2_subdev *sd,
1746 u32 input, u32 output, u32 config)
64f70e7e
HV		 1747{
1748 struct CHIPSTATE *chip = to_state(sd);
1749 struct CHIPDESC *desc = chip->desc;
1da177e4 1750
5fa7b9f3
HV		 1751 if (!(desc->flags & CHIP_HAS_INPUTSEL))
1752 return 0;
5325b427 1753 if (input >= 4)
64f70e7e
HV		 1754 return -EINVAL;
1755 /* There are four inputs: tuner, radio, extern and intern. */
5325b427 1756 chip->input = input;
64f70e7e
HV		 1757 if (chip->muted)
1758 return 0;
1759 chip_write_masked(chip, desc->inputreg,
1760 desc->inputmap[chip->input], desc->inputmask);
1761 return 0;
1762}
1763
1764static int tvaudio_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1765{
1766 struct CHIPSTATE *chip = to_state(sd);
1767 struct CHIPDESC *desc = chip->desc;
64f70e7e 1768
7bcfdf0f 1769 if (!desc->setaudmode)
5fa7b9f3 1770 return 0;
64f70e7e
HV		 1771 if (chip->radio)
1772 return 0;
5fa7b9f3 1773
64f70e7e
HV		 1774 switch (vt->audmode) {
1775 case V4L2_TUNER_MODE_MONO:
1776 case V4L2_TUNER_MODE_STEREO:
1777 case V4L2_TUNER_MODE_LANG1:
1778 case V4L2_TUNER_MODE_LANG2:
64f70e7e 1779 case V4L2_TUNER_MODE_LANG1_LANG2:
64f70e7e
HV		 1780 break;
1781 default:
1782 return -EINVAL;
1783 }
1784 chip->audmode = vt->audmode;
1785
e21adca8
DG		 1786 if (chip->thread)
1787 wake_up_process(chip->thread);
1788 else
7bcfdf0f 1789 desc->setaudmode(chip, vt->audmode);
e21adca8 1790
64f70e7e
HV		 1791 return 0;
1792}
8bf2f8e7 1793
64f70e7e
HV		 1794static int tvaudio_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1795{
1796 struct CHIPSTATE *chip = to_state(sd);
1797 struct CHIPDESC *desc = chip->desc;
2474ed44 1798
7bcfdf0f 1799 if (!desc->getrxsubchans)
5fa7b9f3 1800 return 0;
64f70e7e
HV		 1801 if (chip->radio)
1802 return 0;
5fa7b9f3 1803
64f70e7e 1804 vt->audmode = chip->audmode;
7bcfdf0f 1805 vt->rxsubchans = desc->getrxsubchans(chip);
64f70e7e
HV		 1806 vt->capability = V4L2_TUNER_CAP_STEREO |
1807 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
1808
64f70e7e
HV		 1809 return 0;
1810}
1811
1812static int tvaudio_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1813{
1814 struct CHIPSTATE *chip = to_state(sd);
1815
1816 chip->radio = 0;
1817 return 0;
1818}
1819
1820static int tvaudio_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1821{
1822 struct CHIPSTATE *chip = to_state(sd);
1823 struct CHIPDESC *desc = chip->desc;
1824
7bcfdf0f 1825 /* For chips that provide getrxsubchans and setaudmode, and doesn't
64f70e7e
HV		 1826 automatically follows the stereo carrier, a kthread is
1827 created to set the audio standard. In this case, when then
1828 the video channel is changed, tvaudio starts on MONO mode.
1829 After waiting for 2 seconds, the kernel thread is called,
1830 to follow whatever audio standard is pointed by the
1831 audio carrier.
1832 */
1833 if (chip->thread) {
7bcfdf0f 1834 desc->setaudmode(chip, V4L2_TUNER_MODE_MONO);
e21adca8 1835 chip->prevmode = -1; /* reset previous mode */
64f70e7e 1836 mod_timer(&chip->wt, jiffies+msecs_to_jiffies(2000));
2474ed44 1837 }
64f70e7e
HV		 1838 return 0;
1839}
2474ed44 1840
aecde8b5 1841static int tvaudio_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
64f70e7e
HV		 1842{
1843 struct i2c_client *client = v4l2_get_subdevdata(sd);
1844
1845 return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVAUDIO, 0);
1846}
1847
c9114031
HV		 1848static int tvaudio_log_status(struct v4l2_subdev *sd)
1849{
1850 struct CHIPSTATE *chip = to_state(sd);
1851 struct CHIPDESC *desc = chip->desc;
1852
1853 v4l2_info(sd, "Chip: %s\n", desc->name);
1854 v4l2_ctrl_handler_log_status(&chip->hdl, sd->name);
1855 return 0;
1856}
1857
64f70e7e
HV		 1858/* ----------------------------------------------------------------------- */
1859
c9114031
HV		 1860static const struct v4l2_ctrl_ops tvaudio_ctrl_ops = {
1861 .s_ctrl = tvaudio_s_ctrl,
1862};
1863
64f70e7e 1864static const struct v4l2_subdev_core_ops tvaudio_core_ops = {
c9114031 1865 .log_status = tvaudio_log_status,
64f70e7e 1866 .g_chip_ident = tvaudio_g_chip_ident,
c9114031
HV		 1867 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
1868 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
1869 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
1870 .g_ctrl = v4l2_subdev_g_ctrl,
1871 .s_ctrl = v4l2_subdev_s_ctrl,
1872 .queryctrl = v4l2_subdev_queryctrl,
1873 .querymenu = v4l2_subdev_querymenu,
f41737ec 1874 .s_std = tvaudio_s_std,
64f70e7e
HV		 1875};
1876
1877static const struct v4l2_subdev_tuner_ops tvaudio_tuner_ops = {
1878 .s_radio = tvaudio_s_radio,
1879 .s_frequency = tvaudio_s_frequency,
64f70e7e 1880 .s_tuner = tvaudio_s_tuner,
e6a1a08f 1881 .g_tuner = tvaudio_g_tuner,
64f70e7e
HV		 1882};
1883
1884static const struct v4l2_subdev_audio_ops tvaudio_audio_ops = {
1885 .s_routing = tvaudio_s_routing,
1886};
1887
1888static const struct v4l2_subdev_ops tvaudio_ops = {
1889 .core = &tvaudio_core_ops,
1890 .tuner = &tvaudio_tuner_ops,
1891 .audio = &tvaudio_audio_ops,
1892};
1893
1894/* ----------------------------------------------------------------------- */
1895
1896
1897/* i2c registration */
1898
1899static int tvaudio_probe(struct i2c_client *client, const struct i2c_device_id *id)
1900{
1901 struct CHIPSTATE *chip;
1902 struct CHIPDESC *desc;
1903 struct v4l2_subdev *sd;
1904
1905 if (debug) {
1906 printk(KERN_INFO "tvaudio: TV audio decoder + audio/video mux driver\n");
1907 printk(KERN_INFO "tvaudio: known chips: ");
1908 for (desc = chiplist; desc->name != NULL; desc++)
1909 printk("%s%s", (desc == chiplist) ? "" : ", ", desc->name);
1910 printk("\n");
2474ed44 1911 }
1da177e4 1912
64f70e7e
HV		 1913 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1914 if (!chip)
1915 return -ENOMEM;
1916 sd = &chip->sd;
1917 v4l2_i2c_subdev_init(sd, client, &tvaudio_ops);
8a854284 1918
64f70e7e
HV		 1919 /* find description for the chip */
1920 v4l2_dbg(1, debug, sd, "chip found @ 0x%x\n", client->addr<<1);
1921 for (desc = chiplist; desc->name != NULL; desc++) {
1922 if (0 == *(desc->insmodopt))
1923 continue;
1924 if (client->addr < desc->addr_lo ||
1925 client->addr > desc->addr_hi)
1926 continue;
1927 if (desc->checkit && !desc->checkit(chip))
1928 continue;
1da177e4
LT		 1929 break;
1930 }
64f70e7e
HV		 1931 if (desc->name == NULL) {
1932 v4l2_dbg(1, debug, sd, "no matching chip description found\n");
1933 kfree(chip);
1934 return -EIO;
1935 }
1936 v4l2_info(sd, "%s found @ 0x%x (%s)\n", desc->name, client->addr<<1, client->adapter->name);
1937 if (desc->flags) {
1938 v4l2_dbg(1, debug, sd, "matches:%s%s%s.\n",
1939 (desc->flags & CHIP_HAS_VOLUME) ? " volume" : "",
1940 (desc->flags & CHIP_HAS_BASSTREBLE) ? " bass/treble" : "",
1941 (desc->flags & CHIP_HAS_INPUTSEL) ? " audiomux" : "");
1942 }
8a854284 1943
64f70e7e
HV		 1944 /* fill required data structures */
1945 if (!id)
1946 strlcpy(client->name, desc->name, I2C_NAME_SIZE);
1947 chip->desc = desc;
1948 chip->shadow.count = desc->registers+1;
1949 chip->prevmode = -1;
1950 chip->audmode = V4L2_TUNER_MODE_LANG1;
8a854284 1951
64f70e7e
HV		 1952 /* initialization */
1953 if (desc->initialize != NULL)
1954 desc->initialize(chip);
1955 else
1956 chip_cmd(chip, "init", &desc->init);
8a854284 1957
c9114031
HV		 1958 v4l2_ctrl_handler_init(&chip->hdl, 5);
1959 if (desc->flags & CHIP_HAS_INPUTSEL)
1960 v4l2_ctrl_new_std(&chip->hdl, &tvaudio_ctrl_ops,
1961 V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
64f70e7e
HV		 1962 if (desc->flags & CHIP_HAS_VOLUME) {
1963 if (!desc->volfunc) {
1964 /* This shouldn't be happen. Warn user, but keep working
1965 without volume controls
1966 */
1967 v4l2_info(sd, "volume callback undefined!\n");
1968 desc->flags &= ~CHIP_HAS_VOLUME;
1969 } else {
c9114031
HV		 1970 chip->volume = v4l2_ctrl_new_std(&chip->hdl,
1971 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
1972 0, 65535, 65535 / 100,
1973 desc->volinit ? desc->volinit : 65535);
1974 chip->balance = v4l2_ctrl_new_std(&chip->hdl,
1975 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BALANCE,
1976 0, 65535, 65535 / 100, 32768);
1977 v4l2_ctrl_cluster(2, &chip->volume);
64f70e7e 1978 }
8a854284 1979 }
64f70e7e
HV		 1980 if (desc->flags & CHIP_HAS_BASSTREBLE) {
1981 if (!desc->bassfunc || !desc->treblefunc) {
1982 /* This shouldn't be happen. Warn user, but keep working
1983 without bass/treble controls
1984 */
1985 v4l2_info(sd, "bass/treble callbacks undefined!\n");
1986 desc->flags &= ~CHIP_HAS_BASSTREBLE;
1987 } else {
c9114031
HV		 1988 v4l2_ctrl_new_std(&chip->hdl,
1989 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_BASS,
1990 0, 65535, 65535 / 100,
1991 desc->bassinit ? desc->bassinit : 32768);
1992 v4l2_ctrl_new_std(&chip->hdl,
1993 &tvaudio_ctrl_ops, V4L2_CID_AUDIO_TREBLE,
1994 0, 65535, 65535 / 100,
1995 desc->trebleinit ? desc->trebleinit : 32768);
1da177e4 1996 }
64f70e7e 1997 }
74cab31c 1998
c9114031
HV		 1999 sd->ctrl_handler = &chip->hdl;
2000 if (chip->hdl.error) {
2001 int err = chip->hdl.error;
2002
2003 v4l2_ctrl_handler_free(&chip->hdl);
2004 kfree(chip);
2005 return err;
2006 }
2007 /* set controls to the default values */
2008 v4l2_ctrl_handler_setup(&chip->hdl);
2009
64f70e7e 2010 chip->thread = NULL;
e4129a9c 2011 init_timer(&chip->wt);
64f70e7e 2012 if (desc->flags & CHIP_NEED_CHECKMODE) {
7bcfdf0f 2013 if (!desc->getrxsubchans || !desc->setaudmode) {
64f70e7e
HV		 2014 /* This shouldn't be happen. Warn user, but keep working
2015 without kthread
2016 */
2017 v4l2_info(sd, "set/get mode callbacks undefined!\n");
2018 return 0;
2019 }
2020 /* start async thread */
64f70e7e
HV		 2021 chip->wt.function = chip_thread_wake;
2022 chip->wt.data = (unsigned long)chip;
2023 chip->thread = kthread_run(chip_thread, chip, client->name);
2024 if (IS_ERR(chip->thread)) {
2025 v4l2_warn(sd, "failed to create kthread\n");
2026 chip->thread = NULL;
2027 }
1da177e4
LT		 2028 }
2029 return 0;
2030}
2031
64f70e7e
HV		 2032static int tvaudio_remove(struct i2c_client *client)
2033{
2034 struct v4l2_subdev *sd = i2c_get_clientdata(client);
2035 struct CHIPSTATE *chip = to_state(sd);
2036
2037 del_timer_sync(&chip->wt);
2038 if (chip->thread) {
2039 /* shutdown async thread */
2040 kthread_stop(chip->thread);
2041 chip->thread = NULL;
2042 }
2043
2044 v4l2_device_unregister_subdev(sd);
c9114031 2045 v4l2_ctrl_handler_free(&chip->hdl);
64f70e7e
HV		 2046 kfree(chip);
2047 return 0;
2048}
2049
ae429083
JD		 2050/* This driver supports many devices and the idea is to let the driver
2051 detect which device is present. So rather than listing all supported
2052 devices here, we pretend to support a single, fake device type. */
64f70e7e 2053static const struct i2c_device_id tvaudio_id[] = {
ae429083
JD		 2054 { "tvaudio", 0 },
2055 { }
2056};
64f70e7e 2057MODULE_DEVICE_TABLE(i2c, tvaudio_id);
ae429083 2058
7a004d13
HV		 2059static struct i2c_driver tvaudio_driver = {
2060 .driver = {
2061 .owner = THIS_MODULE,
2062 .name = "tvaudio",
2063 },
2064 .probe = tvaudio_probe,
2065 .remove = tvaudio_remove,
2066 .id_table = tvaudio_id,
08e14054 2067};
7a004d13 2068
c6e8d86f 2069module_i2c_driver(tvaudio_driver);
Linux kernel - Deliverables
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