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Merge branch 'enable-devices' into omap-for-v4.5/fixes
[deliverable/linux.git] / drivers / media / i2c / tvp5150.c
CommitLineData
cd4665c5 1/*
6ac48b45 2 * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder driver
cd4665c5 3 *
6ac48b45
MCC		 4 * Copyright (c) 2005,2006 Mauro Carvalho Chehab (mchehab@infradead.org)
5 * This code is placed under the terms of the GNU General Public License v2
cd4665c5
MCC		 6 */
7
cd4665c5 8#include <linux/i2c.h>
5a0e3ad6 9#include <linux/slab.h>
33b687cf 10#include <linux/videodev2.h>
cd4665c5 11#include <linux/delay.h>
7a707b89 12#include <linux/module.h>
c7d97499 13#include <media/v4l2-async.h>
6b8fe025 14#include <media/v4l2-device.h>
b5dcee22 15#include <media/i2c/tvp5150.h>
6c45ec71 16#include <media/v4l2-ctrls.h>
cd4665c5
MCC		 17
18#include "tvp5150_reg.h"
19
785a3de1
PZ		 20#define TVP5150_H_MAX 720U
21#define TVP5150_V_MAX_525_60 480U
22#define TVP5150_V_MAX_OTHERS 576U
963ddc63
JM		 23#define TVP5150_MAX_CROP_LEFT 511
24#define TVP5150_MAX_CROP_TOP 127
25#define TVP5150_CROP_SHIFT 2
26
6ac48b45 27MODULE_DESCRIPTION("Texas Instruments TVP5150A video decoder driver");
cd4665c5
MCC		 28MODULE_AUTHOR("Mauro Carvalho Chehab");
29MODULE_LICENSE("GPL");
30
cd4665c5 31
ff699e6b 32static int debug;
2a0489d3 33module_param(debug, int, 0644);
6b8fe025 34MODULE_PARM_DESC(debug, "Debug level (0-2)");
cd4665c5
MCC		 35
36struct tvp5150 {
6b8fe025 37 struct v4l2_subdev sd;
6c45ec71 38 struct v4l2_ctrl_handler hdl;
963ddc63 39 struct v4l2_rect rect;
84486d53 40
3ad96835 41 v4l2_std_id norm; /* Current set standard */
5325b427
HV		 42 u32 input;
43 u32 output;
84486d53 44 int enable;
cd4665c5
MCC		 45};
46
6b8fe025 47static inline struct tvp5150 *to_tvp5150(struct v4l2_subdev *sd)
cd4665c5 48{
6b8fe025
HV		 49 return container_of(sd, struct tvp5150, sd);
50}
51
6c45ec71
HV		 52static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
53{
54 return &container_of(ctrl->handler, struct tvp5150, hdl)->sd;
55}
56
6b8fe025
HV		 57static int tvp5150_read(struct v4l2_subdev *sd, unsigned char addr)
58{
59 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 60 int rc;
e35ce2e4
LP		 61
62 rc = i2c_smbus_read_byte_data(c, addr);
63 if (rc < 0) {
64 v4l2_err(sd, "i2c i/o error: rc == %d\n", rc);
65 return rc;
8cd0d4ca 66 }
e1bc80ad 67
e35ce2e4 68 v4l2_dbg(2, debug, sd, "tvp5150: read 0x%02x = 0x%02x\n", addr, rc);
cd4665c5 69
e35ce2e4 70 return rc;
cd4665c5
MCC		 71}
72
6b8fe025 73static inline void tvp5150_write(struct v4l2_subdev *sd, unsigned char addr,
84486d53 74 unsigned char value)
cd4665c5 75{
6b8fe025 76 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 77 int rc;
cd4665c5 78
e35ce2e4
LP		 79 v4l2_dbg(2, debug, sd, "tvp5150: writing 0x%02x 0x%02x\n", addr, value);
80 rc = i2c_smbus_write_byte_data(c, addr, value);
81 if (rc < 0)
82 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d\n", rc);
cd4665c5
MCC		 83}
84
6b8fe025
HV		 85static void dump_reg_range(struct v4l2_subdev *sd, char *s, u8 init,
86 const u8 end, int max_line)
3ad96835 87{
6b8fe025 88 int i = 0;
3ad96835 89
6b8fe025
HV		 90 while (init != (u8)(end + 1)) {
91 if ((i % max_line) == 0) {
92 if (i > 0)
3ad96835 93 printk("\n");
6b8fe025 94 printk("tvp5150: %s reg 0x%02x = ", s, init);
3ad96835 95 }
6b8fe025 96 printk("%02x ", tvp5150_read(sd, init));
3ad96835
MCC		 97
98 init++;
99 i++;
100 }
101 printk("\n");
102}
103
6b8fe025 104static int tvp5150_log_status(struct v4l2_subdev *sd)
cd4665c5 105{
84486d53 106 printk("tvp5150: Video input source selection #1 = 0x%02x\n",
6b8fe025 107 tvp5150_read(sd, TVP5150_VD_IN_SRC_SEL_1));
84486d53 108 printk("tvp5150: Analog channel controls = 0x%02x\n",
6b8fe025 109 tvp5150_read(sd, TVP5150_ANAL_CHL_CTL));
84486d53 110 printk("tvp5150: Operation mode controls = 0x%02x\n",
6b8fe025 111 tvp5150_read(sd, TVP5150_OP_MODE_CTL));
84486d53 112 printk("tvp5150: Miscellaneous controls = 0x%02x\n",
6b8fe025 113 tvp5150_read(sd, TVP5150_MISC_CTL));
3ad96835 114 printk("tvp5150: Autoswitch mask= 0x%02x\n",
6b8fe025 115 tvp5150_read(sd, TVP5150_AUTOSW_MSK));
84486d53 116 printk("tvp5150: Color killer threshold control = 0x%02x\n",
6b8fe025 117 tvp5150_read(sd, TVP5150_COLOR_KIL_THSH_CTL));
3ad96835 118 printk("tvp5150: Luminance processing controls #1 #2 and #3 = %02x %02x %02x\n",
6b8fe025
HV		 119 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_1),
120 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_2),
121 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_3));
84486d53 122 printk("tvp5150: Brightness control = 0x%02x\n",
6b8fe025 123 tvp5150_read(sd, TVP5150_BRIGHT_CTL));
84486d53 124 printk("tvp5150: Color saturation control = 0x%02x\n",
6b8fe025 125 tvp5150_read(sd, TVP5150_SATURATION_CTL));
84486d53 126 printk("tvp5150: Hue control = 0x%02x\n",
6b8fe025 127 tvp5150_read(sd, TVP5150_HUE_CTL));
84486d53 128 printk("tvp5150: Contrast control = 0x%02x\n",
6b8fe025 129 tvp5150_read(sd, TVP5150_CONTRAST_CTL));
84486d53 130 printk("tvp5150: Outputs and data rates select = 0x%02x\n",
6b8fe025 131 tvp5150_read(sd, TVP5150_DATA_RATE_SEL));
84486d53 132 printk("tvp5150: Configuration shared pins = 0x%02x\n",
6b8fe025 133 tvp5150_read(sd, TVP5150_CONF_SHARED_PIN));
3ad96835 134 printk("tvp5150: Active video cropping start = 0x%02x%02x\n",
6b8fe025
HV		 135 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_MSB),
136 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_LSB));
3ad96835 137 printk("tvp5150: Active video cropping stop = 0x%02x%02x\n",
6b8fe025
HV		 138 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_MSB),
139 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_LSB));
84486d53 140 printk("tvp5150: Genlock/RTC = 0x%02x\n",
6b8fe025 141 tvp5150_read(sd, TVP5150_GENLOCK));
84486d53 142 printk("tvp5150: Horizontal sync start = 0x%02x\n",
6b8fe025 143 tvp5150_read(sd, TVP5150_HORIZ_SYNC_START));
84486d53 144 printk("tvp5150: Vertical blanking start = 0x%02x\n",
6b8fe025 145 tvp5150_read(sd, TVP5150_VERT_BLANKING_START));
84486d53 146 printk("tvp5150: Vertical blanking stop = 0x%02x\n",
6b8fe025 147 tvp5150_read(sd, TVP5150_VERT_BLANKING_STOP));
3ad96835 148 printk("tvp5150: Chrominance processing control #1 and #2 = %02x %02x\n",
6b8fe025
HV		 149 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_1),
150 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_2));
84486d53 151 printk("tvp5150: Interrupt reset register B = 0x%02x\n",
6b8fe025 152 tvp5150_read(sd, TVP5150_INT_RESET_REG_B));
84486d53 153 printk("tvp5150: Interrupt enable register B = 0x%02x\n",
6b8fe025 154 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_B));
84486d53 155 printk("tvp5150: Interrupt configuration register B = 0x%02x\n",
6b8fe025 156 tvp5150_read(sd, TVP5150_INTT_CONFIG_REG_B));
84486d53 157 printk("tvp5150: Video standard = 0x%02x\n",
6b8fe025 158 tvp5150_read(sd, TVP5150_VIDEO_STD));
3ad96835 159 printk("tvp5150: Chroma gain factor: Cb=0x%02x Cr=0x%02x\n",
6b8fe025
HV		 160 tvp5150_read(sd, TVP5150_CB_GAIN_FACT),
161 tvp5150_read(sd, TVP5150_CR_GAIN_FACTOR));
84486d53 162 printk("tvp5150: Macrovision on counter = 0x%02x\n",
6b8fe025 163 tvp5150_read(sd, TVP5150_MACROVISION_ON_CTR));
84486d53 164 printk("tvp5150: Macrovision off counter = 0x%02x\n",
6b8fe025 165 tvp5150_read(sd, TVP5150_MACROVISION_OFF_CTR));
3ad96835 166 printk("tvp5150: ITU-R BT.656.%d timing(TVP5150AM1 only)\n",
6b8fe025 167 (tvp5150_read(sd, TVP5150_REV_SELECT) & 1) ? 3 : 4);
3ad96835 168 printk("tvp5150: Device ID = %02x%02x\n",
6b8fe025
HV		 169 tvp5150_read(sd, TVP5150_MSB_DEV_ID),
170 tvp5150_read(sd, TVP5150_LSB_DEV_ID));
3ad96835 171 printk("tvp5150: ROM version = (hex) %02x.%02x\n",
6b8fe025
HV		 172 tvp5150_read(sd, TVP5150_ROM_MAJOR_VER),
173 tvp5150_read(sd, TVP5150_ROM_MINOR_VER));
3ad96835 174 printk("tvp5150: Vertical line count = 0x%02x%02x\n",
6b8fe025
HV		 175 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_MSB),
176 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_LSB));
84486d53 177 printk("tvp5150: Interrupt status register B = 0x%02x\n",
6b8fe025 178 tvp5150_read(sd, TVP5150_INT_STATUS_REG_B));
84486d53 179 printk("tvp5150: Interrupt active register B = 0x%02x\n",
6b8fe025 180 tvp5150_read(sd, TVP5150_INT_ACTIVE_REG_B));
3ad96835 181 printk("tvp5150: Status regs #1 to #5 = %02x %02x %02x %02x %02x\n",
6b8fe025
HV		 182 tvp5150_read(sd, TVP5150_STATUS_REG_1),
183 tvp5150_read(sd, TVP5150_STATUS_REG_2),
184 tvp5150_read(sd, TVP5150_STATUS_REG_3),
185 tvp5150_read(sd, TVP5150_STATUS_REG_4),
186 tvp5150_read(sd, TVP5150_STATUS_REG_5));
3ad96835 187
6b8fe025
HV		 188 dump_reg_range(sd, "Teletext filter 1", TVP5150_TELETEXT_FIL1_INI,
189 TVP5150_TELETEXT_FIL1_END, 8);
190 dump_reg_range(sd, "Teletext filter 2", TVP5150_TELETEXT_FIL2_INI,
191 TVP5150_TELETEXT_FIL2_END, 8);
3ad96835 192
84486d53 193 printk("tvp5150: Teletext filter enable = 0x%02x\n",
6b8fe025 194 tvp5150_read(sd, TVP5150_TELETEXT_FIL_ENA));
84486d53 195 printk("tvp5150: Interrupt status register A = 0x%02x\n",
6b8fe025 196 tvp5150_read(sd, TVP5150_INT_STATUS_REG_A));
84486d53 197 printk("tvp5150: Interrupt enable register A = 0x%02x\n",
6b8fe025 198 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_A));
84486d53 199 printk("tvp5150: Interrupt configuration = 0x%02x\n",
6b8fe025 200 tvp5150_read(sd, TVP5150_INT_CONF));
84486d53 201 printk("tvp5150: VDP status register = 0x%02x\n",
6b8fe025 202 tvp5150_read(sd, TVP5150_VDP_STATUS_REG));
84486d53 203 printk("tvp5150: FIFO word count = 0x%02x\n",
6b8fe025 204 tvp5150_read(sd, TVP5150_FIFO_WORD_COUNT));
84486d53 205 printk("tvp5150: FIFO interrupt threshold = 0x%02x\n",
6b8fe025 206 tvp5150_read(sd, TVP5150_FIFO_INT_THRESHOLD));
84486d53 207 printk("tvp5150: FIFO reset = 0x%02x\n",
6b8fe025 208 tvp5150_read(sd, TVP5150_FIFO_RESET));
84486d53 209 printk("tvp5150: Line number interrupt = 0x%02x\n",
6b8fe025 210 tvp5150_read(sd, TVP5150_LINE_NUMBER_INT));
3ad96835 211 printk("tvp5150: Pixel alignment register = 0x%02x%02x\n",
6b8fe025
HV		 212 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_HIGH),
213 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_LOW));
84486d53 214 printk("tvp5150: FIFO output control = 0x%02x\n",
6b8fe025 215 tvp5150_read(sd, TVP5150_FIFO_OUT_CTRL));
3ad96835 216 printk("tvp5150: Full field enable = 0x%02x\n",
6b8fe025 217 tvp5150_read(sd, TVP5150_FULL_FIELD_ENA));
84486d53 218 printk("tvp5150: Full field mode register = 0x%02x\n",
6b8fe025 219 tvp5150_read(sd, TVP5150_FULL_FIELD_MODE_REG));
3ad96835 220
6b8fe025
HV		 221 dump_reg_range(sd, "CC data", TVP5150_CC_DATA_INI,
222 TVP5150_CC_DATA_END, 8);
3ad96835 223
6b8fe025
HV		 224 dump_reg_range(sd, "WSS data", TVP5150_WSS_DATA_INI,
225 TVP5150_WSS_DATA_END, 8);
3ad96835 226
6b8fe025
HV		 227 dump_reg_range(sd, "VPS data", TVP5150_VPS_DATA_INI,
228 TVP5150_VPS_DATA_END, 8);
3ad96835 229
6b8fe025
HV		 230 dump_reg_range(sd, "VITC data", TVP5150_VITC_DATA_INI,
231 TVP5150_VITC_DATA_END, 10);
3ad96835 232
6b8fe025
HV		 233 dump_reg_range(sd, "Line mode", TVP5150_LINE_MODE_INI,
234 TVP5150_LINE_MODE_END, 8);
235 return 0;
cd4665c5
MCC		 236}
237
238/****************************************************************************
239 Basic functions
240 ****************************************************************************/
cd4665c5 241
6b8fe025 242static inline void tvp5150_selmux(struct v4l2_subdev *sd)
cd4665c5 243{
2962fc01 244 int opmode = 0;
6b8fe025 245 struct tvp5150 *decoder = to_tvp5150(sd);
c7c0b34c 246 int input = 0;
afcc8e8c 247 int val;
84486d53 248
5325b427 249 if ((decoder->output & TVP5150_BLACK_SCREEN) || !decoder->enable)
c7c0b34c 250 input = 8;
4c86f973 251
5325b427 252 switch (decoder->input) {
c7c0b34c
HV		 253 case TVP5150_COMPOSITE1:
254 input |= 2;
255 /* fall through */
256 case TVP5150_COMPOSITE0:
c0477ad9 257 break;
c7c0b34c 258 case TVP5150_SVIDEO:
c0477ad9 259 default:
c7c0b34c 260 input |= 1;
c0477ad9
MCC		 261 break;
262 }
263
6b8fe025 264 v4l2_dbg(1, debug, sd, "Selecting video route: route input=%i, output=%i "
12500f07 265 "=> tvp5150 input=%i, opmode=%i\n",
5325b427
HV		 266 decoder->input, decoder->output,
267 input, opmode);
12500f07 268
6b8fe025
HV		 269 tvp5150_write(sd, TVP5150_OP_MODE_CTL, opmode);
270 tvp5150_write(sd, TVP5150_VD_IN_SRC_SEL_1, input);
f4b8b3ae
MCC		 271
272 /* Svideo should enable YCrCb output and disable GPCL output
273 * For Composite and TV, it should be the reverse
274 */
6b8fe025 275 val = tvp5150_read(sd, TVP5150_MISC_CTL);
8cd0d4ca
DL		 276 if (val < 0) {
277 v4l2_err(sd, "%s: failed with error = %d\n", __func__, val);
278 return;
279 }
280
5325b427 281 if (decoder->input == TVP5150_SVIDEO)
f4b8b3ae
MCC		 282 val = (val & ~0x40) | 0x10;
283 else
284 val = (val & ~0x10) | 0x40;
6b8fe025 285 tvp5150_write(sd, TVP5150_MISC_CTL, val);
cd4665c5
MCC		 286};
287
e1bc80ad
MCC		 288struct i2c_reg_value {
289 unsigned char reg;
290 unsigned char value;
291};
292
293/* Default values as sugested at TVP5150AM1 datasheet */
294static const struct i2c_reg_value tvp5150_init_default[] = {
295 { /* 0x00 */
296 TVP5150_VD_IN_SRC_SEL_1,0x00
297 },
298 { /* 0x01 */
299 TVP5150_ANAL_CHL_CTL,0x15
300 },
301 { /* 0x02 */
302 TVP5150_OP_MODE_CTL,0x00
303 },
304 { /* 0x03 */
305 TVP5150_MISC_CTL,0x01
306 },
307 { /* 0x06 */
308 TVP5150_COLOR_KIL_THSH_CTL,0x10
309 },
310 { /* 0x07 */
311 TVP5150_LUMA_PROC_CTL_1,0x60
312 },
313 { /* 0x08 */
314 TVP5150_LUMA_PROC_CTL_2,0x00
315 },
316 { /* 0x09 */
317 TVP5150_BRIGHT_CTL,0x80
318 },
319 { /* 0x0a */
320 TVP5150_SATURATION_CTL,0x80
321 },
322 { /* 0x0b */
323 TVP5150_HUE_CTL,0x00
324 },
325 { /* 0x0c */
326 TVP5150_CONTRAST_CTL,0x80
327 },
328 { /* 0x0d */
329 TVP5150_DATA_RATE_SEL,0x47
330 },
331 { /* 0x0e */
332 TVP5150_LUMA_PROC_CTL_3,0x00
333 },
334 { /* 0x0f */
335 TVP5150_CONF_SHARED_PIN,0x08
336 },
337 { /* 0x11 */
338 TVP5150_ACT_VD_CROP_ST_MSB,0x00
339 },
340 { /* 0x12 */
341 TVP5150_ACT_VD_CROP_ST_LSB,0x00
342 },
343 { /* 0x13 */
344 TVP5150_ACT_VD_CROP_STP_MSB,0x00
345 },
346 { /* 0x14 */
347 TVP5150_ACT_VD_CROP_STP_LSB,0x00
348 },
349 { /* 0x15 */
350 TVP5150_GENLOCK,0x01
351 },
352 { /* 0x16 */
353 TVP5150_HORIZ_SYNC_START,0x80
354 },
355 { /* 0x18 */
356 TVP5150_VERT_BLANKING_START,0x00
357 },
358 { /* 0x19 */
359 TVP5150_VERT_BLANKING_STOP,0x00
360 },
361 { /* 0x1a */
362 TVP5150_CHROMA_PROC_CTL_1,0x0c
363 },
364 { /* 0x1b */
365 TVP5150_CHROMA_PROC_CTL_2,0x14
366 },
367 { /* 0x1c */
368 TVP5150_INT_RESET_REG_B,0x00
369 },
370 { /* 0x1d */
371 TVP5150_INT_ENABLE_REG_B,0x00
372 },
373 { /* 0x1e */
374 TVP5150_INTT_CONFIG_REG_B,0x00
375 },
376 { /* 0x28 */
377 TVP5150_VIDEO_STD,0x00
378 },
379 { /* 0x2e */
380 TVP5150_MACROVISION_ON_CTR,0x0f
381 },
382 { /* 0x2f */
383 TVP5150_MACROVISION_OFF_CTR,0x01
384 },
385 { /* 0xbb */
386 TVP5150_TELETEXT_FIL_ENA,0x00
387 },
388 { /* 0xc0 */
389 TVP5150_INT_STATUS_REG_A,0x00
390 },
391 { /* 0xc1 */
392 TVP5150_INT_ENABLE_REG_A,0x00
393 },
394 { /* 0xc2 */
395 TVP5150_INT_CONF,0x04
396 },
397 { /* 0xc8 */
398 TVP5150_FIFO_INT_THRESHOLD,0x80
399 },
400 { /* 0xc9 */
401 TVP5150_FIFO_RESET,0x00
402 },
403 { /* 0xca */
404 TVP5150_LINE_NUMBER_INT,0x00
405 },
406 { /* 0xcb */
407 TVP5150_PIX_ALIGN_REG_LOW,0x4e
408 },
409 { /* 0xcc */
410 TVP5150_PIX_ALIGN_REG_HIGH,0x00
411 },
412 { /* 0xcd */
413 TVP5150_FIFO_OUT_CTRL,0x01
414 },
415 { /* 0xcf */
3ad96835 416 TVP5150_FULL_FIELD_ENA,0x00
e1bc80ad
MCC		 417 },
418 { /* 0xd0 */
3ad96835 419 TVP5150_LINE_MODE_INI,0x00
e1bc80ad
MCC		 420 },
421 { /* 0xfc */
422 TVP5150_FULL_FIELD_MODE_REG,0x7f
423 },
424 { /* end of data */
425 0xff,0xff
426 }
427};
428
429/* Default values as sugested at TVP5150AM1 datasheet */
430static const struct i2c_reg_value tvp5150_init_enable[] = {
431 {
432 TVP5150_CONF_SHARED_PIN, 2
433 },{ /* Automatic offset and AGC enabled */
434 TVP5150_ANAL_CHL_CTL, 0x15
435 },{ /* Activate YCrCb output 0x9 or 0xd ? */
436 TVP5150_MISC_CTL, 0x6f
437 },{ /* Activates video std autodetection for all standards */
438 TVP5150_AUTOSW_MSK, 0x0
439 },{ /* Default format: 0x47. For 4:2:2: 0x40 */
440 TVP5150_DATA_RATE_SEL, 0x47
441 },{
442 TVP5150_CHROMA_PROC_CTL_1, 0x0c
443 },{
444 TVP5150_CHROMA_PROC_CTL_2, 0x54
445 },{ /* Non documented, but initialized on WinTV USB2 */
446 0x27, 0x20
447 },{
448 0xff,0xff
449 }
450};
451
6ac48b45
MCC		 452struct tvp5150_vbi_type {
453 unsigned int vbi_type;
454 unsigned int ini_line;
455 unsigned int end_line;
456 unsigned int by_field :1;
457};
458
e1bc80ad
MCC		 459struct i2c_vbi_ram_value {
460 u16 reg;
6ac48b45
MCC		 461 struct tvp5150_vbi_type type;
462 unsigned char values[16];
e1bc80ad
MCC		 463};
464
6ac48b45
MCC		 465/* This struct have the values for each supported VBI Standard
466 * by
467 tvp5150_vbi_types should follow the same order as vbi_ram_default
3ad96835
MCC		 468 * value 0 means rom position 0x10, value 1 means rom position 0x30
469 * and so on. There are 16 possible locations from 0 to 15.
470 */
3ad96835 471
a9cff90e 472static struct i2c_vbi_ram_value vbi_ram_default[] =
cd4665c5 473{
9bc7400a
HV		 474 /* FIXME: Current api doesn't handle all VBI types, those not
475 yet supported are placed under #if 0 */
476#if 0
6ac48b45
MCC		 477 {0x010, /* Teletext, SECAM, WST System A */
478 {V4L2_SLICED_TELETEXT_SECAM,6,23,1},
479 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
480 0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 481 },
9bc7400a 482#endif
6ac48b45 483 {0x030, /* Teletext, PAL, WST System B */
9bc7400a 484 {V4L2_SLICED_TELETEXT_B,6,22,1},
6ac48b45
MCC		 485 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
486 0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 487 },
9bc7400a 488#if 0
6ac48b45
MCC		 489 {0x050, /* Teletext, PAL, WST System C */
490 {V4L2_SLICED_TELETEXT_PAL_C,6,22,1},
491 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
492 0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 493 },
6ac48b45
MCC		 494 {0x070, /* Teletext, NTSC, WST System B */
495 {V4L2_SLICED_TELETEXT_NTSC_B,10,21,1},
496 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
497 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 498 },
6ac48b45
MCC		 499 {0x090, /* Tetetext, NTSC NABTS System C */
500 {V4L2_SLICED_TELETEXT_NTSC_C,10,21,1},
501 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
502 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
e1bc80ad 503 },
6ac48b45
MCC		 504 {0x0b0, /* Teletext, NTSC-J, NABTS System D */
505 {V4L2_SLICED_TELETEXT_NTSC_D,10,21,1},
506 { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
507 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 508 },
6ac48b45
MCC		 509 {0x0d0, /* Closed Caption, PAL/SECAM */
510 {V4L2_SLICED_CAPTION_625,22,22,1},
511 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
512 0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 513 },
9bc7400a 514#endif
6ac48b45
MCC		 515 {0x0f0, /* Closed Caption, NTSC */
516 {V4L2_SLICED_CAPTION_525,21,21,1},
517 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
518 0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 519 },
6ac48b45 520 {0x110, /* Wide Screen Signal, PAL/SECAM */
12db5607 521 {V4L2_SLICED_WSS_625,23,23,1},
6ac48b45
MCC		 522 { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
523 0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
e1bc80ad 524 },
9bc7400a 525#if 0
6ac48b45
MCC		 526 {0x130, /* Wide Screen Signal, NTSC C */
527 {V4L2_SLICED_WSS_525,20,20,1},
528 { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
529 0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
e1bc80ad 530 },
6ac48b45
MCC		 531 {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
532 {V4l2_SLICED_VITC_625,6,22,0},
533 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
534 0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 535 },
6ac48b45
MCC		 536 {0x170, /* Vertical Interval Timecode (VITC), NTSC */
537 {V4l2_SLICED_VITC_525,10,20,0},
538 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
539 0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 540 },
9bc7400a 541#endif
6ac48b45
MCC		 542 {0x190, /* Video Program System (VPS), PAL */
543 {V4L2_SLICED_VPS,16,16,0},
544 { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
545 0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
3ad96835 546 },
6ac48b45
MCC		 547 /* 0x1d0 User programmable */
548
549 /* End of struct */
550 { (u16)-1 }
e1bc80ad 551};
4c86f973 552
6b8fe025 553static int tvp5150_write_inittab(struct v4l2_subdev *sd,
6ac48b45 554 const struct i2c_reg_value *regs)
e1bc80ad
MCC		 555{
556 while (regs->reg != 0xff) {
6b8fe025 557 tvp5150_write(sd, regs->reg, regs->value);
e1bc80ad
MCC		 558 regs++;
559 }
560 return 0;
561}
84486d53 562
6b8fe025 563static int tvp5150_vdp_init(struct v4l2_subdev *sd,
6ac48b45 564 const struct i2c_vbi_ram_value *regs)
e1bc80ad
MCC		 565{
566 unsigned int i;
cd4665c5 567
e1bc80ad 568 /* Disable Full Field */
6b8fe025 569 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
cd4665c5 570
e1bc80ad 571 /* Before programming, Line mode should be at 0xff */
6b8fe025
HV		 572 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
573 tvp5150_write(sd, i, 0xff);
cd4665c5 574
e1bc80ad 575 /* Load Ram Table */
6b8fe025
HV		 576 while (regs->reg != (u16)-1) {
577 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
578 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
cd4665c5 579
6b8fe025
HV		 580 for (i = 0; i < 16; i++)
581 tvp5150_write(sd, TVP5150_VDP_CONF_RAM_DATA, regs->values[i]);
84486d53 582
e1bc80ad
MCC		 583 regs++;
584 }
585 return 0;
586}
cd4665c5 587
6ac48b45 588/* Fills VBI capabilities based on i2c_vbi_ram_value struct */
6b8fe025 589static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
6ac48b45
MCC		 590 struct v4l2_sliced_vbi_cap *cap)
591{
6b8fe025 592 const struct i2c_vbi_ram_value *regs = vbi_ram_default;
6ac48b45
MCC		 593 int line;
594
bccfa449 595 v4l2_dbg(1, debug, sd, "g_sliced_vbi_cap\n");
6ac48b45
MCC		 596 memset(cap, 0, sizeof *cap);
597
598 while (regs->reg != (u16)-1 ) {
599 for (line=regs->type.ini_line;line<=regs->type.end_line;line++) {
600 cap->service_lines[0][line] |= regs->type.vbi_type;
601 }
602 cap->service_set |= regs->type.vbi_type;
603
604 regs++;
605 }
6b8fe025 606 return 0;
6ac48b45
MCC		 607}
608
3ad96835
MCC		 609/* Set vbi processing
610 * type - one of tvp5150_vbi_types
611 * line - line to gather data
612 * fields: bit 0 field1, bit 1, field2
613 * flags (default=0xf0) is a bitmask, were set means:
614 * bit 7: enable filtering null bytes on CC
615 * bit 6: send data also to FIFO
616 * bit 5: don't allow data with errors on FIFO
617 * bit 4: enable ECC when possible
618 * pix_align = pix alignment:
619 * LSB = field1
620 * MSB = field2
621 */
6b8fe025 622static int tvp5150_set_vbi(struct v4l2_subdev *sd,
2701dacb
MCC		 623 const struct i2c_vbi_ram_value *regs,
624 unsigned int type,u8 flags, int line,
625 const int fields)
3ad96835 626{
6b8fe025
HV		 627 struct tvp5150 *decoder = to_tvp5150(sd);
628 v4l2_std_id std = decoder->norm;
3ad96835 629 u8 reg;
2701dacb 630 int pos=0;
3ad96835
MCC		 631
632 if (std == V4L2_STD_ALL) {
6b8fe025 633 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 634 return 0;
7d5b7b98 635 } else if (std & V4L2_STD_625_50) {
3ad96835
MCC		 636 /* Don't follow NTSC Line number convension */
637 line += 3;
638 }
639
640 if (line<6||line>27)
2701dacb
MCC		 641 return 0;
642
643 while (regs->reg != (u16)-1 ) {
644 if ((type & regs->type.vbi_type) &&
645 (line>=regs->type.ini_line) &&
646 (line<=regs->type.end_line)) {
647 type=regs->type.vbi_type;
648 break;
649 }
650
651 regs++;
652 pos++;
653 }
654 if (regs->reg == (u16)-1)
655 return 0;
3ad96835 656
2701dacb 657 type=pos | (flags & 0xf0);
3ad96835
MCC		 658 reg=((line-6)<<1)+TVP5150_LINE_MODE_INI;
659
660 if (fields&1) {
6b8fe025 661 tvp5150_write(sd, reg, type);
3ad96835
MCC		 662 }
663
664 if (fields&2) {
6b8fe025 665 tvp5150_write(sd, reg+1, type);
3ad96835
MCC		 666 }
667
2701dacb 668 return type;
3ad96835
MCC		 669}
670
6b8fe025 671static int tvp5150_get_vbi(struct v4l2_subdev *sd,
12db5607
MCC		 672 const struct i2c_vbi_ram_value *regs, int line)
673{
6b8fe025
HV		 674 struct tvp5150 *decoder = to_tvp5150(sd);
675 v4l2_std_id std = decoder->norm;
12db5607 676 u8 reg;
6b8fe025 677 int pos, type = 0;
8cd0d4ca 678 int i, ret = 0;
12db5607
MCC		 679
680 if (std == V4L2_STD_ALL) {
6b8fe025 681 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 682 return 0;
7d5b7b98 683 } else if (std & V4L2_STD_625_50) {
12db5607
MCC		 684 /* Don't follow NTSC Line number convension */
685 line += 3;
686 }
687
6b8fe025 688 if (line < 6 || line > 27)
12db5607
MCC		 689 return 0;
690
6b8fe025 691 reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
12db5607 692
8cd0d4ca
DL		 693 for (i = 0; i <= 1; i++) {
694 ret = tvp5150_read(sd, reg + i);
695 if (ret < 0) {
696 v4l2_err(sd, "%s: failed with error = %d\n",
697 __func__, ret);
698 return 0;
699 }
700 pos = ret & 0x0f;
701 if (pos < 0x0f)
702 type |= regs[pos].type.vbi_type;
703 }
12db5607
MCC		 704
705 return type;
706}
6b8fe025
HV		 707
708static int tvp5150_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
e1bc80ad 709{
6b8fe025
HV		 710 struct tvp5150 *decoder = to_tvp5150(sd);
711 int fmt = 0;
e1bc80ad 712
6b8fe025 713 decoder->norm = std;
e1bc80ad
MCC		 714
715 /* First tests should be against specific std */
716
26811ae0 717 if (std == V4L2_STD_NTSC_443) {
2da12fcb 718 fmt = VIDEO_STD_NTSC_4_43_BIT;
26811ae0 719 } else if (std == V4L2_STD_PAL_M) {
2da12fcb 720 fmt = VIDEO_STD_PAL_M_BIT;
26811ae0 721 } else if (std == V4L2_STD_PAL_N || std == V4L2_STD_PAL_Nc) {
2da12fcb 722 fmt = VIDEO_STD_PAL_COMBINATION_N_BIT;
e1bc80ad
MCC		 723 } else {
724 /* Then, test against generic ones */
6b8fe025 725 if (std & V4L2_STD_NTSC)
2da12fcb 726 fmt = VIDEO_STD_NTSC_MJ_BIT;
6b8fe025 727 else if (std & V4L2_STD_PAL)
2da12fcb 728 fmt = VIDEO_STD_PAL_BDGHIN_BIT;
6b8fe025 729 else if (std & V4L2_STD_SECAM)
2da12fcb 730 fmt = VIDEO_STD_SECAM_BIT;
e1bc80ad 731 }
84486d53 732
6b8fe025
HV		 733 v4l2_dbg(1, debug, sd, "Set video std register to %d.\n", fmt);
734 tvp5150_write(sd, TVP5150_VIDEO_STD, fmt);
e1bc80ad
MCC		 735 return 0;
736}
737
6b8fe025
HV		 738static int tvp5150_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
739{
740 struct tvp5150 *decoder = to_tvp5150(sd);
741
742 if (decoder->norm == std)
743 return 0;
744
963ddc63
JM		 745 /* Change cropping height limits */
746 if (std & V4L2_STD_525_60)
747 decoder->rect.height = TVP5150_V_MAX_525_60;
748 else
749 decoder->rect.height = TVP5150_V_MAX_OTHERS;
750
751
6b8fe025
HV		 752 return tvp5150_set_std(sd, std);
753}
754
755static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
e1bc80ad 756{
6b8fe025 757 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 758
e1bc80ad 759 /* Initializes TVP5150 to its default values */
6b8fe025 760 tvp5150_write_inittab(sd, tvp5150_init_default);
e1bc80ad
MCC		 761
762 /* Initializes VDP registers */
6b8fe025 763 tvp5150_vdp_init(sd, vbi_ram_default);
e1bc80ad
MCC		 764
765 /* Selects decoder input */
6b8fe025 766 tvp5150_selmux(sd);
e1bc80ad
MCC		 767
768 /* Initializes TVP5150 to stream enabled values */
6b8fe025 769 tvp5150_write_inittab(sd, tvp5150_init_enable);
e1bc80ad
MCC		 770
771 /* Initialize image preferences */
6c45ec71 772 v4l2_ctrl_handler_setup(&decoder->hdl);
e1bc80ad 773
6b8fe025
HV		 774 tvp5150_set_std(sd, decoder->norm);
775 return 0;
cd4665c5
MCC		 776};
777
6c45ec71 778static int tvp5150_s_ctrl(struct v4l2_ctrl *ctrl)
a6c2ba28 779{
6c45ec71 780 struct v4l2_subdev *sd = to_sd(ctrl);
a6c2ba28 781
782 switch (ctrl->id) {
783 case V4L2_CID_BRIGHTNESS:
6c45ec71 784 tvp5150_write(sd, TVP5150_BRIGHT_CTL, ctrl->val);
a6c2ba28 785 return 0;
786 case V4L2_CID_CONTRAST:
6c45ec71 787 tvp5150_write(sd, TVP5150_CONTRAST_CTL, ctrl->val);
a6c2ba28 788 return 0;
789 case V4L2_CID_SATURATION:
6c45ec71 790 tvp5150_write(sd, TVP5150_SATURATION_CTL, ctrl->val);
a6c2ba28 791 return 0;
792 case V4L2_CID_HUE:
6c45ec71 793 tvp5150_write(sd, TVP5150_HUE_CTL, ctrl->val);
a6c2ba28 794 return 0;
a6c2ba28 795 }
c0477ad9 796 return -EINVAL;
a6c2ba28 797}
798
ec2c4f3f
JM		 799static v4l2_std_id tvp5150_read_std(struct v4l2_subdev *sd)
800{
801 int val = tvp5150_read(sd, TVP5150_STATUS_REG_5);
802
803 switch (val & 0x0F) {
804 case 0x01:
805 return V4L2_STD_NTSC;
806 case 0x03:
807 return V4L2_STD_PAL;
808 case 0x05:
809 return V4L2_STD_PAL_M;
810 case 0x07:
811 return V4L2_STD_PAL_N | V4L2_STD_PAL_Nc;
812 case 0x09:
813 return V4L2_STD_NTSC_443;
814 case 0xb:
815 return V4L2_STD_SECAM;
816 default:
817 return V4L2_STD_UNKNOWN;
818 }
819}
820
ebcff5fc
HV		 821static int tvp5150_enum_mbus_code(struct v4l2_subdev *sd,
822 struct v4l2_subdev_pad_config *cfg,
823 struct v4l2_subdev_mbus_code_enum *code)
ec2c4f3f 824{
ebcff5fc 825 if (code->pad || code->index)
ec2c4f3f
JM		 826 return -EINVAL;
827
ebcff5fc 828 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
ec2c4f3f
JM		 829 return 0;
830}
831
da298c6d
HV		 832static int tvp5150_fill_fmt(struct v4l2_subdev *sd,
833 struct v4l2_subdev_pad_config *cfg,
834 struct v4l2_subdev_format *format)
ec2c4f3f 835{
da298c6d 836 struct v4l2_mbus_framefmt *f;
ec2c4f3f 837 struct tvp5150 *decoder = to_tvp5150(sd);
ec2c4f3f 838
da298c6d 839 if (!format || format->pad)
ec2c4f3f
JM		 840 return -EINVAL;
841
da298c6d
HV		 842 f = &format->format;
843
ec2c4f3f
JM		 844 tvp5150_reset(sd, 0);
845
963ddc63
JM		 846 f->width = decoder->rect.width;
847 f->height = decoder->rect.height;
ec2c4f3f 848
f5fe58fd 849 f->code = MEDIA_BUS_FMT_UYVY8_2X8;
ec2c4f3f
JM		 850 f->field = V4L2_FIELD_SEQ_TB;
851 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
852
853 v4l2_dbg(1, debug, sd, "width = %d, height = %d\n", f->width,
854 f->height);
855 return 0;
856}
857
4f996594 858static int tvp5150_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
963ddc63
JM		 859{
860 struct v4l2_rect rect = a->c;
861 struct tvp5150 *decoder = to_tvp5150(sd);
862 v4l2_std_id std;
f90580ca 863 unsigned int hmax;
963ddc63
JM		 864
865 v4l2_dbg(1, debug, sd, "%s left=%d, top=%d, width=%d, height=%d\n",
866 __func__, rect.left, rect.top, rect.width, rect.height);
867
868 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
869 return -EINVAL;
870
871 /* tvp5150 has some special limits */
872 rect.left = clamp(rect.left, 0, TVP5150_MAX_CROP_LEFT);
f90580ca
RR		 873 rect.width = clamp_t(unsigned int, rect.width,
874 TVP5150_H_MAX - TVP5150_MAX_CROP_LEFT - rect.left,
875 TVP5150_H_MAX - rect.left);
963ddc63
JM		 876 rect.top = clamp(rect.top, 0, TVP5150_MAX_CROP_TOP);
877
878 /* Calculate height based on current standard */
879 if (decoder->norm == V4L2_STD_ALL)
880 std = tvp5150_read_std(sd);
881 else
882 std = decoder->norm;
883
884 if (std & V4L2_STD_525_60)
885 hmax = TVP5150_V_MAX_525_60;
886 else
887 hmax = TVP5150_V_MAX_OTHERS;
888
f90580ca
RR		 889 rect.height = clamp_t(unsigned int, rect.height,
890 hmax - TVP5150_MAX_CROP_TOP - rect.top,
891 hmax - rect.top);
963ddc63
JM		 892
893 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, rect.top);
894 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP,
895 rect.top + rect.height - hmax);
896 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_MSB,
897 rect.left >> TVP5150_CROP_SHIFT);
898 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_LSB,
899 rect.left | (1 << TVP5150_CROP_SHIFT));
900 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_MSB,
901 (rect.left + rect.width - TVP5150_MAX_CROP_LEFT) >>
902 TVP5150_CROP_SHIFT);
903 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_LSB,
904 rect.left + rect.width - TVP5150_MAX_CROP_LEFT);
905
906 decoder->rect = rect;
907
908 return 0;
909}
910
911static int tvp5150_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
912{
12bd10c7 913 struct tvp5150 *decoder = to_tvp5150(sd);
963ddc63
JM		 914
915 a->c = decoder->rect;
916 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
917
918 return 0;
919}
920
921static int tvp5150_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
922{
12bd10c7 923 struct tvp5150 *decoder = to_tvp5150(sd);
963ddc63
JM		 924 v4l2_std_id std;
925
926 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
927 return -EINVAL;
928
929 a->bounds.left = 0;
930 a->bounds.top = 0;
931 a->bounds.width = TVP5150_H_MAX;
932
933 /* Calculate height based on current standard */
934 if (decoder->norm == V4L2_STD_ALL)
935 std = tvp5150_read_std(sd);
936 else
937 std = decoder->norm;
938
939 if (std & V4L2_STD_525_60)
940 a->bounds.height = TVP5150_V_MAX_525_60;
941 else
942 a->bounds.height = TVP5150_V_MAX_OTHERS;
943
944 a->defrect = a->bounds;
945 a->pixelaspect.numerator = 1;
946 a->pixelaspect.denominator = 1;
947
948 return 0;
949}
950
84486d53
MCC		 951/****************************************************************************
952 I2C Command
953 ****************************************************************************/
c7c0b34c 954
5325b427
HV		 955static int tvp5150_s_routing(struct v4l2_subdev *sd,
956 u32 input, u32 output, u32 config)
6b8fe025
HV		 957{
958 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 959
5325b427
HV		 960 decoder->input = input;
961 decoder->output = output;
6b8fe025
HV		 962 tvp5150_selmux(sd);
963 return 0;
964}
6ac48b45 965
d37dad49
HV		 966static int tvp5150_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
967{
968 /* this is for capturing 36 raw vbi lines
969 if there's a way to cut off the beginning 2 vbi lines
970 with the tvp5150 then the vbi line count could be lowered
971 to 17 lines/field again, although I couldn't find a register
972 which could do that cropping */
973 if (fmt->sample_format == V4L2_PIX_FMT_GREY)
974 tvp5150_write(sd, TVP5150_LUMA_PROC_CTL_1, 0x70);
975 if (fmt->count[0] == 18 && fmt->count[1] == 18) {
976 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, 0x00);
977 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP, 0x01);
978 }
979 return 0;
980}
981
982static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
6b8fe025 983{
6b8fe025
HV		 984 int i;
985
6b8fe025
HV		 986 if (svbi->service_set != 0) {
987 for (i = 0; i <= 23; i++) {
988 svbi->service_lines[1][i] = 0;
989 svbi->service_lines[0][i] =
990 tvp5150_set_vbi(sd, vbi_ram_default,
991 svbi->service_lines[0][i], 0xf0, i, 3);
2c5aacc6 992 }
6b8fe025
HV		 993 /* Enables FIFO */
994 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 1);
995 } else {
996 /* Disables FIFO*/
997 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 0);
12db5607 998
6b8fe025
HV		 999 /* Disable Full Field */
1000 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
12db5607 1001
6b8fe025
HV		 1002 /* Disable Line modes */
1003 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
1004 tvp5150_write(sd, i, 0xff);
12db5607 1005 }
6b8fe025
HV		 1006 return 0;
1007}
12db5607 1008
d37dad49
HV		 1009static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
1010{
1011 int i, mask = 0;
1012
30634e8e 1013 memset(svbi->service_lines, 0, sizeof(svbi->service_lines));
12db5607 1014
6b8fe025
HV		 1015 for (i = 0; i <= 23; i++) {
1016 svbi->service_lines[0][i] =
1017 tvp5150_get_vbi(sd, vbi_ram_default, i);
1018 mask |= svbi->service_lines[0][i];
2701dacb 1019 }
6b8fe025
HV		 1020 svbi->service_set = mask;
1021 return 0;
1022}
1023
21dcd8cc 1024#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1025static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025 1026{
8cd0d4ca
DL		 1027 int res;
1028
8cd0d4ca
DL		 1029 res = tvp5150_read(sd, reg->reg & 0xff);
1030 if (res < 0) {
1031 v4l2_err(sd, "%s: failed with error = %d\n", __func__, res);
1032 return res;
1033 }
1034
1035 reg->val = res;
aecde8b5 1036 reg->size = 1;
6b8fe025
HV		 1037 return 0;
1038}
84486d53 1039
977ba3b1 1040static int tvp5150_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
6b8fe025 1041{
6b8fe025
HV		 1042 tvp5150_write(sd, reg->reg & 0xff, reg->val & 0xff);
1043 return 0;
1044}
1045#endif
a6c2ba28 1046
6b8fe025
HV		 1047static int tvp5150_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1048{
1049 int status = tvp5150_read(sd, 0x88);
a6c2ba28 1050
6b8fe025
HV		 1051 vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
1052 return 0;
1053}
a6c2ba28 1054
6b8fe025
HV		 1055/* ----------------------------------------------------------------------- */
1056
6c45ec71
HV		 1057static const struct v4l2_ctrl_ops tvp5150_ctrl_ops = {
1058 .s_ctrl = tvp5150_s_ctrl,
1059};
1060
6b8fe025
HV		 1061static const struct v4l2_subdev_core_ops tvp5150_core_ops = {
1062 .log_status = tvp5150_log_status,
6b8fe025
HV		 1063 .reset = tvp5150_reset,
1064#ifdef CONFIG_VIDEO_ADV_DEBUG
1065 .g_register = tvp5150_g_register,
1066 .s_register = tvp5150_s_register,
1067#endif
1068};
1069
1070static const struct v4l2_subdev_tuner_ops tvp5150_tuner_ops = {
6b8fe025
HV		 1071 .g_tuner = tvp5150_g_tuner,
1072};
1073
1074static const struct v4l2_subdev_video_ops tvp5150_video_ops = {
8774bed9 1075 .s_std = tvp5150_s_std,
6b8fe025 1076 .s_routing = tvp5150_s_routing,
963ddc63
JM		 1077 .s_crop = tvp5150_s_crop,
1078 .g_crop = tvp5150_g_crop,
1079 .cropcap = tvp5150_cropcap,
32cd527f
HV		 1080};
1081
1082static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {
6b8fe025 1083 .g_sliced_vbi_cap = tvp5150_g_sliced_vbi_cap,
d37dad49
HV		 1084 .g_sliced_fmt = tvp5150_g_sliced_fmt,
1085 .s_sliced_fmt = tvp5150_s_sliced_fmt,
1086 .s_raw_fmt = tvp5150_s_raw_fmt,
6b8fe025
HV		 1087};
1088
ebcff5fc
HV		 1089static const struct v4l2_subdev_pad_ops tvp5150_pad_ops = {
1090 .enum_mbus_code = tvp5150_enum_mbus_code,
da298c6d
HV		 1091 .set_fmt = tvp5150_fill_fmt,
1092 .get_fmt = tvp5150_fill_fmt,
ebcff5fc
HV		 1093};
1094
6b8fe025
HV		 1095static const struct v4l2_subdev_ops tvp5150_ops = {
1096 .core = &tvp5150_core_ops,
1097 .tuner = &tvp5150_tuner_ops,
1098 .video = &tvp5150_video_ops,
32cd527f 1099 .vbi = &tvp5150_vbi_ops,
ebcff5fc 1100 .pad = &tvp5150_pad_ops,
6b8fe025
HV		 1101};
1102
1103
cd4665c5
MCC		 1104/****************************************************************************
1105 I2C Client & Driver
1106 ****************************************************************************/
cd4665c5 1107
6b8fe025
HV		 1108static int tvp5150_probe(struct i2c_client *c,
1109 const struct i2c_device_id *id)
cd4665c5 1110{
cd4665c5 1111 struct tvp5150 *core;
6b8fe025 1112 struct v4l2_subdev *sd;
8cd0d4ca
DL		 1113 int tvp5150_id[4];
1114 int i, res;
cd4665c5
MCC		 1115
1116 /* Check if the adapter supports the needed features */
6b8fe025 1117 if (!i2c_check_functionality(c->adapter,
cd4665c5 1118 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
6b8fe025 1119 return -EIO;
cd4665c5 1120
c02b211d
LP		 1121 core = devm_kzalloc(&c->dev, sizeof(*core), GFP_KERNEL);
1122 if (!core)
cd4665c5 1123 return -ENOMEM;
6b8fe025
HV		 1124 sd = &core->sd;
1125 v4l2_i2c_subdev_init(sd, c, &tvp5150_ops);
8cd0d4ca
DL		 1126
1127 /*
1128 * Read consequent registers - TVP5150_MSB_DEV_ID, TVP5150_LSB_DEV_ID,
1129 * TVP5150_ROM_MAJOR_VER, TVP5150_ROM_MINOR_VER
1130 */
1131 for (i = 0; i < 4; i++) {
1132 res = tvp5150_read(sd, TVP5150_MSB_DEV_ID + i);
1133 if (res < 0)
c02b211d 1134 return res;
8cd0d4ca
DL		 1135 tvp5150_id[i] = res;
1136 }
1137
6b8fe025
HV		 1138 v4l_info(c, "chip found @ 0x%02x (%s)\n",
1139 c->addr << 1, c->adapter->name);
cd4665c5 1140
8cd0d4ca
DL		 1141 if (tvp5150_id[2] == 4 && tvp5150_id[3] == 0) { /* Is TVP5150AM1 */
1142 v4l2_info(sd, "tvp%02x%02xam1 detected.\n",
1143 tvp5150_id[0], tvp5150_id[1]);
0e09a3c9
MCC		 1144
1145 /* ITU-T BT.656.4 timing */
1146 tvp5150_write(sd, TVP5150_REV_SELECT, 0);
1147 } else {
8cd0d4ca
DL		 1148 /* Is TVP5150A */
1149 if (tvp5150_id[2] == 3 || tvp5150_id[3] == 0x21) {
1150 v4l2_info(sd, "tvp%02x%02xa detected.\n",
385dded8 1151 tvp5150_id[0], tvp5150_id[1]);
0e09a3c9
MCC		 1152 } else {
1153 v4l2_info(sd, "*** unknown tvp%02x%02x chip detected.\n",
385dded8 1154 tvp5150_id[0], tvp5150_id[1]);
8cd0d4ca
DL		 1155 v4l2_info(sd, "*** Rom ver is %d.%d\n",
1156 tvp5150_id[2], tvp5150_id[3]);
0e09a3c9
MCC		 1157 }
1158 }
1159
3ad96835 1160 core->norm = V4L2_STD_ALL; /* Default is autodetect */
5325b427 1161 core->input = TVP5150_COMPOSITE1;
4c86f973 1162 core->enable = 1;
6c45ec71
HV		 1163
1164 v4l2_ctrl_handler_init(&core->hdl, 4);
1165 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1166 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1167 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1168 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1169 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1170 V4L2_CID_SATURATION, 0, 255, 1, 128);
1171 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1172 V4L2_CID_HUE, -128, 127, 1, 0);
1173 sd->ctrl_handler = &core->hdl;
1174 if (core->hdl.error) {
8cd0d4ca 1175 res = core->hdl.error;
c7d97499 1176 goto err;
6c45ec71
HV		 1177 }
1178 v4l2_ctrl_handler_setup(&core->hdl);
4c86f973 1179
963ddc63
JM		 1180 /* Default is no cropping */
1181 core->rect.top = 0;
1182 if (tvp5150_read_std(sd) & V4L2_STD_525_60)
1183 core->rect.height = TVP5150_V_MAX_525_60;
1184 else
1185 core->rect.height = TVP5150_V_MAX_OTHERS;
1186 core->rect.left = 0;
1187 core->rect.width = TVP5150_H_MAX;
1188
c7d97499
JMC		 1189 res = v4l2_async_register_subdev(sd);
1190 if (res < 0)
1191 goto err;
1192
f1e5ee45 1193 if (debug > 1)
6b8fe025 1194 tvp5150_log_status(sd);
cd4665c5 1195 return 0;
c7d97499
JMC		 1196
1197err:
1198 v4l2_ctrl_handler_free(&core->hdl);
1199 return res;
cd4665c5
MCC		 1200}
1201
6b8fe025 1202static int tvp5150_remove(struct i2c_client *c)
cd4665c5 1203{
6b8fe025 1204 struct v4l2_subdev *sd = i2c_get_clientdata(c);
6c45ec71 1205 struct tvp5150 *decoder = to_tvp5150(sd);
cd4665c5 1206
6b8fe025 1207 v4l2_dbg(1, debug, sd,
e1bc80ad
MCC		 1208 "tvp5150.c: removing tvp5150 adapter on address 0x%x\n",
1209 c->addr << 1);
1210
c7d97499 1211 v4l2_async_unregister_subdev(sd);
6c45ec71 1212 v4l2_ctrl_handler_free(&decoder->hdl);
cd4665c5
MCC		 1213 return 0;
1214}
1215
1216/* ----------------------------------------------------------------------- */
1217
6b8fe025
HV		 1218static const struct i2c_device_id tvp5150_id[] = {
1219 { "tvp5150", 0 },
1220 { }
1221};
1222MODULE_DEVICE_TABLE(i2c, tvp5150_id);
84486d53 1223
c771145b
HV		 1224static struct i2c_driver tvp5150_driver = {
1225 .driver = {
c771145b
HV		 1226 .name = "tvp5150",
1227 },
1228 .probe = tvp5150_probe,
1229 .remove = tvp5150_remove,
1230 .id_table = tvp5150_id,
cd4665c5 1231};
c771145b 1232
c6e8d86f 1233module_i2c_driver(tvp5150_driver);
Linux kernel - Deliverables
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