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[media] v4l2-async: call registered_async after subdev registration
[deliverable/linux.git] / drivers / media / i2c / tvp5150.c
CommitLineData
cd4665c5 1/*
6ac48b45 2 * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder driver
cd4665c5 3 *
6ac48b45
MCC		 4 * Copyright (c) 2005,2006 Mauro Carvalho Chehab (mchehab@infradead.org)
5 * This code is placed under the terms of the GNU General Public License v2
cd4665c5
MCC		 6 */
7
cd4665c5 8#include <linux/i2c.h>
5a0e3ad6 9#include <linux/slab.h>
33b687cf 10#include <linux/videodev2.h>
cd4665c5 11#include <linux/delay.h>
09aa2609 12#include <linux/gpio/consumer.h>
7a707b89 13#include <linux/module.h>
c7d97499 14#include <media/v4l2-async.h>
6b8fe025 15#include <media/v4l2-device.h>
b5dcee22 16#include <media/i2c/tvp5150.h>
6c45ec71 17#include <media/v4l2-ctrls.h>
a2e5f1b3 18#include <media/v4l2-of.h>
55606310 19#include <media/v4l2-mc.h>
cd4665c5
MCC		 20
21#include "tvp5150_reg.h"
22
785a3de1
PZ		 23#define TVP5150_H_MAX 720U
24#define TVP5150_V_MAX_525_60 480U
25#define TVP5150_V_MAX_OTHERS 576U
963ddc63
JM		 26#define TVP5150_MAX_CROP_LEFT 511
27#define TVP5150_MAX_CROP_TOP 127
28#define TVP5150_CROP_SHIFT 2
29
6ac48b45 30MODULE_DESCRIPTION("Texas Instruments TVP5150A video decoder driver");
cd4665c5
MCC		 31MODULE_AUTHOR("Mauro Carvalho Chehab");
32MODULE_LICENSE("GPL");
33
cd4665c5 34
ff699e6b 35static int debug;
2a0489d3 36module_param(debug, int, 0644);
6b8fe025 37MODULE_PARM_DESC(debug, "Debug level (0-2)");
cd4665c5
MCC		 38
39struct tvp5150 {
6b8fe025 40 struct v4l2_subdev sd;
55606310
MCC		 41#ifdef CONFIG_MEDIA_CONTROLLER
42 struct media_pad pads[DEMOD_NUM_PADS];
43#endif
6c45ec71 44 struct v4l2_ctrl_handler hdl;
963ddc63 45 struct v4l2_rect rect;
84486d53 46
3ad96835 47 v4l2_std_id norm; /* Current set standard */
5325b427
HV		 48 u32 input;
49 u32 output;
84486d53 50 int enable;
a2e5f1b3
JMC		 51
52 enum v4l2_mbus_type mbus_type;
cd4665c5
MCC		 53};
54
6b8fe025 55static inline struct tvp5150 *to_tvp5150(struct v4l2_subdev *sd)
cd4665c5 56{
6b8fe025
HV		 57 return container_of(sd, struct tvp5150, sd);
58}
59
6c45ec71
HV		 60static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
61{
62 return &container_of(ctrl->handler, struct tvp5150, hdl)->sd;
63}
64
6b8fe025
HV		 65static int tvp5150_read(struct v4l2_subdev *sd, unsigned char addr)
66{
67 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 68 int rc;
e35ce2e4
LP		 69
70 rc = i2c_smbus_read_byte_data(c, addr);
71 if (rc < 0) {
72 v4l2_err(sd, "i2c i/o error: rc == %d\n", rc);
73 return rc;
8cd0d4ca 74 }
e1bc80ad 75
e35ce2e4 76 v4l2_dbg(2, debug, sd, "tvp5150: read 0x%02x = 0x%02x\n", addr, rc);
cd4665c5 77
e35ce2e4 78 return rc;
cd4665c5
MCC		 79}
80
6b8fe025 81static inline void tvp5150_write(struct v4l2_subdev *sd, unsigned char addr,
84486d53 82 unsigned char value)
cd4665c5 83{
6b8fe025 84 struct i2c_client *c = v4l2_get_subdevdata(sd);
cd4665c5 85 int rc;
cd4665c5 86
e35ce2e4
LP		 87 v4l2_dbg(2, debug, sd, "tvp5150: writing 0x%02x 0x%02x\n", addr, value);
88 rc = i2c_smbus_write_byte_data(c, addr, value);
89 if (rc < 0)
90 v4l2_dbg(0, debug, sd, "i2c i/o error: rc == %d\n", rc);
cd4665c5
MCC		 91}
92
6b8fe025
HV		 93static void dump_reg_range(struct v4l2_subdev *sd, char *s, u8 init,
94 const u8 end, int max_line)
3ad96835 95{
6b8fe025 96 int i = 0;
3ad96835 97
6b8fe025
HV		 98 while (init != (u8)(end + 1)) {
99 if ((i % max_line) == 0) {
100 if (i > 0)
3ad96835 101 printk("\n");
6b8fe025 102 printk("tvp5150: %s reg 0x%02x = ", s, init);
3ad96835 103 }
6b8fe025 104 printk("%02x ", tvp5150_read(sd, init));
3ad96835
MCC		 105
106 init++;
107 i++;
108 }
109 printk("\n");
110}
111
6b8fe025 112static int tvp5150_log_status(struct v4l2_subdev *sd)
cd4665c5 113{
84486d53 114 printk("tvp5150: Video input source selection #1 = 0x%02x\n",
6b8fe025 115 tvp5150_read(sd, TVP5150_VD_IN_SRC_SEL_1));
84486d53 116 printk("tvp5150: Analog channel controls = 0x%02x\n",
6b8fe025 117 tvp5150_read(sd, TVP5150_ANAL_CHL_CTL));
84486d53 118 printk("tvp5150: Operation mode controls = 0x%02x\n",
6b8fe025 119 tvp5150_read(sd, TVP5150_OP_MODE_CTL));
84486d53 120 printk("tvp5150: Miscellaneous controls = 0x%02x\n",
6b8fe025 121 tvp5150_read(sd, TVP5150_MISC_CTL));
3ad96835 122 printk("tvp5150: Autoswitch mask= 0x%02x\n",
6b8fe025 123 tvp5150_read(sd, TVP5150_AUTOSW_MSK));
84486d53 124 printk("tvp5150: Color killer threshold control = 0x%02x\n",
6b8fe025 125 tvp5150_read(sd, TVP5150_COLOR_KIL_THSH_CTL));
3ad96835 126 printk("tvp5150: Luminance processing controls #1 #2 and #3 = %02x %02x %02x\n",
6b8fe025
HV		 127 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_1),
128 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_2),
129 tvp5150_read(sd, TVP5150_LUMA_PROC_CTL_3));
84486d53 130 printk("tvp5150: Brightness control = 0x%02x\n",
6b8fe025 131 tvp5150_read(sd, TVP5150_BRIGHT_CTL));
84486d53 132 printk("tvp5150: Color saturation control = 0x%02x\n",
6b8fe025 133 tvp5150_read(sd, TVP5150_SATURATION_CTL));
84486d53 134 printk("tvp5150: Hue control = 0x%02x\n",
6b8fe025 135 tvp5150_read(sd, TVP5150_HUE_CTL));
84486d53 136 printk("tvp5150: Contrast control = 0x%02x\n",
6b8fe025 137 tvp5150_read(sd, TVP5150_CONTRAST_CTL));
84486d53 138 printk("tvp5150: Outputs and data rates select = 0x%02x\n",
6b8fe025 139 tvp5150_read(sd, TVP5150_DATA_RATE_SEL));
84486d53 140 printk("tvp5150: Configuration shared pins = 0x%02x\n",
6b8fe025 141 tvp5150_read(sd, TVP5150_CONF_SHARED_PIN));
3ad96835 142 printk("tvp5150: Active video cropping start = 0x%02x%02x\n",
6b8fe025
HV		 143 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_MSB),
144 tvp5150_read(sd, TVP5150_ACT_VD_CROP_ST_LSB));
3ad96835 145 printk("tvp5150: Active video cropping stop = 0x%02x%02x\n",
6b8fe025
HV		 146 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_MSB),
147 tvp5150_read(sd, TVP5150_ACT_VD_CROP_STP_LSB));
84486d53 148 printk("tvp5150: Genlock/RTC = 0x%02x\n",
6b8fe025 149 tvp5150_read(sd, TVP5150_GENLOCK));
84486d53 150 printk("tvp5150: Horizontal sync start = 0x%02x\n",
6b8fe025 151 tvp5150_read(sd, TVP5150_HORIZ_SYNC_START));
84486d53 152 printk("tvp5150: Vertical blanking start = 0x%02x\n",
6b8fe025 153 tvp5150_read(sd, TVP5150_VERT_BLANKING_START));
84486d53 154 printk("tvp5150: Vertical blanking stop = 0x%02x\n",
6b8fe025 155 tvp5150_read(sd, TVP5150_VERT_BLANKING_STOP));
3ad96835 156 printk("tvp5150: Chrominance processing control #1 and #2 = %02x %02x\n",
6b8fe025
HV		 157 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_1),
158 tvp5150_read(sd, TVP5150_CHROMA_PROC_CTL_2));
84486d53 159 printk("tvp5150: Interrupt reset register B = 0x%02x\n",
6b8fe025 160 tvp5150_read(sd, TVP5150_INT_RESET_REG_B));
84486d53 161 printk("tvp5150: Interrupt enable register B = 0x%02x\n",
6b8fe025 162 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_B));
84486d53 163 printk("tvp5150: Interrupt configuration register B = 0x%02x\n",
6b8fe025 164 tvp5150_read(sd, TVP5150_INTT_CONFIG_REG_B));
84486d53 165 printk("tvp5150: Video standard = 0x%02x\n",
6b8fe025 166 tvp5150_read(sd, TVP5150_VIDEO_STD));
3ad96835 167 printk("tvp5150: Chroma gain factor: Cb=0x%02x Cr=0x%02x\n",
6b8fe025
HV		 168 tvp5150_read(sd, TVP5150_CB_GAIN_FACT),
169 tvp5150_read(sd, TVP5150_CR_GAIN_FACTOR));
84486d53 170 printk("tvp5150: Macrovision on counter = 0x%02x\n",
6b8fe025 171 tvp5150_read(sd, TVP5150_MACROVISION_ON_CTR));
84486d53 172 printk("tvp5150: Macrovision off counter = 0x%02x\n",
6b8fe025 173 tvp5150_read(sd, TVP5150_MACROVISION_OFF_CTR));
3ad96835 174 printk("tvp5150: ITU-R BT.656.%d timing(TVP5150AM1 only)\n",
6b8fe025 175 (tvp5150_read(sd, TVP5150_REV_SELECT) & 1) ? 3 : 4);
3ad96835 176 printk("tvp5150: Device ID = %02x%02x\n",
6b8fe025
HV		 177 tvp5150_read(sd, TVP5150_MSB_DEV_ID),
178 tvp5150_read(sd, TVP5150_LSB_DEV_ID));
3ad96835 179 printk("tvp5150: ROM version = (hex) %02x.%02x\n",
6b8fe025
HV		 180 tvp5150_read(sd, TVP5150_ROM_MAJOR_VER),
181 tvp5150_read(sd, TVP5150_ROM_MINOR_VER));
3ad96835 182 printk("tvp5150: Vertical line count = 0x%02x%02x\n",
6b8fe025
HV		 183 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_MSB),
184 tvp5150_read(sd, TVP5150_VERT_LN_COUNT_LSB));
84486d53 185 printk("tvp5150: Interrupt status register B = 0x%02x\n",
6b8fe025 186 tvp5150_read(sd, TVP5150_INT_STATUS_REG_B));
84486d53 187 printk("tvp5150: Interrupt active register B = 0x%02x\n",
6b8fe025 188 tvp5150_read(sd, TVP5150_INT_ACTIVE_REG_B));
3ad96835 189 printk("tvp5150: Status regs #1 to #5 = %02x %02x %02x %02x %02x\n",
6b8fe025
HV		 190 tvp5150_read(sd, TVP5150_STATUS_REG_1),
191 tvp5150_read(sd, TVP5150_STATUS_REG_2),
192 tvp5150_read(sd, TVP5150_STATUS_REG_3),
193 tvp5150_read(sd, TVP5150_STATUS_REG_4),
194 tvp5150_read(sd, TVP5150_STATUS_REG_5));
3ad96835 195
6b8fe025
HV		 196 dump_reg_range(sd, "Teletext filter 1", TVP5150_TELETEXT_FIL1_INI,
197 TVP5150_TELETEXT_FIL1_END, 8);
198 dump_reg_range(sd, "Teletext filter 2", TVP5150_TELETEXT_FIL2_INI,
199 TVP5150_TELETEXT_FIL2_END, 8);
3ad96835 200
84486d53 201 printk("tvp5150: Teletext filter enable = 0x%02x\n",
6b8fe025 202 tvp5150_read(sd, TVP5150_TELETEXT_FIL_ENA));
84486d53 203 printk("tvp5150: Interrupt status register A = 0x%02x\n",
6b8fe025 204 tvp5150_read(sd, TVP5150_INT_STATUS_REG_A));
84486d53 205 printk("tvp5150: Interrupt enable register A = 0x%02x\n",
6b8fe025 206 tvp5150_read(sd, TVP5150_INT_ENABLE_REG_A));
84486d53 207 printk("tvp5150: Interrupt configuration = 0x%02x\n",
6b8fe025 208 tvp5150_read(sd, TVP5150_INT_CONF));
84486d53 209 printk("tvp5150: VDP status register = 0x%02x\n",
6b8fe025 210 tvp5150_read(sd, TVP5150_VDP_STATUS_REG));
84486d53 211 printk("tvp5150: FIFO word count = 0x%02x\n",
6b8fe025 212 tvp5150_read(sd, TVP5150_FIFO_WORD_COUNT));
84486d53 213 printk("tvp5150: FIFO interrupt threshold = 0x%02x\n",
6b8fe025 214 tvp5150_read(sd, TVP5150_FIFO_INT_THRESHOLD));
84486d53 215 printk("tvp5150: FIFO reset = 0x%02x\n",
6b8fe025 216 tvp5150_read(sd, TVP5150_FIFO_RESET));
84486d53 217 printk("tvp5150: Line number interrupt = 0x%02x\n",
6b8fe025 218 tvp5150_read(sd, TVP5150_LINE_NUMBER_INT));
3ad96835 219 printk("tvp5150: Pixel alignment register = 0x%02x%02x\n",
6b8fe025
HV		 220 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_HIGH),
221 tvp5150_read(sd, TVP5150_PIX_ALIGN_REG_LOW));
84486d53 222 printk("tvp5150: FIFO output control = 0x%02x\n",
6b8fe025 223 tvp5150_read(sd, TVP5150_FIFO_OUT_CTRL));
3ad96835 224 printk("tvp5150: Full field enable = 0x%02x\n",
6b8fe025 225 tvp5150_read(sd, TVP5150_FULL_FIELD_ENA));
84486d53 226 printk("tvp5150: Full field mode register = 0x%02x\n",
6b8fe025 227 tvp5150_read(sd, TVP5150_FULL_FIELD_MODE_REG));
3ad96835 228
6b8fe025
HV		 229 dump_reg_range(sd, "CC data", TVP5150_CC_DATA_INI,
230 TVP5150_CC_DATA_END, 8);
3ad96835 231
6b8fe025
HV		 232 dump_reg_range(sd, "WSS data", TVP5150_WSS_DATA_INI,
233 TVP5150_WSS_DATA_END, 8);
3ad96835 234
6b8fe025
HV		 235 dump_reg_range(sd, "VPS data", TVP5150_VPS_DATA_INI,
236 TVP5150_VPS_DATA_END, 8);
3ad96835 237
6b8fe025
HV		 238 dump_reg_range(sd, "VITC data", TVP5150_VITC_DATA_INI,
239 TVP5150_VITC_DATA_END, 10);
3ad96835 240
6b8fe025
HV		 241 dump_reg_range(sd, "Line mode", TVP5150_LINE_MODE_INI,
242 TVP5150_LINE_MODE_END, 8);
243 return 0;
cd4665c5
MCC		 244}
245
246/****************************************************************************
247 Basic functions
248 ****************************************************************************/
cd4665c5 249
6b8fe025 250static inline void tvp5150_selmux(struct v4l2_subdev *sd)
cd4665c5 251{
2962fc01 252 int opmode = 0;
6b8fe025 253 struct tvp5150 *decoder = to_tvp5150(sd);
c7c0b34c 254 int input = 0;
afcc8e8c 255 int val;
84486d53 256
5325b427 257 if ((decoder->output & TVP5150_BLACK_SCREEN) || !decoder->enable)
c7c0b34c 258 input = 8;
4c86f973 259
5325b427 260 switch (decoder->input) {
c7c0b34c
HV		 261 case TVP5150_COMPOSITE1:
262 input |= 2;
263 /* fall through */
264 case TVP5150_COMPOSITE0:
c0477ad9 265 break;
c7c0b34c 266 case TVP5150_SVIDEO:
c0477ad9 267 default:
c7c0b34c 268 input |= 1;
c0477ad9
MCC		 269 break;
270 }
271
6b8fe025 272 v4l2_dbg(1, debug, sd, "Selecting video route: route input=%i, output=%i "
12500f07 273 "=> tvp5150 input=%i, opmode=%i\n",
5325b427
HV		 274 decoder->input, decoder->output,
275 input, opmode);
12500f07 276
6b8fe025
HV		 277 tvp5150_write(sd, TVP5150_OP_MODE_CTL, opmode);
278 tvp5150_write(sd, TVP5150_VD_IN_SRC_SEL_1, input);
f4b8b3ae
MCC		 279
280 /* Svideo should enable YCrCb output and disable GPCL output
281 * For Composite and TV, it should be the reverse
282 */
6b8fe025 283 val = tvp5150_read(sd, TVP5150_MISC_CTL);
8cd0d4ca
DL		 284 if (val < 0) {
285 v4l2_err(sd, "%s: failed with error = %d\n", __func__, val);
286 return;
287 }
288
5325b427 289 if (decoder->input == TVP5150_SVIDEO)
f4b8b3ae
MCC		 290 val = (val & ~0x40) | 0x10;
291 else
292 val = (val & ~0x10) | 0x40;
6b8fe025 293 tvp5150_write(sd, TVP5150_MISC_CTL, val);
cd4665c5
MCC		 294};
295
e1bc80ad
MCC		 296struct i2c_reg_value {
297 unsigned char reg;
298 unsigned char value;
299};
300
301/* Default values as sugested at TVP5150AM1 datasheet */
302static const struct i2c_reg_value tvp5150_init_default[] = {
303 { /* 0x00 */
304 TVP5150_VD_IN_SRC_SEL_1,0x00
305 },
306 { /* 0x01 */
307 TVP5150_ANAL_CHL_CTL,0x15
308 },
309 { /* 0x02 */
310 TVP5150_OP_MODE_CTL,0x00
311 },
312 { /* 0x03 */
313 TVP5150_MISC_CTL,0x01
314 },
315 { /* 0x06 */
316 TVP5150_COLOR_KIL_THSH_CTL,0x10
317 },
318 { /* 0x07 */
319 TVP5150_LUMA_PROC_CTL_1,0x60
320 },
321 { /* 0x08 */
322 TVP5150_LUMA_PROC_CTL_2,0x00
323 },
324 { /* 0x09 */
325 TVP5150_BRIGHT_CTL,0x80
326 },
327 { /* 0x0a */
328 TVP5150_SATURATION_CTL,0x80
329 },
330 { /* 0x0b */
331 TVP5150_HUE_CTL,0x00
332 },
333 { /* 0x0c */
334 TVP5150_CONTRAST_CTL,0x80
335 },
336 { /* 0x0d */
337 TVP5150_DATA_RATE_SEL,0x47
338 },
339 { /* 0x0e */
340 TVP5150_LUMA_PROC_CTL_3,0x00
341 },
342 { /* 0x0f */
343 TVP5150_CONF_SHARED_PIN,0x08
344 },
345 { /* 0x11 */
346 TVP5150_ACT_VD_CROP_ST_MSB,0x00
347 },
348 { /* 0x12 */
349 TVP5150_ACT_VD_CROP_ST_LSB,0x00
350 },
351 { /* 0x13 */
352 TVP5150_ACT_VD_CROP_STP_MSB,0x00
353 },
354 { /* 0x14 */
355 TVP5150_ACT_VD_CROP_STP_LSB,0x00
356 },
357 { /* 0x15 */
358 TVP5150_GENLOCK,0x01
359 },
360 { /* 0x16 */
361 TVP5150_HORIZ_SYNC_START,0x80
362 },
363 { /* 0x18 */
364 TVP5150_VERT_BLANKING_START,0x00
365 },
366 { /* 0x19 */
367 TVP5150_VERT_BLANKING_STOP,0x00
368 },
369 { /* 0x1a */
370 TVP5150_CHROMA_PROC_CTL_1,0x0c
371 },
372 { /* 0x1b */
373 TVP5150_CHROMA_PROC_CTL_2,0x14
374 },
375 { /* 0x1c */
376 TVP5150_INT_RESET_REG_B,0x00
377 },
378 { /* 0x1d */
379 TVP5150_INT_ENABLE_REG_B,0x00
380 },
381 { /* 0x1e */
382 TVP5150_INTT_CONFIG_REG_B,0x00
383 },
384 { /* 0x28 */
385 TVP5150_VIDEO_STD,0x00
386 },
387 { /* 0x2e */
388 TVP5150_MACROVISION_ON_CTR,0x0f
389 },
390 { /* 0x2f */
391 TVP5150_MACROVISION_OFF_CTR,0x01
392 },
393 { /* 0xbb */
394 TVP5150_TELETEXT_FIL_ENA,0x00
395 },
396 { /* 0xc0 */
397 TVP5150_INT_STATUS_REG_A,0x00
398 },
399 { /* 0xc1 */
400 TVP5150_INT_ENABLE_REG_A,0x00
401 },
402 { /* 0xc2 */
403 TVP5150_INT_CONF,0x04
404 },
405 { /* 0xc8 */
406 TVP5150_FIFO_INT_THRESHOLD,0x80
407 },
408 { /* 0xc9 */
409 TVP5150_FIFO_RESET,0x00
410 },
411 { /* 0xca */
412 TVP5150_LINE_NUMBER_INT,0x00
413 },
414 { /* 0xcb */
415 TVP5150_PIX_ALIGN_REG_LOW,0x4e
416 },
417 { /* 0xcc */
418 TVP5150_PIX_ALIGN_REG_HIGH,0x00
419 },
420 { /* 0xcd */
421 TVP5150_FIFO_OUT_CTRL,0x01
422 },
423 { /* 0xcf */
3ad96835 424 TVP5150_FULL_FIELD_ENA,0x00
e1bc80ad
MCC		 425 },
426 { /* 0xd0 */
3ad96835 427 TVP5150_LINE_MODE_INI,0x00
e1bc80ad
MCC		 428 },
429 { /* 0xfc */
430 TVP5150_FULL_FIELD_MODE_REG,0x7f
431 },
432 { /* end of data */
433 0xff,0xff
434 }
435};
436
437/* Default values as sugested at TVP5150AM1 datasheet */
438static const struct i2c_reg_value tvp5150_init_enable[] = {
439 {
440 TVP5150_CONF_SHARED_PIN, 2
441 },{ /* Automatic offset and AGC enabled */
442 TVP5150_ANAL_CHL_CTL, 0x15
443 },{ /* Activate YCrCb output 0x9 or 0xd ? */
444 TVP5150_MISC_CTL, 0x6f
445 },{ /* Activates video std autodetection for all standards */
446 TVP5150_AUTOSW_MSK, 0x0
447 },{ /* Default format: 0x47. For 4:2:2: 0x40 */
448 TVP5150_DATA_RATE_SEL, 0x47
449 },{
450 TVP5150_CHROMA_PROC_CTL_1, 0x0c
451 },{
452 TVP5150_CHROMA_PROC_CTL_2, 0x54
453 },{ /* Non documented, but initialized on WinTV USB2 */
454 0x27, 0x20
455 },{
456 0xff,0xff
457 }
458};
459
6ac48b45
MCC		 460struct tvp5150_vbi_type {
461 unsigned int vbi_type;
462 unsigned int ini_line;
463 unsigned int end_line;
464 unsigned int by_field :1;
465};
466
e1bc80ad
MCC		 467struct i2c_vbi_ram_value {
468 u16 reg;
6ac48b45
MCC		 469 struct tvp5150_vbi_type type;
470 unsigned char values[16];
e1bc80ad
MCC		 471};
472
6ac48b45
MCC		 473/* This struct have the values for each supported VBI Standard
474 * by
475 tvp5150_vbi_types should follow the same order as vbi_ram_default
3ad96835
MCC		 476 * value 0 means rom position 0x10, value 1 means rom position 0x30
477 * and so on. There are 16 possible locations from 0 to 15.
478 */
3ad96835 479
a9cff90e 480static struct i2c_vbi_ram_value vbi_ram_default[] =
cd4665c5 481{
9bc7400a
HV		 482 /* FIXME: Current api doesn't handle all VBI types, those not
483 yet supported are placed under #if 0 */
484#if 0
6ac48b45
MCC		 485 {0x010, /* Teletext, SECAM, WST System A */
486 {V4L2_SLICED_TELETEXT_SECAM,6,23,1},
487 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x26,
488 0xe6, 0xb4, 0x0e, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 489 },
9bc7400a 490#endif
6ac48b45 491 {0x030, /* Teletext, PAL, WST System B */
9bc7400a 492 {V4L2_SLICED_TELETEXT_B,6,22,1},
6ac48b45
MCC		 493 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x2b,
494 0xa6, 0x72, 0x10, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 495 },
9bc7400a 496#if 0
6ac48b45
MCC		 497 {0x050, /* Teletext, PAL, WST System C */
498 {V4L2_SLICED_TELETEXT_PAL_C,6,22,1},
499 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
500 0xa6, 0x98, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 501 },
6ac48b45
MCC		 502 {0x070, /* Teletext, NTSC, WST System B */
503 {V4L2_SLICED_TELETEXT_NTSC_B,10,21,1},
504 { 0xaa, 0xaa, 0xff, 0xff, 0x27, 0x2e, 0x20, 0x23,
505 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 506 },
6ac48b45
MCC		 507 {0x090, /* Tetetext, NTSC NABTS System C */
508 {V4L2_SLICED_TELETEXT_NTSC_C,10,21,1},
509 { 0xaa, 0xaa, 0xff, 0xff, 0xe7, 0x2e, 0x20, 0x22,
510 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x15, 0x00 }
e1bc80ad 511 },
6ac48b45
MCC		 512 {0x0b0, /* Teletext, NTSC-J, NABTS System D */
513 {V4L2_SLICED_TELETEXT_NTSC_D,10,21,1},
514 { 0xaa, 0xaa, 0xff, 0xff, 0xa7, 0x2e, 0x20, 0x23,
515 0x69, 0x93, 0x0d, 0x00, 0x00, 0x00, 0x10, 0x00 }
e1bc80ad 516 },
6ac48b45
MCC		 517 {0x0d0, /* Closed Caption, PAL/SECAM */
518 {V4L2_SLICED_CAPTION_625,22,22,1},
519 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
520 0xa6, 0x7b, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 521 },
9bc7400a 522#endif
6ac48b45
MCC		 523 {0x0f0, /* Closed Caption, NTSC */
524 {V4L2_SLICED_CAPTION_525,21,21,1},
525 { 0xaa, 0x2a, 0xff, 0x3f, 0x04, 0x51, 0x6e, 0x02,
526 0x69, 0x8c, 0x09, 0x00, 0x00, 0x00, 0x27, 0x00 }
e1bc80ad 527 },
6ac48b45 528 {0x110, /* Wide Screen Signal, PAL/SECAM */
12db5607 529 {V4L2_SLICED_WSS_625,23,23,1},
6ac48b45
MCC		 530 { 0x5b, 0x55, 0xc5, 0xff, 0x00, 0x71, 0x6e, 0x42,
531 0xa6, 0xcd, 0x0f, 0x00, 0x00, 0x00, 0x3a, 0x00 }
e1bc80ad 532 },
9bc7400a 533#if 0
6ac48b45
MCC		 534 {0x130, /* Wide Screen Signal, NTSC C */
535 {V4L2_SLICED_WSS_525,20,20,1},
536 { 0x38, 0x00, 0x3f, 0x00, 0x00, 0x71, 0x6e, 0x43,
537 0x69, 0x7c, 0x08, 0x00, 0x00, 0x00, 0x39, 0x00 }
e1bc80ad 538 },
6ac48b45
MCC		 539 {0x150, /* Vertical Interval Timecode (VITC), PAL/SECAM */
540 {V4l2_SLICED_VITC_625,6,22,0},
541 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
542 0xa6, 0x85, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 543 },
6ac48b45
MCC		 544 {0x170, /* Vertical Interval Timecode (VITC), NTSC */
545 {V4l2_SLICED_VITC_525,10,20,0},
546 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x8f, 0x6d, 0x49,
547 0x69, 0x94, 0x08, 0x00, 0x00, 0x00, 0x4c, 0x00 }
e1bc80ad 548 },
9bc7400a 549#endif
6ac48b45
MCC		 550 {0x190, /* Video Program System (VPS), PAL */
551 {V4L2_SLICED_VPS,16,16,0},
552 { 0xaa, 0xaa, 0xff, 0xff, 0xba, 0xce, 0x2b, 0x0d,
553 0xa6, 0xda, 0x0b, 0x00, 0x00, 0x00, 0x60, 0x00 }
3ad96835 554 },
6ac48b45
MCC		 555 /* 0x1d0 User programmable */
556
557 /* End of struct */
558 { (u16)-1 }
e1bc80ad 559};
4c86f973 560
6b8fe025 561static int tvp5150_write_inittab(struct v4l2_subdev *sd,
6ac48b45 562 const struct i2c_reg_value *regs)
e1bc80ad
MCC		 563{
564 while (regs->reg != 0xff) {
6b8fe025 565 tvp5150_write(sd, regs->reg, regs->value);
e1bc80ad
MCC		 566 regs++;
567 }
568 return 0;
569}
84486d53 570
6b8fe025 571static int tvp5150_vdp_init(struct v4l2_subdev *sd,
6ac48b45 572 const struct i2c_vbi_ram_value *regs)
e1bc80ad
MCC		 573{
574 unsigned int i;
cd4665c5 575
e1bc80ad 576 /* Disable Full Field */
6b8fe025 577 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
cd4665c5 578
e1bc80ad 579 /* Before programming, Line mode should be at 0xff */
6b8fe025
HV		 580 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
581 tvp5150_write(sd, i, 0xff);
cd4665c5 582
e1bc80ad 583 /* Load Ram Table */
6b8fe025
HV		 584 while (regs->reg != (u16)-1) {
585 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_HIGH, regs->reg >> 8);
586 tvp5150_write(sd, TVP5150_CONF_RAM_ADDR_LOW, regs->reg);
cd4665c5 587
6b8fe025
HV		 588 for (i = 0; i < 16; i++)
589 tvp5150_write(sd, TVP5150_VDP_CONF_RAM_DATA, regs->values[i]);
84486d53 590
e1bc80ad
MCC		 591 regs++;
592 }
593 return 0;
594}
cd4665c5 595
6ac48b45 596/* Fills VBI capabilities based on i2c_vbi_ram_value struct */
6b8fe025 597static int tvp5150_g_sliced_vbi_cap(struct v4l2_subdev *sd,
6ac48b45
MCC		 598 struct v4l2_sliced_vbi_cap *cap)
599{
6b8fe025 600 const struct i2c_vbi_ram_value *regs = vbi_ram_default;
6ac48b45
MCC		 601 int line;
602
bccfa449 603 v4l2_dbg(1, debug, sd, "g_sliced_vbi_cap\n");
6ac48b45
MCC		 604 memset(cap, 0, sizeof *cap);
605
606 while (regs->reg != (u16)-1 ) {
607 for (line=regs->type.ini_line;line<=regs->type.end_line;line++) {
608 cap->service_lines[0][line] |= regs->type.vbi_type;
609 }
610 cap->service_set |= regs->type.vbi_type;
611
612 regs++;
613 }
6b8fe025 614 return 0;
6ac48b45
MCC		 615}
616
3ad96835
MCC		 617/* Set vbi processing
618 * type - one of tvp5150_vbi_types
619 * line - line to gather data
620 * fields: bit 0 field1, bit 1, field2
621 * flags (default=0xf0) is a bitmask, were set means:
622 * bit 7: enable filtering null bytes on CC
623 * bit 6: send data also to FIFO
624 * bit 5: don't allow data with errors on FIFO
625 * bit 4: enable ECC when possible
626 * pix_align = pix alignment:
627 * LSB = field1
628 * MSB = field2
629 */
6b8fe025 630static int tvp5150_set_vbi(struct v4l2_subdev *sd,
2701dacb
MCC		 631 const struct i2c_vbi_ram_value *regs,
632 unsigned int type,u8 flags, int line,
633 const int fields)
3ad96835 634{
6b8fe025
HV		 635 struct tvp5150 *decoder = to_tvp5150(sd);
636 v4l2_std_id std = decoder->norm;
3ad96835 637 u8 reg;
2701dacb 638 int pos=0;
3ad96835
MCC		 639
640 if (std == V4L2_STD_ALL) {
6b8fe025 641 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 642 return 0;
7d5b7b98 643 } else if (std & V4L2_STD_625_50) {
3ad96835
MCC		 644 /* Don't follow NTSC Line number convension */
645 line += 3;
646 }
647
648 if (line<6||line>27)
2701dacb
MCC		 649 return 0;
650
651 while (regs->reg != (u16)-1 ) {
652 if ((type & regs->type.vbi_type) &&
653 (line>=regs->type.ini_line) &&
654 (line<=regs->type.end_line)) {
655 type=regs->type.vbi_type;
656 break;
657 }
658
659 regs++;
660 pos++;
661 }
662 if (regs->reg == (u16)-1)
663 return 0;
3ad96835 664
2701dacb 665 type=pos | (flags & 0xf0);
3ad96835
MCC		 666 reg=((line-6)<<1)+TVP5150_LINE_MODE_INI;
667
668 if (fields&1) {
6b8fe025 669 tvp5150_write(sd, reg, type);
3ad96835
MCC		 670 }
671
672 if (fields&2) {
6b8fe025 673 tvp5150_write(sd, reg+1, type);
3ad96835
MCC		 674 }
675
2701dacb 676 return type;
3ad96835
MCC		 677}
678
6b8fe025 679static int tvp5150_get_vbi(struct v4l2_subdev *sd,
12db5607
MCC		 680 const struct i2c_vbi_ram_value *regs, int line)
681{
6b8fe025
HV		 682 struct tvp5150 *decoder = to_tvp5150(sd);
683 v4l2_std_id std = decoder->norm;
12db5607 684 u8 reg;
6b8fe025 685 int pos, type = 0;
8cd0d4ca 686 int i, ret = 0;
12db5607
MCC		 687
688 if (std == V4L2_STD_ALL) {
6b8fe025 689 v4l2_err(sd, "VBI can't be configured without knowing number of lines\n");
12db5607 690 return 0;
7d5b7b98 691 } else if (std & V4L2_STD_625_50) {
12db5607
MCC		 692 /* Don't follow NTSC Line number convension */
693 line += 3;
694 }
695
6b8fe025 696 if (line < 6 || line > 27)
12db5607
MCC		 697 return 0;
698
6b8fe025 699 reg = ((line - 6) << 1) + TVP5150_LINE_MODE_INI;
12db5607 700
8cd0d4ca
DL		 701 for (i = 0; i <= 1; i++) {
702 ret = tvp5150_read(sd, reg + i);
703 if (ret < 0) {
704 v4l2_err(sd, "%s: failed with error = %d\n",
705 __func__, ret);
706 return 0;
707 }
708 pos = ret & 0x0f;
709 if (pos < 0x0f)
710 type |= regs[pos].type.vbi_type;
711 }
12db5607
MCC		 712
713 return type;
714}
6b8fe025
HV		 715
716static int tvp5150_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
e1bc80ad 717{
6b8fe025
HV		 718 struct tvp5150 *decoder = to_tvp5150(sd);
719 int fmt = 0;
e1bc80ad 720
6b8fe025 721 decoder->norm = std;
e1bc80ad
MCC		 722
723 /* First tests should be against specific std */
724
26811ae0 725 if (std == V4L2_STD_NTSC_443) {
2da12fcb 726 fmt = VIDEO_STD_NTSC_4_43_BIT;
26811ae0 727 } else if (std == V4L2_STD_PAL_M) {
2da12fcb 728 fmt = VIDEO_STD_PAL_M_BIT;
26811ae0 729 } else if (std == V4L2_STD_PAL_N || std == V4L2_STD_PAL_Nc) {
2da12fcb 730 fmt = VIDEO_STD_PAL_COMBINATION_N_BIT;
e1bc80ad
MCC		 731 } else {
732 /* Then, test against generic ones */
6b8fe025 733 if (std & V4L2_STD_NTSC)
2da12fcb 734 fmt = VIDEO_STD_NTSC_MJ_BIT;
6b8fe025 735 else if (std & V4L2_STD_PAL)
2da12fcb 736 fmt = VIDEO_STD_PAL_BDGHIN_BIT;
6b8fe025 737 else if (std & V4L2_STD_SECAM)
2da12fcb 738 fmt = VIDEO_STD_SECAM_BIT;
e1bc80ad 739 }
84486d53 740
6b8fe025
HV		 741 v4l2_dbg(1, debug, sd, "Set video std register to %d.\n", fmt);
742 tvp5150_write(sd, TVP5150_VIDEO_STD, fmt);
e1bc80ad
MCC		 743 return 0;
744}
745
6b8fe025
HV		 746static int tvp5150_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
747{
748 struct tvp5150 *decoder = to_tvp5150(sd);
749
750 if (decoder->norm == std)
751 return 0;
752
963ddc63
JM		 753 /* Change cropping height limits */
754 if (std & V4L2_STD_525_60)
755 decoder->rect.height = TVP5150_V_MAX_525_60;
756 else
757 decoder->rect.height = TVP5150_V_MAX_OTHERS;
758
759
6b8fe025
HV		 760 return tvp5150_set_std(sd, std);
761}
762
763static int tvp5150_reset(struct v4l2_subdev *sd, u32 val)
e1bc80ad 764{
6b8fe025 765 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 766
e1bc80ad 767 /* Initializes TVP5150 to its default values */
6b8fe025 768 tvp5150_write_inittab(sd, tvp5150_init_default);
e1bc80ad
MCC		 769
770 /* Initializes VDP registers */
6b8fe025 771 tvp5150_vdp_init(sd, vbi_ram_default);
e1bc80ad
MCC		 772
773 /* Selects decoder input */
6b8fe025 774 tvp5150_selmux(sd);
e1bc80ad
MCC		 775
776 /* Initializes TVP5150 to stream enabled values */
6b8fe025 777 tvp5150_write_inittab(sd, tvp5150_init_enable);
e1bc80ad
MCC		 778
779 /* Initialize image preferences */
6c45ec71 780 v4l2_ctrl_handler_setup(&decoder->hdl);
e1bc80ad 781
6b8fe025 782 tvp5150_set_std(sd, decoder->norm);
a2e5f1b3
JMC		 783
784 if (decoder->mbus_type == V4L2_MBUS_PARALLEL)
785 tvp5150_write(sd, TVP5150_DATA_RATE_SEL, 0x40);
786
6b8fe025 787 return 0;
cd4665c5
MCC		 788};
789
6c45ec71 790static int tvp5150_s_ctrl(struct v4l2_ctrl *ctrl)
a6c2ba28 791{
6c45ec71 792 struct v4l2_subdev *sd = to_sd(ctrl);
a6c2ba28 793
794 switch (ctrl->id) {
795 case V4L2_CID_BRIGHTNESS:
6c45ec71 796 tvp5150_write(sd, TVP5150_BRIGHT_CTL, ctrl->val);
a6c2ba28 797 return 0;
798 case V4L2_CID_CONTRAST:
6c45ec71 799 tvp5150_write(sd, TVP5150_CONTRAST_CTL, ctrl->val);
a6c2ba28 800 return 0;
801 case V4L2_CID_SATURATION:
6c45ec71 802 tvp5150_write(sd, TVP5150_SATURATION_CTL, ctrl->val);
a6c2ba28 803 return 0;
804 case V4L2_CID_HUE:
6c45ec71 805 tvp5150_write(sd, TVP5150_HUE_CTL, ctrl->val);
a6c2ba28 806 return 0;
a6c2ba28 807 }
c0477ad9 808 return -EINVAL;
a6c2ba28 809}
810
ec2c4f3f
JM		 811static v4l2_std_id tvp5150_read_std(struct v4l2_subdev *sd)
812{
813 int val = tvp5150_read(sd, TVP5150_STATUS_REG_5);
814
815 switch (val & 0x0F) {
816 case 0x01:
817 return V4L2_STD_NTSC;
818 case 0x03:
819 return V4L2_STD_PAL;
820 case 0x05:
821 return V4L2_STD_PAL_M;
822 case 0x07:
823 return V4L2_STD_PAL_N | V4L2_STD_PAL_Nc;
824 case 0x09:
825 return V4L2_STD_NTSC_443;
826 case 0xb:
827 return V4L2_STD_SECAM;
828 default:
829 return V4L2_STD_UNKNOWN;
830 }
831}
832
da298c6d
HV		 833static int tvp5150_fill_fmt(struct v4l2_subdev *sd,
834 struct v4l2_subdev_pad_config *cfg,
835 struct v4l2_subdev_format *format)
ec2c4f3f 836{
da298c6d 837 struct v4l2_mbus_framefmt *f;
ec2c4f3f 838 struct tvp5150 *decoder = to_tvp5150(sd);
ec2c4f3f 839
da298c6d 840 if (!format || format->pad)
ec2c4f3f
JM		 841 return -EINVAL;
842
da298c6d
HV		 843 f = &format->format;
844
ec2c4f3f
JM		 845 tvp5150_reset(sd, 0);
846
963ddc63 847 f->width = decoder->rect.width;
4f57d27b 848 f->height = decoder->rect.height / 2;
ec2c4f3f 849
f5fe58fd 850 f->code = MEDIA_BUS_FMT_UYVY8_2X8;
4f57d27b 851 f->field = V4L2_FIELD_ALTERNATE;
ec2c4f3f
JM		 852 f->colorspace = V4L2_COLORSPACE_SMPTE170M;
853
854 v4l2_dbg(1, debug, sd, "width = %d, height = %d\n", f->width,
855 f->height);
856 return 0;
857}
858
4f996594 859static int tvp5150_s_crop(struct v4l2_subdev *sd, const struct v4l2_crop *a)
963ddc63
JM		 860{
861 struct v4l2_rect rect = a->c;
862 struct tvp5150 *decoder = to_tvp5150(sd);
863 v4l2_std_id std;
f90580ca 864 unsigned int hmax;
963ddc63
JM		 865
866 v4l2_dbg(1, debug, sd, "%s left=%d, top=%d, width=%d, height=%d\n",
867 __func__, rect.left, rect.top, rect.width, rect.height);
868
869 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
870 return -EINVAL;
871
872 /* tvp5150 has some special limits */
873 rect.left = clamp(rect.left, 0, TVP5150_MAX_CROP_LEFT);
f90580ca
RR		 874 rect.width = clamp_t(unsigned int, rect.width,
875 TVP5150_H_MAX - TVP5150_MAX_CROP_LEFT - rect.left,
876 TVP5150_H_MAX - rect.left);
963ddc63
JM		 877 rect.top = clamp(rect.top, 0, TVP5150_MAX_CROP_TOP);
878
879 /* Calculate height based on current standard */
880 if (decoder->norm == V4L2_STD_ALL)
881 std = tvp5150_read_std(sd);
882 else
883 std = decoder->norm;
884
885 if (std & V4L2_STD_525_60)
886 hmax = TVP5150_V_MAX_525_60;
887 else
888 hmax = TVP5150_V_MAX_OTHERS;
889
f90580ca
RR		 890 rect.height = clamp_t(unsigned int, rect.height,
891 hmax - TVP5150_MAX_CROP_TOP - rect.top,
892 hmax - rect.top);
963ddc63
JM		 893
894 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, rect.top);
895 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP,
896 rect.top + rect.height - hmax);
897 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_MSB,
898 rect.left >> TVP5150_CROP_SHIFT);
899 tvp5150_write(sd, TVP5150_ACT_VD_CROP_ST_LSB,
900 rect.left | (1 << TVP5150_CROP_SHIFT));
901 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_MSB,
902 (rect.left + rect.width - TVP5150_MAX_CROP_LEFT) >>
903 TVP5150_CROP_SHIFT);
904 tvp5150_write(sd, TVP5150_ACT_VD_CROP_STP_LSB,
905 rect.left + rect.width - TVP5150_MAX_CROP_LEFT);
906
907 decoder->rect = rect;
908
909 return 0;
910}
911
912static int tvp5150_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
913{
12bd10c7 914 struct tvp5150 *decoder = to_tvp5150(sd);
963ddc63
JM		 915
916 a->c = decoder->rect;
917 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
918
919 return 0;
920}
921
922static int tvp5150_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
923{
12bd10c7 924 struct tvp5150 *decoder = to_tvp5150(sd);
963ddc63
JM		 925 v4l2_std_id std;
926
927 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
928 return -EINVAL;
929
930 a->bounds.left = 0;
931 a->bounds.top = 0;
932 a->bounds.width = TVP5150_H_MAX;
933
934 /* Calculate height based on current standard */
935 if (decoder->norm == V4L2_STD_ALL)
936 std = tvp5150_read_std(sd);
937 else
938 std = decoder->norm;
939
940 if (std & V4L2_STD_525_60)
941 a->bounds.height = TVP5150_V_MAX_525_60;
942 else
943 a->bounds.height = TVP5150_V_MAX_OTHERS;
944
945 a->defrect = a->bounds;
946 a->pixelaspect.numerator = 1;
947 a->pixelaspect.denominator = 1;
948
949 return 0;
950}
951
dd3a46bb
LP		 952static int tvp5150_g_mbus_config(struct v4l2_subdev *sd,
953 struct v4l2_mbus_config *cfg)
954{
a2e5f1b3
JMC		 955 struct tvp5150 *decoder = to_tvp5150(sd);
956
957 cfg->type = decoder->mbus_type;
dd3a46bb
LP		 958 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING
959 | V4L2_MBUS_FIELD_EVEN_LOW | V4L2_MBUS_DATA_ACTIVE_HIGH;
960
961 return 0;
962}
963
e545ac87
LP		 964/****************************************************************************
965 V4L2 subdev pad ops
966 ****************************************************************************/
967static int tvp5150_enum_mbus_code(struct v4l2_subdev *sd,
968 struct v4l2_subdev_pad_config *cfg,
969 struct v4l2_subdev_mbus_code_enum *code)
970{
971 if (code->pad || code->index)
972 return -EINVAL;
973
974 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
975 return 0;
976}
977
978static int tvp5150_enum_frame_size(struct v4l2_subdev *sd,
979 struct v4l2_subdev_pad_config *cfg,
980 struct v4l2_subdev_frame_size_enum *fse)
981{
982 struct tvp5150 *decoder = to_tvp5150(sd);
983
984 if (fse->index >= 8 || fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
985 return -EINVAL;
986
987 fse->code = MEDIA_BUS_FMT_UYVY8_2X8;
988 fse->min_width = decoder->rect.width;
989 fse->max_width = decoder->rect.width;
990 fse->min_height = decoder->rect.height / 2;
991 fse->max_height = decoder->rect.height / 2;
992
993 return 0;
994}
995
84486d53
MCC		 996/****************************************************************************
997 I2C Command
998 ****************************************************************************/
c7c0b34c 999
460b6c08
LP		 1000static int tvp5150_s_stream(struct v4l2_subdev *sd, int enable)
1001{
a2e5f1b3 1002 struct tvp5150 *decoder = to_tvp5150(sd);
841502d7
MCC		 1003 /* Output format: 8-bit ITU-R BT.656 with embedded syncs */
1004 int val = 0x09;
a2e5f1b3
JMC		 1005
1006 /* Output format: 8-bit 4:2:2 YUV with discrete sync */
841502d7
MCC		 1007 if (decoder->mbus_type == V4L2_MBUS_PARALLEL)
1008 val = 0x0d;
a2e5f1b3 1009
460b6c08
LP		 1010 /* Initializes TVP5150 to its default values */
1011 /* # set PCLK (27MHz) */
1012 tvp5150_write(sd, TVP5150_CONF_SHARED_PIN, 0x00);
1013
460b6c08 1014 if (enable)
841502d7 1015 tvp5150_write(sd, TVP5150_MISC_CTL, val);
460b6c08
LP		 1016 else
1017 tvp5150_write(sd, TVP5150_MISC_CTL, 0x00);
1018
1019 return 0;
1020}
1021
5325b427
HV		 1022static int tvp5150_s_routing(struct v4l2_subdev *sd,
1023 u32 input, u32 output, u32 config)
6b8fe025
HV		 1024{
1025 struct tvp5150 *decoder = to_tvp5150(sd);
84486d53 1026
5325b427
HV		 1027 decoder->input = input;
1028 decoder->output = output;
6b8fe025
HV		 1029 tvp5150_selmux(sd);
1030 return 0;
1031}
6ac48b45 1032
d37dad49
HV		 1033static int tvp5150_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
1034{
1035 /* this is for capturing 36 raw vbi lines
1036 if there's a way to cut off the beginning 2 vbi lines
1037 with the tvp5150 then the vbi line count could be lowered
1038 to 17 lines/field again, although I couldn't find a register
1039 which could do that cropping */
1040 if (fmt->sample_format == V4L2_PIX_FMT_GREY)
1041 tvp5150_write(sd, TVP5150_LUMA_PROC_CTL_1, 0x70);
1042 if (fmt->count[0] == 18 && fmt->count[1] == 18) {
1043 tvp5150_write(sd, TVP5150_VERT_BLANKING_START, 0x00);
1044 tvp5150_write(sd, TVP5150_VERT_BLANKING_STOP, 0x01);
1045 }
1046 return 0;
1047}
1048
1049static int tvp5150_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
6b8fe025 1050{
6b8fe025
HV		 1051 int i;
1052
6b8fe025
HV		 1053 if (svbi->service_set != 0) {
1054 for (i = 0; i <= 23; i++) {
1055 svbi->service_lines[1][i] = 0;
1056 svbi->service_lines[0][i] =
1057 tvp5150_set_vbi(sd, vbi_ram_default,
1058 svbi->service_lines[0][i], 0xf0, i, 3);
2c5aacc6 1059 }
6b8fe025
HV		 1060 /* Enables FIFO */
1061 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 1);
1062 } else {
1063 /* Disables FIFO*/
1064 tvp5150_write(sd, TVP5150_FIFO_OUT_CTRL, 0);
12db5607 1065
6b8fe025
HV		 1066 /* Disable Full Field */
1067 tvp5150_write(sd, TVP5150_FULL_FIELD_ENA, 0);
12db5607 1068
6b8fe025
HV		 1069 /* Disable Line modes */
1070 for (i = TVP5150_LINE_MODE_INI; i <= TVP5150_LINE_MODE_END; i++)
1071 tvp5150_write(sd, i, 0xff);
12db5607 1072 }
6b8fe025
HV		 1073 return 0;
1074}
12db5607 1075
d37dad49
HV		 1076static int tvp5150_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
1077{
1078 int i, mask = 0;
1079
30634e8e 1080 memset(svbi->service_lines, 0, sizeof(svbi->service_lines));
12db5607 1081
6b8fe025
HV		 1082 for (i = 0; i <= 23; i++) {
1083 svbi->service_lines[0][i] =
1084 tvp5150_get_vbi(sd, vbi_ram_default, i);
1085 mask |= svbi->service_lines[0][i];
2701dacb 1086 }
6b8fe025
HV		 1087 svbi->service_set = mask;
1088 return 0;
1089}
1090
21dcd8cc 1091#ifdef CONFIG_VIDEO_ADV_DEBUG
aecde8b5 1092static int tvp5150_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
6b8fe025 1093{
8cd0d4ca
DL		 1094 int res;
1095
8cd0d4ca
DL		 1096 res = tvp5150_read(sd, reg->reg & 0xff);
1097 if (res < 0) {
1098 v4l2_err(sd, "%s: failed with error = %d\n", __func__, res);
1099 return res;
1100 }
1101
1102 reg->val = res;
aecde8b5 1103 reg->size = 1;
6b8fe025
HV		 1104 return 0;
1105}
84486d53 1106
977ba3b1 1107static int tvp5150_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
6b8fe025 1108{
6b8fe025
HV		 1109 tvp5150_write(sd, reg->reg & 0xff, reg->val & 0xff);
1110 return 0;
1111}
1112#endif
a6c2ba28 1113
6b8fe025
HV		 1114static int tvp5150_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1115{
1116 int status = tvp5150_read(sd, 0x88);
a6c2ba28 1117
6b8fe025
HV		 1118 vt->signal = ((status & 0x04) && (status & 0x02)) ? 0xffff : 0x0;
1119 return 0;
1120}
a6c2ba28 1121
6b8fe025
HV		 1122/* ----------------------------------------------------------------------- */
1123
6c45ec71
HV		 1124static const struct v4l2_ctrl_ops tvp5150_ctrl_ops = {
1125 .s_ctrl = tvp5150_s_ctrl,
1126};
1127
6b8fe025
HV		 1128static const struct v4l2_subdev_core_ops tvp5150_core_ops = {
1129 .log_status = tvp5150_log_status,
6b8fe025
HV		 1130 .reset = tvp5150_reset,
1131#ifdef CONFIG_VIDEO_ADV_DEBUG
1132 .g_register = tvp5150_g_register,
1133 .s_register = tvp5150_s_register,
1134#endif
1135};
1136
1137static const struct v4l2_subdev_tuner_ops tvp5150_tuner_ops = {
6b8fe025
HV		 1138 .g_tuner = tvp5150_g_tuner,
1139};
1140
1141static const struct v4l2_subdev_video_ops tvp5150_video_ops = {
8774bed9 1142 .s_std = tvp5150_s_std,
460b6c08 1143 .s_stream = tvp5150_s_stream,
6b8fe025 1144 .s_routing = tvp5150_s_routing,
963ddc63
JM		 1145 .s_crop = tvp5150_s_crop,
1146 .g_crop = tvp5150_g_crop,
1147 .cropcap = tvp5150_cropcap,
dd3a46bb 1148 .g_mbus_config = tvp5150_g_mbus_config,
32cd527f
HV		 1149};
1150
1151static const struct v4l2_subdev_vbi_ops tvp5150_vbi_ops = {
6b8fe025 1152 .g_sliced_vbi_cap = tvp5150_g_sliced_vbi_cap,
d37dad49
HV		 1153 .g_sliced_fmt = tvp5150_g_sliced_fmt,
1154 .s_sliced_fmt = tvp5150_s_sliced_fmt,
1155 .s_raw_fmt = tvp5150_s_raw_fmt,
6b8fe025
HV		 1156};
1157
ebcff5fc
HV		 1158static const struct v4l2_subdev_pad_ops tvp5150_pad_ops = {
1159 .enum_mbus_code = tvp5150_enum_mbus_code,
e545ac87 1160 .enum_frame_size = tvp5150_enum_frame_size,
da298c6d
HV		 1161 .set_fmt = tvp5150_fill_fmt,
1162 .get_fmt = tvp5150_fill_fmt,
ebcff5fc
HV		 1163};
1164
6b8fe025
HV		 1165static const struct v4l2_subdev_ops tvp5150_ops = {
1166 .core = &tvp5150_core_ops,
1167 .tuner = &tvp5150_tuner_ops,
1168 .video = &tvp5150_video_ops,
32cd527f 1169 .vbi = &tvp5150_vbi_ops,
ebcff5fc 1170 .pad = &tvp5150_pad_ops,
6b8fe025
HV		 1171};
1172
1173
cd4665c5
MCC		 1174/****************************************************************************
1175 I2C Client & Driver
1176 ****************************************************************************/
cd4665c5 1177
7871597a
LP		 1178static int tvp5150_detect_version(struct tvp5150 *core)
1179{
1180 struct v4l2_subdev *sd = &core->sd;
1181 struct i2c_client *c = v4l2_get_subdevdata(sd);
1182 unsigned int i;
1183 u16 dev_id;
1184 u16 rom_ver;
1185 u8 regs[4];
1186 int res;
1187
1188 /*
1189 * Read consequent registers - TVP5150_MSB_DEV_ID, TVP5150_LSB_DEV_ID,
1190 * TVP5150_ROM_MAJOR_VER, TVP5150_ROM_MINOR_VER
1191 */
1192 for (i = 0; i < 4; i++) {
1193 res = tvp5150_read(sd, TVP5150_MSB_DEV_ID + i);
1194 if (res < 0)
1195 return res;
1196 regs[i] = res;
1197 }
1198
1199 dev_id = (regs[0] << 8) | regs[1];
1200 rom_ver = (regs[2] << 8) | regs[3];
1201
1202 v4l2_info(sd, "tvp%04x (%u.%u) chip found @ 0x%02x (%s)\n",
1203 dev_id, regs[2], regs[3], c->addr << 1, c->adapter->name);
1204
1205 if (dev_id == 0x5150 && rom_ver == 0x0321) { /* TVP51510A */
1206 v4l2_info(sd, "tvp5150a detected.\n");
1207 } else if (dev_id == 0x5150 && rom_ver == 0x0400) { /* TVP5150AM1 */
1208 v4l2_info(sd, "tvp5150am1 detected.\n");
1209
1210 /* ITU-T BT.656.4 timing */
1211 tvp5150_write(sd, TVP5150_REV_SELECT, 0);
05676b3e
LP		 1212 } else if (dev_id == 0x5151 && rom_ver == 0x0100) { /* TVP5151 */
1213 v4l2_info(sd, "tvp5151 detected.\n");
7871597a
LP		 1214 } else {
1215 v4l2_info(sd, "*** unknown tvp%04x chip detected.\n", dev_id);
1216 }
1217
1218 return 0;
1219}
1220
09aa2609
JMC		 1221static int tvp5150_init(struct i2c_client *c)
1222{
1223 struct gpio_desc *pdn_gpio;
1224 struct gpio_desc *reset_gpio;
1225
1226 pdn_gpio = devm_gpiod_get_optional(&c->dev, "pdn", GPIOD_OUT_HIGH);
1227 if (IS_ERR(pdn_gpio))
1228 return PTR_ERR(pdn_gpio);
1229
1230 if (pdn_gpio) {
1231 gpiod_set_value_cansleep(pdn_gpio, 0);
1232 /* Delay time between power supplies active and reset */
1233 msleep(20);
1234 }
1235
1236 reset_gpio = devm_gpiod_get_optional(&c->dev, "reset", GPIOD_OUT_HIGH);
1237 if (IS_ERR(reset_gpio))
1238 return PTR_ERR(reset_gpio);
1239
1240 if (reset_gpio) {
1241 /* RESETB pulse duration */
1242 ndelay(500);
1243 gpiod_set_value_cansleep(reset_gpio, 0);
1244 /* Delay time between end of reset to I2C active */
1245 usleep_range(200, 250);
1246 }
1247
1248 return 0;
1249}
1250
a2e5f1b3
JMC		 1251static int tvp5150_parse_dt(struct tvp5150 *decoder, struct device_node *np)
1252{
1253 struct v4l2_of_endpoint bus_cfg;
1254 struct device_node *ep;
1255 unsigned int flags;
1256 int ret = 0;
1257
1258 ep = of_graph_get_next_endpoint(np, NULL);
1259 if (!ep)
1260 return -EINVAL;
1261
1262 ret = v4l2_of_parse_endpoint(ep, &bus_cfg);
1263 if (ret)
1264 goto err;
1265
1266 flags = bus_cfg.bus.parallel.flags;
1267
1268 if (bus_cfg.bus_type == V4L2_MBUS_PARALLEL &&
1269 !(flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH &&
1270 flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH &&
1271 flags & V4L2_MBUS_FIELD_EVEN_LOW))
1272 return -EINVAL;
1273
1274 decoder->mbus_type = bus_cfg.bus_type;
1275
1276err:
1277 of_node_put(ep);
1278 return ret;
1279}
1280
6b8fe025
HV		 1281static int tvp5150_probe(struct i2c_client *c,
1282 const struct i2c_device_id *id)
cd4665c5 1283{
cd4665c5 1284 struct tvp5150 *core;
6b8fe025 1285 struct v4l2_subdev *sd;
a2e5f1b3 1286 struct device_node *np = c->dev.of_node;
7871597a 1287 int res;
cd4665c5
MCC		 1288
1289 /* Check if the adapter supports the needed features */
6b8fe025 1290 if (!i2c_check_functionality(c->adapter,
cd4665c5 1291 I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
6b8fe025 1292 return -EIO;
cd4665c5 1293
09aa2609
JMC		 1294 res = tvp5150_init(c);
1295 if (res)
1296 return res;
1297
c02b211d
LP		 1298 core = devm_kzalloc(&c->dev, sizeof(*core), GFP_KERNEL);
1299 if (!core)
cd4665c5 1300 return -ENOMEM;
a2e5f1b3 1301
6b8fe025 1302 sd = &core->sd;
a2e5f1b3
JMC		 1303
1304 if (IS_ENABLED(CONFIG_OF) && np) {
1305 res = tvp5150_parse_dt(core, np);
1306 if (res) {
1307 v4l2_err(sd, "DT parsing error: %d\n", res);
1308 return res;
1309 }
1310 } else {
1311 /* Default to BT.656 embedded sync */
1312 core->mbus_type = V4L2_MBUS_BT656;
1313 }
1314
6b8fe025 1315 v4l2_i2c_subdev_init(sd, c, &tvp5150_ops);
e545ac87
LP		 1316 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1317
1318#if defined(CONFIG_MEDIA_CONTROLLER)
55606310
MCC		 1319 core->pads[DEMOD_PAD_IF_INPUT].flags = MEDIA_PAD_FL_SINK;
1320 core->pads[DEMOD_PAD_VID_OUT].flags = MEDIA_PAD_FL_SOURCE;
1321 core->pads[DEMOD_PAD_VBI_OUT].flags = MEDIA_PAD_FL_SOURCE;
f92c70ad
MCC		 1322
1323 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;
1324
55606310 1325 res = media_entity_pads_init(&sd->entity, DEMOD_NUM_PADS, core->pads);
e545ac87
LP		 1326 if (res < 0)
1327 return res;
1328#endif
8cd0d4ca 1329
7871597a
LP		 1330 res = tvp5150_detect_version(core);
1331 if (res < 0)
1332 return res;
0e09a3c9 1333
3ad96835 1334 core->norm = V4L2_STD_ALL; /* Default is autodetect */
5325b427 1335 core->input = TVP5150_COMPOSITE1;
4c86f973 1336 core->enable = 1;
6c45ec71 1337
b1950b8d 1338 v4l2_ctrl_handler_init(&core->hdl, 5);
6c45ec71
HV		 1339 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1340 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1341 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1342 V4L2_CID_CONTRAST, 0, 255, 1, 128);
1343 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1344 V4L2_CID_SATURATION, 0, 255, 1, 128);
1345 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1346 V4L2_CID_HUE, -128, 127, 1, 0);
b1950b8d
LP		 1347 v4l2_ctrl_new_std(&core->hdl, &tvp5150_ctrl_ops,
1348 V4L2_CID_PIXEL_RATE, 27000000,
1349 27000000, 1, 27000000);
6c45ec71
HV		 1350 sd->ctrl_handler = &core->hdl;
1351 if (core->hdl.error) {
8cd0d4ca 1352 res = core->hdl.error;
c7d97499 1353 goto err;
6c45ec71
HV		 1354 }
1355 v4l2_ctrl_handler_setup(&core->hdl);
4c86f973 1356
963ddc63
JM		 1357 /* Default is no cropping */
1358 core->rect.top = 0;
1359 if (tvp5150_read_std(sd) & V4L2_STD_525_60)
1360 core->rect.height = TVP5150_V_MAX_525_60;
1361 else
1362 core->rect.height = TVP5150_V_MAX_OTHERS;
1363 core->rect.left = 0;
1364 core->rect.width = TVP5150_H_MAX;
1365
c7d97499
JMC		 1366 res = v4l2_async_register_subdev(sd);
1367 if (res < 0)
1368 goto err;
1369
f1e5ee45 1370 if (debug > 1)
6b8fe025 1371 tvp5150_log_status(sd);
cd4665c5 1372 return 0;
c7d97499
JMC		 1373
1374err:
1375 v4l2_ctrl_handler_free(&core->hdl);
1376 return res;
cd4665c5
MCC		 1377}
1378
6b8fe025 1379static int tvp5150_remove(struct i2c_client *c)
cd4665c5 1380{
6b8fe025 1381 struct v4l2_subdev *sd = i2c_get_clientdata(c);
6c45ec71 1382 struct tvp5150 *decoder = to_tvp5150(sd);
cd4665c5 1383
6b8fe025 1384 v4l2_dbg(1, debug, sd,
e1bc80ad
MCC		 1385 "tvp5150.c: removing tvp5150 adapter on address 0x%x\n",
1386 c->addr << 1);
1387
c7d97499 1388 v4l2_async_unregister_subdev(sd);
6c45ec71 1389 v4l2_ctrl_handler_free(&decoder->hdl);
cd4665c5
MCC		 1390 return 0;
1391}
1392
1393/* ----------------------------------------------------------------------- */
1394
6b8fe025
HV		 1395static const struct i2c_device_id tvp5150_id[] = {
1396 { "tvp5150", 0 },
1397 { }
1398};
1399MODULE_DEVICE_TABLE(i2c, tvp5150_id);
84486d53 1400
7ef930a7
EG		 1401#if IS_ENABLED(CONFIG_OF)
1402static const struct of_device_id tvp5150_of_match[] = {
1403 { .compatible = "ti,tvp5150", },
1404 { /* sentinel */ },
1405};
1406MODULE_DEVICE_TABLE(of, tvp5150_of_match);
1407#endif
1408
c771145b
HV		 1409static struct i2c_driver tvp5150_driver = {
1410 .driver = {
7ef930a7 1411 .of_match_table = of_match_ptr(tvp5150_of_match),
c771145b
HV		 1412 .name = "tvp5150",
1413 },
1414 .probe = tvp5150_probe,
1415 .remove = tvp5150_remove,
1416 .id_table = tvp5150_id,
cd4665c5 1417};
c771145b 1418
c6e8d86f 1419module_i2c_driver(tvp5150_driver);
Linux kernel - Deliverables
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