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0b675536 SNC |
1 | /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics |
2 | * Digitizer with Horizontal PLL registers | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Inc | |
5 | * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> | |
6 | * | |
7 | * This code is partially based upon the TVP5150 driver | |
8 | * written by Mauro Carvalho Chehab (mchehab@infradead.org), | |
9 | * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> | |
10 | * and the TVP7002 driver in the TI LSP 2.10.00.14. Revisions by | |
11 | * Muralidharan Karicheri and Snehaprabha Narnakaje (TI). | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | */ | |
27 | #include <linux/delay.h> | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
0b675536 | 30 | #include <linux/videodev2.h> |
7a707b89 | 31 | #include <linux/module.h> |
eb8305b1 | 32 | #include <linux/v4l2-dv-timings.h> |
0b675536 SNC |
33 | #include <media/tvp7002.h> |
34 | #include <media/v4l2-device.h> | |
35 | #include <media/v4l2-chip-ident.h> | |
36 | #include <media/v4l2-common.h> | |
0eb73de0 | 37 | #include <media/v4l2-ctrls.h> |
0b675536 SNC |
38 | #include "tvp7002_reg.h" |
39 | ||
40 | MODULE_DESCRIPTION("TI TVP7002 Video and Graphics Digitizer driver"); | |
41 | MODULE_AUTHOR("Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>"); | |
42 | MODULE_LICENSE("GPL"); | |
43 | ||
44 | /* Module Name */ | |
45 | #define TVP7002_MODULE_NAME "tvp7002" | |
46 | ||
47 | /* I2C retry attempts */ | |
48 | #define I2C_RETRY_COUNT (5) | |
49 | ||
50 | /* End of registers */ | |
51 | #define TVP7002_EOR 0x5c | |
52 | ||
53 | /* Read write definition for registers */ | |
54 | #define TVP7002_READ 0 | |
55 | #define TVP7002_WRITE 1 | |
56 | #define TVP7002_RESERVED 2 | |
57 | ||
58 | /* Interlaced vs progressive mask and shift */ | |
59 | #define TVP7002_IP_SHIFT 5 | |
60 | #define TVP7002_INPR_MASK (0x01 << TVP7002_IP_SHIFT) | |
61 | ||
62 | /* Shift for CPL and LPF registers */ | |
63 | #define TVP7002_CL_SHIFT 8 | |
64 | #define TVP7002_CL_MASK 0x0f | |
65 | ||
66 | /* Debug functions */ | |
90ab5ee9 | 67 | static bool debug; |
0b675536 SNC |
68 | module_param(debug, bool, 0644); |
69 | MODULE_PARM_DESC(debug, "Debug level (0-2)"); | |
70 | ||
71 | /* Structure for register values */ | |
72 | struct i2c_reg_value { | |
73 | u8 reg; | |
74 | u8 value; | |
75 | u8 type; | |
76 | }; | |
77 | ||
78 | /* | |
79 | * Register default values (according to tvp7002 datasheet) | |
80 | * In the case of read-only registers, the value (0xff) is | |
81 | * never written. R/W functionality is controlled by the | |
82 | * writable bit in the register struct definition. | |
83 | */ | |
84 | static const struct i2c_reg_value tvp7002_init_default[] = { | |
85 | { TVP7002_CHIP_REV, 0xff, TVP7002_READ }, | |
86 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, | |
87 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, | |
88 | { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, | |
89 | { TVP7002_HPLL_PHASE_SEL, 0x80, TVP7002_WRITE }, | |
90 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
91 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
92 | { TVP7002_HSYNC_OUT_W, 0x60, TVP7002_WRITE }, | |
93 | { TVP7002_B_FINE_GAIN, 0x00, TVP7002_WRITE }, | |
94 | { TVP7002_G_FINE_GAIN, 0x00, TVP7002_WRITE }, | |
95 | { TVP7002_R_FINE_GAIN, 0x00, TVP7002_WRITE }, | |
96 | { TVP7002_B_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, | |
97 | { TVP7002_G_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, | |
98 | { TVP7002_R_FINE_OFF_MSBS, 0x80, TVP7002_WRITE }, | |
99 | { TVP7002_SYNC_CTL_1, 0x20, TVP7002_WRITE }, | |
100 | { TVP7002_HPLL_AND_CLAMP_CTL, 0x2e, TVP7002_WRITE }, | |
101 | { TVP7002_SYNC_ON_G_THRS, 0x5d, TVP7002_WRITE }, | |
102 | { TVP7002_SYNC_SEPARATOR_THRS, 0x47, TVP7002_WRITE }, | |
103 | { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, | |
104 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
105 | { TVP7002_SYNC_DETECT_STAT, 0xff, TVP7002_READ }, | |
106 | { TVP7002_OUT_FORMATTER, 0x47, TVP7002_WRITE }, | |
107 | { TVP7002_MISC_CTL_1, 0x01, TVP7002_WRITE }, | |
108 | { TVP7002_MISC_CTL_2, 0x00, TVP7002_WRITE }, | |
109 | { TVP7002_MISC_CTL_3, 0x01, TVP7002_WRITE }, | |
110 | { TVP7002_IN_MUX_SEL_1, 0x00, TVP7002_WRITE }, | |
111 | { TVP7002_IN_MUX_SEL_2, 0x67, TVP7002_WRITE }, | |
112 | { TVP7002_B_AND_G_COARSE_GAIN, 0x77, TVP7002_WRITE }, | |
113 | { TVP7002_R_COARSE_GAIN, 0x07, TVP7002_WRITE }, | |
114 | { TVP7002_FINE_OFF_LSBS, 0x00, TVP7002_WRITE }, | |
115 | { TVP7002_B_COARSE_OFF, 0x10, TVP7002_WRITE }, | |
116 | { TVP7002_G_COARSE_OFF, 0x10, TVP7002_WRITE }, | |
117 | { TVP7002_R_COARSE_OFF, 0x10, TVP7002_WRITE }, | |
118 | { TVP7002_HSOUT_OUT_START, 0x08, TVP7002_WRITE }, | |
119 | { TVP7002_MISC_CTL_4, 0x00, TVP7002_WRITE }, | |
120 | { TVP7002_B_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, | |
121 | { TVP7002_G_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, | |
122 | { TVP7002_R_DGTL_ALC_OUT_LSBS, 0xff, TVP7002_READ }, | |
123 | { TVP7002_AUTO_LVL_CTL_ENABLE, 0x80, TVP7002_WRITE }, | |
124 | { TVP7002_DGTL_ALC_OUT_MSBS, 0xff, TVP7002_READ }, | |
125 | { TVP7002_AUTO_LVL_CTL_FILTER, 0x53, TVP7002_WRITE }, | |
126 | { 0x29, 0x08, TVP7002_RESERVED }, | |
127 | { TVP7002_FINE_CLAMP_CTL, 0x07, TVP7002_WRITE }, | |
128 | /* PWR_CTL is controlled only by the probe and reset functions */ | |
129 | { TVP7002_PWR_CTL, 0x00, TVP7002_RESERVED }, | |
130 | { TVP7002_ADC_SETUP, 0x50, TVP7002_WRITE }, | |
131 | { TVP7002_COARSE_CLAMP_CTL, 0x00, TVP7002_WRITE }, | |
132 | { TVP7002_SOG_CLAMP, 0x80, TVP7002_WRITE }, | |
425b91c9 | 133 | { TVP7002_RGB_COARSE_CLAMP_CTL, 0x8c, TVP7002_WRITE }, |
0b675536 SNC |
134 | { TVP7002_SOG_COARSE_CLAMP_CTL, 0x04, TVP7002_WRITE }, |
135 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
136 | { 0x32, 0x18, TVP7002_RESERVED }, | |
137 | { 0x33, 0x60, TVP7002_RESERVED }, | |
138 | { TVP7002_MVIS_STRIPPER_W, 0xff, TVP7002_RESERVED }, | |
139 | { TVP7002_VSYNC_ALGN, 0x10, TVP7002_WRITE }, | |
140 | { TVP7002_SYNC_BYPASS, 0x00, TVP7002_WRITE }, | |
141 | { TVP7002_L_FRAME_STAT_LSBS, 0xff, TVP7002_READ }, | |
142 | { TVP7002_L_FRAME_STAT_MSBS, 0xff, TVP7002_READ }, | |
143 | { TVP7002_CLK_L_STAT_LSBS, 0xff, TVP7002_READ }, | |
144 | { TVP7002_CLK_L_STAT_MSBS, 0xff, TVP7002_READ }, | |
145 | { TVP7002_HSYNC_W, 0xff, TVP7002_READ }, | |
146 | { TVP7002_VSYNC_W, 0xff, TVP7002_READ }, | |
147 | { TVP7002_L_LENGTH_TOL, 0x03, TVP7002_WRITE }, | |
148 | { 0x3e, 0x60, TVP7002_RESERVED }, | |
149 | { TVP7002_VIDEO_BWTH_CTL, 0x01, TVP7002_WRITE }, | |
150 | { TVP7002_AVID_START_PIXEL_LSBS, 0x01, TVP7002_WRITE }, | |
151 | { TVP7002_AVID_START_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, | |
152 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x06, TVP7002_WRITE }, | |
153 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c, TVP7002_WRITE }, | |
154 | { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, | |
155 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
156 | { TVP7002_VBLK_F_0_DURATION, 0x1e, TVP7002_WRITE }, | |
157 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
158 | { TVP7002_FBIT_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, | |
159 | { TVP7002_FBIT_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
160 | { TVP7002_YUV_Y_G_COEF_LSBS, 0xe3, TVP7002_WRITE }, | |
161 | { TVP7002_YUV_Y_G_COEF_MSBS, 0x16, TVP7002_WRITE }, | |
162 | { TVP7002_YUV_Y_B_COEF_LSBS, 0x4f, TVP7002_WRITE }, | |
163 | { TVP7002_YUV_Y_B_COEF_MSBS, 0x02, TVP7002_WRITE }, | |
164 | { TVP7002_YUV_Y_R_COEF_LSBS, 0xce, TVP7002_WRITE }, | |
165 | { TVP7002_YUV_Y_R_COEF_MSBS, 0x06, TVP7002_WRITE }, | |
166 | { TVP7002_YUV_U_G_COEF_LSBS, 0xab, TVP7002_WRITE }, | |
167 | { TVP7002_YUV_U_G_COEF_MSBS, 0xf3, TVP7002_WRITE }, | |
168 | { TVP7002_YUV_U_B_COEF_LSBS, 0x00, TVP7002_WRITE }, | |
169 | { TVP7002_YUV_U_B_COEF_MSBS, 0x10, TVP7002_WRITE }, | |
170 | { TVP7002_YUV_U_R_COEF_LSBS, 0x55, TVP7002_WRITE }, | |
171 | { TVP7002_YUV_U_R_COEF_MSBS, 0xfc, TVP7002_WRITE }, | |
172 | { TVP7002_YUV_V_G_COEF_LSBS, 0x78, TVP7002_WRITE }, | |
173 | { TVP7002_YUV_V_G_COEF_MSBS, 0xf1, TVP7002_WRITE }, | |
174 | { TVP7002_YUV_V_B_COEF_LSBS, 0x88, TVP7002_WRITE }, | |
175 | { TVP7002_YUV_V_B_COEF_MSBS, 0xfe, TVP7002_WRITE }, | |
176 | { TVP7002_YUV_V_R_COEF_LSBS, 0x00, TVP7002_WRITE }, | |
177 | { TVP7002_YUV_V_R_COEF_MSBS, 0x10, TVP7002_WRITE }, | |
178 | /* This signals end of register values */ | |
179 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
180 | }; | |
181 | ||
182 | /* Register parameters for 480P */ | |
183 | static const struct i2c_reg_value tvp7002_parms_480P[] = { | |
184 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x35, TVP7002_WRITE }, | |
560afa7d | 185 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xa0, TVP7002_WRITE }, |
0b675536 | 186 | { TVP7002_HPLL_CRTL, 0x02, TVP7002_WRITE }, |
0b675536 SNC |
187 | { TVP7002_AVID_START_PIXEL_LSBS, 0x91, TVP7002_WRITE }, |
188 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
189 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B, TVP7002_WRITE }, | |
190 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
191 | { TVP7002_VBLK_F_0_START_L_OFF, 0x03, TVP7002_WRITE }, | |
192 | { TVP7002_VBLK_F_1_START_L_OFF, 0x01, TVP7002_WRITE }, | |
193 | { TVP7002_VBLK_F_0_DURATION, 0x13, TVP7002_WRITE }, | |
194 | { TVP7002_VBLK_F_1_DURATION, 0x13, TVP7002_WRITE }, | |
195 | { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, | |
196 | { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, | |
197 | { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, | |
198 | { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, | |
199 | { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, | |
200 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
201 | }; | |
202 | ||
203 | /* Register parameters for 576P */ | |
204 | static const struct i2c_reg_value tvp7002_parms_576P[] = { | |
205 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x36, TVP7002_WRITE }, | |
206 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, | |
207 | { TVP7002_HPLL_CRTL, 0x18, TVP7002_WRITE }, | |
0b675536 SNC |
208 | { TVP7002_AVID_START_PIXEL_LSBS, 0x9B, TVP7002_WRITE }, |
209 | { TVP7002_AVID_START_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
210 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x0F, TVP7002_WRITE }, | |
211 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x00, TVP7002_WRITE }, | |
212 | { TVP7002_VBLK_F_0_START_L_OFF, 0x00, TVP7002_WRITE }, | |
213 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
214 | { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, | |
215 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
216 | { TVP7002_ALC_PLACEMENT, 0x18, TVP7002_WRITE }, | |
217 | { TVP7002_CLAMP_START, 0x06, TVP7002_WRITE }, | |
218 | { TVP7002_CLAMP_W, 0x10, TVP7002_WRITE }, | |
219 | { TVP7002_HPLL_PRE_COAST, 0x03, TVP7002_WRITE }, | |
220 | { TVP7002_HPLL_POST_COAST, 0x03, TVP7002_WRITE }, | |
221 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
222 | }; | |
223 | ||
224 | /* Register parameters for 1080I60 */ | |
225 | static const struct i2c_reg_value tvp7002_parms_1080I60[] = { | |
226 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, | |
560afa7d | 227 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, |
0b675536 | 228 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, |
0b675536 SNC |
229 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
230 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
231 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | |
232 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, | |
233 | { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, | |
234 | { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, | |
235 | { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, | |
236 | { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, | |
237 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
238 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
239 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
240 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
241 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
242 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
243 | }; | |
244 | ||
245 | /* Register parameters for 1080P60 */ | |
246 | static const struct i2c_reg_value tvp7002_parms_1080P60[] = { | |
247 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x89, TVP7002_WRITE }, | |
560afa7d | 248 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x80, TVP7002_WRITE }, |
0b675536 | 249 | { TVP7002_HPLL_CRTL, 0xE0, TVP7002_WRITE }, |
0b675536 SNC |
250 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
251 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
252 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | |
253 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, | |
254 | { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, | |
255 | { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, | |
256 | { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, | |
257 | { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, | |
258 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
259 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
260 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
261 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
262 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
263 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
264 | }; | |
265 | ||
266 | /* Register parameters for 1080I50 */ | |
267 | static const struct i2c_reg_value tvp7002_parms_1080I50[] = { | |
268 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0xa5, TVP7002_WRITE }, | |
269 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x00, TVP7002_WRITE }, | |
270 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, | |
0b675536 SNC |
271 | { TVP7002_AVID_START_PIXEL_LSBS, 0x06, TVP7002_WRITE }, |
272 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
273 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x8a, TVP7002_WRITE }, | |
274 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x08, TVP7002_WRITE }, | |
275 | { TVP7002_VBLK_F_0_START_L_OFF, 0x02, TVP7002_WRITE }, | |
276 | { TVP7002_VBLK_F_1_START_L_OFF, 0x02, TVP7002_WRITE }, | |
277 | { TVP7002_VBLK_F_0_DURATION, 0x16, TVP7002_WRITE }, | |
278 | { TVP7002_VBLK_F_1_DURATION, 0x17, TVP7002_WRITE }, | |
279 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
280 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
281 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
282 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
283 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
284 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
285 | }; | |
286 | ||
287 | /* Register parameters for 720P60 */ | |
288 | static const struct i2c_reg_value tvp7002_parms_720P60[] = { | |
289 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x67, TVP7002_WRITE }, | |
560afa7d | 290 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0x20, TVP7002_WRITE }, |
0b675536 | 291 | { TVP7002_HPLL_CRTL, 0xa0, TVP7002_WRITE }, |
0b675536 SNC |
292 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, |
293 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
294 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, | |
295 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, | |
296 | { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, | |
297 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
298 | { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, | |
299 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
300 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
301 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
302 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
303 | { TVP7002_HPLL_PRE_COAST, 0x00, TVP7002_WRITE }, | |
304 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
305 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
306 | }; | |
307 | ||
308 | /* Register parameters for 720P50 */ | |
309 | static const struct i2c_reg_value tvp7002_parms_720P50[] = { | |
310 | { TVP7002_HPLL_FDBK_DIV_MSBS, 0x7b, TVP7002_WRITE }, | |
560afa7d | 311 | { TVP7002_HPLL_FDBK_DIV_LSBS, 0xc0, TVP7002_WRITE }, |
0b675536 | 312 | { TVP7002_HPLL_CRTL, 0x98, TVP7002_WRITE }, |
0b675536 SNC |
313 | { TVP7002_AVID_START_PIXEL_LSBS, 0x47, TVP7002_WRITE }, |
314 | { TVP7002_AVID_START_PIXEL_MSBS, 0x01, TVP7002_WRITE }, | |
315 | { TVP7002_AVID_STOP_PIXEL_LSBS, 0x4B, TVP7002_WRITE }, | |
316 | { TVP7002_AVID_STOP_PIXEL_MSBS, 0x06, TVP7002_WRITE }, | |
317 | { TVP7002_VBLK_F_0_START_L_OFF, 0x05, TVP7002_WRITE }, | |
318 | { TVP7002_VBLK_F_1_START_L_OFF, 0x00, TVP7002_WRITE }, | |
319 | { TVP7002_VBLK_F_0_DURATION, 0x2D, TVP7002_WRITE }, | |
320 | { TVP7002_VBLK_F_1_DURATION, 0x00, TVP7002_WRITE }, | |
321 | { TVP7002_ALC_PLACEMENT, 0x5a, TVP7002_WRITE }, | |
322 | { TVP7002_CLAMP_START, 0x32, TVP7002_WRITE }, | |
323 | { TVP7002_CLAMP_W, 0x20, TVP7002_WRITE }, | |
324 | { TVP7002_HPLL_PRE_COAST, 0x01, TVP7002_WRITE }, | |
325 | { TVP7002_HPLL_POST_COAST, 0x00, TVP7002_WRITE }, | |
326 | { TVP7002_EOR, 0xff, TVP7002_RESERVED } | |
327 | }; | |
328 | ||
f0cd015e HV |
329 | /* Timings definition for handling device operation */ |
330 | struct tvp7002_timings_definition { | |
eb8305b1 | 331 | struct v4l2_dv_timings timings; |
0b675536 SNC |
332 | const struct i2c_reg_value *p_settings; |
333 | enum v4l2_colorspace color_space; | |
334 | enum v4l2_field scanmode; | |
335 | u16 progressive; | |
336 | u16 lines_per_frame; | |
337 | u16 cpl_min; | |
338 | u16 cpl_max; | |
339 | }; | |
340 | ||
f0cd015e HV |
341 | /* Struct list for digital video timings */ |
342 | static const struct tvp7002_timings_definition tvp7002_timings[] = { | |
0b675536 | 343 | { |
eb8305b1 | 344 | V4L2_DV_BT_CEA_1280X720P60, |
0b675536 SNC |
345 | tvp7002_parms_720P60, |
346 | V4L2_COLORSPACE_REC709, | |
347 | V4L2_FIELD_NONE, | |
348 | 1, | |
349 | 0x2EE, | |
350 | 135, | |
351 | 153 | |
352 | }, | |
353 | { | |
eb8305b1 | 354 | V4L2_DV_BT_CEA_1920X1080I60, |
0b675536 SNC |
355 | tvp7002_parms_1080I60, |
356 | V4L2_COLORSPACE_REC709, | |
357 | V4L2_FIELD_INTERLACED, | |
358 | 0, | |
359 | 0x465, | |
360 | 181, | |
361 | 205 | |
362 | }, | |
363 | { | |
eb8305b1 | 364 | V4L2_DV_BT_CEA_1920X1080I50, |
0b675536 SNC |
365 | tvp7002_parms_1080I50, |
366 | V4L2_COLORSPACE_REC709, | |
367 | V4L2_FIELD_INTERLACED, | |
368 | 0, | |
369 | 0x465, | |
370 | 217, | |
371 | 245 | |
372 | }, | |
373 | { | |
eb8305b1 | 374 | V4L2_DV_BT_CEA_1280X720P50, |
0b675536 SNC |
375 | tvp7002_parms_720P50, |
376 | V4L2_COLORSPACE_REC709, | |
377 | V4L2_FIELD_NONE, | |
378 | 1, | |
379 | 0x2EE, | |
380 | 163, | |
381 | 183 | |
382 | }, | |
383 | { | |
eb8305b1 | 384 | V4L2_DV_BT_CEA_1920X1080P60, |
0b675536 SNC |
385 | tvp7002_parms_1080P60, |
386 | V4L2_COLORSPACE_REC709, | |
387 | V4L2_FIELD_NONE, | |
388 | 1, | |
389 | 0x465, | |
390 | 90, | |
391 | 102 | |
392 | }, | |
393 | { | |
eb8305b1 | 394 | V4L2_DV_BT_CEA_720X480P59_94, |
0b675536 SNC |
395 | tvp7002_parms_480P, |
396 | V4L2_COLORSPACE_SMPTE170M, | |
397 | V4L2_FIELD_NONE, | |
398 | 1, | |
399 | 0x20D, | |
400 | 0xffff, | |
401 | 0xffff | |
402 | }, | |
403 | { | |
eb8305b1 | 404 | V4L2_DV_BT_CEA_720X576P50, |
0b675536 SNC |
405 | tvp7002_parms_576P, |
406 | V4L2_COLORSPACE_SMPTE170M, | |
407 | V4L2_FIELD_NONE, | |
408 | 1, | |
409 | 0x271, | |
410 | 0xffff, | |
411 | 0xffff | |
412 | } | |
413 | }; | |
414 | ||
f0cd015e | 415 | #define NUM_TIMINGS ARRAY_SIZE(tvp7002_timings) |
0b675536 SNC |
416 | |
417 | /* Device definition */ | |
418 | struct tvp7002 { | |
419 | struct v4l2_subdev sd; | |
0eb73de0 | 420 | struct v4l2_ctrl_handler hdl; |
0b675536 SNC |
421 | const struct tvp7002_config *pdata; |
422 | ||
423 | int ver; | |
424 | int streaming; | |
425 | ||
f0cd015e | 426 | const struct tvp7002_timings_definition *current_timings; |
0b675536 SNC |
427 | }; |
428 | ||
429 | /* | |
430 | * to_tvp7002 - Obtain device handler TVP7002 | |
431 | * @sd: ptr to v4l2_subdev struct | |
432 | * | |
433 | * Returns device handler tvp7002. | |
434 | */ | |
435 | static inline struct tvp7002 *to_tvp7002(struct v4l2_subdev *sd) | |
436 | { | |
437 | return container_of(sd, struct tvp7002, sd); | |
438 | } | |
439 | ||
0eb73de0 HV |
440 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) |
441 | { | |
442 | return &container_of(ctrl->handler, struct tvp7002, hdl)->sd; | |
443 | } | |
444 | ||
0b675536 SNC |
445 | /* |
446 | * tvp7002_read - Read a value from a register in an TVP7002 | |
447 | * @sd: ptr to v4l2_subdev struct | |
6fa7dac4 | 448 | * @addr: TVP7002 register address |
0b675536 SNC |
449 | * @dst: pointer to 8-bit destination |
450 | * | |
451 | * Returns value read if successful, or non-zero (-1) otherwise. | |
452 | */ | |
453 | static int tvp7002_read(struct v4l2_subdev *sd, u8 addr, u8 *dst) | |
454 | { | |
455 | struct i2c_client *c = v4l2_get_subdevdata(sd); | |
456 | int retry; | |
457 | int error; | |
458 | ||
459 | for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { | |
460 | error = i2c_smbus_read_byte_data(c, addr); | |
461 | ||
462 | if (error >= 0) { | |
463 | *dst = (u8)error; | |
464 | return 0; | |
465 | } | |
466 | ||
467 | msleep_interruptible(10); | |
468 | } | |
469 | v4l2_err(sd, "TVP7002 read error %d\n", error); | |
470 | return error; | |
471 | } | |
472 | ||
473 | /* | |
474 | * tvp7002_read_err() - Read a register value with error code | |
475 | * @sd: pointer to standard V4L2 sub-device structure | |
476 | * @reg: destination register | |
477 | * @val: value to be read | |
6fa7dac4 | 478 | * @err: pointer to error value |
0b675536 SNC |
479 | * |
480 | * Read a value in a register and save error value in pointer. | |
481 | * Also update the register table if successful | |
482 | */ | |
483 | static inline void tvp7002_read_err(struct v4l2_subdev *sd, u8 reg, | |
484 | u8 *dst, int *err) | |
485 | { | |
486 | if (!*err) | |
487 | *err = tvp7002_read(sd, reg, dst); | |
488 | } | |
489 | ||
490 | /* | |
491 | * tvp7002_write() - Write a value to a register in TVP7002 | |
492 | * @sd: ptr to v4l2_subdev struct | |
493 | * @addr: TVP7002 register address | |
494 | * @value: value to be written to the register | |
495 | * | |
496 | * Write a value to a register in an TVP7002 decoder device. | |
497 | * Returns zero if successful, or non-zero otherwise. | |
498 | */ | |
499 | static int tvp7002_write(struct v4l2_subdev *sd, u8 addr, u8 value) | |
500 | { | |
501 | struct i2c_client *c; | |
502 | int retry; | |
503 | int error; | |
504 | ||
505 | c = v4l2_get_subdevdata(sd); | |
506 | ||
507 | for (retry = 0; retry < I2C_RETRY_COUNT; retry++) { | |
508 | error = i2c_smbus_write_byte_data(c, addr, value); | |
509 | ||
510 | if (error >= 0) | |
511 | return 0; | |
512 | ||
513 | v4l2_warn(sd, "Write: retry ... %d\n", retry); | |
514 | msleep_interruptible(10); | |
515 | } | |
516 | v4l2_err(sd, "TVP7002 write error %d\n", error); | |
517 | return error; | |
518 | } | |
519 | ||
520 | /* | |
521 | * tvp7002_write_err() - Write a register value with error code | |
522 | * @sd: pointer to standard V4L2 sub-device structure | |
523 | * @reg: destination register | |
524 | * @val: value to be written | |
6fa7dac4 | 525 | * @err: pointer to error value |
0b675536 SNC |
526 | * |
527 | * Write a value in a register and save error value in pointer. | |
528 | * Also update the register table if successful | |
529 | */ | |
530 | static inline void tvp7002_write_err(struct v4l2_subdev *sd, u8 reg, | |
531 | u8 val, int *err) | |
532 | { | |
533 | if (!*err) | |
534 | *err = tvp7002_write(sd, reg, val); | |
535 | } | |
536 | ||
537 | /* | |
538 | * tvp7002_g_chip_ident() - Get chip identification number | |
539 | * @sd: ptr to v4l2_subdev struct | |
540 | * @chip: ptr to v4l2_dbg_chip_ident struct | |
541 | * | |
542 | * Obtains the chip's identification number. | |
543 | * Returns zero or -EINVAL if read operation fails. | |
544 | */ | |
545 | static int tvp7002_g_chip_ident(struct v4l2_subdev *sd, | |
546 | struct v4l2_dbg_chip_ident *chip) | |
547 | { | |
548 | u8 rev; | |
549 | int error; | |
550 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
551 | ||
552 | error = tvp7002_read(sd, TVP7002_CHIP_REV, &rev); | |
553 | ||
554 | if (error < 0) | |
555 | return error; | |
556 | ||
557 | return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_TVP7002, rev); | |
558 | } | |
559 | ||
560 | /* | |
561 | * tvp7002_write_inittab() - Write initialization values | |
562 | * @sd: ptr to v4l2_subdev struct | |
563 | * @regs: ptr to i2c_reg_value struct | |
564 | * | |
565 | * Write initialization values. | |
566 | * Returns zero or -EINVAL if read operation fails. | |
567 | */ | |
568 | static int tvp7002_write_inittab(struct v4l2_subdev *sd, | |
569 | const struct i2c_reg_value *regs) | |
570 | { | |
571 | int error = 0; | |
572 | ||
573 | /* Initialize the first (defined) registers */ | |
574 | while (TVP7002_EOR != regs->reg) { | |
575 | if (TVP7002_WRITE == regs->type) | |
576 | tvp7002_write_err(sd, regs->reg, regs->value, &error); | |
577 | regs++; | |
578 | } | |
579 | ||
580 | return error; | |
581 | } | |
582 | ||
eb8305b1 HV |
583 | static int tvp7002_s_dv_timings(struct v4l2_subdev *sd, |
584 | struct v4l2_dv_timings *dv_timings) | |
585 | { | |
586 | struct tvp7002 *device = to_tvp7002(sd); | |
587 | const struct v4l2_bt_timings *bt = &dv_timings->bt; | |
588 | int i; | |
589 | ||
590 | if (dv_timings->type != V4L2_DV_BT_656_1120) | |
591 | return -EINVAL; | |
f0cd015e HV |
592 | for (i = 0; i < NUM_TIMINGS; i++) { |
593 | const struct v4l2_bt_timings *t = &tvp7002_timings[i].timings.bt; | |
eb8305b1 HV |
594 | |
595 | if (!memcmp(bt, t, &bt->standards - &bt->width)) { | |
f0cd015e HV |
596 | device->current_timings = &tvp7002_timings[i]; |
597 | return tvp7002_write_inittab(sd, tvp7002_timings[i].p_settings); | |
eb8305b1 HV |
598 | } |
599 | } | |
600 | return -EINVAL; | |
601 | } | |
602 | ||
603 | static int tvp7002_g_dv_timings(struct v4l2_subdev *sd, | |
604 | struct v4l2_dv_timings *dv_timings) | |
605 | { | |
606 | struct tvp7002 *device = to_tvp7002(sd); | |
607 | ||
f0cd015e | 608 | *dv_timings = device->current_timings->timings; |
eb8305b1 HV |
609 | return 0; |
610 | } | |
611 | ||
0b675536 SNC |
612 | /* |
613 | * tvp7002_s_ctrl() - Set a control | |
0eb73de0 | 614 | * @ctrl: ptr to v4l2_ctrl struct |
0b675536 SNC |
615 | * |
616 | * Set a control in TVP7002 decoder device. | |
617 | * Returns zero when successful or -EINVAL if register access fails. | |
618 | */ | |
0eb73de0 | 619 | static int tvp7002_s_ctrl(struct v4l2_ctrl *ctrl) |
0b675536 | 620 | { |
0eb73de0 | 621 | struct v4l2_subdev *sd = to_sd(ctrl); |
0b675536 SNC |
622 | int error = 0; |
623 | ||
624 | switch (ctrl->id) { | |
625 | case V4L2_CID_GAIN: | |
0eb73de0 HV |
626 | tvp7002_write_err(sd, TVP7002_R_FINE_GAIN, ctrl->val, &error); |
627 | tvp7002_write_err(sd, TVP7002_G_FINE_GAIN, ctrl->val, &error); | |
628 | tvp7002_write_err(sd, TVP7002_B_FINE_GAIN, ctrl->val, &error); | |
629 | return error; | |
0b675536 | 630 | } |
0eb73de0 | 631 | return -EINVAL; |
0b675536 SNC |
632 | } |
633 | ||
db7b5460 HV |
634 | /* |
635 | * tvp7002_mbus_fmt() - V4L2 decoder interface handler for try/s/g_mbus_fmt | |
636 | * @sd: pointer to standard V4L2 sub-device structure | |
637 | * @f: pointer to mediabus format structure | |
638 | * | |
639 | * Negotiate the image capture size and mediabus format. | |
640 | * There is only one possible format, so this single function works for | |
641 | * get, set and try. | |
642 | */ | |
643 | static int tvp7002_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *f) | |
644 | { | |
645 | struct tvp7002 *device = to_tvp7002(sd); | |
f96067af | 646 | const struct v4l2_bt_timings *bt = &device->current_timings->timings.bt; |
db7b5460 | 647 | |
f96067af HV |
648 | f->width = bt->width; |
649 | f->height = bt->height; | |
db7b5460 | 650 | f->code = V4L2_MBUS_FMT_YUYV10_1X20; |
f0cd015e HV |
651 | f->field = device->current_timings->scanmode; |
652 | f->colorspace = device->current_timings->color_space; | |
db7b5460 HV |
653 | |
654 | v4l2_dbg(1, debug, sd, "MBUS_FMT: Width - %d, Height - %d", | |
655 | f->width, f->height); | |
656 | return 0; | |
657 | } | |
658 | ||
0b675536 | 659 | /* |
f0cd015e | 660 | * tvp7002_query_dv() - query DV timings |
0b675536 | 661 | * @sd: pointer to standard V4L2 sub-device structure |
f0cd015e | 662 | * @index: index into the tvp7002_timings array |
0b675536 | 663 | * |
f0cd015e | 664 | * Returns the current DV timings detected by TVP7002. If no active input is |
0b675536 SNC |
665 | * detected, returns -EINVAL |
666 | */ | |
eb8305b1 | 667 | static int tvp7002_query_dv(struct v4l2_subdev *sd, int *index) |
0b675536 | 668 | { |
f0cd015e | 669 | const struct tvp7002_timings_definition *timings = tvp7002_timings; |
0b675536 SNC |
670 | u8 progressive; |
671 | u32 lpfr; | |
672 | u32 cpln; | |
673 | int error = 0; | |
674 | u8 lpf_lsb; | |
675 | u8 lpf_msb; | |
676 | u8 cpl_lsb; | |
677 | u8 cpl_msb; | |
0b675536 | 678 | |
eb8305b1 | 679 | /* Return invalid index if no active input is detected */ |
f0cd015e | 680 | *index = NUM_TIMINGS; |
ab0ab190 | 681 | |
0b675536 SNC |
682 | /* Read standards from device registers */ |
683 | tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_LSBS, &lpf_lsb, &error); | |
684 | tvp7002_read_err(sd, TVP7002_L_FRAME_STAT_MSBS, &lpf_msb, &error); | |
685 | ||
686 | if (error < 0) | |
687 | return error; | |
688 | ||
689 | tvp7002_read_err(sd, TVP7002_CLK_L_STAT_LSBS, &cpl_lsb, &error); | |
690 | tvp7002_read_err(sd, TVP7002_CLK_L_STAT_MSBS, &cpl_msb, &error); | |
691 | ||
692 | if (error < 0) | |
693 | return error; | |
694 | ||
695 | /* Get lines per frame, clocks per line and interlaced/progresive */ | |
696 | lpfr = lpf_lsb | ((TVP7002_CL_MASK & lpf_msb) << TVP7002_CL_SHIFT); | |
697 | cpln = cpl_lsb | ((TVP7002_CL_MASK & cpl_msb) << TVP7002_CL_SHIFT); | |
698 | progressive = (lpf_msb & TVP7002_INPR_MASK) >> TVP7002_IP_SHIFT; | |
699 | ||
700 | /* Do checking of video modes */ | |
f0cd015e HV |
701 | for (*index = 0; *index < NUM_TIMINGS; (*index)++, timings++) |
702 | if (lpfr == timings->lines_per_frame && | |
703 | progressive == timings->progressive) { | |
704 | if (timings->cpl_min == 0xffff) | |
0b675536 | 705 | break; |
f0cd015e | 706 | if (cpln >= timings->cpl_min && cpln <= timings->cpl_max) |
0b675536 SNC |
707 | break; |
708 | } | |
709 | ||
f0cd015e | 710 | if (*index == NUM_TIMINGS) { |
cf19cd3d | 711 | v4l2_dbg(1, debug, sd, "detection failed: lpf = %x, cpl = %x\n", |
0b675536 | 712 | lpfr, cpln); |
eb8305b1 | 713 | return -ENOLINK; |
0b675536 SNC |
714 | } |
715 | ||
0b675536 | 716 | /* Update lines per frame and clocks per line info */ |
f0cd015e | 717 | v4l2_dbg(1, debug, sd, "detected timings: %d\n", *index); |
eb8305b1 HV |
718 | return 0; |
719 | } | |
720 | ||
eb8305b1 HV |
721 | static int tvp7002_query_dv_timings(struct v4l2_subdev *sd, |
722 | struct v4l2_dv_timings *timings) | |
723 | { | |
724 | int index; | |
725 | int err = tvp7002_query_dv(sd, &index); | |
726 | ||
727 | if (err) | |
728 | return err; | |
f0cd015e | 729 | *timings = tvp7002_timings[index].timings; |
0b675536 SNC |
730 | return 0; |
731 | } | |
732 | ||
733 | #ifdef CONFIG_VIDEO_ADV_DEBUG | |
734 | /* | |
735 | * tvp7002_g_register() - Get the value of a register | |
736 | * @sd: ptr to v4l2_subdev struct | |
6fa7dac4 | 737 | * @reg: ptr to v4l2_dbg_register struct |
0b675536 SNC |
738 | * |
739 | * Get the value of a TVP7002 decoder device register. | |
740 | * Returns zero when successful, -EINVAL if register read fails or | |
741 | * access to I2C client fails, -EPERM if the call is not allowed | |
eb78bd7d | 742 | * by disabled CAP_SYS_ADMIN. |
0b675536 SNC |
743 | */ |
744 | static int tvp7002_g_register(struct v4l2_subdev *sd, | |
745 | struct v4l2_dbg_register *reg) | |
746 | { | |
747 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
dfbd5d4d HV |
748 | u8 val; |
749 | int ret; | |
0b675536 SNC |
750 | |
751 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
752 | return -EINVAL; | |
753 | if (!capable(CAP_SYS_ADMIN)) | |
754 | return -EPERM; | |
755 | ||
dfbd5d4d HV |
756 | ret = tvp7002_read(sd, reg->reg & 0xff, &val); |
757 | reg->val = val; | |
758 | return ret; | |
0b675536 SNC |
759 | } |
760 | ||
761 | /* | |
762 | * tvp7002_s_register() - set a control | |
763 | * @sd: ptr to v4l2_subdev struct | |
6fa7dac4 | 764 | * @reg: ptr to v4l2_dbg_register struct |
0b675536 SNC |
765 | * |
766 | * Get the value of a TVP7002 decoder device register. | |
767 | * Returns zero when successful, -EINVAL if register read fails or | |
768 | * -EPERM if call not allowed. | |
769 | */ | |
770 | static int tvp7002_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 771 | const struct v4l2_dbg_register *reg) |
0b675536 SNC |
772 | { |
773 | struct i2c_client *client = v4l2_get_subdevdata(sd); | |
0b675536 SNC |
774 | |
775 | if (!v4l2_chip_match_i2c_client(client, ®->match)) | |
776 | return -EINVAL; | |
777 | if (!capable(CAP_SYS_ADMIN)) | |
778 | return -EPERM; | |
779 | ||
dfbd5d4d | 780 | return tvp7002_write(sd, reg->reg & 0xff, reg->val & 0xff); |
0b675536 SNC |
781 | } |
782 | #endif | |
783 | ||
db7b5460 HV |
784 | /* |
785 | * tvp7002_enum_mbus_fmt() - Enum supported mediabus formats | |
786 | * @sd: pointer to standard V4L2 sub-device structure | |
787 | * @index: format index | |
788 | * @code: pointer to mediabus format | |
789 | * | |
790 | * Enumerate supported mediabus formats. | |
791 | */ | |
792 | ||
793 | static int tvp7002_enum_mbus_fmt(struct v4l2_subdev *sd, unsigned index, | |
794 | enum v4l2_mbus_pixelcode *code) | |
795 | { | |
796 | /* Check requested format index is within range */ | |
797 | if (index) | |
798 | return -EINVAL; | |
799 | *code = V4L2_MBUS_FMT_YUYV10_1X20; | |
800 | return 0; | |
801 | } | |
802 | ||
0b675536 SNC |
803 | /* |
804 | * tvp7002_s_stream() - V4L2 decoder i/f handler for s_stream | |
805 | * @sd: pointer to standard V4L2 sub-device structure | |
806 | * @enable: streaming enable or disable | |
807 | * | |
808 | * Sets streaming to enable or disable, if possible. | |
809 | */ | |
810 | static int tvp7002_s_stream(struct v4l2_subdev *sd, int enable) | |
811 | { | |
812 | struct tvp7002 *device = to_tvp7002(sd); | |
813 | int error = 0; | |
814 | ||
815 | if (device->streaming == enable) | |
816 | return 0; | |
817 | ||
818 | if (enable) { | |
819 | /* Set output state on (low impedance means stream on) */ | |
820 | error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x00); | |
821 | device->streaming = enable; | |
822 | } else { | |
823 | /* Set output state off (high impedance means stream off) */ | |
824 | error = tvp7002_write(sd, TVP7002_MISC_CTL_2, 0x03); | |
825 | if (error) | |
826 | v4l2_dbg(1, debug, sd, "Unable to stop streaming\n"); | |
827 | ||
828 | device->streaming = enable; | |
829 | } | |
830 | ||
831 | return error; | |
832 | } | |
833 | ||
834 | /* | |
835 | * tvp7002_log_status() - Print information about register settings | |
836 | * @sd: ptr to v4l2_subdev struct | |
837 | * | |
838 | * Log register values of a TVP7002 decoder device. | |
839 | * Returns zero or -EINVAL if read operation fails. | |
840 | */ | |
841 | static int tvp7002_log_status(struct v4l2_subdev *sd) | |
842 | { | |
0b675536 | 843 | struct tvp7002 *device = to_tvp7002(sd); |
f96067af HV |
844 | const struct v4l2_bt_timings *bt; |
845 | int detected; | |
0b675536 | 846 | |
f96067af HV |
847 | /* Find my current timings */ |
848 | tvp7002_query_dv(sd, &detected); | |
0b675536 | 849 | |
f96067af HV |
850 | bt = &device->current_timings->timings.bt; |
851 | v4l2_info(sd, "Selected DV Timings: %ux%u\n", bt->width, bt->height); | |
852 | if (detected == NUM_TIMINGS) { | |
853 | v4l2_info(sd, "Detected DV Timings: None\n"); | |
0b675536 | 854 | } else { |
f96067af HV |
855 | bt = &tvp7002_timings[detected].timings.bt; |
856 | v4l2_info(sd, "Detected DV Timings: %ux%u\n", | |
857 | bt->width, bt->height); | |
0b675536 SNC |
858 | } |
859 | v4l2_info(sd, "Streaming enabled: %s\n", | |
860 | device->streaming ? "yes" : "no"); | |
861 | ||
862 | /* Print the current value of the gain control */ | |
0eb73de0 | 863 | v4l2_ctrl_handler_log_status(&device->hdl, sd->name); |
0b675536 SNC |
864 | |
865 | return 0; | |
866 | } | |
867 | ||
eb8305b1 HV |
868 | static int tvp7002_enum_dv_timings(struct v4l2_subdev *sd, |
869 | struct v4l2_enum_dv_timings *timings) | |
870 | { | |
871 | /* Check requested format index is within range */ | |
f0cd015e | 872 | if (timings->index >= NUM_TIMINGS) |
eb8305b1 HV |
873 | return -EINVAL; |
874 | ||
f0cd015e | 875 | timings->timings = tvp7002_timings[timings->index].timings; |
eb8305b1 HV |
876 | return 0; |
877 | } | |
878 | ||
0eb73de0 HV |
879 | static const struct v4l2_ctrl_ops tvp7002_ctrl_ops = { |
880 | .s_ctrl = tvp7002_s_ctrl, | |
881 | }; | |
882 | ||
0b675536 SNC |
883 | /* V4L2 core operation handlers */ |
884 | static const struct v4l2_subdev_core_ops tvp7002_core_ops = { | |
885 | .g_chip_ident = tvp7002_g_chip_ident, | |
886 | .log_status = tvp7002_log_status, | |
0eb73de0 HV |
887 | .g_ext_ctrls = v4l2_subdev_g_ext_ctrls, |
888 | .try_ext_ctrls = v4l2_subdev_try_ext_ctrls, | |
889 | .s_ext_ctrls = v4l2_subdev_s_ext_ctrls, | |
890 | .g_ctrl = v4l2_subdev_g_ctrl, | |
891 | .s_ctrl = v4l2_subdev_s_ctrl, | |
892 | .queryctrl = v4l2_subdev_queryctrl, | |
893 | .querymenu = v4l2_subdev_querymenu, | |
0b675536 SNC |
894 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
895 | .g_register = tvp7002_g_register, | |
896 | .s_register = tvp7002_s_register, | |
897 | #endif | |
898 | }; | |
899 | ||
900 | /* Specific video subsystem operation handlers */ | |
901 | static const struct v4l2_subdev_video_ops tvp7002_video_ops = { | |
eb8305b1 HV |
902 | .g_dv_timings = tvp7002_g_dv_timings, |
903 | .s_dv_timings = tvp7002_s_dv_timings, | |
904 | .enum_dv_timings = tvp7002_enum_dv_timings, | |
905 | .query_dv_timings = tvp7002_query_dv_timings, | |
0b675536 | 906 | .s_stream = tvp7002_s_stream, |
db7b5460 HV |
907 | .g_mbus_fmt = tvp7002_mbus_fmt, |
908 | .try_mbus_fmt = tvp7002_mbus_fmt, | |
909 | .s_mbus_fmt = tvp7002_mbus_fmt, | |
910 | .enum_mbus_fmt = tvp7002_enum_mbus_fmt, | |
0b675536 SNC |
911 | }; |
912 | ||
913 | /* V4L2 top level operation handlers */ | |
914 | static const struct v4l2_subdev_ops tvp7002_ops = { | |
915 | .core = &tvp7002_core_ops, | |
916 | .video = &tvp7002_video_ops, | |
917 | }; | |
918 | ||
0b675536 SNC |
919 | /* |
920 | * tvp7002_probe - Probe a TVP7002 device | |
6fa7dac4 MR |
921 | * @c: ptr to i2c_client struct |
922 | * @id: ptr to i2c_device_id struct | |
0b675536 SNC |
923 | * |
924 | * Initialize the TVP7002 device | |
925 | * Returns zero when successful, -EINVAL if register read fails or | |
926 | * -EIO if i2c access is not available. | |
927 | */ | |
928 | static int tvp7002_probe(struct i2c_client *c, const struct i2c_device_id *id) | |
929 | { | |
930 | struct v4l2_subdev *sd; | |
931 | struct tvp7002 *device; | |
f96067af | 932 | struct v4l2_dv_timings timings; |
0b675536 SNC |
933 | int polarity_a; |
934 | int polarity_b; | |
935 | u8 revision; | |
936 | ||
937 | int error; | |
938 | ||
939 | /* Check if the adapter supports the needed features */ | |
940 | if (!i2c_check_functionality(c->adapter, | |
941 | I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) | |
942 | return -EIO; | |
943 | ||
944 | if (!c->dev.platform_data) { | |
945 | v4l_err(c, "No platform data!!\n"); | |
946 | return -ENODEV; | |
947 | } | |
948 | ||
f3e8e4f1 | 949 | device = devm_kzalloc(&c->dev, sizeof(struct tvp7002), GFP_KERNEL); |
0b675536 SNC |
950 | |
951 | if (!device) | |
952 | return -ENOMEM; | |
953 | ||
0b675536 SNC |
954 | sd = &device->sd; |
955 | device->pdata = c->dev.platform_data; | |
f0cd015e | 956 | device->current_timings = tvp7002_timings; |
0b675536 SNC |
957 | |
958 | /* Tell v4l2 the device is ready */ | |
959 | v4l2_i2c_subdev_init(sd, c, &tvp7002_ops); | |
960 | v4l_info(c, "tvp7002 found @ 0x%02x (%s)\n", | |
961 | c->addr, c->adapter->name); | |
962 | ||
963 | error = tvp7002_read(sd, TVP7002_CHIP_REV, &revision); | |
964 | if (error < 0) | |
f3e8e4f1 | 965 | return error; |
0b675536 SNC |
966 | |
967 | /* Get revision number */ | |
968 | v4l2_info(sd, "Rev. %02x detected.\n", revision); | |
969 | if (revision != 0x02) | |
970 | v4l2_info(sd, "Unknown revision detected.\n"); | |
971 | ||
972 | /* Initializes TVP7002 to its default values */ | |
973 | error = tvp7002_write_inittab(sd, tvp7002_init_default); | |
974 | ||
975 | if (error < 0) | |
f3e8e4f1 | 976 | return error; |
0b675536 SNC |
977 | |
978 | /* Set polarity information after registers have been set */ | |
979 | polarity_a = 0x20 | device->pdata->hs_polarity << 5 | |
980 | | device->pdata->vs_polarity << 2; | |
981 | error = tvp7002_write(sd, TVP7002_SYNC_CTL_1, polarity_a); | |
982 | if (error < 0) | |
f3e8e4f1 | 983 | return error; |
0b675536 SNC |
984 | |
985 | polarity_b = 0x01 | device->pdata->fid_polarity << 2 | |
986 | | device->pdata->sog_polarity << 1 | |
987 | | device->pdata->clk_polarity; | |
988 | error = tvp7002_write(sd, TVP7002_MISC_CTL_3, polarity_b); | |
989 | if (error < 0) | |
f3e8e4f1 | 990 | return error; |
0b675536 SNC |
991 | |
992 | /* Set registers according to default video mode */ | |
f96067af HV |
993 | timings = device->current_timings->timings; |
994 | error = tvp7002_s_dv_timings(sd, &timings); | |
0b675536 | 995 | |
0eb73de0 HV |
996 | v4l2_ctrl_handler_init(&device->hdl, 1); |
997 | v4l2_ctrl_new_std(&device->hdl, &tvp7002_ctrl_ops, | |
998 | V4L2_CID_GAIN, 0, 255, 1, 0); | |
999 | sd->ctrl_handler = &device->hdl; | |
1000 | if (device->hdl.error) { | |
1001 | int err = device->hdl.error; | |
1002 | ||
1003 | v4l2_ctrl_handler_free(&device->hdl); | |
0eb73de0 HV |
1004 | return err; |
1005 | } | |
1006 | v4l2_ctrl_handler_setup(&device->hdl); | |
1007 | ||
f3e8e4f1 | 1008 | return 0; |
0b675536 SNC |
1009 | } |
1010 | ||
1011 | /* | |
1012 | * tvp7002_remove - Remove TVP7002 device support | |
1013 | * @c: ptr to i2c_client struct | |
1014 | * | |
1015 | * Reset the TVP7002 device | |
1016 | * Returns zero. | |
1017 | */ | |
1018 | static int tvp7002_remove(struct i2c_client *c) | |
1019 | { | |
1020 | struct v4l2_subdev *sd = i2c_get_clientdata(c); | |
1021 | struct tvp7002 *device = to_tvp7002(sd); | |
1022 | ||
1023 | v4l2_dbg(1, debug, sd, "Removing tvp7002 adapter" | |
1024 | "on address 0x%x\n", c->addr); | |
1025 | ||
1026 | v4l2_device_unregister_subdev(sd); | |
0eb73de0 | 1027 | v4l2_ctrl_handler_free(&device->hdl); |
0b675536 SNC |
1028 | return 0; |
1029 | } | |
1030 | ||
1031 | /* I2C Device ID table */ | |
1032 | static const struct i2c_device_id tvp7002_id[] = { | |
1033 | { "tvp7002", 0 }, | |
1034 | { } | |
1035 | }; | |
1036 | MODULE_DEVICE_TABLE(i2c, tvp7002_id); | |
1037 | ||
1038 | /* I2C driver data */ | |
1039 | static struct i2c_driver tvp7002_driver = { | |
1040 | .driver = { | |
1041 | .owner = THIS_MODULE, | |
1042 | .name = TVP7002_MODULE_NAME, | |
1043 | }, | |
1044 | .probe = tvp7002_probe, | |
1045 | .remove = tvp7002_remove, | |
1046 | .id_table = tvp7002_id, | |
1047 | }; | |
1048 | ||
c6e8d86f | 1049 | module_i2c_driver(tvp7002_driver); |