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d2da2611 SNC |
1 | /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics |
2 | * Digitizer with Horizontal PLL registers | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments Inc | |
5 | * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com> | |
6 | * | |
7 | * This code is partially based upon the TVP5150 driver | |
8 | * written by Mauro Carvalho Chehab (mchehab@infradead.org), | |
9 | * the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com> | |
10 | * and the TVP7002 driver in the TI LSP 2.10.00.14 | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
26 | ||
27 | /* Naming conventions | |
28 | * ------------------ | |
29 | * | |
30 | * FDBK: Feedback | |
31 | * DIV: Divider | |
32 | * CTL: Control | |
33 | * SEL: Select | |
34 | * IN: Input | |
35 | * OUT: Output | |
36 | * R: Red | |
37 | * G: Green | |
38 | * B: Blue | |
39 | * OFF: Offset | |
40 | * THRS: Threshold | |
41 | * DGTL: Digital | |
42 | * LVL: Level | |
43 | * PWR: Power | |
44 | * MVIS: Macrovision | |
45 | * W: Width | |
46 | * H: Height | |
47 | * ALGN: Alignment | |
48 | * CLK: Clocks | |
49 | * TOL: Tolerance | |
50 | * BWTH: Bandwidth | |
51 | * COEF: Coefficient | |
52 | * STAT: Status | |
53 | * AUTO: Automatic | |
54 | * FLD: Field | |
55 | * L: Line | |
56 | */ | |
57 | ||
58 | #define TVP7002_CHIP_REV 0x00 | |
59 | #define TVP7002_HPLL_FDBK_DIV_MSBS 0x01 | |
60 | #define TVP7002_HPLL_FDBK_DIV_LSBS 0x02 | |
61 | #define TVP7002_HPLL_CRTL 0x03 | |
62 | #define TVP7002_HPLL_PHASE_SEL 0x04 | |
63 | #define TVP7002_CLAMP_START 0x05 | |
64 | #define TVP7002_CLAMP_W 0x06 | |
65 | #define TVP7002_HSYNC_OUT_W 0x07 | |
66 | #define TVP7002_B_FINE_GAIN 0x08 | |
67 | #define TVP7002_G_FINE_GAIN 0x09 | |
68 | #define TVP7002_R_FINE_GAIN 0x0a | |
69 | #define TVP7002_B_FINE_OFF_MSBS 0x0b | |
70 | #define TVP7002_G_FINE_OFF_MSBS 0x0c | |
71 | #define TVP7002_R_FINE_OFF_MSBS 0x0d | |
72 | #define TVP7002_SYNC_CTL_1 0x0e | |
73 | #define TVP7002_HPLL_AND_CLAMP_CTL 0x0f | |
74 | #define TVP7002_SYNC_ON_G_THRS 0x10 | |
75 | #define TVP7002_SYNC_SEPARATOR_THRS 0x11 | |
76 | #define TVP7002_HPLL_PRE_COAST 0x12 | |
77 | #define TVP7002_HPLL_POST_COAST 0x13 | |
78 | #define TVP7002_SYNC_DETECT_STAT 0x14 | |
79 | #define TVP7002_OUT_FORMATTER 0x15 | |
80 | #define TVP7002_MISC_CTL_1 0x16 | |
81 | #define TVP7002_MISC_CTL_2 0x17 | |
82 | #define TVP7002_MISC_CTL_3 0x18 | |
83 | #define TVP7002_IN_MUX_SEL_1 0x19 | |
84 | #define TVP7002_IN_MUX_SEL_2 0x1a | |
85 | #define TVP7002_B_AND_G_COARSE_GAIN 0x1b | |
86 | #define TVP7002_R_COARSE_GAIN 0x1c | |
87 | #define TVP7002_FINE_OFF_LSBS 0x1d | |
88 | #define TVP7002_B_COARSE_OFF 0x1e | |
89 | #define TVP7002_G_COARSE_OFF 0x1f | |
90 | #define TVP7002_R_COARSE_OFF 0x20 | |
91 | #define TVP7002_HSOUT_OUT_START 0x21 | |
92 | #define TVP7002_MISC_CTL_4 0x22 | |
93 | #define TVP7002_B_DGTL_ALC_OUT_LSBS 0x23 | |
94 | #define TVP7002_G_DGTL_ALC_OUT_LSBS 0x24 | |
95 | #define TVP7002_R_DGTL_ALC_OUT_LSBS 0x25 | |
96 | #define TVP7002_AUTO_LVL_CTL_ENABLE 0x26 | |
97 | #define TVP7002_DGTL_ALC_OUT_MSBS 0x27 | |
98 | #define TVP7002_AUTO_LVL_CTL_FILTER 0x28 | |
99 | /* Reserved 0x29*/ | |
100 | #define TVP7002_FINE_CLAMP_CTL 0x2a | |
101 | #define TVP7002_PWR_CTL 0x2b | |
102 | #define TVP7002_ADC_SETUP 0x2c | |
103 | #define TVP7002_COARSE_CLAMP_CTL 0x2d | |
104 | #define TVP7002_SOG_CLAMP 0x2e | |
105 | #define TVP7002_RGB_COARSE_CLAMP_CTL 0x2f | |
106 | #define TVP7002_SOG_COARSE_CLAMP_CTL 0x30 | |
107 | #define TVP7002_ALC_PLACEMENT 0x31 | |
108 | /* Reserved 0x32 */ | |
109 | /* Reserved 0x33 */ | |
110 | #define TVP7002_MVIS_STRIPPER_W 0x34 | |
111 | #define TVP7002_VSYNC_ALGN 0x35 | |
112 | #define TVP7002_SYNC_BYPASS 0x36 | |
113 | #define TVP7002_L_FRAME_STAT_LSBS 0x37 | |
114 | #define TVP7002_L_FRAME_STAT_MSBS 0x38 | |
115 | #define TVP7002_CLK_L_STAT_LSBS 0x39 | |
116 | #define TVP7002_CLK_L_STAT_MSBS 0x3a | |
117 | #define TVP7002_HSYNC_W 0x3b | |
118 | #define TVP7002_VSYNC_W 0x3c | |
119 | #define TVP7002_L_LENGTH_TOL 0x3d | |
120 | /* Reserved 0x3e */ | |
121 | #define TVP7002_VIDEO_BWTH_CTL 0x3f | |
122 | #define TVP7002_AVID_START_PIXEL_LSBS 0x40 | |
123 | #define TVP7002_AVID_START_PIXEL_MSBS 0x41 | |
124 | #define TVP7002_AVID_STOP_PIXEL_LSBS 0x42 | |
125 | #define TVP7002_AVID_STOP_PIXEL_MSBS 0x43 | |
126 | #define TVP7002_VBLK_F_0_START_L_OFF 0x44 | |
127 | #define TVP7002_VBLK_F_1_START_L_OFF 0x45 | |
128 | #define TVP7002_VBLK_F_0_DURATION 0x46 | |
129 | #define TVP7002_VBLK_F_1_DURATION 0x47 | |
130 | #define TVP7002_FBIT_F_0_START_L_OFF 0x48 | |
131 | #define TVP7002_FBIT_F_1_START_L_OFF 0x49 | |
132 | #define TVP7002_YUV_Y_G_COEF_LSBS 0x4a | |
133 | #define TVP7002_YUV_Y_G_COEF_MSBS 0x4b | |
134 | #define TVP7002_YUV_Y_B_COEF_LSBS 0x4c | |
135 | #define TVP7002_YUV_Y_B_COEF_MSBS 0x4d | |
136 | #define TVP7002_YUV_Y_R_COEF_LSBS 0x4e | |
137 | #define TVP7002_YUV_Y_R_COEF_MSBS 0x4f | |
138 | #define TVP7002_YUV_U_G_COEF_LSBS 0x50 | |
139 | #define TVP7002_YUV_U_G_COEF_MSBS 0x51 | |
140 | #define TVP7002_YUV_U_B_COEF_LSBS 0x52 | |
141 | #define TVP7002_YUV_U_B_COEF_MSBS 0x53 | |
142 | #define TVP7002_YUV_U_R_COEF_LSBS 0x54 | |
143 | #define TVP7002_YUV_U_R_COEF_MSBS 0x55 | |
144 | #define TVP7002_YUV_V_G_COEF_LSBS 0x56 | |
145 | #define TVP7002_YUV_V_G_COEF_MSBS 0x57 | |
146 | #define TVP7002_YUV_V_B_COEF_LSBS 0x58 | |
147 | #define TVP7002_YUV_V_B_COEF_MSBS 0x59 | |
148 | #define TVP7002_YUV_V_R_COEF_LSBS 0x5a | |
149 | #define TVP7002_YUV_V_R_COEF_MSBS 0x5b | |
150 |