Commit | Line | Data |
---|---|---|
1c1e45d1 HV |
1 | /* |
2 | * cx18 ADEC audio functions | |
3 | * | |
4 | * Derived from cx25840-core.c | |
5 | * | |
6 | * Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl> | |
6afdeaf8 | 7 | * Copyright (C) 2008 Andy Walls <awalls@md.metrocast.net> |
1c1e45d1 HV |
8 | * |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
22 | * 02110-1301, USA. | |
23 | */ | |
24 | ||
25 | #include "cx18-driver.h" | |
b1526421 | 26 | #include "cx18-io.h" |
1a267046 | 27 | #include "cx18-cards.h" |
1c1e45d1 HV |
28 | |
29 | int cx18_av_write(struct cx18 *cx, u16 addr, u8 value) | |
30 | { | |
b1526421 | 31 | u32 reg = 0xc40000 + (addr & ~3); |
1c1e45d1 HV |
32 | u32 mask = 0xff; |
33 | int shift = (addr & 3) * 8; | |
b1526421 | 34 | u32 x = cx18_read_reg(cx, reg); |
1c1e45d1 HV |
35 | |
36 | x = (x & ~(mask << shift)) | ((u32)value << shift); | |
b1526421 | 37 | cx18_write_reg(cx, x, reg); |
1c1e45d1 HV |
38 | return 0; |
39 | } | |
40 | ||
ced07371 AW |
41 | int cx18_av_write_expect(struct cx18 *cx, u16 addr, u8 value, u8 eval, u8 mask) |
42 | { | |
43 | u32 reg = 0xc40000 + (addr & ~3); | |
44 | int shift = (addr & 3) * 8; | |
45 | u32 x = cx18_read_reg(cx, reg); | |
46 | ||
47 | x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); | |
48 | cx18_write_reg_expect(cx, x, reg, | |
49 | ((u32)eval << shift), ((u32)mask << shift)); | |
50 | return 0; | |
51 | } | |
52 | ||
1c1e45d1 HV |
53 | int cx18_av_write4(struct cx18 *cx, u16 addr, u32 value) |
54 | { | |
b1526421 | 55 | cx18_write_reg(cx, value, 0xc40000 + addr); |
1c1e45d1 HV |
56 | return 0; |
57 | } | |
58 | ||
ced07371 AW |
59 | int |
60 | cx18_av_write4_expect(struct cx18 *cx, u16 addr, u32 value, u32 eval, u32 mask) | |
61 | { | |
62 | cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); | |
63 | return 0; | |
64 | } | |
65 | ||
d267d851 AW |
66 | int cx18_av_write4_noretry(struct cx18 *cx, u16 addr, u32 value) |
67 | { | |
68 | cx18_write_reg_noretry(cx, value, 0xc40000 + addr); | |
69 | return 0; | |
70 | } | |
71 | ||
1c1e45d1 HV |
72 | u8 cx18_av_read(struct cx18 *cx, u16 addr) |
73 | { | |
b1526421 | 74 | u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3)); |
1c1e45d1 HV |
75 | int shift = (addr & 3) * 8; |
76 | ||
77 | return (x >> shift) & 0xff; | |
78 | } | |
79 | ||
80 | u32 cx18_av_read4(struct cx18 *cx, u16 addr) | |
81 | { | |
b1526421 | 82 | return cx18_read_reg(cx, 0xc40000 + addr); |
1c1e45d1 HV |
83 | } |
84 | ||
85 | int cx18_av_and_or(struct cx18 *cx, u16 addr, unsigned and_mask, | |
86 | u8 or_value) | |
87 | { | |
88 | return cx18_av_write(cx, addr, | |
89 | (cx18_av_read(cx, addr) & and_mask) | | |
90 | or_value); | |
91 | } | |
92 | ||
93 | int cx18_av_and_or4(struct cx18 *cx, u16 addr, u32 and_mask, | |
94 | u32 or_value) | |
95 | { | |
96 | return cx18_av_write4(cx, addr, | |
97 | (cx18_av_read4(cx, addr) & and_mask) | | |
98 | or_value); | |
99 | } | |
100 | ||
7f3ea4de | 101 | static void cx18_av_init(struct cx18 *cx) |
1c1e45d1 | 102 | { |
f4672dff AW |
103 | /* |
104 | * The crystal freq used in calculations in this driver will be | |
105 | * 28.636360 MHz. | |
106 | * Aim to run the PLLs' VCOs near 400 MHz to minimze errors. | |
107 | */ | |
108 | ||
109 | /* | |
110 | * VDCLK Integer = 0x0f, Post Divider = 0x04 | |
111 | * AIMCLK Integer = 0x0e, Post Divider = 0x16 | |
112 | */ | |
113 | cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f); | |
114 | ||
115 | /* VDCLK Fraction = 0x2be2fe */ | |
116 | /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */ | |
117 | cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe); | |
118 | ||
119 | /* AIMCLK Fraction = 0x05227ad */ | |
120 | /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/ | |
121 | cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad); | |
122 | ||
123 | /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */ | |
124 | cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56); | |
f4672dff AW |
125 | } |
126 | ||
127 | static void cx18_av_initialize(struct v4l2_subdev *sd) | |
128 | { | |
129 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
130 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
a75b9be1 | 131 | int default_volume; |
1c1e45d1 HV |
132 | u32 v; |
133 | ||
134 | cx18_av_loadfw(cx); | |
135 | /* Stop 8051 code execution */ | |
ced07371 AW |
136 | cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000, |
137 | 0x03000000, 0x13000000); | |
1c1e45d1 HV |
138 | |
139 | /* initallize the PLL by toggling sleep bit */ | |
140 | v = cx18_av_read4(cx, CXADEC_HOST_REG1); | |
ced07371 AW |
141 | /* enable sleep mode - register appears to be read only... */ |
142 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe); | |
1c1e45d1 | 143 | /* disable sleep mode */ |
ced07371 AW |
144 | cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe, |
145 | v & 0xfffe, 0xffff); | |
1c1e45d1 HV |
146 | |
147 | /* initialize DLLs */ | |
148 | v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF; | |
149 | /* disable FLD */ | |
150 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v); | |
151 | /* enable FLD */ | |
152 | cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100); | |
153 | ||
154 | v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF; | |
155 | /* disable FLD */ | |
156 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v); | |
157 | /* enable FLD */ | |
158 | cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100); | |
159 | ||
160 | /* set analog bias currents. Set Vreg to 1.20V. */ | |
161 | cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802); | |
162 | ||
163 | v = cx18_av_read4(cx, CXADEC_AFE_DIAG_CTRL3) | 1; | |
164 | /* enable TUNE_FIL_RST */ | |
ced07371 | 165 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F); |
1c1e45d1 | 166 | /* disable TUNE_FIL_RST */ |
ced07371 AW |
167 | cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, |
168 | v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F); | |
1c1e45d1 HV |
169 | |
170 | /* enable 656 output */ | |
171 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00); | |
172 | ||
173 | /* video output drive strength */ | |
174 | cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2); | |
175 | ||
176 | /* reset video */ | |
177 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000); | |
178 | cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0); | |
179 | ||
f4672dff AW |
180 | /* |
181 | * Disable Video Auto-config of the Analog Front End and Video PLL. | |
182 | * | |
183 | * Since we only use BT.656 pixel mode, which works for both 525 and 625 | |
184 | * line systems, it's just easier for us to set registers | |
185 | * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL), | |
186 | * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC) | |
187 | * ourselves, than to run around cleaning up after the auto-config. | |
188 | * | |
189 | * (Note: my CX23418 chip doesn't seem to let the ACFG_DIS bit | |
190 | * get set to 1, but OTOH, it doesn't seem to do AFE and VID PLL | |
191 | * autoconfig either.) | |
192 | * | |
193 | * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3. | |
194 | */ | |
195 | cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000); | |
196 | ||
197 | /* Setup the Video and and Aux/Audio PLLs */ | |
7f3ea4de | 198 | cx18_av_init(cx); |
f4672dff | 199 | |
1c1e45d1 HV |
200 | /* set video to auto-detect */ |
201 | /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */ | |
202 | /* set the comb notch = 1 */ | |
203 | cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800); | |
204 | ||
205 | /* Enable wtw_en in CRUSH_CTRL (Set bit 22) */ | |
206 | /* Enable maj_sel in CRUSH_CTRL (Set bit 20) */ | |
207 | cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000); | |
208 | ||
209 | /* Set VGA_TRACK_RANGE to 0x20 */ | |
210 | cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000); | |
211 | ||
302df970 AW |
212 | /* |
213 | * Initial VBI setup | |
214 | * VIP-1.1, 10 bit mode, enable Raw, disable sliced, | |
812b1f9d AW |
215 | * don't clamp raw samples when codes are in use, 1 byte user D-words, |
216 | * IDID0 has line #, RP code V bit transition on VBLANK, data during | |
302df970 AW |
217 | * blanking intervals |
218 | */ | |
812b1f9d | 219 | cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e); |
1c1e45d1 HV |
220 | |
221 | /* Set the video input. | |
222 | The setting in MODE_CTRL gets lost when we do the above setup */ | |
223 | /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */ | |
224 | /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */ | |
225 | ||
f4672dff AW |
226 | /* |
227 | * Analog Front End (AFE) | |
228 | * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2 | |
229 | * bypass_ch[1-3] use filter | |
230 | * droop_comp_ch[1-3] disable | |
231 | * clamp_en_ch[1-3] disable | |
232 | * aud_in_sel ADC2 | |
233 | * luma_in_sel ADC1 | |
234 | * chroma_in_sel ADC2 | |
235 | * clamp_sel_ch[2-3] midcode | |
236 | * clamp_sel_ch1 video decoder | |
237 | * vga_sel_ch3 audio decoder | |
238 | * vga_sel_ch[1-2] video decoder | |
239 | * half_bw_ch[1-3] disable | |
240 | * +12db_ch[1-3] disable | |
241 | */ | |
242 | cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00); | |
1c1e45d1 HV |
243 | |
244 | /* if(dwEnable && dw3DCombAvailable) { */ | |
245 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */ | |
246 | /* } else { */ | |
247 | /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */ | |
248 | /* } */ | |
249 | cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F); | |
a75b9be1 HV |
250 | default_volume = cx18_av_read(cx, 0x8d4); |
251 | /* | |
252 | * Enforce the legacy volume scale mapping limits to avoid | |
253 | * -ERANGE errors when initializing the volume control | |
254 | */ | |
255 | if (default_volume > 228) { | |
256 | /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */ | |
257 | default_volume = 228; | |
258 | cx18_av_write(cx, 0x8d4, 228); | |
259 | } else if (default_volume < 20) { | |
260 | /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */ | |
261 | default_volume = 20; | |
262 | cx18_av_write(cx, 0x8d4, 20); | |
263 | } | |
264 | default_volume = (((228 - default_volume) >> 1) + 23) << 9; | |
265 | state->volume->cur.val = state->volume->default_value = default_volume; | |
266 | v4l2_ctrl_handler_setup(&state->hdl); | |
1c1e45d1 HV |
267 | } |
268 | ||
1a267046 AW |
269 | static int cx18_av_reset(struct v4l2_subdev *sd, u32 val) |
270 | { | |
f4672dff | 271 | cx18_av_initialize(sd); |
cc26b076 HV |
272 | return 0; |
273 | } | |
fa3e7036 | 274 | |
cc26b076 HV |
275 | static int cx18_av_load_fw(struct v4l2_subdev *sd) |
276 | { | |
277 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
cc26b076 HV |
278 | |
279 | if (!state->is_initialized) { | |
280 | /* initialize on first use */ | |
281 | state->is_initialized = 1; | |
f4672dff | 282 | cx18_av_initialize(sd); |
1a267046 AW |
283 | } |
284 | return 0; | |
285 | } | |
1c1e45d1 | 286 | |
03b52c36 HV |
287 | void cx18_av_std_setup(struct cx18 *cx) |
288 | { | |
289 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 290 | struct v4l2_subdev *sd = &state->sd; |
03b52c36 | 291 | v4l2_std_id std = state->std; |
86bc85b3 AW |
292 | |
293 | /* | |
294 | * Video ADC crystal clock to pixel clock SRC decimation ratio | |
295 | * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b | |
296 | */ | |
297 | const int src_decimation = 0x21f; | |
298 | ||
03b52c36 | 299 | int hblank, hactive, burst, vblank, vactive, sc; |
86bc85b3 | 300 | int vblank656; |
03b52c36 HV |
301 | int luma_lpf, uv_lpf, comb; |
302 | u32 pll_int, pll_frac, pll_post; | |
303 | ||
304 | /* datasheet startup, step 8d */ | |
305 | if (std & ~V4L2_STD_NTSC) | |
306 | cx18_av_write(cx, 0x49f, 0x11); | |
307 | else | |
308 | cx18_av_write(cx, 0x49f, 0x14); | |
309 | ||
5ab74052 AW |
310 | /* |
311 | * Note: At the end of a field, there are 3 sets of half line duration | |
312 | * (double horizontal rate) pulses: | |
313 | * | |
314 | * 5 (625) or 6 (525) half-lines to blank for the vertical retrace | |
315 | * 5 (625) or 6 (525) vertical sync pulses of half line duration | |
316 | * 5 (625) or 6 (525) half-lines of equalization pulses | |
317 | */ | |
03b52c36 | 318 | if (std & V4L2_STD_625_50) { |
5ab74052 AW |
319 | /* |
320 | * The following relationships of half line counts should hold: | |
929a3ad1 | 321 | * 625 = vblank656 + vactive |
5ab74052 AW |
322 | * 10 = vblank656 - vblank = vsync pulses + equalization pulses |
323 | * | |
324 | * vblank656: half lines after line 625/mid-313 of blanked video | |
325 | * vblank: half lines, after line 5/317, of blanked video | |
929a3ad1 AW |
326 | * vactive: half lines of active video + |
327 | * 5 half lines after the end of active video | |
5ab74052 AW |
328 | * |
329 | * As far as I can tell: | |
330 | * vblank656 starts counting from the falling edge of the first | |
331 | * vsync pulse (start of line 1 or mid-313) | |
332 | * vblank starts counting from the after the 5 vsync pulses and | |
333 | * 5 or 4 equalization pulses (start of line 6 or 318) | |
334 | * | |
335 | * For 625 line systems the driver will extract VBI information | |
336 | * from lines 6-23 and lines 318-335 (but the slicer can only | |
337 | * handle 17 lines, not the 18 in the vblank region). | |
929a3ad1 AW |
338 | * In addition, we need vblank656 and vblank to be one whole |
339 | * line longer, to cover line 24 and 336, so the SAV/EAV RP | |
340 | * codes get generated such that the encoder can actually | |
341 | * extract line 23 & 335 (WSS). We'll lose 1 line in each field | |
342 | * at the top of the screen. | |
343 | * | |
344 | * It appears the 5 half lines that happen after active | |
345 | * video must be included in vactive (579 instead of 574), | |
346 | * otherwise the colors get badly displayed in various regions | |
347 | * of the screen. I guess the chroma comb filter gets confused | |
348 | * without them (at least when a PVR-350 is the PAL source). | |
5ab74052 | 349 | */ |
929a3ad1 AW |
350 | vblank656 = 48; /* lines 1 - 24 & 313 - 336 */ |
351 | vblank = 38; /* lines 6 - 24 & 318 - 336 */ | |
352 | vactive = 579; /* lines 24 - 313 & 337 - 626 */ | |
5ab74052 AW |
353 | |
354 | /* | |
355 | * For a 13.5 Mpps clock and 15,625 Hz line rate, a line is | |
356 | * is 864 pixels = 720 active + 144 blanking. ITU-R BT.601 | |
357 | * specifies 12 luma clock periods or ~ 0.9 * 13.5 Mpps after | |
358 | * the end of active video to start a horizontal line, so that | |
359 | * leaves 132 pixels of hblank to ignore. | |
360 | */ | |
03b52c36 HV |
361 | hblank = 132; |
362 | hactive = 720; | |
03b52c36 | 363 | |
86bc85b3 AW |
364 | /* |
365 | * Burst gate delay (for 625 line systems) | |
366 | * Hsync leading edge to color burst rise = 5.6 us | |
367 | * Color burst width = 2.25 us | |
368 | * Gate width = 4 pixel clocks | |
369 | * (5.6 us + 2.25/2 us) * 13.5 Mpps + 4/2 clocks = 92.79 clocks | |
370 | */ | |
5ab74052 | 371 | burst = 93; |
03b52c36 HV |
372 | luma_lpf = 2; |
373 | if (std & V4L2_STD_PAL) { | |
374 | uv_lpf = 1; | |
375 | comb = 0x20; | |
86bc85b3 AW |
376 | /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */ |
377 | sc = 688700; | |
03b52c36 HV |
378 | } else if (std == V4L2_STD_PAL_Nc) { |
379 | uv_lpf = 1; | |
380 | comb = 0x20; | |
86bc85b3 AW |
381 | /* sc = 3582056.25 * src_decimation/28636360 * 2^13 */ |
382 | sc = 556422; | |
03b52c36 HV |
383 | } else { /* SECAM */ |
384 | uv_lpf = 0; | |
385 | comb = 0; | |
86bc85b3 AW |
386 | /* (fr + fb)/2 = (4406260 + 4250000)/2 = 4328130 */ |
387 | /* sc = 4328130 * src_decimation/28636360 * 2^13 */ | |
388 | sc = 672314; | |
03b52c36 HV |
389 | } |
390 | } else { | |
812b1f9d AW |
391 | /* |
392 | * The following relationships of half line counts should hold: | |
5ab74052 AW |
393 | * 525 = prevsync + vblank656 + vactive |
394 | * 12 = vblank656 - vblank = vsync pulses + equalization pulses | |
812b1f9d | 395 | * |
5ab74052 | 396 | * prevsync: 6 half-lines before the vsync pulses |
af7c58b1 AW |
397 | * vblank656: half lines, after line 3/mid-266, of blanked video |
398 | * vblank: half lines, after line 9/272, of blanked video | |
5ab74052 | 399 | * vactive: half lines of active video |
812b1f9d | 400 | * |
af7c58b1 | 401 | * As far as I can tell: |
812b1f9d | 402 | * vblank656 starts counting from the falling edge of the first |
af7c58b1 | 403 | * vsync pulse (start of line 4 or mid-266) |
812b1f9d | 404 | * vblank starts counting from the after the 6 vsync pulses and |
af7c58b1 | 405 | * 6 or 5 equalization pulses (start of line 10 or 272) |
812b1f9d AW |
406 | * |
407 | * For 525 line systems the driver will extract VBI information | |
af7c58b1 | 408 | * from lines 10-21 and lines 273-284. |
812b1f9d | 409 | */ |
af7c58b1 AW |
410 | vblank656 = 38; /* lines 4 - 22 & 266 - 284 */ |
411 | vblank = 26; /* lines 10 - 22 & 272 - 284 */ | |
412 | vactive = 481; /* lines 23 - 263 & 285 - 525 */ | |
812b1f9d | 413 | |
af7c58b1 AW |
414 | /* |
415 | * For a 13.5 Mpps clock and 15,734.26 Hz line rate, a line is | |
416 | * is 858 pixels = 720 active + 138 blanking. The Hsync leading | |
417 | * edge should happen 1.2 us * 13.5 Mpps ~= 16 pixels after the | |
418 | * end of active video, leaving 122 pixels of hblank to ignore | |
419 | * before active video starts. | |
420 | */ | |
03b52c36 HV |
421 | hactive = 720; |
422 | hblank = 122; | |
03b52c36 HV |
423 | luma_lpf = 1; |
424 | uv_lpf = 1; | |
03b52c36 | 425 | |
86bc85b3 AW |
426 | /* |
427 | * Burst gate delay (for 525 line systems) | |
428 | * Hsync leading edge to color burst rise = 5.3 us | |
429 | * Color burst width = 2.5 us | |
430 | * Gate width = 4 pixel clocks | |
431 | * (5.3 us + 2.5/2 us) * 13.5 Mpps + 4/2 clocks = 90.425 clocks | |
432 | */ | |
03b52c36 | 433 | if (std == V4L2_STD_PAL_60) { |
86bc85b3 | 434 | burst = 90; |
03b52c36 HV |
435 | luma_lpf = 2; |
436 | comb = 0x20; | |
86bc85b3 AW |
437 | /* sc = 4433618.75 * src_decimation/28636360 * 2^13 */ |
438 | sc = 688700; | |
03b52c36 | 439 | } else if (std == V4L2_STD_PAL_M) { |
86bc85b3 AW |
440 | /* The 97 needs to be verified against PAL-M timings */ |
441 | burst = 97; | |
03b52c36 | 442 | comb = 0x20; |
86bc85b3 AW |
443 | /* sc = 3575611.49 * src_decimation/28636360 * 2^13 */ |
444 | sc = 555421; | |
03b52c36 | 445 | } else { |
86bc85b3 | 446 | burst = 90; |
03b52c36 | 447 | comb = 0x66; |
86bc85b3 AW |
448 | /* sc = 3579545.45.. * src_decimation/28636360 * 2^13 */ |
449 | sc = 556032; | |
03b52c36 HV |
450 | } |
451 | } | |
452 | ||
453 | /* DEBUG: Displays configured PLL frequency */ | |
454 | pll_int = cx18_av_read(cx, 0x108); | |
455 | pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff; | |
456 | pll_post = cx18_av_read(cx, 0x109); | |
6246d4e1 AW |
457 | CX18_DEBUG_INFO_DEV(sd, "PLL regs = int: %u, frac: %u, post: %u\n", |
458 | pll_int, pll_frac, pll_post); | |
03b52c36 HV |
459 | |
460 | if (pll_post) { | |
86bc85b3 | 461 | int fsc, pll; |
9ad4c655 | 462 | u64 tmp; |
03b52c36 | 463 | |
55d81aa5 | 464 | pll = (28636360L * ((((u64)pll_int) << 25) + pll_frac)) >> 25; |
03b52c36 | 465 | pll /= pll_post; |
86bc85b3 | 466 | CX18_DEBUG_INFO_DEV(sd, "Video PLL = %d.%06d MHz\n", |
6246d4e1 | 467 | pll / 1000000, pll % 1000000); |
86bc85b3 | 468 | CX18_DEBUG_INFO_DEV(sd, "Pixel rate = %d.%06d Mpixel/sec\n", |
6246d4e1 | 469 | pll / 8000000, (pll / 8) % 1000000); |
03b52c36 | 470 | |
86bc85b3 AW |
471 | CX18_DEBUG_INFO_DEV(sd, "ADC XTAL/pixel clock decimation ratio " |
472 | "= %d.%03d\n", src_decimation / 256, | |
473 | ((src_decimation % 256) * 1000) / 256); | |
03b52c36 | 474 | |
9ad4c655 AW |
475 | tmp = 28636360 * (u64) sc; |
476 | do_div(tmp, src_decimation); | |
477 | fsc = tmp >> 13; | |
6246d4e1 | 478 | CX18_DEBUG_INFO_DEV(sd, |
86bc85b3 AW |
479 | "Chroma sub-carrier initial freq = %d.%06d " |
480 | "MHz\n", fsc / 1000000, fsc % 1000000); | |
6246d4e1 AW |
481 | |
482 | CX18_DEBUG_INFO_DEV(sd, "hblank %i, hactive %i, vblank %i, " | |
483 | "vactive %i, vblank656 %i, src_dec %i, " | |
484 | "burst 0x%02x, luma_lpf %i, uv_lpf %i, " | |
485 | "comb 0x%02x, sc 0x%06x\n", | |
486 | hblank, hactive, vblank, vactive, vblank656, | |
487 | src_decimation, burst, luma_lpf, uv_lpf, | |
488 | comb, sc); | |
03b52c36 HV |
489 | } |
490 | ||
491 | /* Sets horizontal blanking delay and active lines */ | |
492 | cx18_av_write(cx, 0x470, hblank); | |
85273c38 JP |
493 | cx18_av_write(cx, 0x471, |
494 | (((hblank >> 8) & 0x3) | (hactive << 4)) & 0xff); | |
03b52c36 HV |
495 | cx18_av_write(cx, 0x472, hactive >> 4); |
496 | ||
497 | /* Sets burst gate delay */ | |
498 | cx18_av_write(cx, 0x473, burst); | |
499 | ||
500 | /* Sets vertical blanking delay and active duration */ | |
501 | cx18_av_write(cx, 0x474, vblank); | |
85273c38 JP |
502 | cx18_av_write(cx, 0x475, |
503 | (((vblank >> 8) & 0x3) | (vactive << 4)) & 0xff); | |
03b52c36 HV |
504 | cx18_av_write(cx, 0x476, vactive >> 4); |
505 | cx18_av_write(cx, 0x477, vblank656); | |
506 | ||
507 | /* Sets src decimation rate */ | |
85273c38 JP |
508 | cx18_av_write(cx, 0x478, src_decimation & 0xff); |
509 | cx18_av_write(cx, 0x479, (src_decimation >> 8) & 0xff); | |
03b52c36 HV |
510 | |
511 | /* Sets Luma and UV Low pass filters */ | |
512 | cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30)); | |
513 | ||
514 | /* Enables comb filters */ | |
515 | cx18_av_write(cx, 0x47b, comb); | |
516 | ||
517 | /* Sets SC Step*/ | |
518 | cx18_av_write(cx, 0x47c, sc); | |
85273c38 JP |
519 | cx18_av_write(cx, 0x47d, (sc >> 8) & 0xff); |
520 | cx18_av_write(cx, 0x47e, (sc >> 16) & 0xff); | |
03b52c36 | 521 | |
03b52c36 | 522 | if (std & V4L2_STD_625_50) { |
812b1f9d AW |
523 | state->slicer_line_delay = 1; |
524 | state->slicer_line_offset = (6 + state->slicer_line_delay - 2); | |
03b52c36 | 525 | } else { |
812b1f9d AW |
526 | state->slicer_line_delay = 0; |
527 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
03b52c36 | 528 | } |
812b1f9d | 529 | cx18_av_write(cx, 0x47f, state->slicer_line_delay); |
03b52c36 HV |
530 | } |
531 | ||
1c1e45d1 HV |
532 | static void input_change(struct cx18 *cx) |
533 | { | |
534 | struct cx18_av_state *state = &cx->av_state; | |
535 | v4l2_std_id std = state->std; | |
ced07371 | 536 | u8 v; |
1c1e45d1 HV |
537 | |
538 | /* Follow step 8c and 8d of section 3.16 in the cx18_av datasheet */ | |
c1738904 HV |
539 | cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11); |
540 | cx18_av_and_or(cx, 0x401, ~0x60, 0); | |
541 | cx18_av_and_or(cx, 0x401, ~0x60, 0x60); | |
1c1e45d1 HV |
542 | |
543 | if (std & V4L2_STD_525_60) { | |
544 | if (std == V4L2_STD_NTSC_M_JP) { | |
545 | /* Japan uses EIAJ audio standard */ | |
ced07371 AW |
546 | cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff); |
547 | cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f); | |
1c1e45d1 HV |
548 | } else if (std == V4L2_STD_NTSC_M_KR) { |
549 | /* South Korea uses A2 audio standard */ | |
ced07371 AW |
550 | cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff); |
551 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
552 | } else { |
553 | /* Others use the BTSC audio standard */ | |
ced07371 AW |
554 | cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff); |
555 | cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f); | |
1c1e45d1 | 556 | } |
1c1e45d1 HV |
557 | } else if (std & V4L2_STD_PAL) { |
558 | /* Follow tuner change procedure for PAL */ | |
ced07371 AW |
559 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
560 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
561 | } else if (std & V4L2_STD_SECAM) { |
562 | /* Select autodetect for SECAM */ | |
ced07371 AW |
563 | cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); |
564 | cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); | |
1c1e45d1 HV |
565 | } |
566 | ||
ced07371 AW |
567 | v = cx18_av_read(cx, 0x803); |
568 | if (v & 0x10) { | |
1c1e45d1 | 569 | /* restart audio decoder microcontroller */ |
ced07371 AW |
570 | v &= ~0x10; |
571 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
572 | v |= 0x10; | |
573 | cx18_av_write_expect(cx, 0x803, v, v, 0x1f); | |
1c1e45d1 HV |
574 | } |
575 | } | |
576 | ||
1a267046 | 577 | static int cx18_av_s_frequency(struct v4l2_subdev *sd, |
b530a447 | 578 | const struct v4l2_frequency *freq) |
1a267046 AW |
579 | { |
580 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
581 | input_change(cx); | |
582 | return 0; | |
583 | } | |
584 | ||
1c1e45d1 HV |
585 | static int set_input(struct cx18 *cx, enum cx18_av_video_input vid_input, |
586 | enum cx18_av_audio_input aud_input) | |
587 | { | |
588 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 589 | struct v4l2_subdev *sd = &state->sd; |
f4672dff AW |
590 | |
591 | enum analog_signal_type { | |
592 | NONE, CVBS, Y, C, SIF, Pb, Pr | |
593 | } ch[3] = {NONE, NONE, NONE}; | |
594 | ||
595 | u8 afe_mux_cfg; | |
596 | u8 adc2_cfg; | |
d9a325a8 | 597 | u8 input_mode; |
f4672dff AW |
598 | u32 afe_cfg; |
599 | int i; | |
1c1e45d1 | 600 | |
6246d4e1 AW |
601 | CX18_DEBUG_INFO_DEV(sd, "decoder set video input %d, audio input %d\n", |
602 | vid_input, aud_input); | |
1c1e45d1 | 603 | |
f4672dff AW |
604 | if (vid_input >= CX18_AV_COMPOSITE1 && |
605 | vid_input <= CX18_AV_COMPOSITE8) { | |
606 | afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1); | |
607 | ch[0] = CVBS; | |
d9a325a8 AW |
608 | input_mode = 0x0; |
609 | } else if (vid_input >= CX18_AV_COMPONENT_LUMA1) { | |
610 | int luma = vid_input & 0xf000; | |
611 | int r_chroma = vid_input & 0xf0000; | |
612 | int b_chroma = vid_input & 0xf00000; | |
613 | ||
614 | if ((vid_input & ~0xfff000) || | |
615 | luma < CX18_AV_COMPONENT_LUMA1 || | |
616 | luma > CX18_AV_COMPONENT_LUMA8 || | |
617 | r_chroma < CX18_AV_COMPONENT_R_CHROMA4 || | |
618 | r_chroma > CX18_AV_COMPONENT_R_CHROMA6 || | |
619 | b_chroma < CX18_AV_COMPONENT_B_CHROMA7 || | |
620 | b_chroma > CX18_AV_COMPONENT_B_CHROMA8) { | |
621 | CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n", | |
622 | vid_input); | |
623 | return -EINVAL; | |
624 | } | |
625 | afe_mux_cfg = (luma - CX18_AV_COMPONENT_LUMA1) >> 12; | |
626 | ch[0] = Y; | |
627 | afe_mux_cfg |= (r_chroma - CX18_AV_COMPONENT_R_CHROMA4) >> 12; | |
628 | ch[1] = Pr; | |
629 | afe_mux_cfg |= (b_chroma - CX18_AV_COMPONENT_B_CHROMA7) >> 14; | |
630 | ch[2] = Pb; | |
631 | input_mode = 0x6; | |
1c1e45d1 HV |
632 | } else { |
633 | int luma = vid_input & 0xf0; | |
634 | int chroma = vid_input & 0xf00; | |
635 | ||
636 | if ((vid_input & ~0xff0) || | |
637 | luma < CX18_AV_SVIDEO_LUMA1 || | |
45270a15 | 638 | luma > CX18_AV_SVIDEO_LUMA8 || |
1c1e45d1 HV |
639 | chroma < CX18_AV_SVIDEO_CHROMA4 || |
640 | chroma > CX18_AV_SVIDEO_CHROMA8) { | |
d9a325a8 | 641 | CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n", |
6246d4e1 | 642 | vid_input); |
1c1e45d1 HV |
643 | return -EINVAL; |
644 | } | |
f4672dff AW |
645 | afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4); |
646 | ch[0] = Y; | |
1c1e45d1 | 647 | if (chroma >= CX18_AV_SVIDEO_CHROMA7) { |
f4672dff AW |
648 | afe_mux_cfg &= 0x3f; |
649 | afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2; | |
650 | ch[2] = C; | |
1c1e45d1 | 651 | } else { |
f4672dff AW |
652 | afe_mux_cfg &= 0xcf; |
653 | afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4; | |
654 | ch[1] = C; | |
1c1e45d1 | 655 | } |
d9a325a8 | 656 | input_mode = 0x2; |
1c1e45d1 HV |
657 | } |
658 | ||
659 | switch (aud_input) { | |
81cb727d HV |
660 | case CX18_AV_AUDIO_SERIAL1: |
661 | case CX18_AV_AUDIO_SERIAL2: | |
1c1e45d1 HV |
662 | /* do nothing, use serial audio input */ |
663 | break; | |
f4672dff AW |
664 | case CX18_AV_AUDIO4: |
665 | afe_mux_cfg &= ~0x30; | |
666 | ch[1] = SIF; | |
667 | break; | |
668 | case CX18_AV_AUDIO5: | |
669 | afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10; | |
670 | ch[1] = SIF; | |
671 | break; | |
672 | case CX18_AV_AUDIO6: | |
673 | afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20; | |
674 | ch[1] = SIF; | |
675 | break; | |
676 | case CX18_AV_AUDIO7: | |
677 | afe_mux_cfg &= ~0xc0; | |
678 | ch[2] = SIF; | |
679 | break; | |
680 | case CX18_AV_AUDIO8: | |
681 | afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40; | |
682 | ch[2] = SIF; | |
683 | break; | |
1c1e45d1 HV |
684 | |
685 | default: | |
6246d4e1 AW |
686 | CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n", |
687 | aud_input); | |
1c1e45d1 HV |
688 | return -EINVAL; |
689 | } | |
690 | ||
f4672dff AW |
691 | /* Set up analog front end multiplexers */ |
692 | cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7); | |
d9a325a8 AW |
693 | /* Set INPUT_MODE to Composite, S-Video, or Component */ |
694 | cx18_av_and_or(cx, 0x401, ~0x6, input_mode); | |
ced07371 | 695 | |
1c1e45d1 | 696 | /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */ |
f4672dff AW |
697 | adc2_cfg = cx18_av_read(cx, 0x102); |
698 | if (ch[2] == NONE) | |
699 | adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */ | |
ced07371 | 700 | else |
f4672dff AW |
701 | adc2_cfg |= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */ |
702 | ||
1c1e45d1 | 703 | /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */ |
f4672dff AW |
704 | if (ch[1] != NONE && ch[2] != NONE) |
705 | adc2_cfg |= 0x4; /* Set dual mode */ | |
1c1e45d1 | 706 | else |
f4672dff AW |
707 | adc2_cfg &= ~0x4; /* Clear dual mode */ |
708 | cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17); | |
709 | ||
710 | /* Configure the analog front end */ | |
711 | afe_cfg = cx18_av_read4(cx, CXADEC_AFE_CTRL); | |
712 | afe_cfg &= 0xff000000; | |
713 | afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */ | |
714 | if (ch[1] != NONE && ch[2] != NONE) | |
715 | afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */ | |
716 | ||
717 | for (i = 0; i < 3; i++) { | |
718 | switch (ch[i]) { | |
719 | default: | |
720 | case NONE: | |
721 | /* CLAMP_SEL = Fixed to midcode clamp level */ | |
722 | afe_cfg |= (0x00000200 << i); | |
723 | break; | |
724 | case CVBS: | |
725 | case Y: | |
726 | if (i > 0) | |
727 | afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */ | |
728 | break; | |
729 | case C: | |
730 | case Pb: | |
731 | case Pr: | |
732 | /* CLAMP_SEL = Fixed to midcode clamp level */ | |
733 | afe_cfg |= (0x00000200 << i); | |
734 | if (i == 0 && ch[i] == C) | |
735 | afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */ | |
736 | break; | |
737 | case SIF: | |
738 | /* | |
739 | * VGA_GAIN_SEL = Audio Decoder | |
740 | * CLAMP_SEL = Fixed to midcode clamp level | |
741 | */ | |
742 | afe_cfg |= (0x00000240 << i); | |
743 | if (i == 0) | |
744 | afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */ | |
745 | break; | |
746 | } | |
747 | } | |
ced07371 | 748 | |
f4672dff | 749 | cx18_av_write4(cx, CXADEC_AFE_CTRL, afe_cfg); |
1c1e45d1 HV |
750 | |
751 | state->vid_input = vid_input; | |
752 | state->aud_input = aud_input; | |
753 | cx18_av_audio_set_path(cx); | |
754 | input_change(cx); | |
755 | return 0; | |
756 | } | |
757 | ||
1a267046 | 758 | static int cx18_av_s_video_routing(struct v4l2_subdev *sd, |
5325b427 | 759 | u32 input, u32 output, u32 config) |
1a267046 AW |
760 | { |
761 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
762 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
5325b427 | 763 | return set_input(cx, input, state->aud_input); |
1a267046 | 764 | } |
1c1e45d1 | 765 | |
1a267046 | 766 | static int cx18_av_s_audio_routing(struct v4l2_subdev *sd, |
5325b427 | 767 | u32 input, u32 output, u32 config) |
1c1e45d1 | 768 | { |
1a267046 AW |
769 | struct cx18_av_state *state = to_cx18_av_state(sd); |
770 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
5325b427 | 771 | return set_input(cx, state->vid_input, input); |
1a267046 AW |
772 | } |
773 | ||
774 | static int cx18_av_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt) | |
775 | { | |
776 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
777 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
778 | u8 vpres; | |
779 | u8 mode; | |
780 | int val = 0; | |
781 | ||
782 | if (state->radio) | |
783 | return 0; | |
784 | ||
785 | vpres = cx18_av_read(cx, 0x40e) & 0x20; | |
786 | vt->signal = vpres ? 0xffff : 0x0; | |
787 | ||
788 | vt->capability |= | |
789 | V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 | | |
790 | V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP; | |
791 | ||
792 | mode = cx18_av_read(cx, 0x804); | |
793 | ||
794 | /* get rxsubchans and audmode */ | |
795 | if ((mode & 0xf) == 1) | |
796 | val |= V4L2_TUNER_SUB_STEREO; | |
797 | else | |
798 | val |= V4L2_TUNER_SUB_MONO; | |
799 | ||
800 | if (mode == 2 || mode == 4) | |
801 | val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; | |
802 | ||
803 | if (mode & 0x10) | |
804 | val |= V4L2_TUNER_SUB_SAP; | |
805 | ||
806 | vt->rxsubchans = val; | |
807 | vt->audmode = state->audmode; | |
808 | return 0; | |
809 | } | |
810 | ||
2f73c7c5 | 811 | static int cx18_av_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt) |
1a267046 AW |
812 | { |
813 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
814 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
815 | u8 v; | |
816 | ||
817 | if (state->radio) | |
818 | return 0; | |
819 | ||
820 | v = cx18_av_read(cx, 0x809); | |
821 | v &= ~0xf; | |
822 | ||
823 | switch (vt->audmode) { | |
824 | case V4L2_TUNER_MODE_MONO: | |
825 | /* mono -> mono | |
826 | stereo -> mono | |
827 | bilingual -> lang1 */ | |
828 | break; | |
829 | case V4L2_TUNER_MODE_STEREO: | |
830 | case V4L2_TUNER_MODE_LANG1: | |
831 | /* mono -> mono | |
832 | stereo -> stereo | |
833 | bilingual -> lang1 */ | |
834 | v |= 0x4; | |
835 | break; | |
836 | case V4L2_TUNER_MODE_LANG1_LANG2: | |
837 | /* mono -> mono | |
838 | stereo -> stereo | |
839 | bilingual -> lang1/lang2 */ | |
840 | v |= 0x7; | |
841 | break; | |
842 | case V4L2_TUNER_MODE_LANG2: | |
843 | /* mono -> mono | |
844 | stereo -> stereo | |
845 | bilingual -> lang2 */ | |
846 | v |= 0x1; | |
847 | break; | |
848 | default: | |
849 | return -EINVAL; | |
850 | } | |
851 | cx18_av_write_expect(cx, 0x809, v, v, 0xff); | |
852 | state->audmode = vt->audmode; | |
853 | return 0; | |
854 | } | |
855 | ||
856 | static int cx18_av_s_std(struct v4l2_subdev *sd, v4l2_std_id norm) | |
857 | { | |
858 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
859 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
860 | ||
1c1e45d1 HV |
861 | u8 fmt = 0; /* zero is autodetect */ |
862 | u8 pal_m = 0; | |
863 | ||
1a267046 AW |
864 | if (state->radio == 0 && state->std == norm) |
865 | return 0; | |
866 | ||
867 | state->radio = 0; | |
868 | state->std = norm; | |
869 | ||
1c1e45d1 HV |
870 | /* First tests should be against specific std */ |
871 | if (state->std == V4L2_STD_NTSC_M_JP) { | |
872 | fmt = 0x2; | |
873 | } else if (state->std == V4L2_STD_NTSC_443) { | |
874 | fmt = 0x3; | |
875 | } else if (state->std == V4L2_STD_PAL_M) { | |
876 | pal_m = 1; | |
877 | fmt = 0x5; | |
878 | } else if (state->std == V4L2_STD_PAL_N) { | |
879 | fmt = 0x6; | |
880 | } else if (state->std == V4L2_STD_PAL_Nc) { | |
881 | fmt = 0x7; | |
882 | } else if (state->std == V4L2_STD_PAL_60) { | |
883 | fmt = 0x8; | |
884 | } else { | |
885 | /* Then, test against generic ones */ | |
886 | if (state->std & V4L2_STD_NTSC) | |
887 | fmt = 0x1; | |
888 | else if (state->std & V4L2_STD_PAL) | |
889 | fmt = 0x4; | |
890 | else if (state->std & V4L2_STD_SECAM) | |
891 | fmt = 0xc; | |
892 | } | |
893 | ||
6246d4e1 | 894 | CX18_DEBUG_INFO_DEV(sd, "changing video std to fmt %i\n", fmt); |
1c1e45d1 HV |
895 | |
896 | /* Follow step 9 of section 3.16 in the cx18_av datasheet. | |
897 | Without this PAL may display a vertical ghosting effect. | |
898 | This happens for example with the Yuan MPC622. */ | |
899 | if (fmt >= 4 && fmt < 8) { | |
900 | /* Set format to NTSC-M */ | |
c1738904 | 901 | cx18_av_and_or(cx, 0x400, ~0xf, 1); |
1c1e45d1 HV |
902 | /* Turn off LCOMB */ |
903 | cx18_av_and_or(cx, 0x47b, ~6, 0); | |
904 | } | |
c1738904 HV |
905 | cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20); |
906 | cx18_av_and_or(cx, 0x403, ~0x3, pal_m); | |
03b52c36 | 907 | cx18_av_std_setup(cx); |
1c1e45d1 HV |
908 | input_change(cx); |
909 | return 0; | |
910 | } | |
911 | ||
1a267046 AW |
912 | static int cx18_av_s_radio(struct v4l2_subdev *sd) |
913 | { | |
914 | struct cx18_av_state *state = to_cx18_av_state(sd); | |
915 | state->radio = 1; | |
916 | return 0; | |
917 | } | |
1c1e45d1 | 918 | |
a75b9be1 | 919 | static int cx18_av_s_ctrl(struct v4l2_ctrl *ctrl) |
1c1e45d1 | 920 | { |
a75b9be1 | 921 | struct v4l2_subdev *sd = to_sd(ctrl); |
1a267046 AW |
922 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
923 | ||
1c1e45d1 HV |
924 | switch (ctrl->id) { |
925 | case V4L2_CID_BRIGHTNESS: | |
a75b9be1 | 926 | cx18_av_write(cx, 0x414, ctrl->val - 128); |
1c1e45d1 HV |
927 | break; |
928 | ||
929 | case V4L2_CID_CONTRAST: | |
a75b9be1 | 930 | cx18_av_write(cx, 0x415, ctrl->val << 1); |
1c1e45d1 HV |
931 | break; |
932 | ||
933 | case V4L2_CID_SATURATION: | |
a75b9be1 HV |
934 | cx18_av_write(cx, 0x420, ctrl->val << 1); |
935 | cx18_av_write(cx, 0x421, ctrl->val << 1); | |
1c1e45d1 HV |
936 | break; |
937 | ||
938 | case V4L2_CID_HUE: | |
a75b9be1 | 939 | cx18_av_write(cx, 0x422, ctrl->val); |
1c1e45d1 HV |
940 | break; |
941 | ||
1c1e45d1 HV |
942 | default: |
943 | return -EINVAL; | |
944 | } | |
1c1e45d1 HV |
945 | return 0; |
946 | } | |
947 | ||
6e80c473 HV |
948 | static int cx18_av_set_fmt(struct v4l2_subdev *sd, |
949 | struct v4l2_subdev_pad_config *cfg, | |
950 | struct v4l2_subdev_format *format) | |
1c1e45d1 | 951 | { |
6e80c473 | 952 | struct v4l2_mbus_framefmt *fmt = &format->format; |
1a267046 AW |
953 | struct cx18_av_state *state = to_cx18_av_state(sd); |
954 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1c1e45d1 HV |
955 | int HSC, VSC, Vsrc, Hsrc, filter, Vlines; |
956 | int is_50Hz = !(state->std & V4L2_STD_525_60); | |
957 | ||
6e80c473 | 958 | if (format->pad || fmt->code != MEDIA_BUS_FMT_FIXED) |
e17ad1de | 959 | return -EINVAL; |
1c1e45d1 | 960 | |
e17ad1de HV |
961 | fmt->field = V4L2_FIELD_INTERLACED; |
962 | fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; | |
1c1e45d1 | 963 | |
e17ad1de HV |
964 | Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4; |
965 | Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4; | |
1c1e45d1 | 966 | |
e17ad1de HV |
967 | Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4; |
968 | Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4; | |
1c1e45d1 | 969 | |
e17ad1de HV |
970 | /* |
971 | * This adjustment reflects the excess of vactive, set in | |
972 | * cx18_av_std_setup(), above standard values: | |
973 | * | |
974 | * 480 + 1 for 60 Hz systems | |
975 | * 576 + 3 for 50 Hz systems | |
976 | */ | |
977 | Vlines = fmt->height + (is_50Hz ? 3 : 1); | |
1c1e45d1 | 978 | |
e17ad1de HV |
979 | /* |
980 | * Invalid height and width scaling requests are: | |
981 | * 1. width less than 1/16 of the source width | |
982 | * 2. width greater than the source width | |
983 | * 3. height less than 1/8 of the source height | |
984 | * 4. height greater than the source height | |
985 | */ | |
986 | if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) || | |
987 | (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) { | |
988 | CX18_ERR_DEV(sd, "%dx%d is not a valid size!\n", | |
989 | fmt->width, fmt->height); | |
990 | return -ERANGE; | |
991 | } | |
1c1e45d1 | 992 | |
6e80c473 HV |
993 | if (format->which == V4L2_SUBDEV_FORMAT_TRY) |
994 | return 0; | |
995 | ||
e17ad1de HV |
996 | HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20); |
997 | VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9)); | |
998 | VSC &= 0x1fff; | |
1c1e45d1 | 999 | |
e17ad1de HV |
1000 | if (fmt->width >= 385) |
1001 | filter = 0; | |
1002 | else if (fmt->width > 192) | |
1003 | filter = 1; | |
1004 | else if (fmt->width > 96) | |
1005 | filter = 2; | |
1006 | else | |
1007 | filter = 3; | |
1008 | ||
1009 | CX18_DEBUG_INFO_DEV(sd, | |
1010 | "decoder set size %dx%d -> scale %ux%u\n", | |
1011 | fmt->width, fmt->height, HSC, VSC); | |
1012 | ||
1013 | /* HSCALE=HSC */ | |
1014 | cx18_av_write(cx, 0x418, HSC & 0xff); | |
1015 | cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff); | |
1016 | cx18_av_write(cx, 0x41a, HSC >> 16); | |
1017 | /* VSCALE=VSC */ | |
1018 | cx18_av_write(cx, 0x41c, VSC & 0xff); | |
1019 | cx18_av_write(cx, 0x41d, VSC >> 8); | |
1020 | /* VS_INTRLACE=1 VFILT=filter */ | |
1021 | cx18_av_write(cx, 0x41e, 0x8 | filter); | |
1022 | return 0; | |
1023 | } | |
1024 | ||
1a267046 | 1025 | static int cx18_av_s_stream(struct v4l2_subdev *sd, int enable) |
e474200d | 1026 | { |
1a267046 | 1027 | struct cx18 *cx = v4l2_get_subdevdata(sd); |
1c1e45d1 | 1028 | |
6246d4e1 | 1029 | CX18_DEBUG_INFO_DEV(sd, "%s output\n", enable ? "enable" : "disable"); |
1a267046 | 1030 | if (enable) { |
1c1e45d1 HV |
1031 | cx18_av_write(cx, 0x115, 0x8c); |
1032 | cx18_av_write(cx, 0x116, 0x07); | |
1a267046 | 1033 | } else { |
1c1e45d1 HV |
1034 | cx18_av_write(cx, 0x115, 0x00); |
1035 | cx18_av_write(cx, 0x116, 0x00); | |
1c1e45d1 | 1036 | } |
1c1e45d1 HV |
1037 | return 0; |
1038 | } | |
1039 | ||
1c1e45d1 HV |
1040 | static void log_video_status(struct cx18 *cx) |
1041 | { | |
1042 | static const char *const fmt_strs[] = { | |
1043 | "0x0", | |
1044 | "NTSC-M", "NTSC-J", "NTSC-4.43", | |
1045 | "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60", | |
1046 | "0x9", "0xA", "0xB", | |
1047 | "SECAM", | |
1048 | "0xD", "0xE", "0xF" | |
1049 | }; | |
1050 | ||
1051 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 1052 | struct v4l2_subdev *sd = &state->sd; |
1c1e45d1 HV |
1053 | u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf; |
1054 | u8 gen_stat1 = cx18_av_read(cx, 0x40d); | |
1055 | u8 gen_stat2 = cx18_av_read(cx, 0x40e); | |
1056 | int vid_input = state->vid_input; | |
1057 | ||
6246d4e1 AW |
1058 | CX18_INFO_DEV(sd, "Video signal: %spresent\n", |
1059 | (gen_stat2 & 0x20) ? "" : "not "); | |
1060 | CX18_INFO_DEV(sd, "Detected format: %s\n", | |
1061 | fmt_strs[gen_stat1 & 0xf]); | |
1c1e45d1 | 1062 | |
6246d4e1 AW |
1063 | CX18_INFO_DEV(sd, "Specified standard: %s\n", |
1064 | vidfmt_sel ? fmt_strs[vidfmt_sel] | |
1065 | : "automatic detection"); | |
1c1e45d1 HV |
1066 | |
1067 | if (vid_input >= CX18_AV_COMPOSITE1 && | |
1068 | vid_input <= CX18_AV_COMPOSITE8) { | |
6246d4e1 AW |
1069 | CX18_INFO_DEV(sd, "Specified video input: Composite %d\n", |
1070 | vid_input - CX18_AV_COMPOSITE1 + 1); | |
1c1e45d1 | 1071 | } else { |
6246d4e1 AW |
1072 | CX18_INFO_DEV(sd, "Specified video input: " |
1073 | "S-Video (Luma In%d, Chroma In%d)\n", | |
1074 | (vid_input & 0xf0) >> 4, | |
1075 | (vid_input & 0xf00) >> 8); | |
1c1e45d1 HV |
1076 | } |
1077 | ||
6246d4e1 AW |
1078 | CX18_INFO_DEV(sd, "Specified audioclock freq: %d Hz\n", |
1079 | state->audclk_freq); | |
1c1e45d1 HV |
1080 | } |
1081 | ||
1c1e45d1 HV |
1082 | static void log_audio_status(struct cx18 *cx) |
1083 | { | |
1084 | struct cx18_av_state *state = &cx->av_state; | |
6246d4e1 | 1085 | struct v4l2_subdev *sd = &state->sd; |
1c1e45d1 | 1086 | u8 download_ctl = cx18_av_read(cx, 0x803); |
63b8c709 HV |
1087 | u8 mod_det_stat0 = cx18_av_read(cx, 0x804); |
1088 | u8 mod_det_stat1 = cx18_av_read(cx, 0x805); | |
1c1e45d1 HV |
1089 | u8 audio_config = cx18_av_read(cx, 0x808); |
1090 | u8 pref_mode = cx18_av_read(cx, 0x809); | |
1091 | u8 afc0 = cx18_av_read(cx, 0x80b); | |
1092 | u8 mute_ctl = cx18_av_read(cx, 0x8d3); | |
1093 | int aud_input = state->aud_input; | |
1094 | char *p; | |
1095 | ||
1096 | switch (mod_det_stat0) { | |
1097 | case 0x00: p = "mono"; break; | |
1098 | case 0x01: p = "stereo"; break; | |
1099 | case 0x02: p = "dual"; break; | |
1100 | case 0x04: p = "tri"; break; | |
1101 | case 0x10: p = "mono with SAP"; break; | |
1102 | case 0x11: p = "stereo with SAP"; break; | |
1103 | case 0x12: p = "dual with SAP"; break; | |
1104 | case 0x14: p = "tri with SAP"; break; | |
1105 | case 0xfe: p = "forced mode"; break; | |
63b8c709 | 1106 | default: p = "not defined"; break; |
1c1e45d1 | 1107 | } |
6246d4e1 | 1108 | CX18_INFO_DEV(sd, "Detected audio mode: %s\n", p); |
1c1e45d1 HV |
1109 | |
1110 | switch (mod_det_stat1) { | |
63b8c709 | 1111 | case 0x00: p = "not defined"; break; |
1c1e45d1 HV |
1112 | case 0x01: p = "EIAJ"; break; |
1113 | case 0x02: p = "A2-M"; break; | |
1114 | case 0x03: p = "A2-BG"; break; | |
1115 | case 0x04: p = "A2-DK1"; break; | |
1116 | case 0x05: p = "A2-DK2"; break; | |
1117 | case 0x06: p = "A2-DK3"; break; | |
1118 | case 0x07: p = "A1 (6.0 MHz FM Mono)"; break; | |
1119 | case 0x08: p = "AM-L"; break; | |
1120 | case 0x09: p = "NICAM-BG"; break; | |
1121 | case 0x0a: p = "NICAM-DK"; break; | |
1122 | case 0x0b: p = "NICAM-I"; break; | |
1123 | case 0x0c: p = "NICAM-L"; break; | |
1124 | case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break; | |
63b8c709 HV |
1125 | case 0x0e: p = "IF FM Radio"; break; |
1126 | case 0x0f: p = "BTSC"; break; | |
1127 | case 0x10: p = "detected chrominance"; break; | |
1128 | case 0xfd: p = "unknown audio standard"; break; | |
1129 | case 0xfe: p = "forced audio standard"; break; | |
1c1e45d1 | 1130 | case 0xff: p = "no detected audio standard"; break; |
63b8c709 | 1131 | default: p = "not defined"; break; |
1c1e45d1 | 1132 | } |
6246d4e1 AW |
1133 | CX18_INFO_DEV(sd, "Detected audio standard: %s\n", p); |
1134 | CX18_INFO_DEV(sd, "Audio muted: %s\n", | |
1135 | (mute_ctl & 0x2) ? "yes" : "no"); | |
1136 | CX18_INFO_DEV(sd, "Audio microcontroller: %s\n", | |
1137 | (download_ctl & 0x10) ? "running" : "stopped"); | |
1c1e45d1 HV |
1138 | |
1139 | switch (audio_config >> 4) { | |
63b8c709 HV |
1140 | case 0x00: p = "undefined"; break; |
1141 | case 0x01: p = "BTSC"; break; | |
1142 | case 0x02: p = "EIAJ"; break; | |
1143 | case 0x03: p = "A2-M"; break; | |
1144 | case 0x04: p = "A2-BG"; break; | |
1145 | case 0x05: p = "A2-DK1"; break; | |
1146 | case 0x06: p = "A2-DK2"; break; | |
1147 | case 0x07: p = "A2-DK3"; break; | |
1148 | case 0x08: p = "A1 (6.0 MHz FM Mono)"; break; | |
1149 | case 0x09: p = "AM-L"; break; | |
1150 | case 0x0a: p = "NICAM-BG"; break; | |
1151 | case 0x0b: p = "NICAM-DK"; break; | |
1152 | case 0x0c: p = "NICAM-I"; break; | |
1153 | case 0x0d: p = "NICAM-L"; break; | |
1154 | case 0x0e: p = "FM radio"; break; | |
1c1e45d1 | 1155 | case 0x0f: p = "automatic detection"; break; |
63b8c709 | 1156 | default: p = "undefined"; break; |
1c1e45d1 | 1157 | } |
6246d4e1 | 1158 | CX18_INFO_DEV(sd, "Configured audio standard: %s\n", p); |
1c1e45d1 HV |
1159 | |
1160 | if ((audio_config >> 4) < 0xF) { | |
1161 | switch (audio_config & 0xF) { | |
1162 | case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break; | |
1163 | case 0x01: p = "MONO2 (LANGUAGE B)"; break; | |
1164 | case 0x02: p = "MONO3 (STEREO forced MONO)"; break; | |
1165 | case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break; | |
1166 | case 0x04: p = "STEREO"; break; | |
63b8c709 HV |
1167 | case 0x05: p = "DUAL1 (AC)"; break; |
1168 | case 0x06: p = "DUAL2 (BC)"; break; | |
1169 | case 0x07: p = "DUAL3 (AB)"; break; | |
1c1e45d1 HV |
1170 | default: p = "undefined"; |
1171 | } | |
6246d4e1 | 1172 | CX18_INFO_DEV(sd, "Configured audio mode: %s\n", p); |
1c1e45d1 HV |
1173 | } else { |
1174 | switch (audio_config & 0xF) { | |
1175 | case 0x00: p = "BG"; break; | |
1176 | case 0x01: p = "DK1"; break; | |
1177 | case 0x02: p = "DK2"; break; | |
1178 | case 0x03: p = "DK3"; break; | |
1179 | case 0x04: p = "I"; break; | |
1180 | case 0x05: p = "L"; break; | |
1181 | case 0x06: p = "BTSC"; break; | |
1182 | case 0x07: p = "EIAJ"; break; | |
1183 | case 0x08: p = "A2-M"; break; | |
63b8c709 HV |
1184 | case 0x09: p = "FM Radio (4.5 MHz)"; break; |
1185 | case 0x0a: p = "FM Radio (5.5 MHz)"; break; | |
1186 | case 0x0b: p = "S-Video"; break; | |
1c1e45d1 | 1187 | case 0x0f: p = "automatic standard and mode detection"; break; |
63b8c709 | 1188 | default: p = "undefined"; break; |
1c1e45d1 | 1189 | } |
6246d4e1 | 1190 | CX18_INFO_DEV(sd, "Configured audio system: %s\n", p); |
1c1e45d1 HV |
1191 | } |
1192 | ||
1193 | if (aud_input) | |
6246d4e1 AW |
1194 | CX18_INFO_DEV(sd, "Specified audio input: Tuner (In%d)\n", |
1195 | aud_input); | |
1c1e45d1 | 1196 | else |
6246d4e1 | 1197 | CX18_INFO_DEV(sd, "Specified audio input: External\n"); |
1c1e45d1 HV |
1198 | |
1199 | switch (pref_mode & 0xf) { | |
1200 | case 0: p = "mono/language A"; break; | |
1201 | case 1: p = "language B"; break; | |
1202 | case 2: p = "language C"; break; | |
1203 | case 3: p = "analog fallback"; break; | |
1204 | case 4: p = "stereo"; break; | |
1205 | case 5: p = "language AC"; break; | |
1206 | case 6: p = "language BC"; break; | |
1207 | case 7: p = "language AB"; break; | |
63b8c709 | 1208 | default: p = "undefined"; break; |
1c1e45d1 | 1209 | } |
6246d4e1 | 1210 | CX18_INFO_DEV(sd, "Preferred audio mode: %s\n", p); |
1c1e45d1 HV |
1211 | |
1212 | if ((audio_config & 0xf) == 0xf) { | |
63b8c709 | 1213 | switch ((afc0 >> 3) & 0x1) { |
1c1e45d1 HV |
1214 | case 0: p = "system DK"; break; |
1215 | case 1: p = "system L"; break; | |
1216 | } | |
6246d4e1 | 1217 | CX18_INFO_DEV(sd, "Selected 65 MHz format: %s\n", p); |
1c1e45d1 | 1218 | |
63b8c709 HV |
1219 | switch (afc0 & 0x7) { |
1220 | case 0: p = "Chroma"; break; | |
1221 | case 1: p = "BTSC"; break; | |
1222 | case 2: p = "EIAJ"; break; | |
1223 | case 3: p = "A2-M"; break; | |
1224 | case 4: p = "autodetect"; break; | |
1225 | default: p = "undefined"; break; | |
1c1e45d1 | 1226 | } |
6246d4e1 | 1227 | CX18_INFO_DEV(sd, "Selected 45 MHz format: %s\n", p); |
1c1e45d1 HV |
1228 | } |
1229 | } | |
1a267046 AW |
1230 | |
1231 | static int cx18_av_log_status(struct v4l2_subdev *sd) | |
1232 | { | |
1233 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1234 | log_video_status(cx); | |
1235 | log_audio_status(cx); | |
1236 | return 0; | |
1237 | } | |
1238 | ||
1a267046 AW |
1239 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1240 | static int cx18_av_g_register(struct v4l2_subdev *sd, | |
1241 | struct v4l2_dbg_register *reg) | |
1242 | { | |
1243 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1244 | ||
1a267046 AW |
1245 | if ((reg->reg & 0x3) != 0) |
1246 | return -EINVAL; | |
1a267046 AW |
1247 | reg->size = 4; |
1248 | reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc); | |
1249 | return 0; | |
1250 | } | |
1251 | ||
1252 | static int cx18_av_s_register(struct v4l2_subdev *sd, | |
977ba3b1 | 1253 | const struct v4l2_dbg_register *reg) |
1a267046 AW |
1254 | { |
1255 | struct cx18 *cx = v4l2_get_subdevdata(sd); | |
1256 | ||
1a267046 AW |
1257 | if ((reg->reg & 0x3) != 0) |
1258 | return -EINVAL; | |
1a267046 AW |
1259 | cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val); |
1260 | return 0; | |
1261 | } | |
1262 | #endif | |
1263 | ||
a75b9be1 HV |
1264 | static const struct v4l2_ctrl_ops cx18_av_ctrl_ops = { |
1265 | .s_ctrl = cx18_av_s_ctrl, | |
1266 | }; | |
1267 | ||
1a267046 | 1268 | static const struct v4l2_subdev_core_ops cx18_av_general_ops = { |
1a267046 | 1269 | .log_status = cx18_av_log_status, |
cc26b076 | 1270 | .load_fw = cx18_av_load_fw, |
1a267046 | 1271 | .reset = cx18_av_reset, |
1a267046 AW |
1272 | #ifdef CONFIG_VIDEO_ADV_DEBUG |
1273 | .g_register = cx18_av_g_register, | |
1274 | .s_register = cx18_av_s_register, | |
1275 | #endif | |
1276 | }; | |
1277 | ||
1278 | static const struct v4l2_subdev_tuner_ops cx18_av_tuner_ops = { | |
1279 | .s_radio = cx18_av_s_radio, | |
1280 | .s_frequency = cx18_av_s_frequency, | |
1281 | .g_tuner = cx18_av_g_tuner, | |
1282 | .s_tuner = cx18_av_s_tuner, | |
1a267046 AW |
1283 | }; |
1284 | ||
1285 | static const struct v4l2_subdev_audio_ops cx18_av_audio_ops = { | |
1286 | .s_clock_freq = cx18_av_s_clock_freq, | |
1287 | .s_routing = cx18_av_s_audio_routing, | |
1288 | }; | |
1289 | ||
1290 | static const struct v4l2_subdev_video_ops cx18_av_video_ops = { | |
8774bed9 | 1291 | .s_std = cx18_av_s_std, |
1a267046 | 1292 | .s_routing = cx18_av_s_video_routing, |
1a267046 | 1293 | .s_stream = cx18_av_s_stream, |
1a267046 AW |
1294 | }; |
1295 | ||
32cd527f HV |
1296 | static const struct v4l2_subdev_vbi_ops cx18_av_vbi_ops = { |
1297 | .decode_vbi_line = cx18_av_decode_vbi_line, | |
1585927d HV |
1298 | .g_sliced_fmt = cx18_av_g_sliced_fmt, |
1299 | .s_sliced_fmt = cx18_av_s_sliced_fmt, | |
1300 | .s_raw_fmt = cx18_av_s_raw_fmt, | |
32cd527f HV |
1301 | }; |
1302 | ||
6e80c473 HV |
1303 | static const struct v4l2_subdev_pad_ops cx18_av_pad_ops = { |
1304 | .set_fmt = cx18_av_set_fmt, | |
1305 | }; | |
1306 | ||
1a267046 AW |
1307 | static const struct v4l2_subdev_ops cx18_av_ops = { |
1308 | .core = &cx18_av_general_ops, | |
1309 | .tuner = &cx18_av_tuner_ops, | |
1310 | .audio = &cx18_av_audio_ops, | |
1311 | .video = &cx18_av_video_ops, | |
32cd527f | 1312 | .vbi = &cx18_av_vbi_ops, |
6e80c473 | 1313 | .pad = &cx18_av_pad_ops, |
1a267046 AW |
1314 | }; |
1315 | ||
ff2a2001 | 1316 | int cx18_av_probe(struct cx18 *cx) |
1a267046 | 1317 | { |
fa3e7036 | 1318 | struct cx18_av_state *state = &cx->av_state; |
ff2a2001 | 1319 | struct v4l2_subdev *sd; |
7f3ea4de | 1320 | int err; |
fa3e7036 AW |
1321 | |
1322 | state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff; | |
fa3e7036 AW |
1323 | |
1324 | state->vid_input = CX18_AV_COMPOSITE7; | |
1325 | state->aud_input = CX18_AV_AUDIO8; | |
1326 | state->audclk_freq = 48000; | |
1327 | state->audmode = V4L2_TUNER_MODE_LANG1; | |
1328 | state->slicer_line_delay = 0; | |
1329 | state->slicer_line_offset = (10 + state->slicer_line_delay - 2); | |
1330 | ||
ff2a2001 AW |
1331 | sd = &state->sd; |
1332 | v4l2_subdev_init(sd, &cx18_av_ops); | |
1333 | v4l2_set_subdevdata(sd, cx); | |
1334 | snprintf(sd->name, sizeof(sd->name), | |
6246d4e1 | 1335 | "%s %03x", cx->v4l2_dev.name, (state->rev >> 4)); |
ff2a2001 | 1336 | sd->grp_id = CX18_HW_418_AV; |
a75b9be1 HV |
1337 | v4l2_ctrl_handler_init(&state->hdl, 9); |
1338 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1339 | V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); | |
1340 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1341 | V4L2_CID_CONTRAST, 0, 127, 1, 64); | |
1342 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1343 | V4L2_CID_SATURATION, 0, 127, 1, 64); | |
1344 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, | |
1345 | V4L2_CID_HUE, -128, 127, 1, 0); | |
1346 | ||
1347 | state->volume = v4l2_ctrl_new_std(&state->hdl, | |
1348 | &cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME, | |
1349 | 0, 65535, 65535 / 100, 0); | |
1350 | v4l2_ctrl_new_std(&state->hdl, | |
1351 | &cx18_av_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE, | |
1352 | 0, 1, 1, 0); | |
1353 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, | |
1354 | V4L2_CID_AUDIO_BALANCE, | |
1355 | 0, 65535, 65535 / 100, 32768); | |
1356 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, | |
1357 | V4L2_CID_AUDIO_BASS, | |
1358 | 0, 65535, 65535 / 100, 32768); | |
1359 | v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, | |
1360 | V4L2_CID_AUDIO_TREBLE, | |
1361 | 0, 65535, 65535 / 100, 32768); | |
1362 | sd->ctrl_handler = &state->hdl; | |
1363 | if (state->hdl.error) { | |
1364 | int err = state->hdl.error; | |
1365 | ||
1366 | v4l2_ctrl_handler_free(&state->hdl); | |
1367 | return err; | |
1368 | } | |
7f3ea4de | 1369 | err = v4l2_device_register_subdev(&cx->v4l2_dev, sd); |
a75b9be1 HV |
1370 | if (err) |
1371 | v4l2_ctrl_handler_free(&state->hdl); | |
1372 | else | |
7f3ea4de HV |
1373 | cx18_av_init(cx); |
1374 | return err; | |
1a267046 | 1375 | } |