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Merge branch 'for-john' of git://git.kernel.org/pub/scm/linux/kernel/git/jberg/mac80211
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-cards.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/delay.h>
7b888014 26#include <media/cx25840.h>
78db8547 27#include <linux/firmware.h>
cff4fa84 28#include <misc/altera.h>
d19770e5
ST		 29
30#include "cx23885.h"
90a71b1c 31#include "tuner-xc2028.h"
b8f0d306 32#include "netup-eeprom.h"
5a23b076 33#include "netup-init.h"
78db8547 34#include "altera-ci.h"
0cf8af57 35#include "xc4000.h"
78db8547 36#include "xc5000.h"
29f8a0a5 37#include "cx23888-ir.h"
d19770e5 38
89343055 39static unsigned int netup_card_rev = 4;
2d12421d
AO		 40module_param(netup_card_rev, int, 0644);
41MODULE_PARM_DESC(netup_card_rev,
42 "NetUP Dual DVB-T/C CI card revision");
fa647f24
AW		 43static unsigned int enable_885_ir;
44module_param(enable_885_ir, int, 0644);
45MODULE_PARM_DESC(enable_885_ir,
46 "Enable integrated IR controller for supported\n"
47 "\t\t CX2388[57] boards that are wired for it:\n"
48 "\t\t\tHVR-1250 (reported safe)\n"
076f0e35 49 "\t\t\tTerraTec Cinergy T PCIe Dual (not well tested, appears to be safe)\n"
fa647f24
AW		 50 "\t\t\tTeVii S470 (reported unsafe)\n"
51 "\t\t This can cause an interrupt storm with some cards.\n"
52 "\t\t Default: 0 [Disabled]");
53
d19770e5
ST		 54/* ------------------------------------------------------------------ */
55/* board config info */
56
57struct cx23885_board cx23885_boards[] = {
58 [CX23885_BOARD_UNKNOWN] = {
59 .name = "UNKNOWN/GENERIC",
c7712613
ST		 60 /* Ensure safe default for unknown boards */
61 .clk_freq = 0,
d19770e5
ST		 62 .input = {{
63 .type = CX23885_VMUX_COMPOSITE1,
64 .vmux = 0,
9c8ced51 65 }, {
d19770e5
ST		 66 .type = CX23885_VMUX_COMPOSITE2,
67 .vmux = 1,
9c8ced51 68 }, {
d19770e5
ST		 69 .type = CX23885_VMUX_COMPOSITE3,
70 .vmux = 2,
9c8ced51 71 }, {
d19770e5
ST		 72 .type = CX23885_VMUX_COMPOSITE4,
73 .vmux = 3,
9c8ced51 74 } },
d19770e5
ST		 75 },
76 [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
77 .name = "Hauppauge WinTV-HVR1800lp",
d19770e5
ST		 78 .portc = CX23885_MPEG_DVB,
79 .input = {{
80 .type = CX23885_VMUX_TELEVISION,
81 .vmux = 0,
82 .gpio0 = 0xff00,
9c8ced51 83 }, {
d19770e5
ST		 84 .type = CX23885_VMUX_DEBUG,
85 .vmux = 0,
86 .gpio0 = 0xff01,
9c8ced51 87 }, {
d19770e5
ST		 88 .type = CX23885_VMUX_COMPOSITE1,
89 .vmux = 1,
90 .gpio0 = 0xff02,
9c8ced51 91 }, {
d19770e5
ST		 92 .type = CX23885_VMUX_SVIDEO,
93 .vmux = 2,
94 .gpio0 = 0xff02,
9c8ced51 95 } },
d19770e5
ST		 96 },
97 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
98 .name = "Hauppauge WinTV-HVR1800",
7b888014 99 .porta = CX23885_ANALOG_VIDEO,
a589b665 100 .portb = CX23885_MPEG_ENCODER,
d19770e5 101 .portc = CX23885_MPEG_DVB,
7b888014
ST		 102 .tuner_type = TUNER_PHILIPS_TDA8290,
103 .tuner_addr = 0x42, /* 0x84 >> 1 */
557f48d5 104 .tuner_bus = 1,
d19770e5
ST		 105 .input = {{
106 .type = CX23885_VMUX_TELEVISION,
7b888014
ST		 107 .vmux = CX25840_VIN7_CH3 |
108 CX25840_VIN5_CH2 |
109 CX25840_VIN2_CH1,
33cdeb35 110 .amux = CX25840_AUDIO8,
7b888014 111 .gpio0 = 0,
9c8ced51 112 }, {
d19770e5 113 .type = CX23885_VMUX_COMPOSITE1,
7b888014
ST		 114 .vmux = CX25840_VIN7_CH3 |
115 CX25840_VIN4_CH2 |
116 CX25840_VIN6_CH1,
33cdeb35 117 .amux = CX25840_AUDIO7,
7b888014 118 .gpio0 = 0,
9c8ced51 119 }, {
d19770e5 120 .type = CX23885_VMUX_SVIDEO,
7b888014
ST		 121 .vmux = CX25840_VIN7_CH3 |
122 CX25840_VIN4_CH2 |
123 CX25840_VIN8_CH1 |
124 CX25840_SVIDEO_ON,
33cdeb35 125 .amux = CX25840_AUDIO7,
7b888014 126 .gpio0 = 0,
9c8ced51 127 } },
d19770e5 128 },
a77743bc
ST		 129 [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
130 .name = "Hauppauge WinTV-HVR1250",
d214ddc8 131 .porta = CX23885_ANALOG_VIDEO,
a77743bc 132 .portc = CX23885_MPEG_DVB,
d214ddc8
DH		 133#ifdef MT2131_NO_ANALOG_SUPPORT_YET
134 .tuner_type = TUNER_PHILIPS_TDA8290,
135 .tuner_addr = 0x42, /* 0x84 >> 1 */
136 .tuner_bus = 1,
137#endif
138 .force_bff = 1,
a77743bc 139 .input = {{
d214ddc8 140#ifdef MT2131_NO_ANALOG_SUPPORT_YET
a77743bc 141 .type = CX23885_VMUX_TELEVISION,
d214ddc8
DH		 142 .vmux = CX25840_VIN7_CH3 |
143 CX25840_VIN5_CH2 |
144 CX25840_VIN2_CH1,
145 .amux = CX25840_AUDIO8,
a77743bc 146 .gpio0 = 0xff00,
9c8ced51 147 }, {
d214ddc8 148#endif
a77743bc 149 .type = CX23885_VMUX_COMPOSITE1,
d214ddc8
DH		 150 .vmux = CX25840_VIN7_CH3 |
151 CX25840_VIN4_CH2 |
152 CX25840_VIN6_CH1,
153 .amux = CX25840_AUDIO7,
a77743bc 154 .gpio0 = 0xff02,
9c8ced51 155 }, {
a77743bc 156 .type = CX23885_VMUX_SVIDEO,
d214ddc8
DH		 157 .vmux = CX25840_VIN7_CH3 |
158 CX25840_VIN4_CH2 |
159 CX25840_VIN8_CH1 |
160 CX25840_SVIDEO_ON,
161 .amux = CX25840_AUDIO7,
a77743bc 162 .gpio0 = 0xff02,
9c8ced51 163 } },
a77743bc 164 },
9bc37caa
MK		 165 [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
166 .name = "DViCO FusionHDTV5 Express",
a6a3f140 167 .portb = CX23885_MPEG_DVB,
9bc37caa 168 },
d1987d55
ST		 169 [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
170 .name = "Hauppauge WinTV-HVR1500Q",
171 .portc = CX23885_MPEG_DVB,
172 },
07b4a835
MK		 173 [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
174 .name = "Hauppauge WinTV-HVR1500",
18d64476 175 .porta = CX23885_ANALOG_VIDEO,
07b4a835 176 .portc = CX23885_MPEG_DVB,
18d64476
MM		 177 .tuner_type = TUNER_XC2028,
178 .tuner_addr = 0x61, /* 0xc2 >> 1 */
179 .input = {{
180 .type = CX23885_VMUX_TELEVISION,
181 .vmux = CX25840_VIN7_CH3 |
182 CX25840_VIN5_CH2 |
183 CX25840_VIN2_CH1,
184 .gpio0 = 0,
185 }, {
186 .type = CX23885_VMUX_COMPOSITE1,
187 .vmux = CX25840_VIN7_CH3 |
188 CX25840_VIN4_CH2 |
189 CX25840_VIN6_CH1,
190 .gpio0 = 0,
191 }, {
192 .type = CX23885_VMUX_SVIDEO,
193 .vmux = CX25840_VIN7_CH3 |
194 CX25840_VIN4_CH2 |
195 CX25840_VIN8_CH1 |
196 CX25840_SVIDEO_ON,
197 .gpio0 = 0,
198 } },
07b4a835 199 },
b3ea0166
ST		 200 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
201 .name = "Hauppauge WinTV-HVR1200",
202 .portc = CX23885_MPEG_DVB,
203 },
a780a31c
ST		 204 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
205 .name = "Hauppauge WinTV-HVR1700",
206 .portc = CX23885_MPEG_DVB,
207 },
66762373
ST		 208 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
209 .name = "Hauppauge WinTV-HVR1400",
210 .portc = CX23885_MPEG_DVB,
211 },
335377b7
MK		 212 [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
213 .name = "DViCO FusionHDTV7 Dual Express",
aaadeac8 214 .portb = CX23885_MPEG_DVB,
335377b7
MK		 215 .portc = CX23885_MPEG_DVB,
216 },
aef2d186
ST		 217 [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
218 .name = "DViCO FusionHDTV DVB-T Dual Express",
219 .portb = CX23885_MPEG_DVB,
220 .portc = CX23885_MPEG_DVB,
221 },
4c56b04a
ST		 222 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
223 .name = "Leadtek Winfast PxDVR3200 H",
224 .portc = CX23885_MPEG_DVB,
225 },
0cf8af57 226 [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000] = {
227 .name = "Leadtek Winfast PxDVR3200 H XC4000",
228 .porta = CX23885_ANALOG_VIDEO,
229 .portc = CX23885_MPEG_DVB,
230 .tuner_type = TUNER_XC4000,
231 .tuner_addr = 0x61,
9ee8537f
MS		 232 .radio_type = UNSET,
233 .radio_addr = ADDR_UNSET,
0cf8af57 234 .input = {{
235 .type = CX23885_VMUX_TELEVISION,
236 .vmux = CX25840_VIN2_CH1 |
237 CX25840_VIN5_CH2 |
238 CX25840_NONE0_CH3,
239 }, {
240 .type = CX23885_VMUX_COMPOSITE1,
241 .vmux = CX25840_COMPOSITE1,
242 }, {
243 .type = CX23885_VMUX_SVIDEO,
244 .vmux = CX25840_SVIDEO_LUMA3 |
245 CX25840_SVIDEO_CHROMA4,
246 }, {
247 .type = CX23885_VMUX_COMPONENT,
248 .vmux = CX25840_VIN7_CH1 |
249 CX25840_VIN6_CH2 |
250 CX25840_VIN8_CH3 |
251 CX25840_COMPONENT_ON,
252 } },
253 },
9bb1b7e8
IL		 254 [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
255 .name = "Compro VideoMate E650F",
256 .portc = CX23885_MPEG_DVB,
257 },
96318d0c
IL		 258 [CX23885_BOARD_TBS_6920] = {
259 .name = "TurboSight TBS 6920",
260 .portb = CX23885_MPEG_DVB,
261 },
579943f5
IL		 262 [CX23885_BOARD_TEVII_S470] = {
263 .name = "TeVii S470",
264 .portb = CX23885_MPEG_DVB,
265 },
c9b8b04b
IL		 266 [CX23885_BOARD_DVBWORLD_2005] = {
267 .name = "DVBWorld DVB-S2 2005",
268 .portb = CX23885_MPEG_DVB,
269 },
5a23b076 270 [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
78db8547 271 .ci_type = 1,
5a23b076
IL		 272 .name = "NetUP Dual DVB-S2 CI",
273 .portb = CX23885_MPEG_DVB,
274 .portc = CX23885_MPEG_DVB,
275 },
2074dffa
ST		 276 [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
277 .name = "Hauppauge WinTV-HVR1270",
a5dbf457 278 .portc = CX23885_MPEG_DVB,
2074dffa 279 },
d099becb
MK		 280 [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
281 .name = "Hauppauge WinTV-HVR1275",
282 .portc = CX23885_MPEG_DVB,
283 },
19bc5796
MK		 284 [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
285 .name = "Hauppauge WinTV-HVR1255",
0ac60acb 286 .porta = CX23885_ANALOG_VIDEO,
19bc5796 287 .portc = CX23885_MPEG_DVB,
0ac60acb
DH		 288 .tuner_type = TUNER_ABSENT,
289 .tuner_addr = 0x42, /* 0x84 >> 1 */
290 .force_bff = 1,
291 .input = {{
292 .type = CX23885_VMUX_TELEVISION,
293 .vmux = CX25840_VIN7_CH3 |
294 CX25840_VIN5_CH2 |
295 CX25840_VIN2_CH1 |
296 CX25840_DIF_ON,
297 .amux = CX25840_AUDIO8,
298 }, {
299 .type = CX23885_VMUX_COMPOSITE1,
300 .vmux = CX25840_VIN7_CH3 |
301 CX25840_VIN4_CH2 |
302 CX25840_VIN6_CH1,
303 .amux = CX25840_AUDIO7,
304 }, {
305 .type = CX23885_VMUX_SVIDEO,
306 .vmux = CX25840_VIN7_CH3 |
307 CX25840_VIN4_CH2 |
308 CX25840_VIN8_CH1 |
309 CX25840_SVIDEO_ON,
310 .amux = CX25840_AUDIO7,
311 } },
312 },
313 [CX23885_BOARD_HAUPPAUGE_HVR1255_22111] = {
314 .name = "Hauppauge WinTV-HVR1255",
315 .porta = CX23885_ANALOG_VIDEO,
316 .portc = CX23885_MPEG_DVB,
317 .tuner_type = TUNER_ABSENT,
318 .tuner_addr = 0x42, /* 0x84 >> 1 */
319 .force_bff = 1,
320 .input = {{
321 .type = CX23885_VMUX_TELEVISION,
322 .vmux = CX25840_VIN7_CH3 |
323 CX25840_VIN5_CH2 |
324 CX25840_VIN2_CH1 |
325 CX25840_DIF_ON,
326 .amux = CX25840_AUDIO8,
327 }, {
328 .type = CX23885_VMUX_SVIDEO,
329 .vmux = CX25840_VIN7_CH3 |
330 CX25840_VIN4_CH2 |
331 CX25840_VIN8_CH1 |
332 CX25840_SVIDEO_ON,
333 .amux = CX25840_AUDIO7,
334 } },
19bc5796 335 },
6b926eca
MK		 336 [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
337 .name = "Hauppauge WinTV-HVR1210",
338 .portc = CX23885_MPEG_DVB,
339 },
493b7127
DW		 340 [CX23885_BOARD_MYGICA_X8506] = {
341 .name = "Mygica X8506 DMB-TH",
6f0d8c02
DW		 342 .tuner_type = TUNER_XC5000,
343 .tuner_addr = 0x61,
557f48d5 344 .tuner_bus = 1,
bc1548ad 345 .porta = CX23885_ANALOG_VIDEO,
493b7127 346 .portb = CX23885_MPEG_DVB,
bc1548ad 347 .input = {
6f0d8c02
DW		 348 {
349 .type = CX23885_VMUX_TELEVISION,
350 .vmux = CX25840_COMPOSITE2,
351 },
bc1548ad
DW		 352 {
353 .type = CX23885_VMUX_COMPOSITE1,
354 .vmux = CX25840_COMPOSITE8,
355 },
356 {
357 .type = CX23885_VMUX_SVIDEO,
358 .vmux = CX25840_SVIDEO_LUMA3 |
359 CX25840_SVIDEO_CHROMA4,
360 },
361 {
362 .type = CX23885_VMUX_COMPONENT,
363 .vmux = CX25840_COMPONENT_ON |
364 CX25840_VIN1_CH1 |
365 CX25840_VIN6_CH2 |
366 CX25840_VIN7_CH3,
367 },
368 },
493b7127 369 },
2365b2d3
DW		 370 [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
371 .name = "Magic-Pro ProHDTV Extreme 2",
6f0d8c02
DW		 372 .tuner_type = TUNER_XC5000,
373 .tuner_addr = 0x61,
557f48d5 374 .tuner_bus = 1,
bc1548ad 375 .porta = CX23885_ANALOG_VIDEO,
2365b2d3 376 .portb = CX23885_MPEG_DVB,
bc1548ad 377 .input = {
6f0d8c02
DW		 378 {
379 .type = CX23885_VMUX_TELEVISION,
380 .vmux = CX25840_COMPOSITE2,
381 },
bc1548ad
DW		 382 {
383 .type = CX23885_VMUX_COMPOSITE1,
384 .vmux = CX25840_COMPOSITE8,
385 },
386 {
387 .type = CX23885_VMUX_SVIDEO,
388 .vmux = CX25840_SVIDEO_LUMA3 |
389 CX25840_SVIDEO_CHROMA4,
390 },
391 {
392 .type = CX23885_VMUX_COMPONENT,
393 .vmux = CX25840_COMPONENT_ON |
394 CX25840_VIN1_CH1 |
395 CX25840_VIN6_CH2 |
396 CX25840_VIN7_CH3,
397 },
398 },
2365b2d3 399 },
13697380
ST		 400 [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
401 .name = "Hauppauge WinTV-HVR1850",
35045137 402 .porta = CX23885_ANALOG_VIDEO,
13697380
ST		 403 .portb = CX23885_MPEG_ENCODER,
404 .portc = CX23885_MPEG_DVB,
35045137
ST		 405 .tuner_type = TUNER_ABSENT,
406 .tuner_addr = 0x42, /* 0x84 >> 1 */
407 .force_bff = 1,
408 .input = {{
409 .type = CX23885_VMUX_TELEVISION,
410 .vmux = CX25840_VIN7_CH3 |
411 CX25840_VIN5_CH2 |
412 CX25840_VIN2_CH1 |
413 CX25840_DIF_ON,
414 .amux = CX25840_AUDIO8,
415 }, {
416 .type = CX23885_VMUX_COMPOSITE1,
417 .vmux = CX25840_VIN7_CH3 |
418 CX25840_VIN4_CH2 |
419 CX25840_VIN6_CH1,
420 .amux = CX25840_AUDIO7,
421 }, {
422 .type = CX23885_VMUX_SVIDEO,
423 .vmux = CX25840_VIN7_CH3 |
424 CX25840_VIN4_CH2 |
425 CX25840_VIN8_CH1 |
426 CX25840_SVIDEO_ON,
427 .amux = CX25840_AUDIO7,
428 } },
13697380 429 },
34e383dd
VG		 430 [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
431 .name = "Compro VideoMate E800",
432 .portc = CX23885_MPEG_DVB,
433 },
aee0b24c
MK		 434 [CX23885_BOARD_HAUPPAUGE_HVR1290] = {
435 .name = "Hauppauge WinTV-HVR1290",
436 .portc = CX23885_MPEG_DVB,
437 },
ea5697fe
DW		 438 [CX23885_BOARD_MYGICA_X8558PRO] = {
439 .name = "Mygica X8558 PRO DMB-TH",
440 .portb = CX23885_MPEG_DVB,
441 .portc = CX23885_MPEG_DVB,
442 },
0b32d65c
KK		 443 [CX23885_BOARD_LEADTEK_WINFAST_PXTV1200] = {
444 .name = "LEADTEK WinFast PxTV1200",
445 .porta = CX23885_ANALOG_VIDEO,
446 .tuner_type = TUNER_XC2028,
447 .tuner_addr = 0x61,
557f48d5 448 .tuner_bus = 1,
0b32d65c
KK		 449 .input = {{
450 .type = CX23885_VMUX_TELEVISION,
451 .vmux = CX25840_VIN2_CH1 |
452 CX25840_VIN5_CH2 |
453 CX25840_NONE0_CH3,
454 }, {
455 .type = CX23885_VMUX_COMPOSITE1,
456 .vmux = CX25840_COMPOSITE1,
457 }, {
458 .type = CX23885_VMUX_SVIDEO,
459 .vmux = CX25840_SVIDEO_LUMA3 |
460 CX25840_SVIDEO_CHROMA4,
461 }, {
462 .type = CX23885_VMUX_COMPONENT,
463 .vmux = CX25840_VIN7_CH1 |
464 CX25840_VIN6_CH2 |
465 CX25840_VIN8_CH3 |
466 CX25840_COMPONENT_ON,
467 } },
468 },
9028f58f
AC		 469 [CX23885_BOARD_GOTVIEW_X5_3D_HYBRID] = {
470 .name = "GoTView X5 3D Hybrid",
471 .tuner_type = TUNER_XC5000,
472 .tuner_addr = 0x64,
557f48d5 473 .tuner_bus = 1,
9028f58f
AC		 474 .porta = CX23885_ANALOG_VIDEO,
475 .portb = CX23885_MPEG_DVB,
476 .input = {{
477 .type = CX23885_VMUX_TELEVISION,
478 .vmux = CX25840_VIN2_CH1 |
479 CX25840_VIN5_CH2,
480 .gpio0 = 0x02,
481 }, {
482 .type = CX23885_VMUX_COMPOSITE1,
483 .vmux = CX23885_VMUX_COMPOSITE1,
484 }, {
485 .type = CX23885_VMUX_SVIDEO,
486 .vmux = CX25840_SVIDEO_LUMA3 |
487 CX25840_SVIDEO_CHROMA4,
488 } },
489 },
78db8547
IL		 490 [CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF] = {
491 .ci_type = 2,
492 .name = "NetUP Dual DVB-T/C-CI RF",
493 .porta = CX23885_ANALOG_VIDEO,
494 .portb = CX23885_MPEG_DVB,
495 .portc = CX23885_MPEG_DVB,
10d0dcd7
IL		 496 .num_fds_portb = 2,
497 .num_fds_portc = 2,
78db8547
IL		 498 .tuner_type = TUNER_XC5000,
499 .tuner_addr = 0x64,
500 .input = { {
501 .type = CX23885_VMUX_TELEVISION,
502 .vmux = CX25840_COMPOSITE1,
503 } },
504 },
2cb9ccd4
ST		 505 [CX23885_BOARD_MPX885] = {
506 .name = "MPX-885",
507 .porta = CX23885_ANALOG_VIDEO,
508 .input = {{
509 .type = CX23885_VMUX_COMPOSITE1,
510 .vmux = CX25840_COMPOSITE1,
511 .amux = CX25840_AUDIO6,
512 .gpio0 = 0,
513 }, {
514 .type = CX23885_VMUX_COMPOSITE2,
515 .vmux = CX25840_COMPOSITE2,
516 .amux = CX25840_AUDIO6,
517 .gpio0 = 0,
518 }, {
519 .type = CX23885_VMUX_COMPOSITE3,
520 .vmux = CX25840_COMPOSITE3,
521 .amux = CX25840_AUDIO7,
522 .gpio0 = 0,
523 }, {
524 .type = CX23885_VMUX_COMPOSITE4,
525 .vmux = CX25840_COMPOSITE4,
526 .amux = CX25840_AUDIO7,
527 .gpio0 = 0,
528 } },
529 },
87988753
AJD		 530 [CX23885_BOARD_MYGICA_X8507] = {
531 .name = "Mygica X8507",
532 .tuner_type = TUNER_XC5000,
533 .tuner_addr = 0x61,
534 .tuner_bus = 1,
535 .porta = CX23885_ANALOG_VIDEO,
536 .input = {
537 {
538 .type = CX23885_VMUX_TELEVISION,
539 .vmux = CX25840_COMPOSITE2,
540 .amux = CX25840_AUDIO8,
541 },
542 {
543 .type = CX23885_VMUX_COMPOSITE1,
544 .vmux = CX25840_COMPOSITE8,
082c0576 545 .amux = CX25840_AUDIO7,
87988753
AJD		 546 },
547 {
548 .type = CX23885_VMUX_SVIDEO,
549 .vmux = CX25840_SVIDEO_LUMA3 |
550 CX25840_SVIDEO_CHROMA4,
082c0576 551 .amux = CX25840_AUDIO7,
87988753
AJD		 552 },
553 {
554 .type = CX23885_VMUX_COMPONENT,
555 .vmux = CX25840_COMPONENT_ON |
556 CX25840_VIN1_CH1 |
557 CX25840_VIN6_CH2 |
558 CX25840_VIN7_CH3,
082c0576 559 .amux = CX25840_AUDIO7,
87988753
AJD		 560 },
561 },
722c90eb
SR		 562 },
563 [CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL] = {
564 .name = "TerraTec Cinergy T PCIe Dual",
565 .portb = CX23885_MPEG_DVB,
566 .portc = CX23885_MPEG_DVB,
7b134e85
IL		 567 },
568 [CX23885_BOARD_TEVII_S471] = {
569 .name = "TeVii S471",
570 .portb = CX23885_MPEG_DVB,
f667190b
MB		 571 },
572 [CX23885_BOARD_PROF_8000] = {
573 .name = "Prof Revolution DVB-S2 8000",
574 .portb = CX23885_MPEG_DVB,
87988753 575 }
d19770e5
ST		 576};
577const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
578
579/* ------------------------------------------------------------------ */
580/* PCI subsystem IDs */
581
582struct cx23885_subid cx23885_subids[] = {
583 {
584 .subvendor = 0x0070,
585 .subdevice = 0x3400,
586 .card = CX23885_BOARD_UNKNOWN,
9c8ced51 587 }, {
d19770e5
ST		 588 .subvendor = 0x0070,
589 .subdevice = 0x7600,
590 .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
9c8ced51 591 }, {
d19770e5
ST		 592 .subvendor = 0x0070,
593 .subdevice = 0x7800,
594 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 595 }, {
d19770e5
ST		 596 .subvendor = 0x0070,
597 .subdevice = 0x7801,
598 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 599 }, {
6ccb8cfb
MK		 600 .subvendor = 0x0070,
601 .subdevice = 0x7809,
602 .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
9c8ced51 603 }, {
a77743bc
ST		 604 .subvendor = 0x0070,
605 .subdevice = 0x7911,
606 .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
9c8ced51 607 }, {
9bc37caa
MK		 608 .subvendor = 0x18ac,
609 .subdevice = 0xd500,
610 .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
9c8ced51 611 }, {
b00fff0b
MK		 612 .subvendor = 0x0070,
613 .subdevice = 0x7790,
614 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 615 }, {
d1987d55
ST		 616 .subvendor = 0x0070,
617 .subdevice = 0x7797,
618 .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
9c8ced51 619 }, {
b00fff0b
MK		 620 .subvendor = 0x0070,
621 .subdevice = 0x7710,
622 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
9c8ced51 623 }, {
07b4a835
MK		 624 .subvendor = 0x0070,
625 .subdevice = 0x7717,
626 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
b3ea0166
ST		 627 }, {
628 .subvendor = 0x0070,
629 .subdevice = 0x71d1,
630 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
3c3852cd
MK		 631 }, {
632 .subvendor = 0x0070,
633 .subdevice = 0x71d3,
634 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
a780a31c
ST		 635 }, {
636 .subvendor = 0x0070,
637 .subdevice = 0x8101,
638 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
66762373
ST		 639 }, {
640 .subvendor = 0x0070,
641 .subdevice = 0x8010,
642 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
9c8ced51 643 }, {
335377b7
MK		 644 .subvendor = 0x18ac,
645 .subdevice = 0xd618,
646 .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
9c8ced51 647 }, {
aef2d186
ST		 648 .subvendor = 0x18ac,
649 .subdevice = 0xdb78,
650 .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
4c56b04a
ST		 651 }, {
652 .subvendor = 0x107d,
653 .subdevice = 0x6681,
654 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
0cf8af57 655 }, {
656 .subvendor = 0x107d,
657 .subdevice = 0x6f39,
658 .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000,
9bb1b7e8
IL		 659 }, {
660 .subvendor = 0x185b,
661 .subdevice = 0xe800,
662 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
96318d0c
IL		 663 }, {
664 .subvendor = 0x6920,
665 .subdevice = 0x8888,
666 .card = CX23885_BOARD_TBS_6920,
579943f5
IL		 667 }, {
668 .subvendor = 0xd470,
669 .subdevice = 0x9022,
670 .card = CX23885_BOARD_TEVII_S470,
c9b8b04b
IL		 671 }, {
672 .subvendor = 0x0001,
673 .subdevice = 0x2005,
674 .card = CX23885_BOARD_DVBWORLD_2005,
5a23b076
IL		 675 }, {
676 .subvendor = 0x1b55,
677 .subdevice = 0x2a2c,
678 .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
2074dffa
ST		 679 }, {
680 .subvendor = 0x0070,
681 .subdevice = 0x2211,
682 .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
d099becb
MK		 683 }, {
684 .subvendor = 0x0070,
685 .subdevice = 0x2215,
686 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
7d7b5284
MK		 687 }, {
688 .subvendor = 0x0070,
689 .subdevice = 0x221d,
690 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
19bc5796
MK		 691 }, {
692 .subvendor = 0x0070,
693 .subdevice = 0x2251,
694 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
7d7b5284
MK		 695 }, {
696 .subvendor = 0x0070,
697 .subdevice = 0x2259,
0ac60acb 698 .card = CX23885_BOARD_HAUPPAUGE_HVR1255_22111,
6b926eca
MK		 699 }, {
700 .subvendor = 0x0070,
701 .subdevice = 0x2291,
702 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
703 }, {
704 .subvendor = 0x0070,
705 .subdevice = 0x2295,
706 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
7d7b5284
MK		 707 }, {
708 .subvendor = 0x0070,
709 .subdevice = 0x2299,
710 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
711 }, {
712 .subvendor = 0x0070,
713 .subdevice = 0x229d,
714 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
715 }, {
716 .subvendor = 0x0070,
717 .subdevice = 0x22f0,
718 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
719 }, {
720 .subvendor = 0x0070,
721 .subdevice = 0x22f1,
722 .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
723 }, {
724 .subvendor = 0x0070,
725 .subdevice = 0x22f2,
726 .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
727 }, {
728 .subvendor = 0x0070,
729 .subdevice = 0x22f3,
730 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
731 }, {
732 .subvendor = 0x0070,
733 .subdevice = 0x22f4,
734 .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
735 }, {
736 .subvendor = 0x0070,
737 .subdevice = 0x22f5,
738 .card = CX23885_BOARD_HAUPPAUGE_HVR1210, /* HVR1215 */
493b7127
DW		 739 }, {
740 .subvendor = 0x14f1,
741 .subdevice = 0x8651,
742 .card = CX23885_BOARD_MYGICA_X8506,
2365b2d3
DW		 743 }, {
744 .subvendor = 0x14f1,
745 .subdevice = 0x8657,
746 .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
13697380
ST		 747 }, {
748 .subvendor = 0x0070,
749 .subdevice = 0x8541,
750 .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
34e383dd
VG		 751 }, {
752 .subvendor = 0x1858,
753 .subdevice = 0xe800,
754 .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
aee0b24c
MK		 755 }, {
756 .subvendor = 0x0070,
757 .subdevice = 0x8551,
758 .card = CX23885_BOARD_HAUPPAUGE_HVR1290,
ea5697fe
DW		 759 }, {
760 .subvendor = 0x14f1,
761 .subdevice = 0x8578,
762 .card = CX23885_BOARD_MYGICA_X8558PRO,
0b32d65c
KK		 763 }, {
764 .subvendor = 0x107d,
765 .subdevice = 0x6f22,
766 .card = CX23885_BOARD_LEADTEK_WINFAST_PXTV1200,
9028f58f
AC		 767 }, {
768 .subvendor = 0x5654,
769 .subdevice = 0x2390,
770 .card = CX23885_BOARD_GOTVIEW_X5_3D_HYBRID,
78db8547
IL		 771 }, {
772 .subvendor = 0x1b55,
773 .subdevice = 0xe2e4,
774 .card = CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF,
87988753
AJD		 775 }, {
776 .subvendor = 0x14f1,
777 .subdevice = 0x8502,
778 .card = CX23885_BOARD_MYGICA_X8507,
722c90eb
SR		 779 }, {
780 .subvendor = 0x153b,
781 .subdevice = 0x117e,
782 .card = CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL,
7b134e85
IL		 783 }, {
784 .subvendor = 0xd471,
785 .subdevice = 0x9022,
786 .card = CX23885_BOARD_TEVII_S471,
f667190b
MB		 787 }, {
788 .subvendor = 0x8000,
789 .subdevice = 0x3034,
790 .card = CX23885_BOARD_PROF_8000,
d19770e5
ST		 791 },
792};
793const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
794
795void cx23885_card_list(struct cx23885_dev *dev)
796{
797 int i;
798
799 if (0 == dev->pci->subsystem_vendor &&
800 0 == dev->pci->subsystem_device) {
9c8ced51
ST		 801 printk(KERN_INFO
802 "%s: Board has no valid PCIe Subsystem ID and can't\n"
803 "%s: be autodetected. Pass card=<n> insmod option\n"
804 "%s: to workaround that. Redirect complaints to the\n"
805 "%s: vendor of the TV card. Best regards,\n"
d19770e5
ST		 806 "%s: -- tux\n",
807 dev->name, dev->name, dev->name, dev->name, dev->name);
808 } else {
9c8ced51
ST		 809 printk(KERN_INFO
810 "%s: Your board isn't known (yet) to the driver.\n"
811 "%s: Try to pick one of the existing card configs via\n"
d19770e5
ST		 812 "%s: card=<n> insmod option. Updating to the latest\n"
813 "%s: version might help as well.\n",
814 dev->name, dev->name, dev->name, dev->name);
815 }
9c8ced51 816 printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
d19770e5
ST		 817 dev->name);
818 for (i = 0; i < cx23885_bcount; i++)
9c8ced51 819 printk(KERN_INFO "%s: card=%d -> %s\n",
d19770e5
ST		 820 dev->name, i, cx23885_boards[i].name);
821}
822
823static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
824{
825 struct tveeprom tv;
826
9c8ced51
ST		 827 tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
828 eeprom_data);
d19770e5 829
d19770e5 830 /* Make sure we support the board model */
9c8ced51 831 switch (tv.model) {
5308cf09
MK		 832 case 22001:
833 /* WinTV-HVR1270 (PCIe, Retail, half height)
834 * ATSC/QAM and basic analog, IR Blast */
835 case 22009:
836 /* WinTV-HVR1210 (PCIe, Retail, half height)
837 * DVB-T and basic analog, IR Blast */
838 case 22011:
839 /* WinTV-HVR1270 (PCIe, Retail, half height)
840 * ATSC/QAM and basic analog, IR Recv */
841 case 22019:
842 /* WinTV-HVR1210 (PCIe, Retail, half height)
843 * DVB-T and basic analog, IR Recv */
844 case 22021:
845 /* WinTV-HVR1275 (PCIe, Retail, half height)
846 * ATSC/QAM and basic analog, IR Recv */
847 case 22029:
848 /* WinTV-HVR1210 (PCIe, Retail, half height)
849 * DVB-T and basic analog, IR Recv */
850 case 22101:
851 /* WinTV-HVR1270 (PCIe, Retail, full height)
852 * ATSC/QAM and basic analog, IR Blast */
853 case 22109:
854 /* WinTV-HVR1210 (PCIe, Retail, full height)
855 * DVB-T and basic analog, IR Blast */
856 case 22111:
857 /* WinTV-HVR1270 (PCIe, Retail, full height)
858 * ATSC/QAM and basic analog, IR Recv */
859 case 22119:
860 /* WinTV-HVR1210 (PCIe, Retail, full height)
861 * DVB-T and basic analog, IR Recv */
862 case 22121:
863 /* WinTV-HVR1275 (PCIe, Retail, full height)
864 * ATSC/QAM and basic analog, IR Recv */
865 case 22129:
866 /* WinTV-HVR1210 (PCIe, Retail, full height)
867 * DVB-T and basic analog, IR Recv */
36396c89
MK		 868 case 71009:
869 /* WinTV-HVR1200 (PCIe, Retail, full height)
870 * DVB-T and basic analog */
871 case 71359:
872 /* WinTV-HVR1200 (PCIe, OEM, half height)
873 * DVB-T and basic analog */
874 case 71439:
875 /* WinTV-HVR1200 (PCIe, OEM, half height)
876 * DVB-T and basic analog */
877 case 71449:
878 /* WinTV-HVR1200 (PCIe, OEM, full height)
879 * DVB-T and basic analog */
880 case 71939:
881 /* WinTV-HVR1200 (PCIe, OEM, half height)
882 * DVB-T and basic analog */
883 case 71949:
884 /* WinTV-HVR1200 (PCIe, OEM, full height)
885 * DVB-T and basic analog */
886 case 71959:
887 /* WinTV-HVR1200 (PCIe, OEM, full height)
888 * DVB-T and basic analog */
889 case 71979:
890 /* WinTV-HVR1200 (PCIe, OEM, half height)
891 * DVB-T and basic analog */
892 case 71999:
893 /* WinTV-HVR1200 (PCIe, OEM, full height)
894 * DVB-T and basic analog */
9c8ced51
ST		 895 case 76601:
896 /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
897 channel ATSC and MPEG2 HW Encoder */
898 case 77001:
899 /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
900 and Basic analog */
901 case 77011:
902 /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
903 and Basic analog */
904 case 77041:
905 /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
906 and Basic analog */
907 case 77051:
908 /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
909 and Basic analog */
910 case 78011:
911 /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
912 Dual channel ATSC and MPEG2 HW Encoder */
913 case 78501:
914 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
915 Dual channel ATSC and MPEG2 HW Encoder */
916 case 78521:
917 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
918 Dual channel ATSC and MPEG2 HW Encoder */
919 case 78531:
920 /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
921 Dual channel ATSC and MPEG2 HW Encoder */
922 case 78631:
923 /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
924 Dual channel ATSC and MPEG2 HW Encoder */
925 case 79001:
926 /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
927 ATSC and Basic analog */
928 case 79101:
929 /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
930 ATSC and Basic analog */
ebbeb460
AW		 931 case 79501:
932 /* WinTV-HVR1250 (PCIe, No IR, half height,
933 ATSC [at least] and Basic analog) */
9c8ced51
ST		 934 case 79561:
935 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
936 ATSC and Basic analog */
937 case 79571:
938 /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
939 ATSC and Basic analog */
940 case 79671:
941 /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
942 ATSC and Basic analog */
66762373
ST		 943 case 80019:
944 /* WinTV-HVR1400 (Express Card, Retail, IR,
945 * DVB-T and Basic analog */
36396c89
MK		 946 case 81509:
947 /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
948 * DVB-T and MPEG2 HW Encoder */
a780a31c 949 case 81519:
36396c89 950 /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
a780a31c 951 * DVB-T and MPEG2 HW Encoder */
d19770e5 952 break;
13697380 953 case 85021:
73a5f419 954 /* WinTV-HVR1850 (PCIe, Retail, 3.5mm in, IR, FM,
13697380
ST		 955 Dual channel ATSC and MPEG2 HW Encoder */
956 break;
73a5f419
MK		 957 case 85721:
958 /* WinTV-HVR1290 (PCIe, OEM, RCA in, IR,
959 Dual channel ATSC and Basic analog */
960 break;
d19770e5 961 default:
13697380
ST		 962 printk(KERN_WARNING "%s: warning: "
963 "unknown hauppauge model #%d\n",
9c8ced51 964 dev->name, tv.model);
d19770e5
ST		 965 break;
966 }
967
968 printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
969 dev->name, tv.model);
970}
971
d7cba043 972int cx23885_tuner_callback(void *priv, int component, int command, int arg)
8c70017f 973{
89ce2216
ST		 974 struct cx23885_tsport *port = priv;
975 struct cx23885_dev *dev = port->dev;
6df51690
ST		 976 u32 bitmask = 0;
977
c6cff169 978 if ((command == XC2028_RESET_CLK) || (command == XC2028_I2C_FLUSH))
89ce2216
ST		 979 return 0;
980
6df51690
ST		 981 if (command != 0) {
982 printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
983 __func__, command);
984 return -EINVAL;
985 }
8c70017f 986
9c8ced51 987 switch (dev->board) {
90a71b1c
ST		 988 case CX23885_BOARD_HAUPPAUGE_HVR1400:
989 case CX23885_BOARD_HAUPPAUGE_HVR1500:
8c70017f 990 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
4c56b04a 991 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 992 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 993 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 994 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 995 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
90a71b1c 996 /* Tuner Reset Command */
4c56b04a 997 bitmask = 0x04;
6df51690
ST		 998 break;
999 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 1000 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
4c56b04a
ST		 1001 /* Two identical tuners on two different i2c buses,
1002 * we need to reset the correct gpio. */
d4dc673d 1003 if (port->nr == 1)
4c56b04a 1004 bitmask = 0x01;
d4dc673d 1005 else if (port->nr == 2)
4c56b04a 1006 bitmask = 0x04;
8c70017f 1007 break;
9028f58f
AC		 1008 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1009 /* Tuner Reset Command */
1010 bitmask = 0x02;
1011 break;
78db8547
IL		 1012 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1013 altera_ci_tuner_reset(dev, port->nr);
1014 break;
8c70017f
ST		 1015 }
1016
6df51690
ST		 1017 if (bitmask) {
1018 /* Drive the tuner into reset and back out */
1019 cx_clear(GP0_IO, bitmask);
1020 mdelay(200);
1021 cx_set(GP0_IO, bitmask);
1022 }
1023
1024 return 0;
8c70017f 1025}
73c993a8 1026
a6a3f140
ST		 1027void cx23885_gpio_setup(struct cx23885_dev *dev)
1028{
9c8ced51 1029 switch (dev->board) {
a6a3f140
ST		 1030 case CX23885_BOARD_HAUPPAUGE_HVR1250:
1031 /* GPIO-0 cx24227 demodulator reset */
1032 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1033 break;
07b4a835
MK		 1034 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1035 /* GPIO-0 cx24227 demodulator */
1036 /* GPIO-2 xc3028 tuner */
1037
1038 /* Put the parts into reset */
1039 cx_set(GP0_IO, 0x00050000);
1040 cx_clear(GP0_IO, 0x00000005);
1041 msleep(5);
1042
1043 /* Bring the parts out of reset */
1044 cx_set(GP0_IO, 0x00050005);
1045 break;
d1987d55
ST		 1046 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1047 /* GPIO-0 cx24227 demodulator reset */
1048 /* GPIO-2 xc5000 tuner reset */
1049 cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
1050 break;
a6a3f140
ST		 1051 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1052 /* GPIO-0 656_CLK */
1053 /* GPIO-1 656_D0 */
1054 /* GPIO-2 8295A Reset */
1055 /* GPIO-3-10 cx23417 data0-7 */
1056 /* GPIO-11-14 cx23417 addr0-3 */
1057 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1058 /* GPIO-19 IR_RX */
3ba71d21 1059
a589b665
ST		 1060 /* CX23417 GPIO's */
1061 /* EIO15 Zilog Reset */
1062 /* EIO14 S5H1409/CX24227 Reset */
f659c513
ST		 1063 mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
1064
1065 /* Put the demod into reset and protect the eeprom */
1066 mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
1067 mdelay(100);
1068
1069 /* Bring the demod and blaster out of reset */
1070 mc417_gpio_set(dev, GPIO_15 | GPIO_14);
1071 mdelay(100);
a589b665 1072
5206d6ec 1073 /* Force the TDA8295A into reset and back */
21ff3e4f
ST		 1074 cx23885_gpio_enable(dev, GPIO_2, 1);
1075 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 1076 mdelay(20);
21ff3e4f 1077 cx23885_gpio_clear(dev, GPIO_2);
5206d6ec 1078 mdelay(20);
21ff3e4f 1079 cx23885_gpio_set(dev, GPIO_2);
5206d6ec 1080 mdelay(20);
a6a3f140 1081 break;
b3ea0166
ST		 1082 case CX23885_BOARD_HAUPPAUGE_HVR1200:
1083 /* GPIO-0 tda10048 demodulator reset */
1084 /* GPIO-2 tda18271 tuner reset */
1085
a780a31c
ST		 1086 /* Put the parts into reset and back */
1087 cx_set(GP0_IO, 0x00050000);
1088 mdelay(20);
1089 cx_clear(GP0_IO, 0x00000005);
1090 mdelay(20);
1091 cx_set(GP0_IO, 0x00050005);
1092 break;
1093 case CX23885_BOARD_HAUPPAUGE_HVR1700:
1094 /* GPIO-0 TDA10048 demodulator reset */
1095 /* GPIO-2 TDA8295A Reset */
1096 /* GPIO-3-10 cx23417 data0-7 */
1097 /* GPIO-11-14 cx23417 addr0-3 */
1098 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1099
1100 /* The following GPIO's are on the interna AVCore (cx25840) */
1101 /* GPIO-19 IR_RX */
1102 /* GPIO-20 IR_TX 416/DVBT Select */
1103 /* GPIO-21 IIS DAT */
1104 /* GPIO-22 IIS WCLK */
1105 /* GPIO-23 IIS BCLK */
1106
66762373
ST		 1107 /* Put the parts into reset and back */
1108 cx_set(GP0_IO, 0x00050000);
1109 mdelay(20);
1110 cx_clear(GP0_IO, 0x00000005);
1111 mdelay(20);
1112 cx_set(GP0_IO, 0x00050005);
1113 break;
1114 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1115 /* GPIO-0 Dibcom7000p demodulator reset */
1116 /* GPIO-2 xc3028L tuner reset */
1117 /* GPIO-13 LED */
1118
b3ea0166
ST		 1119 /* Put the parts into reset and back */
1120 cx_set(GP0_IO, 0x00050000);
1121 mdelay(20);
1122 cx_clear(GP0_IO, 0x00000005);
1123 mdelay(20);
1124 cx_set(GP0_IO, 0x00050005);
1125 break;
1ecc5aed
ST		 1126 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1127 /* GPIO-0 xc5000 tuner reset i2c bus 0 */
1128 /* GPIO-1 s5h1409 demod reset i2c bus 0 */
1129 /* GPIO-2 xc5000 tuner reset i2c bus 1 */
1130 /* GPIO-3 s5h1409 demod reset i2c bus 0 */
1131
aef2d186
ST		 1132 /* Put the parts into reset and back */
1133 cx_set(GP0_IO, 0x000f0000);
1134 mdelay(20);
1135 cx_clear(GP0_IO, 0x0000000f);
1136 mdelay(20);
1137 cx_set(GP0_IO, 0x000f000f);
1138 break;
1139 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1140 /* GPIO-0 portb xc3028 reset */
1141 /* GPIO-1 portb zl10353 reset */
1142 /* GPIO-2 portc xc3028 reset */
1143 /* GPIO-3 portc zl10353 reset */
1144
1ecc5aed
ST		 1145 /* Put the parts into reset and back */
1146 cx_set(GP0_IO, 0x000f0000);
1147 mdelay(20);
1148 cx_clear(GP0_IO, 0x0000000f);
1149 mdelay(20);
1150 cx_set(GP0_IO, 0x000f000f);
1151 break;
4c56b04a 1152 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1153 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1154 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 1155 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0b32d65c 1156 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
4c56b04a
ST		 1157 /* GPIO-2 xc3028 tuner reset */
1158
1159 /* The following GPIO's are on the internal AVCore (cx25840) */
1160 /* GPIO-? zl10353 demod reset */
1161
1162 /* Put the parts into reset and back */
1163 cx_set(GP0_IO, 0x00040000);
1164 mdelay(20);
1165 cx_clear(GP0_IO, 0x00000004);
1166 mdelay(20);
1167 cx_set(GP0_IO, 0x00040004);
1168 break;
96318d0c 1169 case CX23885_BOARD_TBS_6920:
f667190b 1170 case CX23885_BOARD_PROF_8000:
96318d0c
IL		 1171 cx_write(MC417_CTL, 0x00000036);
1172 cx_write(MC417_OEN, 0x00001000);
09ea33e5
IL		 1173 cx_set(MC417_RWD, 0x00000002);
1174 mdelay(200);
1175 cx_clear(MC417_RWD, 0x00000800);
1176 mdelay(200);
1177 cx_set(MC417_RWD, 0x00000800);
1178 mdelay(200);
96318d0c 1179 break;
5a23b076
IL		 1180 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1181 /* GPIO-0 INTA from CiMax1
1182 GPIO-1 INTB from CiMax2
1183 GPIO-2 reset chips
1184 GPIO-3 to GPIO-10 data/addr for CA
1185 GPIO-11 ~CS0 to CiMax1
1186 GPIO-12 ~CS1 to CiMax2
1187 GPIO-13 ADL0 load LSB addr
1188 GPIO-14 ADL1 load MSB addr
1189 GPIO-15 ~RDY from CiMax
1190 GPIO-17 ~RD to CiMax
1191 GPIO-18 ~WR to CiMax
1192 */
1193 cx_set(GP0_IO, 0x00040000); /* GPIO as out */
1194 /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
1195 cx_clear(GP0_IO, 0x00030004);
1196 mdelay(100);/* reset delay */
1197 cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
1198 cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
1199 /* GPIO-15 IN as ~ACK, rest as OUT */
1200 cx_write(MC417_OEN, 0x00001000);
1201 /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
1202 cx_write(MC417_RWD, 0x0000c300);
1203 /* enable irq */
1204 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1205 break;
2074dffa 1206 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1207 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1208 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1209 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1210 case CX23885_BOARD_HAUPPAUGE_HVR1210:
d099becb 1211 /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
6b926eca
MK		 1212 /* GPIO-6 I2C Gate which can isolate the demod from the bus */
1213 /* GPIO-9 Demod reset */
2074dffa
ST		 1214
1215 /* Put the parts into reset and back */
d099becb
MK		 1216 cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
1217 cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
2074dffa
ST		 1218 cx23885_gpio_clear(dev, GPIO_9);
1219 mdelay(20);
1220 cx23885_gpio_set(dev, GPIO_9);
1221 break;
493b7127 1222 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 1223 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
87988753 1224 case CX23885_BOARD_MYGICA_X8507:
8e069bb9 1225 /* GPIO-0 (0)Analog / (1)Digital TV */
493b7127 1226 /* GPIO-1 reset XC5000 */
2365b2d3 1227 /* GPIO-2 reset LGS8GL5 / LGS8G75 */
8e069bb9
DW		 1228 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
1229 cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
493b7127 1230 mdelay(100);
8e069bb9 1231 cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
493b7127
DW		 1232 mdelay(100);
1233 break;
ea5697fe
DW		 1234 case CX23885_BOARD_MYGICA_X8558PRO:
1235 /* GPIO-0 reset first ATBM8830 */
1236 /* GPIO-1 reset second ATBM8830 */
1237 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
1238 cx23885_gpio_clear(dev, GPIO_0 | GPIO_1);
1239 mdelay(100);
1240 cx23885_gpio_set(dev, GPIO_0 | GPIO_1);
1241 mdelay(100);
1242 break;
13697380 1243 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1244 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1245 /* GPIO-0 656_CLK */
1246 /* GPIO-1 656_D0 */
1247 /* GPIO-2 Wake# */
1248 /* GPIO-3-10 cx23417 data0-7 */
1249 /* GPIO-11-14 cx23417 addr0-3 */
1250 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
1251 /* GPIO-19 IR_RX */
1252 /* GPIO-20 C_IR_TX */
1253 /* GPIO-21 I2S DAT */
1254 /* GPIO-22 I2S WCLK */
1255 /* GPIO-23 I2S BCLK */
1256 /* ALT GPIO: EXP GPIO LATCH */
1257
1258 /* CX23417 GPIO's */
1259 /* GPIO-14 S5H1411/CX24228 Reset */
1260 /* GPIO-13 EEPROM write protect */
1261 mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
1262
1263 /* Put the demod into reset and protect the eeprom */
1264 mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
1265 mdelay(100);
1266
1267 /* Bring the demod out of reset */
1268 mc417_gpio_set(dev, GPIO_14);
1269 mdelay(100);
1270
1271 /* CX24228 GPIO */
1272 /* Connected to IF / Mux */
1273 break;
9028f58f
AC		 1274 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
1275 cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
1276 break;
78db8547
IL		 1277 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1278 /* GPIO-0 ~INT in
1279 GPIO-1 TMS out
1280 GPIO-2 ~reset chips out
1281 GPIO-3 to GPIO-10 data/addr for CA in/out
1282 GPIO-11 ~CS out
1283 GPIO-12 ADDR out
1284 GPIO-13 ~WR out
1285 GPIO-14 ~RD out
1286 GPIO-15 ~RDY in
1287 GPIO-16 TCK out
1288 GPIO-17 TDO in
1289 GPIO-18 TDI out
1290 */
1291 cx_set(GP0_IO, 0x00060000); /* GPIO-1,2 as out */
1292 /* GPIO-0 as INT, reset & TMS low */
1293 cx_clear(GP0_IO, 0x00010006);
1294 mdelay(100);/* reset delay */
1295 cx_set(GP0_IO, 0x00000004); /* reset high */
1296 cx_write(MC417_CTL, 0x00000037);/* enable GPIO-3..18 pins */
1297 /* GPIO-17 is TDO in, GPIO-15 is ~RDY in, rest is out */
1298 cx_write(MC417_OEN, 0x00005000);
1299 /* ~RD, ~WR high; ADDR low; ~CS high */
1300 cx_write(MC417_RWD, 0x00000d00);
1301 /* enable irq */
1302 cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
1303 break;
a6a3f140
ST		 1304 }
1305}
1306
1307int cx23885_ir_init(struct cx23885_dev *dev)
1308{
98d109f9 1309 static struct v4l2_subdev_io_pin_config ir_rxtx_pin_cfg[] = {
81f287da
AW		 1310 {
1311 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1312 .pin = CX23885_PIN_IR_RX_GPIO19,
1313 .function = CX23885_PAD_IR_RX,
1314 .value = 0,
1315 .strength = CX25840_PIN_DRIVE_MEDIUM,
1316 }, {
1317 .flags = V4L2_SUBDEV_IO_PIN_OUTPUT,
1318 .pin = CX23885_PIN_IR_TX_GPIO20,
1319 .function = CX23885_PAD_IR_TX,
1320 .value = 0,
1321 .strength = CX25840_PIN_DRIVE_MEDIUM,
1322 }
1323 };
98d109f9
AW		 1324 const size_t ir_rxtx_pin_cfg_count = ARRAY_SIZE(ir_rxtx_pin_cfg);
1325
1326 static struct v4l2_subdev_io_pin_config ir_rx_pin_cfg[] = {
1327 {
1328 .flags = V4L2_SUBDEV_IO_PIN_INPUT,
1329 .pin = CX23885_PIN_IR_RX_GPIO19,
1330 .function = CX23885_PAD_IR_RX,
1331 .value = 0,
1332 .strength = CX25840_PIN_DRIVE_MEDIUM,
1333 }
1334 };
1335 const size_t ir_rx_pin_cfg_count = ARRAY_SIZE(ir_rx_pin_cfg);
81f287da
AW		 1336
1337 struct v4l2_subdev_ir_parameters params;
29f8a0a5 1338 int ret = 0;
a6a3f140 1339 switch (dev->board) {
07b4a835 1340 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1341 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 1342 case CX23885_BOARD_HAUPPAUGE_HVR1800:
b3ea0166 1343 case CX23885_BOARD_HAUPPAUGE_HVR1200:
66762373 1344 case CX23885_BOARD_HAUPPAUGE_HVR1400:
d099becb 1345 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1346 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1347 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1348 case CX23885_BOARD_HAUPPAUGE_HVR1210:
a6a3f140
ST		 1349 /* FIXME: Implement me */
1350 break;
9b3d8ecc
AW		 1351 case CX23885_BOARD_HAUPPAUGE_HVR1270:
1352 ret = cx23888_ir_probe(dev);
1353 if (ret)
1354 break;
1355 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
1356 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1357 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
1358 break;
29f8a0a5 1359 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1360 case CX23885_BOARD_HAUPPAUGE_HVR1290:
29f8a0a5
AW		 1361 ret = cx23888_ir_probe(dev);
1362 if (ret)
1363 break;
1364 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
81f287da 1365 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
98d109f9 1366 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
81f287da
AW		 1367 /*
1368 * For these boards we need to invert the Tx output via the
1369 * IR controller to have the LED off while idle
1370 */
1371 v4l2_subdev_call(dev->sd_ir, ir, tx_g_parameters, &params);
1372 params.enable = false;
1373 params.shutdown = false;
1374 params.invert_level = true;
1375 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
1376 params.shutdown = true;
1377 v4l2_subdev_call(dev->sd_ir, ir, tx_s_parameters, &params);
29f8a0a5 1378 break;
076f0e35 1379 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
98d109f9 1380 case CX23885_BOARD_TEVII_S470:
fa647f24
AW		 1381 if (!enable_885_ir)
1382 break;
98d109f9
AW		 1383 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1384 if (dev->sd_ir == NULL) {
1385 ret = -ENODEV;
1386 break;
1387 }
1388 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1389 ir_rx_pin_cfg_count, ir_rx_pin_cfg);
98d109f9
AW		 1390 break;
1391 case CX23885_BOARD_HAUPPAUGE_HVR1250:
fa647f24
AW		 1392 if (!enable_885_ir)
1393 break;
98d109f9
AW		 1394 dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_AV_CORE);
1395 if (dev->sd_ir == NULL) {
1396 ret = -ENODEV;
1397 break;
1398 }
1399 v4l2_subdev_call(dev->sd_cx25840, core, s_io_pin_config,
1400 ir_rxtx_pin_cfg_count, ir_rxtx_pin_cfg);
98d109f9 1401 break;
12886871
ST		 1402 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
1403 request_module("ir-kbd-i2c");
1404 break;
a6a3f140
ST		 1405 }
1406
29f8a0a5 1407 return ret;
a6a3f140
ST		 1408}
1409
f59ad611
AW		 1410void cx23885_ir_fini(struct cx23885_dev *dev)
1411{
1412 switch (dev->board) {
9b3d8ecc 1413 case CX23885_BOARD_HAUPPAUGE_HVR1270:
f59ad611 1414 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1415 case CX23885_BOARD_HAUPPAUGE_HVR1290:
dbe83a3b 1416 cx23885_irq_remove(dev, PCI_MSK_IR);
f59ad611
AW		 1417 cx23888_ir_remove(dev);
1418 dev->sd_ir = NULL;
1419 break;
076f0e35 1420 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
98d109f9
AW		 1421 case CX23885_BOARD_TEVII_S470:
1422 case CX23885_BOARD_HAUPPAUGE_HVR1250:
dbe83a3b 1423 cx23885_irq_remove(dev, PCI_MSK_AV_CORE);
98d109f9
AW		 1424 /* sd_ir is a duplicate pointer to the AV Core, just clear it */
1425 dev->sd_ir = NULL;
1426 break;
f59ad611
AW		 1427 }
1428}
1429
78db8547
IL		 1430int netup_jtag_io(void *device, int tms, int tdi, int read_tdo)
1431{
1432 int data;
1433 int tdo = 0;
1434 struct cx23885_dev *dev = (struct cx23885_dev *)device;
1435 /*TMS*/
1436 data = ((cx_read(GP0_IO)) & (~0x00000002));
1437 data |= (tms ? 0x00020002 : 0x00020000);
1438 cx_write(GP0_IO, data);
1439
1440 /*TDI*/
1441 data = ((cx_read(MC417_RWD)) & (~0x0000a000));
1442 data |= (tdi ? 0x00008000 : 0);
1443 cx_write(MC417_RWD, data);
1444 if (read_tdo)
1445 tdo = (data & 0x00004000) ? 1 : 0; /*TDO*/
1446
1447 cx_write(MC417_RWD, data | 0x00002000);
1448 udelay(1);
1449 /*TCK*/
1450 cx_write(MC417_RWD, data);
1451
1452 return tdo;
1453}
1454
f59ad611
AW		 1455void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
1456{
1457 switch (dev->board) {
9b3d8ecc 1458 case CX23885_BOARD_HAUPPAUGE_HVR1270:
f59ad611 1459 case CX23885_BOARD_HAUPPAUGE_HVR1850:
7fec6fee 1460 case CX23885_BOARD_HAUPPAUGE_HVR1290:
dbe83a3b
AW		 1461 if (dev->sd_ir)
1462 cx23885_irq_add_enable(dev, PCI_MSK_IR);
f59ad611 1463 break;
076f0e35 1464 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
98d109f9
AW		 1465 case CX23885_BOARD_TEVII_S470:
1466 case CX23885_BOARD_HAUPPAUGE_HVR1250:
dbe83a3b
AW		 1467 if (dev->sd_ir)
1468 cx23885_irq_add_enable(dev, PCI_MSK_AV_CORE);
98d109f9 1469 break;
f59ad611
AW		 1470 }
1471}
1472
d19770e5
ST		 1473void cx23885_card_setup(struct cx23885_dev *dev)
1474{
a6a3f140
ST		 1475 struct cx23885_tsport *ts1 = &dev->ts1;
1476 struct cx23885_tsport *ts2 = &dev->ts2;
1477
d19770e5
ST		 1478 static u8 eeprom[256];
1479
1480 if (dev->i2c_bus[0].i2c_rc == 0) {
1481 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
44a6481d
MK		 1482 tveeprom_read(&dev->i2c_bus[0].i2c_client,
1483 eeprom, sizeof(eeprom));
d19770e5
ST		 1484 }
1485
1486 switch (dev->board) {
a77743bc 1487 case CX23885_BOARD_HAUPPAUGE_HVR1250:
ebbeb460
AW		 1488 if (dev->i2c_bus[0].i2c_rc == 0) {
1489 if (eeprom[0x80] != 0x84)
1490 hauppauge_eeprom(dev, eeprom+0xc0);
1491 else
1492 hauppauge_eeprom(dev, eeprom+0x80);
1493 }
1494 break;
07b4a835 1495 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1496 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
66762373 1497 case CX23885_BOARD_HAUPPAUGE_HVR1400:
c88133ec
ST		 1498 if (dev->i2c_bus[0].i2c_rc == 0)
1499 hauppauge_eeprom(dev, eeprom+0x80);
1500 break;
d19770e5
ST		 1501 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1502 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1503 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1504 case CX23885_BOARD_HAUPPAUGE_HVR1700:
2074dffa 1505 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1506 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1507 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1508 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1509 case CX23885_BOARD_HAUPPAUGE_HVR1210:
13697380 1510 case CX23885_BOARD_HAUPPAUGE_HVR1850:
aee0b24c 1511 case CX23885_BOARD_HAUPPAUGE_HVR1290:
d19770e5 1512 if (dev->i2c_bus[0].i2c_rc == 0)
c88133ec 1513 hauppauge_eeprom(dev, eeprom+0xc0);
d19770e5
ST		 1514 break;
1515 }
a6a3f140
ST		 1516
1517 switch (dev->board) {
335377b7 1518 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
aef2d186 1519 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
335377b7
MK		 1520 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1521 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1522 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1523 /* break omitted intentionally */
a6a3f140
ST		 1524 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
1525 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1526 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1527 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1528 break;
35045137 1529 case CX23885_BOARD_HAUPPAUGE_HVR1850:
a589b665
ST		 1530 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1531 /* Defaults for VID B - Analog encoder */
1532 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
1533 ts1->gen_ctrl_val = 0x10e;
1534 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1535 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1536
1537 /* APB_TSVALERR_POL (active low)*/
1538 ts1->vld_misc_val = 0x2000;
1539 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
35045137 1540 cx_write(0x130184, 0xc);
a589b665
ST		 1541
1542 /* Defaults for VID C */
1543 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1544 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1545 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
96318d0c
IL		 1546 break;
1547 case CX23885_BOARD_TBS_6920:
09ea33e5
IL		 1548 ts1->gen_ctrl_val = 0x4; /* Parallel */
1549 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1550 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1551 break;
1552 case CX23885_BOARD_TEVII_S470:
7b134e85 1553 case CX23885_BOARD_TEVII_S471:
c9b8b04b 1554 case CX23885_BOARD_DVBWORLD_2005:
f667190b 1555 case CX23885_BOARD_PROF_8000:
96318d0c
IL		 1556 ts1->gen_ctrl_val = 0x5; /* Parallel */
1557 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1558 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
a589b665 1559 break;
5a23b076 1560 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
78db8547 1561 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
722c90eb 1562 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
5a23b076
IL		 1563 ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1564 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1565 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1566 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1567 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1568 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1569 break;
493b7127 1570 case CX23885_BOARD_MYGICA_X8506:
2365b2d3 1571 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
493b7127
DW		 1572 ts1->gen_ctrl_val = 0x5; /* Parallel */
1573 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1574 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1575 break;
ea5697fe
DW		 1576 case CX23885_BOARD_MYGICA_X8558PRO:
1577 ts1->gen_ctrl_val = 0x5; /* Parallel */
1578 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1579 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1580 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1581 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1582 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1583 break;
a6a3f140 1584 case CX23885_BOARD_HAUPPAUGE_HVR1250:
07b4a835 1585 case CX23885_BOARD_HAUPPAUGE_HVR1500:
d1987d55 1586 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
a6a3f140 1587 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
b3ea0166 1588 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1589 case CX23885_BOARD_HAUPPAUGE_HVR1700:
66762373 1590 case CX23885_BOARD_HAUPPAUGE_HVR1400:
4c56b04a 1591 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1592 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1593 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
2074dffa 1594 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1595 case CX23885_BOARD_HAUPPAUGE_HVR1275:
19bc5796 1596 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1597 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
6b926eca 1598 case CX23885_BOARD_HAUPPAUGE_HVR1210:
34e383dd 1599 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
aee0b24c 1600 case CX23885_BOARD_HAUPPAUGE_HVR1290:
9028f58f 1601 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
a6a3f140
ST		 1602 default:
1603 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
1604 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
1605 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
1606 }
1607
ce89cfb4
ST		 1608 /* Certain boards support analog, or require the avcore to be
1609 * loaded, ensure this happens.
1610 */
1611 switch (dev->board) {
fa647f24 1612 case CX23885_BOARD_TEVII_S470:
fa647f24
AW		 1613 /* Currently only enabled for the integrated IR controller */
1614 if (!enable_885_ir)
1615 break;
d214ddc8 1616 case CX23885_BOARD_HAUPPAUGE_HVR1250:
ce89cfb4
ST		 1617 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1618 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
1619 case CX23885_BOARD_HAUPPAUGE_HVR1700:
4c56b04a 1620 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
0cf8af57 1621 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
9bb1b7e8 1622 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
5a23b076 1623 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
78db8547 1624 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
34e383dd 1625 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
0ac60acb
DH		 1626 case CX23885_BOARD_HAUPPAUGE_HVR1255:
1627 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
9b3d8ecc 1628 case CX23885_BOARD_HAUPPAUGE_HVR1270:
c6b7053b 1629 case CX23885_BOARD_HAUPPAUGE_HVR1850:
bc1548ad
DW		 1630 case CX23885_BOARD_MYGICA_X8506:
1631 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
aee0b24c 1632 case CX23885_BOARD_HAUPPAUGE_HVR1290:
0b32d65c 1633 case CX23885_BOARD_LEADTEK_WINFAST_PXTV1200:
9028f58f 1634 case CX23885_BOARD_GOTVIEW_X5_3D_HYBRID:
18d64476 1635 case CX23885_BOARD_HAUPPAUGE_HVR1500:
2cb9ccd4 1636 case CX23885_BOARD_MPX885:
87988753 1637 case CX23885_BOARD_MYGICA_X8507:
722c90eb 1638 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
e6574f2f
HV		 1639 dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
1640 &dev->i2c_bus[2].i2c_adap,
9a1f8b34 1641 "cx25840", 0x88 >> 1, NULL);
d6b1850d
AW		 1642 if (dev->sd_cx25840) {
1643 dev->sd_cx25840->grp_id = CX23885_HW_AV_CORE;
1644 v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
1645 }
ce89cfb4
ST		 1646 break;
1647 }
5a23b076
IL		 1648
1649 /* AUX-PLL 27MHz CLK */
1650 switch (dev->board) {
1651 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1652 netup_initialize(dev);
1653 break;
78db8547
IL		 1654 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1655 int ret;
1656 const struct firmware *fw;
1657 const char *filename = "dvb-netup-altera-01.fw";
1658 char *action = "configure";
b8f0d306 1659 static struct netup_card_info cinfo;
78db8547
IL		 1660 struct altera_config netup_config = {
1661 .dev = dev,
1662 .action = action,
1663 .jtag_io = netup_jtag_io,
1664 };
1665
1666 netup_initialize(dev);
1667
b8f0d306 1668 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
2d12421d
AO		 1669 if (netup_card_rev)
1670 cinfo.rev = netup_card_rev;
1671
b8f0d306
AO		 1672 switch (cinfo.rev) {
1673 case 0x4:
1674 filename = "dvb-netup-altera-04.fw";
1675 break;
1676 default:
1677 filename = "dvb-netup-altera-01.fw";
1678 break;
1679 }
1680 printk(KERN_INFO "NetUP card rev=0x%x fw_filename=%s\n",
1681 cinfo.rev, filename);
1682
78db8547
IL		 1683 ret = request_firmware(&fw, filename, &dev->pci->dev);
1684 if (ret != 0)
1685 printk(KERN_ERR "did not find the firmware file. (%s) "
1686 "Please see linux/Documentation/dvb/ for more details "
1687 "on firmware-problems.", filename);
1688 else
1689 altera_init(&netup_config, fw);
1690
3f84a4e1 1691 release_firmware(fw);
78db8547
IL		 1692 break;
1693 }
5a23b076 1694 }
d19770e5
ST		 1695}
1696
1697/* ------------------------------------------------------------------ */
Linux kernel - Deliverables
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