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Merge tag 'mmc-merge-for-3.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
ST		 46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
5a23b076
IL		 51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
5a23b076 54#include "cimax2.h"
493b7127 55#include "lgs8gxx.h"
5a23b076
IL		 56#include "netup-eeprom.h"
57#include "netup-init.h"
a5dbf457 58#include "lgdt3305.h"
ea5697fe 59#include "atbm8830.h"
09ea33e5
IL		 60#include "ds3000.h"
61#include "cx23885-f300.h"
78db8547
IL		 62#include "altera-ci.h"
63#include "stv0367.h"
722c90eb
SR		 64#include "drxk.h"
65#include "mt2063.h"
f667190b
MB		 66#include "stv090x.h"
67#include "stb6100.h"
68#include "stb6100_cfg.h"
d19770e5 69
4513fc69 70static unsigned int debug;
d19770e5 71
4513fc69
ST		 72#define dprintk(level, fmt, arg...)\
73 do { if (debug >= level)\
74 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
75 } while (0)
d19770e5
ST		 76
77/* ------------------------------------------------------------------ */
78
3ba71d21
MK		 79static unsigned int alt_tuner;
80module_param(alt_tuner, int, 0644);
81MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
82
78e92006
JG		 83DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
84
3ba71d21
MK		 85/* ------------------------------------------------------------------ */
86
d19770e5
ST		 87static int dvb_buf_setup(struct videobuf_queue *q,
88 unsigned int *count, unsigned int *size)
89{
90 struct cx23885_tsport *port = q->priv_data;
91
92 port->ts_packet_size = 188 * 4;
93 port->ts_packet_count = 32;
94
95 *size = port->ts_packet_size * port->ts_packet_count;
96 *count = 32;
97 return 0;
98}
99
44a6481d
MK		 100static int dvb_buf_prepare(struct videobuf_queue *q,
101 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 102{
103 struct cx23885_tsport *port = q->priv_data;
9c8ced51 104 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 105}
106
107static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
108{
109 struct cx23885_tsport *port = q->priv_data;
9c8ced51 110 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 111}
112
44a6481d
MK		 113static void dvb_buf_release(struct videobuf_queue *q,
114 struct videobuf_buffer *vb)
d19770e5 115{
9c8ced51 116 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 117}
118
a7d44baa
MCC		 119static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
120
78db8547
IL		 121static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
122{
123 struct videobuf_dvb_frontends *f;
124 struct videobuf_dvb_frontend *fe;
125
126 f = &port->frontends;
127
128 if (f->gate <= 1) /* undefined or fe0 */
129 fe = videobuf_dvb_get_frontend(f, 1);
130 else
131 fe = videobuf_dvb_get_frontend(f, f->gate);
132
133 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
134 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
a7d44baa
MCC		 135
136 /*
137 * FIXME: Improve this path to avoid calling the
138 * cx23885_dvb_set_frontend() every time it passes here.
139 */
140 cx23885_dvb_set_frontend(fe->dvb.frontend);
78db8547
IL		 141}
142
d19770e5
ST		 143static struct videobuf_queue_ops dvb_qops = {
144 .buf_setup = dvb_buf_setup,
145 .buf_prepare = dvb_buf_prepare,
146 .buf_queue = dvb_buf_queue,
147 .buf_release = dvb_buf_release,
148};
149
86184e06 150static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 151 .demod_address = 0x32 >> 1,
152 .output_mode = S5H1409_SERIAL_OUTPUT,
153 .gpio = S5H1409_GPIO_ON,
2b03238a 154 .qam_if = 44000,
fc959bef 155 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 156 .status_mode = S5H1409_DEMODLOCKING,
157 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 158};
159
b3ea0166
ST		 160static struct tda10048_config hauppauge_hvr1200_config = {
161 .demod_address = 0x10 >> 1,
162 .output_mode = TDA10048_SERIAL_OUTPUT,
163 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 164 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 165 .dtv6_if_freq_khz = TDA10048_IF_3300,
166 .dtv7_if_freq_khz = TDA10048_IF_3800,
167 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 168 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 169};
170
6b926eca
MK		 171static struct tda10048_config hauppauge_hvr1210_config = {
172 .demod_address = 0x10 >> 1,
173 .output_mode = TDA10048_SERIAL_OUTPUT,
174 .fwbulkwritelen = TDA10048_BULKWRITE_200,
175 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 176 .dtv6_if_freq_khz = TDA10048_IF_3300,
177 .dtv7_if_freq_khz = TDA10048_IF_3500,
178 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 179 .clk_freq_khz = TDA10048_CLK_16000,
180};
181
3ba71d21
MK		 182static struct s5h1409_config hauppauge_ezqam_config = {
183 .demod_address = 0x32 >> 1,
184 .output_mode = S5H1409_SERIAL_OUTPUT,
185 .gpio = S5H1409_GPIO_OFF,
186 .qam_if = 4000,
187 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 188 .status_mode = S5H1409_DEMODLOCKING,
189 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 190};
191
fc959bef 192static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 193 .demod_address = 0x32 >> 1,
194 .output_mode = S5H1409_SERIAL_OUTPUT,
195 .gpio = S5H1409_GPIO_OFF,
2b03238a 196 .qam_if = 44000,
fe475163 197 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 198 .status_mode = S5H1409_DEMODLOCKING,
199 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 200};
201
07b4a835
MK		 202static struct s5h1409_config hauppauge_hvr1500_config = {
203 .demod_address = 0x32 >> 1,
204 .output_mode = S5H1409_SERIAL_OUTPUT,
205 .gpio = S5H1409_GPIO_OFF,
206 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 207 .status_mode = S5H1409_DEMODLOCKING,
208 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 209};
210
86184e06 211static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 212 0x61
213};
214
9bc37caa
MK		 215static struct lgdt330x_config fusionhdtv_5_express = {
216 .demod_address = 0x0e,
217 .demod_chip = LGDT3303,
218 .serial_mpeg = 0x40,
219};
220
d1987d55
ST		 221static struct s5h1409_config hauppauge_hvr1500q_config = {
222 .demod_address = 0x32 >> 1,
223 .output_mode = S5H1409_SERIAL_OUTPUT,
224 .gpio = S5H1409_GPIO_ON,
225 .qam_if = 44000,
226 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 227 .status_mode = S5H1409_DEMODLOCKING,
228 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 229};
230
335377b7
MK		 231static struct s5h1409_config dvico_s5h1409_config = {
232 .demod_address = 0x32 >> 1,
233 .output_mode = S5H1409_SERIAL_OUTPUT,
234 .gpio = S5H1409_GPIO_ON,
235 .qam_if = 44000,
236 .inversion = S5H1409_INVERSION_OFF,
237 .status_mode = S5H1409_DEMODLOCKING,
238 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
239};
240
52b50450
MK		 241static struct s5h1411_config dvico_s5h1411_config = {
242 .output_mode = S5H1411_SERIAL_OUTPUT,
243 .gpio = S5H1411_GPIO_ON,
244 .qam_if = S5H1411_IF_44000,
245 .vsb_if = S5H1411_IF_44000,
246 .inversion = S5H1411_INVERSION_OFF,
247 .status_mode = S5H1411_DEMODLOCKING,
248 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
249};
250
19bc5796
MK		 251static struct s5h1411_config hcw_s5h1411_config = {
252 .output_mode = S5H1411_SERIAL_OUTPUT,
253 .gpio = S5H1411_GPIO_OFF,
254 .vsb_if = S5H1411_IF_44000,
255 .qam_if = S5H1411_IF_4000,
256 .inversion = S5H1411_INVERSION_ON,
257 .status_mode = S5H1411_DEMODLOCKING,
258 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
259};
260
d1987d55 261static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 262 .i2c_address = 0x61,
263 .if_khz = 5380,
d1987d55
ST		 264};
265
335377b7
MK		 266static struct xc5000_config dvico_xc5000_tunerconfig = {
267 .i2c_address = 0x64,
268 .if_khz = 5380,
335377b7
MK		 269};
270
4041f1a5
MK		 271static struct tda829x_config tda829x_no_probe = {
272 .probe_tuner = TDA829X_DONT_PROBE,
273};
274
f21e0d7f 275static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 276 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
277 .if_lvl = 6, .rfagc_top = 0x37 },
278 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
279 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 280};
281
b34cdc36
MK		 282static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
283 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
284 .if_lvl = 1, .rfagc_top = 0x37, },
285 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
286 .if_lvl = 1, .rfagc_top = 0x37, },
287 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
288 .if_lvl = 1, .rfagc_top = 0x37, },
289};
290
f21e0d7f
MK		 291static struct tda18271_config hauppauge_tda18271_config = {
292 .std_map = &hauppauge_tda18271_std_map,
293 .gate = TDA18271_GATE_ANALOG,
04a68baa 294 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 295};
296
b3ea0166 297static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 298 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 299 .gate = TDA18271_GATE_ANALOG,
04a68baa 300 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 301};
302
6b926eca
MK		 303static struct tda18271_config hauppauge_hvr1210_tuner_config = {
304 .gate = TDA18271_GATE_DIGITAL,
04a68baa 305 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 306};
307
247bc540 308static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 309 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
310 .if_lvl = 1, .rfagc_top = 0x58 },
311 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
312 .if_lvl = 1, .rfagc_top = 0x58 },
313};
314
247bc540
MK		 315static struct tda18271_config hauppauge_hvr127x_config = {
316 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 317 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 318};
319
247bc540 320static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 321 .i2c_addr = 0x0e,
322 .mpeg_mode = LGDT3305_MPEG_SERIAL,
323 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
324 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
325 .deny_i2c_rptr = 1,
326 .spectral_inversion = 1,
327 .qam_if_khz = 4000,
328 .vsb_if_khz = 3250,
329};
330
b1721d0d 331static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 332 BAND_VHF | BAND_UHF, /* band_caps */
333
334 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
335 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
336 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
337 * P_agc_nb_est=2, P_agc_write=0
338 */
339 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
340 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
341
342 712, /* inv_gain */
343 21, /* time_stabiliz */
344
345 0, /* alpha_level */
346 118, /* thlock */
347
348 0, /* wbd_inv */
349 2867, /* wbd_ref */
350 0, /* wbd_sel */
351 2, /* wbd_alpha */
352
353 0, /* agc1_max */
354 0, /* agc1_min */
355 39718, /* agc2_max */
356 9930, /* agc2_min */
357 0, /* agc1_pt1 */
358 0, /* agc1_pt2 */
359 0, /* agc1_pt3 */
360 0, /* agc1_slope1 */
361 0, /* agc1_slope2 */
362 0, /* agc2_pt1 */
363 128, /* agc2_pt2 */
364 29, /* agc2_slope1 */
365 29, /* agc2_slope2 */
366
367 17, /* alpha_mant */
368 27, /* alpha_exp */
369 23, /* beta_mant */
370 51, /* beta_exp */
371
372 1, /* perform_agc_softsplit */
373};
374
375/* PLL Configuration for COFDM BW_MHz = 8.000000
376 * With external clock = 30.000000 */
b1721d0d 377static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 378 60000, /* internal */
379 30000, /* sampling */
380 1, /* pll_cfg: prediv */
381 8, /* pll_cfg: ratio */
382 3, /* pll_cfg: range */
383 1, /* pll_cfg: reset */
384 0, /* pll_cfg: bypass */
385 0, /* misc: refdiv */
386 0, /* misc: bypclk_div */
387 1, /* misc: IO_CLK_en_core */
388 1, /* misc: ADClkSrc */
389 0, /* misc: modulo */
390 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
391 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
392 20452225, /* timf */
393 30000000 /* xtal_hz */
394};
395
396static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
397 .output_mpeg2_in_188_bytes = 1,
398 .hostbus_diversity = 1,
399 .tuner_is_baseband = 0,
400 .update_lna = NULL,
401
402 .agc_config_count = 1,
403 .agc = &xc3028_agc_config,
404 .bw = &xc3028_bw_config,
405
406 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
407 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
408 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
409
410 .pwm_freq_div = 0,
411 .agc_control = NULL,
412 .spur_protect = 0,
413
414 .output_mode = OUTMODE_MPEG2_SERIAL,
415};
416
aef2d186
ST		 417static struct zl10353_config dvico_fusionhdtv_xc3028 = {
418 .demod_address = 0x0f,
419 .if2 = 45600,
420 .no_tuner = 1,
d4dc673d 421 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 422};
423
f867c3f4
IL		 424static struct stv0900_reg stv0900_ts_regs[] = {
425 { R0900_TSGENERAL, 0x00 },
426 { R0900_P1_TSSPEED, 0x40 },
427 { R0900_P2_TSSPEED, 0x40 },
428 { R0900_P1_TSCFGM, 0xc0 },
429 { R0900_P2_TSCFGM, 0xc0 },
430 { R0900_P1_TSCFGH, 0xe0 },
431 { R0900_P2_TSCFGH, 0xe0 },
432 { R0900_P1_TSCFGL, 0x20 },
433 { R0900_P2_TSCFGL, 0x20 },
434 { 0xffff, 0xff }, /* terminate */
435};
436
5a23b076
IL		 437static struct stv0900_config netup_stv0900_config = {
438 .demod_address = 0x68,
29372a8d 439 .demod_mode = 1, /* dual */
644c7ef0 440 .xtal = 8000000,
5a23b076
IL		 441 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
442 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 443 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 444 .tun1_maddress = 0,/* 0x60 */
445 .tun2_maddress = 3,/* 0x63 */
446 .tun1_adc = 1,/* 1 Vpp */
447 .tun2_adc = 1,/* 1 Vpp */
448};
449
450static struct stv6110_config netup_stv6110_tunerconfig_a = {
451 .i2c_address = 0x60,
644c7ef0
AO		 452 .mclk = 16000000,
453 .clk_div = 1,
873688cd 454 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 455};
456
457static struct stv6110_config netup_stv6110_tunerconfig_b = {
458 .i2c_address = 0x63,
644c7ef0
AO		 459 .mclk = 16000000,
460 .clk_div = 1,
873688cd 461 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 462};
463
96318d0c 464static struct cx24116_config tbs_cx24116_config = {
09ea33e5 465 .demod_address = 0x55,
96318d0c
IL		 466};
467
09ea33e5
IL		 468static struct ds3000_config tevii_ds3000_config = {
469 .demod_address = 0x68,
579943f5
IL		 470};
471
c9b8b04b
IL		 472static struct cx24116_config dvbworld_cx24116_config = {
473 .demod_address = 0x05,
474};
475
493b7127
DW		 476static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
477 .prod = LGS8GXX_PROD_LGS8GL5,
478 .demod_address = 0x19,
479 .serial_ts = 0,
480 .ts_clk_pol = 1,
481 .ts_clk_gated = 1,
482 .if_clk_freq = 30400, /* 30.4 MHz */
483 .if_freq = 5380, /* 5.38 MHz */
484 .if_neg_center = 1,
485 .ext_adc = 0,
486 .adc_signed = 0,
487 .if_neg_edge = 0,
488};
489
490static struct xc5000_config mygica_x8506_xc5000_config = {
491 .i2c_address = 0x61,
492 .if_khz = 5380,
493};
494
f667190b
MB		 495static struct stv090x_config prof_8000_stv090x_config = {
496 .device = STV0903,
497 .demod_mode = STV090x_SINGLE,
498 .clk_mode = STV090x_CLK_EXT,
499 .xtal = 27000000,
500 .address = 0x6A,
501 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
502 .repeater_level = STV090x_RPTLEVEL_64,
503 .adc1_range = STV090x_ADC_2Vpp,
504 .diseqc_envelope_mode = false,
505
506 .tuner_get_frequency = stb6100_get_frequency,
507 .tuner_set_frequency = stb6100_set_frequency,
508 .tuner_set_bandwidth = stb6100_set_bandwidth,
509 .tuner_get_bandwidth = stb6100_get_bandwidth,
510};
511
512static struct stb6100_config prof_8000_stb6100_config = {
513 .tuner_address = 0x60,
514 .refclock = 27000000,
515};
516
517static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
518{
519 struct cx23885_tsport *port = fe->dvb->priv;
520 struct cx23885_dev *dev = port->dev;
521
522 if (voltage == SEC_VOLTAGE_18)
523 cx_write(MC417_RWD, 0x00001e00);
524 else if (voltage == SEC_VOLTAGE_13)
525 cx_write(MC417_RWD, 0x00001a00);
526 else
527 cx_write(MC417_RWD, 0x00001800);
528 return 0;
529}
530
a7d44baa 531static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 532{
a7d44baa 533 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK		 534 struct cx23885_tsport *port = fe->dvb->priv;
535 struct cx23885_dev *dev = port->dev;
536
537 switch (dev->board) {
538 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 539 switch (p->modulation) {
f35b9e80
MK		 540 case VSB_8:
541 cx23885_gpio_clear(dev, GPIO_5);
542 break;
543 case QAM_64:
544 case QAM_256:
545 default:
546 cx23885_gpio_set(dev, GPIO_5);
547 break;
548 }
549 break;
6f0d8c02
DW		 550 case CX23885_BOARD_MYGICA_X8506:
551 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
552 /* Select Digital TV */
553 cx23885_gpio_set(dev, GPIO_0);
554 break;
f35b9e80 555 }
5bdd3962 556 return 0;
f35b9e80
MK		 557}
558
2365b2d3
DW		 559static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
560 .prod = LGS8GXX_PROD_LGS8G75,
561 .demod_address = 0x19,
562 .serial_ts = 0,
563 .ts_clk_pol = 1,
564 .ts_clk_gated = 1,
565 .if_clk_freq = 30400, /* 30.4 MHz */
566 .if_freq = 6500, /* 6.50 MHz */
567 .if_neg_center = 1,
568 .ext_adc = 0,
569 .adc_signed = 1,
570 .adc_vpp = 2, /* 1.6 Vpp */
571 .if_neg_edge = 1,
572};
573
574static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
575 .i2c_address = 0x61,
576 .if_khz = 6500,
577};
578
ea5697fe
DW		 579static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
580 .prod = ATBM8830_PROD_8830,
581 .demod_address = 0x44,
582 .serial_ts = 0,
583 .ts_sampling_edge = 1,
584 .ts_clk_gated = 0,
585 .osc_clk_freq = 30400, /* in kHz */
586 .if_freq = 0, /* zero IF */
587 .zif_swap_iq = 1,
c245c75c
DW		 588 .agc_min = 0x2E,
589 .agc_max = 0xFF,
590 .agc_hold_loop = 0,
ea5697fe
DW		 591};
592
593static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
594 .i2c_address = 0x60,
595 .osc_clk = 20
596};
597
598static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
599 .prod = ATBM8830_PROD_8830,
600 .demod_address = 0x44,
601 .serial_ts = 1,
602 .ts_sampling_edge = 1,
603 .ts_clk_gated = 0,
604 .osc_clk_freq = 30400, /* in kHz */
605 .if_freq = 0, /* zero IF */
606 .zif_swap_iq = 1,
c245c75c
DW		 607 .agc_min = 0x2E,
608 .agc_max = 0xFF,
609 .agc_hold_loop = 0,
ea5697fe
DW		 610};
611
612static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
613 .i2c_address = 0x60,
614 .osc_clk = 20
615};
78db8547
IL		 616static struct stv0367_config netup_stv0367_config[] = {
617 {
618 .demod_address = 0x1c,
619 .xtal = 27000000,
620 .if_khz = 4500,
621 .if_iq_mode = 0,
622 .ts_mode = 1,
623 .clk_pol = 0,
624 }, {
625 .demod_address = 0x1d,
626 .xtal = 27000000,
627 .if_khz = 4500,
628 .if_iq_mode = 0,
629 .ts_mode = 1,
630 .clk_pol = 0,
631 },
632};
633
634static struct xc5000_config netup_xc5000_config[] = {
635 {
636 .i2c_address = 0x61,
637 .if_khz = 4500,
638 }, {
639 .i2c_address = 0x64,
640 .if_khz = 4500,
641 },
642};
643
722c90eb
SR		 644static struct drxk_config terratec_drxk_config[] = {
645 {
646 .adr = 0x29,
647 .no_i2c_bridge = 1,
648 }, {
649 .adr = 0x2a,
650 .no_i2c_bridge = 1,
651 },
652};
653
654static struct mt2063_config terratec_mt2063_config[] = {
655 {
656 .tuner_address = 0x60,
657 }, {
658 .tuner_address = 0x67,
659 },
660};
661
78db8547
IL		 662int netup_altera_fpga_rw(void *device, int flag, int data, int read)
663{
664 struct cx23885_dev *dev = (struct cx23885_dev *)device;
665 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 666 uint32_t mem = 0;
78db8547 667
d164460f 668 mem = cx_read(MC417_RWD);
78db8547
IL		 669 if (read)
670 cx_set(MC417_OEN, ALT_DATA);
671 else {
672 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL		 673 mem &= ~ALT_DATA;
674 mem |= (data & ALT_DATA);
78db8547
IL		 675 }
676
677 if (flag)
d164460f 678 mem |= ALT_AD_RG;
78db8547 679 else
d164460f 680 mem &= ~ALT_AD_RG;
78db8547 681
d164460f 682 mem &= ~ALT_CS;
78db8547 683 if (read)
d164460f 684 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 685 else
d164460f
AO		 686 mem = (mem & ~ALT_WR) | ALT_RD;
687
688 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL		 689
690 for (;;) {
691 mem = cx_read(MC417_RWD);
692 if ((mem & ALT_RDY) == 0)
693 break;
694 if (time_after(jiffies, timeout))
695 break;
696 udelay(1);
697 }
698
699 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
700 if (read)
701 return mem & ALT_DATA;
702
703 return 0;
704};
ea5697fe 705
d19770e5
ST		 706static int dvb_register(struct cx23885_tsport *port)
707{
708 struct cx23885_dev *dev = port->dev;
493b7127 709 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL		 710 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
711 int mfe_shared = 0; /* bus not shared by default */
5a23b076 712 int ret;
363c35fc 713
f972e0bd 714 /* Get the first frontend */
92abe9ee 715 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 716 if (!fe0)
717 return -EINVAL;
d19770e5
ST		 718
719 /* init struct videobuf_dvb */
363c35fc 720 fe0->dvb.name = dev->name;
d19770e5 721
78db8547
IL		 722 /* multi-frontend gate control is undefined or defaults to fe0 */
723 port->frontends.gate = 0;
724
725 /* Sets the gate control callback to be used by i2c command calls */
726 port->gate_ctrl = cx23885_dvb_gate_ctrl;
727
d19770e5
ST		 728 /* init frontend */
729 switch (dev->board) {
a77743bc 730 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 731 i2c_bus = &dev->i2c_bus[0];
363c35fc 732 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 733 &hauppauge_generic_config,
f139fa71 734 &i2c_bus->i2c_adap);
363c35fc
ST		 735 if (fe0->dvb.frontend != NULL) {
736 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 737 &i2c_bus->i2c_adap,
86184e06 738 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 739 }
740 break;
a5dbf457 741 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 742 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 743 i2c_bus = &dev->i2c_bus[0];
744 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 745 &hauppauge_lgdt3305_config,
a5dbf457
MK		 746 &i2c_bus->i2c_adap);
747 if (fe0->dvb.frontend != NULL) {
748 dvb_attach(tda18271_attach, fe0->dvb.frontend,
749 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 750 &hauppauge_hvr127x_config);
a5dbf457
MK		 751 }
752 break;
19bc5796 753 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 754 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK		 755 i2c_bus = &dev->i2c_bus[0];
756 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
757 &hcw_s5h1411_config,
758 &i2c_bus->i2c_adap);
759 if (fe0->dvb.frontend != NULL) {
760 dvb_attach(tda18271_attach, fe0->dvb.frontend,
761 0x60, &dev->i2c_bus[1].i2c_adap,
762 &hauppauge_tda18271_config);
763 }
0ac60acb
DH		 764
765 tda18271_attach(&dev->ts1.analog_fe,
766 0x60, &dev->i2c_bus[1].i2c_adap,
767 &hauppauge_tda18271_config);
768
19bc5796 769 break;
3ba71d21
MK		 770 case CX23885_BOARD_HAUPPAUGE_HVR1800:
771 i2c_bus = &dev->i2c_bus[0];
92abe9ee 772 switch (alt_tuner) {
3ba71d21 773 case 1:
363c35fc 774 fe0->dvb.frontend =
3ba71d21
MK		 775 dvb_attach(s5h1409_attach,
776 &hauppauge_ezqam_config,
777 &i2c_bus->i2c_adap);
363c35fc
ST		 778 if (fe0->dvb.frontend != NULL) {
779 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 780 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 781 &tda829x_no_probe);
363c35fc 782 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 783 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 784 &hauppauge_tda18271_config);
3ba71d21
MK		 785 }
786 break;
787 case 0:
788 default:
363c35fc 789 fe0->dvb.frontend =
3ba71d21
MK		 790 dvb_attach(s5h1409_attach,
791 &hauppauge_generic_config,
792 &i2c_bus->i2c_adap);
363c35fc
ST		 793 if (fe0->dvb.frontend != NULL)
794 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 795 &i2c_bus->i2c_adap,
796 &hauppauge_generic_tunerconfig, 0);
797 break;
798 }
799 break;
fc959bef 800 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 801 i2c_bus = &dev->i2c_bus[0];
363c35fc 802 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 803 &hauppauge_hvr1800lp_config,
f139fa71 804 &i2c_bus->i2c_adap);
363c35fc
ST		 805 if (fe0->dvb.frontend != NULL) {
806 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 807 &i2c_bus->i2c_adap,
fc959bef
ST		 808 &hauppauge_generic_tunerconfig, 0);
809 }
810 break;
9bc37caa 811 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 812 i2c_bus = &dev->i2c_bus[0];
363c35fc 813 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 814 &fusionhdtv_5_express,
f139fa71 815 &i2c_bus->i2c_adap);
363c35fc
ST		 816 if (fe0->dvb.frontend != NULL) {
817 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 818 &i2c_bus->i2c_adap, 0x61,
819 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 820 }
821 break;
d1987d55
ST		 822 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
823 i2c_bus = &dev->i2c_bus[1];
363c35fc 824 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 825 &hauppauge_hvr1500q_config,
826 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 827 if (fe0->dvb.frontend != NULL)
828 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 829 &i2c_bus->i2c_adap,
830 &hauppauge_hvr1500q_tunerconfig);
d1987d55 831 break;
07b4a835
MK		 832 case CX23885_BOARD_HAUPPAUGE_HVR1500:
833 i2c_bus = &dev->i2c_bus[1];
363c35fc 834 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 835 &hauppauge_hvr1500_config,
836 &dev->i2c_bus[0].i2c_adap);
363c35fc 837 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 838 struct dvb_frontend *fe;
839 struct xc2028_config cfg = {
840 .i2c_adap = &i2c_bus->i2c_adap,
841 .i2c_addr = 0x61,
07b4a835
MK		 842 };
843 static struct xc2028_ctrl ctl = {
ef80bfeb 844 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 845 .max_len = 64,
52c3d29c 846 .demod = XC3028_FE_OREN538,
07b4a835
MK		 847 };
848
849 fe = dvb_attach(xc2028_attach,
363c35fc 850 fe0->dvb.frontend, &cfg);
07b4a835
MK		 851 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
852 fe->ops.tuner_ops.set_config(fe, &ctl);
853 }
854 break;
b3ea0166 855 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 856 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 857 i2c_bus = &dev->i2c_bus[0];
363c35fc 858 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 859 &hauppauge_hvr1200_config,
860 &i2c_bus->i2c_adap);
363c35fc
ST		 861 if (fe0->dvb.frontend != NULL) {
862 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 863 &dev->i2c_bus[1].i2c_adap, 0x42,
864 &tda829x_no_probe);
363c35fc 865 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 866 0x60, &dev->i2c_bus[1].i2c_adap,
867 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 868 }
869 break;
870 case CX23885_BOARD_HAUPPAUGE_HVR1210:
871 i2c_bus = &dev->i2c_bus[0];
872 fe0->dvb.frontend = dvb_attach(tda10048_attach,
873 &hauppauge_hvr1210_config,
874 &i2c_bus->i2c_adap);
875 if (fe0->dvb.frontend != NULL) {
876 dvb_attach(tda18271_attach, fe0->dvb.frontend,
877 0x60, &dev->i2c_bus[1].i2c_adap,
878 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 879 }
880 break;
66762373
ST		 881 case CX23885_BOARD_HAUPPAUGE_HVR1400:
882 i2c_bus = &dev->i2c_bus[0];
363c35fc 883 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 884 &i2c_bus->i2c_adap,
885 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 886 if (fe0->dvb.frontend != NULL) {
66762373
ST		 887 struct dvb_frontend *fe;
888 struct xc2028_config cfg = {
889 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
890 .i2c_addr = 0x64,
66762373
ST		 891 };
892 static struct xc2028_ctrl ctl = {
ef80bfeb 893 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 894 .max_len = 64,
9bed77ee 895 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST		 896 /* This is true for all demods with
897 v36 firmware? */
0975fc68 898 .type = XC2028_D2633,
66762373
ST		 899 };
900
901 fe = dvb_attach(xc2028_attach,
363c35fc 902 fe0->dvb.frontend, &cfg);
66762373
ST		 903 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
904 fe->ops.tuner_ops.set_config(fe, &ctl);
905 }
906 break;
335377b7
MK		 907 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
908 i2c_bus = &dev->i2c_bus[port->nr - 1];
909
363c35fc 910 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 911 &dvico_s5h1409_config,
912 &i2c_bus->i2c_adap);
363c35fc
ST		 913 if (fe0->dvb.frontend == NULL)
914 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 915 &dvico_s5h1411_config,
916 &i2c_bus->i2c_adap);
363c35fc
ST		 917 if (fe0->dvb.frontend != NULL)
918 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 919 &i2c_bus->i2c_adap,
920 &dvico_xc5000_tunerconfig);
335377b7 921 break;
aef2d186
ST		 922 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
923 i2c_bus = &dev->i2c_bus[port->nr - 1];
924
363c35fc 925 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 926 &dvico_fusionhdtv_xc3028,
927 &i2c_bus->i2c_adap);
363c35fc 928 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 929 struct dvb_frontend *fe;
930 struct xc2028_config cfg = {
931 .i2c_adap = &i2c_bus->i2c_adap,
932 .i2c_addr = 0x61,
aef2d186
ST		 933 };
934 static struct xc2028_ctrl ctl = {
ef80bfeb 935 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 936 .max_len = 64,
937 .demod = XC3028_FE_ZARLINK456,
938 };
939
363c35fc 940 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 941 &cfg);
942 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
943 fe->ops.tuner_ops.set_config(fe, &ctl);
944 }
945 break;
946 }
4c56b04a 947 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 948 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 949 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 950 i2c_bus = &dev->i2c_bus[0];
951
363c35fc 952 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 953 &dvico_fusionhdtv_xc3028,
954 &i2c_bus->i2c_adap);
363c35fc 955 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 956 struct dvb_frontend *fe;
957 struct xc2028_config cfg = {
958 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
959 .i2c_addr = 0x61,
4c56b04a
ST		 960 };
961 static struct xc2028_ctrl ctl = {
ef80bfeb 962 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 963 .max_len = 64,
964 .demod = XC3028_FE_ZARLINK456,
965 };
966
363c35fc 967 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 968 &cfg);
969 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
970 fe->ops.tuner_ops.set_config(fe, &ctl);
971 }
96318d0c 972 break;
0cf8af57 973 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
974 i2c_bus = &dev->i2c_bus[0];
975
976 fe0->dvb.frontend = dvb_attach(zl10353_attach,
977 &dvico_fusionhdtv_xc3028,
978 &i2c_bus->i2c_adap);
979 if (fe0->dvb.frontend != NULL) {
980 struct dvb_frontend *fe;
981 struct xc4000_config cfg = {
982 .i2c_address = 0x61,
983 .default_pm = 0,
984 .dvb_amplitude = 134,
985 .set_smoothedcvbs = 1,
986 .if_khz = 4560
987 };
988
989 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
990 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS		 991 if (!fe) {
992 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
993 dev->name);
994 goto frontend_detach;
995 }
0cf8af57 996 }
997 break;
96318d0c 998 case CX23885_BOARD_TBS_6920:
09ea33e5 999 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL		 1000
1001 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL		 1002 &tbs_cx24116_config,
1003 &i2c_bus->i2c_adap);
96318d0c 1004 if (fe0->dvb.frontend != NULL)
09ea33e5 1005 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1006
579943f5
IL		 1007 break;
1008 case CX23885_BOARD_TEVII_S470:
1009 i2c_bus = &dev->i2c_bus[1];
1010
09ea33e5
IL		 1011 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1012 &tevii_ds3000_config,
1013 &i2c_bus->i2c_adap);
579943f5 1014 if (fe0->dvb.frontend != NULL)
09ea33e5 1015 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
579943f5 1016
4c56b04a 1017 break;
c9b8b04b
IL		 1018 case CX23885_BOARD_DVBWORLD_2005:
1019 i2c_bus = &dev->i2c_bus[1];
1020
1021 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1022 &dvbworld_cx24116_config,
1023 &i2c_bus->i2c_adap);
1024 break;
5a23b076
IL		 1025 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1026 i2c_bus = &dev->i2c_bus[0];
1027 switch (port->nr) {
1028 /* port B */
1029 case 1:
1030 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1031 &netup_stv0900_config,
1032 &i2c_bus->i2c_adap, 0);
1033 if (fe0->dvb.frontend != NULL) {
1034 if (dvb_attach(stv6110_attach,
1035 fe0->dvb.frontend,
1036 &netup_stv6110_tunerconfig_a,
1037 &i2c_bus->i2c_adap)) {
1038 if (!dvb_attach(lnbh24_attach,
1039 fe0->dvb.frontend,
1040 &i2c_bus->i2c_adap,
9329fb5b
AO		 1041 LNBH24_PCL | LNBH24_TTX,
1042 LNBH24_TEN, 0x09))
5a23b076
IL		 1043 printk(KERN_ERR
1044 "No LNBH24 found!\n");
1045
1046 }
1047 }
1048 break;
1049 /* port C */
1050 case 2:
1051 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1052 &netup_stv0900_config,
1053 &i2c_bus->i2c_adap, 1);
1054 if (fe0->dvb.frontend != NULL) {
1055 if (dvb_attach(stv6110_attach,
1056 fe0->dvb.frontend,
1057 &netup_stv6110_tunerconfig_b,
1058 &i2c_bus->i2c_adap)) {
1059 if (!dvb_attach(lnbh24_attach,
1060 fe0->dvb.frontend,
1061 &i2c_bus->i2c_adap,
9329fb5b
AO		 1062 LNBH24_PCL | LNBH24_TTX,
1063 LNBH24_TEN, 0x0a))
5a23b076
IL		 1064 printk(KERN_ERR
1065 "No LNBH24 found!\n");
1066
1067 }
1068 }
1069 break;
1070 }
1071 break;
493b7127
DW		 1072 case CX23885_BOARD_MYGICA_X8506:
1073 i2c_bus = &dev->i2c_bus[0];
1074 i2c_bus2 = &dev->i2c_bus[1];
1075 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1076 &mygica_x8506_lgs8gl5_config,
1077 &i2c_bus->i2c_adap);
1078 if (fe0->dvb.frontend != NULL) {
1079 dvb_attach(xc5000_attach,
1080 fe0->dvb.frontend,
1081 &i2c_bus2->i2c_adap,
1082 &mygica_x8506_xc5000_config);
1083 }
1084 break;
2365b2d3
DW		 1085 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1086 i2c_bus = &dev->i2c_bus[0];
1087 i2c_bus2 = &dev->i2c_bus[1];
1088 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1089 &magicpro_prohdtve2_lgs8g75_config,
1090 &i2c_bus->i2c_adap);
1091 if (fe0->dvb.frontend != NULL) {
1092 dvb_attach(xc5000_attach,
1093 fe0->dvb.frontend,
1094 &i2c_bus2->i2c_adap,
1095 &magicpro_prohdtve2_xc5000_config);
1096 }
1097 break;
13697380 1098 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST		 1099 i2c_bus = &dev->i2c_bus[0];
1100 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1101 &hcw_s5h1411_config,
1102 &i2c_bus->i2c_adap);
1103 if (fe0->dvb.frontend != NULL)
1104 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1105 0x60, &dev->i2c_bus[0].i2c_adap,
1106 &hauppauge_tda18271_config);
1107
1108 tda18271_attach(&dev->ts1.analog_fe,
1109 0x60, &dev->i2c_bus[1].i2c_adap,
1110 &hauppauge_tda18271_config);
1111
1112 break;
aee0b24c 1113 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1114 i2c_bus = &dev->i2c_bus[0];
1115 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1116 &hcw_s5h1411_config,
1117 &i2c_bus->i2c_adap);
1118 if (fe0->dvb.frontend != NULL)
1119 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1120 0x60, &dev->i2c_bus[0].i2c_adap,
1121 &hauppauge_tda18271_config);
1122 break;
ea5697fe
DW		 1123 case CX23885_BOARD_MYGICA_X8558PRO:
1124 switch (port->nr) {
1125 /* port B */
1126 case 1:
1127 i2c_bus = &dev->i2c_bus[0];
1128 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1129 &mygica_x8558pro_atbm8830_cfg1,
1130 &i2c_bus->i2c_adap);
1131 if (fe0->dvb.frontend != NULL) {
1132 dvb_attach(max2165_attach,
1133 fe0->dvb.frontend,
1134 &i2c_bus->i2c_adap,
1135 &mygic_x8558pro_max2165_cfg1);
1136 }
1137 break;
1138 /* port C */
1139 case 2:
1140 i2c_bus = &dev->i2c_bus[1];
1141 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1142 &mygica_x8558pro_atbm8830_cfg2,
1143 &i2c_bus->i2c_adap);
1144 if (fe0->dvb.frontend != NULL) {
1145 dvb_attach(max2165_attach,
1146 fe0->dvb.frontend,
1147 &i2c_bus->i2c_adap,
1148 &mygic_x8558pro_max2165_cfg2);
1149 }
1150 break;
1151 }
1152 break;
78db8547
IL		 1153 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1154 i2c_bus = &dev->i2c_bus[0];
1155 mfe_shared = 1;/* MFE */
1156 port->frontends.gate = 0;/* not clear for me yet */
1157 /* ports B, C */
1158 /* MFE frontend 1 DVB-T */
1159 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1160 &netup_stv0367_config[port->nr - 1],
1161 &i2c_bus->i2c_adap);
4174ebf5 1162 if (fe0->dvb.frontend != NULL) {
78db8547
IL		 1163 if (NULL == dvb_attach(xc5000_attach,
1164 fe0->dvb.frontend,
1165 &i2c_bus->i2c_adap,
1166 &netup_xc5000_config[port->nr - 1]))
1167 goto frontend_detach;
4174ebf5
AO		 1168 /* load xc5000 firmware */
1169 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1170 }
78db8547
IL		 1171 /* MFE frontend 2 */
1172 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1173 if (fe1 == NULL)
1174 goto frontend_detach;
1175 /* DVB-C init */
1176 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1177 &netup_stv0367_config[port->nr - 1],
1178 &i2c_bus->i2c_adap);
1179 if (fe1->dvb.frontend != NULL) {
1180 fe1->dvb.frontend->id = 1;
1181 if (NULL == dvb_attach(xc5000_attach,
1182 fe1->dvb.frontend,
1183 &i2c_bus->i2c_adap,
1184 &netup_xc5000_config[port->nr - 1]))
1185 goto frontend_detach;
1186 }
1187 break;
722c90eb
SR		 1188 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1189 i2c_bus = &dev->i2c_bus[0];
1190 i2c_bus2 = &dev->i2c_bus[1];
1191
1192 switch (port->nr) {
1193 /* port b */
1194 case 1:
1195 fe0->dvb.frontend = dvb_attach(drxk_attach,
1196 &terratec_drxk_config[0],
1197 &i2c_bus->i2c_adap);
1198 if (fe0->dvb.frontend != NULL) {
1199 if (!dvb_attach(mt2063_attach,
1200 fe0->dvb.frontend,
1201 &terratec_mt2063_config[0],
1202 &i2c_bus2->i2c_adap))
1203 goto frontend_detach;
1204 }
1205 break;
1206 /* port c */
1207 case 2:
1208 fe0->dvb.frontend = dvb_attach(drxk_attach,
1209 &terratec_drxk_config[1],
1210 &i2c_bus->i2c_adap);
1211 if (fe0->dvb.frontend != NULL) {
1212 if (!dvb_attach(mt2063_attach,
1213 fe0->dvb.frontend,
1214 &terratec_mt2063_config[1],
1215 &i2c_bus2->i2c_adap))
1216 goto frontend_detach;
1217 }
1218 break;
1219 }
1220 break;
7b134e85
IL		 1221 case CX23885_BOARD_TEVII_S471:
1222 i2c_bus = &dev->i2c_bus[1];
1223
1224 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1225 &tevii_ds3000_config,
1226 &i2c_bus->i2c_adap);
1227 break;
f667190b
MB		 1228 case CX23885_BOARD_PROF_8000:
1229 i2c_bus = &dev->i2c_bus[0];
1230
1231 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1232 &prof_8000_stv090x_config,
1233 &i2c_bus->i2c_adap,
1234 STV090x_DEMODULATOR_0);
1235 if (fe0->dvb.frontend != NULL) {
1236 if (!dvb_attach(stb6100_attach,
1237 fe0->dvb.frontend,
1238 &prof_8000_stb6100_config,
1239 &i2c_bus->i2c_adap))
1240 goto frontend_detach;
1241
1242 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1243 }
1244 break;
d19770e5 1245 default:
9c8ced51
ST		 1246 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1247 " isn't supported yet\n",
d19770e5
ST		 1248 dev->name);
1249 break;
1250 }
78db8547
IL		 1251
1252 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1253 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL		 1254 dev->name);
1255 goto frontend_detach;
d19770e5 1256 }
78db8547 1257
d7cba043 1258 /* define general-purpose callback pointer */
363c35fc 1259 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL		 1260 if (fe1)
1261 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1262#if 0
1263 /* Ensure all frontends negotiate bus access */
1264 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1265 if (fe1)
1266 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1267#endif
d19770e5
ST		 1268
1269 /* Put the analog decoder in standby to keep it quiet */
622b828a 1270 call_all(dev, core, s_power, 0);
d19770e5 1271
363c35fc
ST		 1272 if (fe0->dvb.frontend->ops.analog_ops.standby)
1273 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1274
d19770e5 1275 /* register everything */
5a23b076 1276 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1277 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1278 if (ret)
78db8547 1279 goto frontend_detach;
363c35fc 1280
5a23b076
IL		 1281 /* init CI & MAC */
1282 switch (dev->board) {
1283 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1284 static struct netup_card_info cinfo;
1285
1286 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1287 memcpy(port->frontends.adapter.proposed_mac,
1288 cinfo.port[port->nr - 1].mac, 6);
be395157 1289 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1290 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL		 1291
1292 netup_ci_init(port);
1293 break;
1294 }
78db8547
IL		 1295 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1296 struct altera_ci_config netup_ci_cfg = {
1297 .dev = dev,/* magic number to identify*/
1298 .adapter = &port->frontends.adapter,/* for CI */
1299 .demux = &fe0->dvb.demux,/* for hw pid filter */
1300 .fpga_rw = netup_altera_fpga_rw,
1301 };
1302
1303 altera_ci_init(&netup_ci_cfg, port->nr);
1304 break;
1305 }
16bfdaa4
PG		 1306 case CX23885_BOARD_TEVII_S470: {
1307 u8 eeprom[256]; /* 24C02 i2c eeprom */
1308
1309 if (port->nr != 1)
1310 break;
1311
1312 /* Read entire EEPROM */
1313 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1314 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1315 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG		 1316 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1317 break;
1318 }
5a23b076
IL		 1319 }
1320
1321 return ret;
78db8547
IL		 1322
1323frontend_detach:
1324 port->gate_ctrl = NULL;
1325 videobuf_dvb_dealloc_frontends(&port->frontends);
1326 return -EINVAL;
d19770e5
ST		 1327}
1328
1329int cx23885_dvb_register(struct cx23885_tsport *port)
1330{
363c35fc
ST		 1331
1332 struct videobuf_dvb_frontend *fe0;
d19770e5 1333 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 1334 int err, i;
1335
1336 /* Here we need to allocate the correct number of frontends,
af901ca1 1337 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 1338 * no cx23885 boards support this - yet. But, if we don't modify this
1339 * code then the second frontend would never be allocated (later)
1340 * and fail with error before the attach in dvb_register().
1341 * Without these changes we risk an OOPS later. The changes here
1342 * are for safety, and should provide a good foundation for the
1343 * future addition of any multi-frontend cx23885 based boards.
1344 */
1345 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1346 port->num_frontends);
d19770e5 1347
eb0c58bb 1348 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1349 if (videobuf_dvb_alloc_frontend(
9c8ced51 1350 &port->frontends, i) == NULL) {
eb0c58bb
ST		 1351 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1352 return -ENOMEM;
1353 }
1354
1355 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1356 if (!fe0)
1357 err = -EINVAL;
363c35fc 1358
eb0c58bb 1359 dprintk(1, "%s\n", __func__);
9c8ced51 1360 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 1361 dev->board,
1362 dev->name,
1363 dev->pci_bus,
1364 dev->pci_slot);
d19770e5 1365
eb0c58bb 1366 err = -ENODEV;
d19770e5 1367
eb0c58bb
ST		 1368 /* dvb stuff */
1369 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 1370 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1371 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1372 &dev->pci->dev, &port->slock,
44a6481d 1373 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1374 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1375 }
d19770e5
ST		 1376 err = dvb_register(port);
1377 if (err != 0)
9c8ced51
ST		 1378 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1379 __func__, err);
d19770e5 1380
d19770e5
ST		 1381 return err;
1382}
1383
1384int cx23885_dvb_unregister(struct cx23885_tsport *port)
1385{
363c35fc
ST		 1386 struct videobuf_dvb_frontend *fe0;
1387
eb0c58bb
ST		 1388 /* FIXME: in an error condition where the we have
1389 * an expected number of frontends (attach problem)
1390 * then this might not clean up correctly, if 1
1391 * is invalid.
1392 * This comment only applies to future boards IF they
1393 * implement MFE support.
1394 */
92abe9ee 1395 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1396 if (fe0 && fe0->dvb.frontend)
363c35fc 1397 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1398
afd96668
HV		 1399 switch (port->dev->board) {
1400 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1401 netup_ci_exit(port);
1402 break;
78db8547
IL		 1403 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1404 altera_ci_release(port->dev, port->nr);
1405 break;
afd96668 1406 }
5a23b076 1407
78db8547
IL		 1408 port->gate_ctrl = NULL;
1409
d19770e5
ST		 1410 return 0;
1411}
44a6481d 1412
Linux kernel - Deliverables
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