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[media] dvb: add cx24117 frontend
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
ST		 46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
5a23b076
IL		 51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
5a23b076 54#include "cimax2.h"
493b7127 55#include "lgs8gxx.h"
5a23b076
IL		 56#include "netup-eeprom.h"
57#include "netup-init.h"
a5dbf457 58#include "lgdt3305.h"
ea5697fe 59#include "atbm8830.h"
73f0af44 60#include "ts2020.h"
09ea33e5
IL		 61#include "ds3000.h"
62#include "cx23885-f300.h"
78db8547
IL		 63#include "altera-ci.h"
64#include "stv0367.h"
722c90eb
SR		 65#include "drxk.h"
66#include "mt2063.h"
f667190b
MB		 67#include "stv090x.h"
68#include "stb6100.h"
69#include "stb6100_cfg.h"
7c62f5a1
MK		 70#include "tda10071.h"
71#include "a8293.h"
0d1b5265 72#include "mb86a20s.h"
d19770e5 73
4513fc69 74static unsigned int debug;
d19770e5 75
4513fc69
ST		 76#define dprintk(level, fmt, arg...)\
77 do { if (debug >= level)\
78 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
79 } while (0)
d19770e5
ST		 80
81/* ------------------------------------------------------------------ */
82
3ba71d21
MK		 83static unsigned int alt_tuner;
84module_param(alt_tuner, int, 0644);
85MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
86
78e92006
JG		 87DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
88
3ba71d21
MK		 89/* ------------------------------------------------------------------ */
90
d19770e5
ST		 91static int dvb_buf_setup(struct videobuf_queue *q,
92 unsigned int *count, unsigned int *size)
93{
94 struct cx23885_tsport *port = q->priv_data;
95
96 port->ts_packet_size = 188 * 4;
97 port->ts_packet_count = 32;
98
99 *size = port->ts_packet_size * port->ts_packet_count;
100 *count = 32;
101 return 0;
102}
103
44a6481d
MK		 104static int dvb_buf_prepare(struct videobuf_queue *q,
105 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 106{
107 struct cx23885_tsport *port = q->priv_data;
9c8ced51 108 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 109}
110
111static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
112{
113 struct cx23885_tsport *port = q->priv_data;
9c8ced51 114 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 115}
116
44a6481d
MK		 117static void dvb_buf_release(struct videobuf_queue *q,
118 struct videobuf_buffer *vb)
d19770e5 119{
9c8ced51 120 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 121}
122
78db8547
IL		 123static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
124{
125 struct videobuf_dvb_frontends *f;
126 struct videobuf_dvb_frontend *fe;
127
128 f = &port->frontends;
129
130 if (f->gate <= 1) /* undefined or fe0 */
131 fe = videobuf_dvb_get_frontend(f, 1);
132 else
133 fe = videobuf_dvb_get_frontend(f, f->gate);
134
135 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
136 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
137}
138
d19770e5
ST		 139static struct videobuf_queue_ops dvb_qops = {
140 .buf_setup = dvb_buf_setup,
141 .buf_prepare = dvb_buf_prepare,
142 .buf_queue = dvb_buf_queue,
143 .buf_release = dvb_buf_release,
144};
145
86184e06 146static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 147 .demod_address = 0x32 >> 1,
148 .output_mode = S5H1409_SERIAL_OUTPUT,
149 .gpio = S5H1409_GPIO_ON,
2b03238a 150 .qam_if = 44000,
fc959bef 151 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 152 .status_mode = S5H1409_DEMODLOCKING,
153 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 154};
155
b3ea0166
ST		 156static struct tda10048_config hauppauge_hvr1200_config = {
157 .demod_address = 0x10 >> 1,
158 .output_mode = TDA10048_SERIAL_OUTPUT,
159 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 160 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 161 .dtv6_if_freq_khz = TDA10048_IF_3300,
162 .dtv7_if_freq_khz = TDA10048_IF_3800,
163 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 164 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 165};
166
6b926eca
MK		 167static struct tda10048_config hauppauge_hvr1210_config = {
168 .demod_address = 0x10 >> 1,
169 .output_mode = TDA10048_SERIAL_OUTPUT,
170 .fwbulkwritelen = TDA10048_BULKWRITE_200,
171 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 172 .dtv6_if_freq_khz = TDA10048_IF_3300,
173 .dtv7_if_freq_khz = TDA10048_IF_3500,
174 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 175 .clk_freq_khz = TDA10048_CLK_16000,
176};
177
3ba71d21
MK		 178static struct s5h1409_config hauppauge_ezqam_config = {
179 .demod_address = 0x32 >> 1,
180 .output_mode = S5H1409_SERIAL_OUTPUT,
181 .gpio = S5H1409_GPIO_OFF,
182 .qam_if = 4000,
183 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 184 .status_mode = S5H1409_DEMODLOCKING,
185 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 186};
187
fc959bef 188static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 189 .demod_address = 0x32 >> 1,
190 .output_mode = S5H1409_SERIAL_OUTPUT,
191 .gpio = S5H1409_GPIO_OFF,
2b03238a 192 .qam_if = 44000,
fe475163 193 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 194 .status_mode = S5H1409_DEMODLOCKING,
195 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 196};
197
07b4a835
MK		 198static struct s5h1409_config hauppauge_hvr1500_config = {
199 .demod_address = 0x32 >> 1,
200 .output_mode = S5H1409_SERIAL_OUTPUT,
201 .gpio = S5H1409_GPIO_OFF,
202 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 203 .status_mode = S5H1409_DEMODLOCKING,
204 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 205};
206
86184e06 207static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 208 0x61
209};
210
9bc37caa
MK		 211static struct lgdt330x_config fusionhdtv_5_express = {
212 .demod_address = 0x0e,
213 .demod_chip = LGDT3303,
214 .serial_mpeg = 0x40,
215};
216
d1987d55
ST		 217static struct s5h1409_config hauppauge_hvr1500q_config = {
218 .demod_address = 0x32 >> 1,
219 .output_mode = S5H1409_SERIAL_OUTPUT,
220 .gpio = S5H1409_GPIO_ON,
221 .qam_if = 44000,
222 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 223 .status_mode = S5H1409_DEMODLOCKING,
224 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 225};
226
335377b7
MK		 227static struct s5h1409_config dvico_s5h1409_config = {
228 .demod_address = 0x32 >> 1,
229 .output_mode = S5H1409_SERIAL_OUTPUT,
230 .gpio = S5H1409_GPIO_ON,
231 .qam_if = 44000,
232 .inversion = S5H1409_INVERSION_OFF,
233 .status_mode = S5H1409_DEMODLOCKING,
234 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
235};
236
52b50450
MK		 237static struct s5h1411_config dvico_s5h1411_config = {
238 .output_mode = S5H1411_SERIAL_OUTPUT,
239 .gpio = S5H1411_GPIO_ON,
240 .qam_if = S5H1411_IF_44000,
241 .vsb_if = S5H1411_IF_44000,
242 .inversion = S5H1411_INVERSION_OFF,
243 .status_mode = S5H1411_DEMODLOCKING,
244 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
245};
246
19bc5796
MK		 247static struct s5h1411_config hcw_s5h1411_config = {
248 .output_mode = S5H1411_SERIAL_OUTPUT,
249 .gpio = S5H1411_GPIO_OFF,
250 .vsb_if = S5H1411_IF_44000,
251 .qam_if = S5H1411_IF_4000,
252 .inversion = S5H1411_INVERSION_ON,
253 .status_mode = S5H1411_DEMODLOCKING,
254 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
255};
256
d1987d55 257static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 258 .i2c_address = 0x61,
259 .if_khz = 5380,
d1987d55
ST		 260};
261
335377b7
MK		 262static struct xc5000_config dvico_xc5000_tunerconfig = {
263 .i2c_address = 0x64,
264 .if_khz = 5380,
335377b7
MK		 265};
266
4041f1a5
MK		 267static struct tda829x_config tda829x_no_probe = {
268 .probe_tuner = TDA829X_DONT_PROBE,
269};
270
f21e0d7f 271static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 272 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
273 .if_lvl = 6, .rfagc_top = 0x37 },
274 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
275 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 276};
277
b34cdc36
MK		 278static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
279 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
280 .if_lvl = 1, .rfagc_top = 0x37, },
281 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
282 .if_lvl = 1, .rfagc_top = 0x37, },
283 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
284 .if_lvl = 1, .rfagc_top = 0x37, },
285};
286
f21e0d7f
MK		 287static struct tda18271_config hauppauge_tda18271_config = {
288 .std_map = &hauppauge_tda18271_std_map,
289 .gate = TDA18271_GATE_ANALOG,
04a68baa 290 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 291};
292
b3ea0166 293static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 294 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 295 .gate = TDA18271_GATE_ANALOG,
04a68baa 296 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 297};
298
6b926eca
MK		 299static struct tda18271_config hauppauge_hvr1210_tuner_config = {
300 .gate = TDA18271_GATE_DIGITAL,
04a68baa 301 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 302};
303
247bc540 304static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 305 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
306 .if_lvl = 1, .rfagc_top = 0x58 },
307 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
308 .if_lvl = 1, .rfagc_top = 0x58 },
309};
310
247bc540
MK		 311static struct tda18271_config hauppauge_hvr127x_config = {
312 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 313 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 314};
315
247bc540 316static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 317 .i2c_addr = 0x0e,
318 .mpeg_mode = LGDT3305_MPEG_SERIAL,
319 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
320 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
321 .deny_i2c_rptr = 1,
322 .spectral_inversion = 1,
323 .qam_if_khz = 4000,
324 .vsb_if_khz = 3250,
325};
326
b1721d0d 327static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 328 BAND_VHF | BAND_UHF, /* band_caps */
329
330 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
331 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
332 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
333 * P_agc_nb_est=2, P_agc_write=0
334 */
335 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
336 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
337
338 712, /* inv_gain */
339 21, /* time_stabiliz */
340
341 0, /* alpha_level */
342 118, /* thlock */
343
344 0, /* wbd_inv */
345 2867, /* wbd_ref */
346 0, /* wbd_sel */
347 2, /* wbd_alpha */
348
349 0, /* agc1_max */
350 0, /* agc1_min */
351 39718, /* agc2_max */
352 9930, /* agc2_min */
353 0, /* agc1_pt1 */
354 0, /* agc1_pt2 */
355 0, /* agc1_pt3 */
356 0, /* agc1_slope1 */
357 0, /* agc1_slope2 */
358 0, /* agc2_pt1 */
359 128, /* agc2_pt2 */
360 29, /* agc2_slope1 */
361 29, /* agc2_slope2 */
362
363 17, /* alpha_mant */
364 27, /* alpha_exp */
365 23, /* beta_mant */
366 51, /* beta_exp */
367
368 1, /* perform_agc_softsplit */
369};
370
371/* PLL Configuration for COFDM BW_MHz = 8.000000
372 * With external clock = 30.000000 */
b1721d0d 373static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 374 60000, /* internal */
375 30000, /* sampling */
376 1, /* pll_cfg: prediv */
377 8, /* pll_cfg: ratio */
378 3, /* pll_cfg: range */
379 1, /* pll_cfg: reset */
380 0, /* pll_cfg: bypass */
381 0, /* misc: refdiv */
382 0, /* misc: bypclk_div */
383 1, /* misc: IO_CLK_en_core */
384 1, /* misc: ADClkSrc */
385 0, /* misc: modulo */
386 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
387 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
388 20452225, /* timf */
389 30000000 /* xtal_hz */
390};
391
392static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
393 .output_mpeg2_in_188_bytes = 1,
394 .hostbus_diversity = 1,
395 .tuner_is_baseband = 0,
396 .update_lna = NULL,
397
398 .agc_config_count = 1,
399 .agc = &xc3028_agc_config,
400 .bw = &xc3028_bw_config,
401
402 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
403 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
404 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
405
406 .pwm_freq_div = 0,
407 .agc_control = NULL,
408 .spur_protect = 0,
409
410 .output_mode = OUTMODE_MPEG2_SERIAL,
411};
412
aef2d186
ST		 413static struct zl10353_config dvico_fusionhdtv_xc3028 = {
414 .demod_address = 0x0f,
415 .if2 = 45600,
416 .no_tuner = 1,
d4dc673d 417 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 418};
419
f867c3f4
IL		 420static struct stv0900_reg stv0900_ts_regs[] = {
421 { R0900_TSGENERAL, 0x00 },
422 { R0900_P1_TSSPEED, 0x40 },
423 { R0900_P2_TSSPEED, 0x40 },
424 { R0900_P1_TSCFGM, 0xc0 },
425 { R0900_P2_TSCFGM, 0xc0 },
426 { R0900_P1_TSCFGH, 0xe0 },
427 { R0900_P2_TSCFGH, 0xe0 },
428 { R0900_P1_TSCFGL, 0x20 },
429 { R0900_P2_TSCFGL, 0x20 },
430 { 0xffff, 0xff }, /* terminate */
431};
432
5a23b076
IL		 433static struct stv0900_config netup_stv0900_config = {
434 .demod_address = 0x68,
29372a8d 435 .demod_mode = 1, /* dual */
644c7ef0 436 .xtal = 8000000,
5a23b076
IL		 437 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
438 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 439 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 440 .tun1_maddress = 0,/* 0x60 */
441 .tun2_maddress = 3,/* 0x63 */
442 .tun1_adc = 1,/* 1 Vpp */
443 .tun2_adc = 1,/* 1 Vpp */
444};
445
446static struct stv6110_config netup_stv6110_tunerconfig_a = {
447 .i2c_address = 0x60,
644c7ef0
AO		 448 .mclk = 16000000,
449 .clk_div = 1,
873688cd 450 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 451};
452
453static struct stv6110_config netup_stv6110_tunerconfig_b = {
454 .i2c_address = 0x63,
644c7ef0
AO		 455 .mclk = 16000000,
456 .clk_div = 1,
873688cd 457 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 458};
459
96318d0c 460static struct cx24116_config tbs_cx24116_config = {
09ea33e5 461 .demod_address = 0x55,
96318d0c
IL		 462};
463
09ea33e5
IL		 464static struct ds3000_config tevii_ds3000_config = {
465 .demod_address = 0x68,
579943f5
IL		 466};
467
73f0af44
KD		 468static struct ts2020_config tevii_ts2020_config = {
469 .tuner_address = 0x60,
b858c331 470 .clk_out_div = 1,
73f0af44
KD		 471};
472
c9b8b04b
IL		 473static struct cx24116_config dvbworld_cx24116_config = {
474 .demod_address = 0x05,
475};
476
493b7127
DW		 477static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
478 .prod = LGS8GXX_PROD_LGS8GL5,
479 .demod_address = 0x19,
480 .serial_ts = 0,
481 .ts_clk_pol = 1,
482 .ts_clk_gated = 1,
483 .if_clk_freq = 30400, /* 30.4 MHz */
484 .if_freq = 5380, /* 5.38 MHz */
485 .if_neg_center = 1,
486 .ext_adc = 0,
487 .adc_signed = 0,
488 .if_neg_edge = 0,
489};
490
491static struct xc5000_config mygica_x8506_xc5000_config = {
492 .i2c_address = 0x61,
493 .if_khz = 5380,
494};
495
0d1b5265
MCC		 496static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
497 .demod_address = 0x10,
498};
499
500static struct xc5000_config mygica_x8507_xc5000_config = {
501 .i2c_address = 0x61,
502 .if_khz = 4000,
503};
504
f667190b 505static struct stv090x_config prof_8000_stv090x_config = {
b858c331
IL		 506 .device = STV0903,
507 .demod_mode = STV090x_SINGLE,
508 .clk_mode = STV090x_CLK_EXT,
509 .xtal = 27000000,
510 .address = 0x6A,
511 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
512 .repeater_level = STV090x_RPTLEVEL_64,
513 .adc1_range = STV090x_ADC_2Vpp,
514 .diseqc_envelope_mode = false,
515
516 .tuner_get_frequency = stb6100_get_frequency,
517 .tuner_set_frequency = stb6100_set_frequency,
518 .tuner_set_bandwidth = stb6100_set_bandwidth,
519 .tuner_get_bandwidth = stb6100_get_bandwidth,
f667190b
MB		 520};
521
522static struct stb6100_config prof_8000_stb6100_config = {
523 .tuner_address = 0x60,
524 .refclock = 27000000,
525};
526
527static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
528{
529 struct cx23885_tsport *port = fe->dvb->priv;
530 struct cx23885_dev *dev = port->dev;
531
532 if (voltage == SEC_VOLTAGE_18)
533 cx_write(MC417_RWD, 0x00001e00);
534 else if (voltage == SEC_VOLTAGE_13)
535 cx_write(MC417_RWD, 0x00001a00);
536 else
537 cx_write(MC417_RWD, 0x00001800);
538 return 0;
539}
540
a7d44baa 541static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 542{
a7d44baa 543 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK		 544 struct cx23885_tsport *port = fe->dvb->priv;
545 struct cx23885_dev *dev = port->dev;
546
547 switch (dev->board) {
548 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 549 switch (p->modulation) {
f35b9e80
MK		 550 case VSB_8:
551 cx23885_gpio_clear(dev, GPIO_5);
552 break;
553 case QAM_64:
554 case QAM_256:
555 default:
556 cx23885_gpio_set(dev, GPIO_5);
557 break;
558 }
559 break;
6f0d8c02 560 case CX23885_BOARD_MYGICA_X8506:
0d1b5265 561 case CX23885_BOARD_MYGICA_X8507:
6f0d8c02
DW		 562 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
563 /* Select Digital TV */
564 cx23885_gpio_set(dev, GPIO_0);
565 break;
f35b9e80 566 }
15472faf
MCC		 567
568 /* Call the real set_frontend */
569 if (port->set_frontend)
570 return port->set_frontend(fe);
571
5bdd3962 572 return 0;
f35b9e80
MK		 573}
574
15472faf
MCC		 575static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
576 struct dvb_frontend *fe)
577{
578 port->set_frontend = fe->ops.set_frontend;
579 fe->ops.set_frontend = cx23885_dvb_set_frontend;
580}
581
2365b2d3
DW		 582static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
583 .prod = LGS8GXX_PROD_LGS8G75,
584 .demod_address = 0x19,
585 .serial_ts = 0,
586 .ts_clk_pol = 1,
587 .ts_clk_gated = 1,
588 .if_clk_freq = 30400, /* 30.4 MHz */
589 .if_freq = 6500, /* 6.50 MHz */
590 .if_neg_center = 1,
591 .ext_adc = 0,
592 .adc_signed = 1,
593 .adc_vpp = 2, /* 1.6 Vpp */
594 .if_neg_edge = 1,
595};
596
597static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
598 .i2c_address = 0x61,
599 .if_khz = 6500,
600};
601
ea5697fe
DW		 602static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
603 .prod = ATBM8830_PROD_8830,
604 .demod_address = 0x44,
605 .serial_ts = 0,
606 .ts_sampling_edge = 1,
607 .ts_clk_gated = 0,
608 .osc_clk_freq = 30400, /* in kHz */
609 .if_freq = 0, /* zero IF */
610 .zif_swap_iq = 1,
c245c75c
DW		 611 .agc_min = 0x2E,
612 .agc_max = 0xFF,
613 .agc_hold_loop = 0,
ea5697fe
DW		 614};
615
616static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
617 .i2c_address = 0x60,
618 .osc_clk = 20
619};
620
621static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
622 .prod = ATBM8830_PROD_8830,
623 .demod_address = 0x44,
624 .serial_ts = 1,
625 .ts_sampling_edge = 1,
626 .ts_clk_gated = 0,
627 .osc_clk_freq = 30400, /* in kHz */
628 .if_freq = 0, /* zero IF */
629 .zif_swap_iq = 1,
c245c75c
DW		 630 .agc_min = 0x2E,
631 .agc_max = 0xFF,
632 .agc_hold_loop = 0,
ea5697fe
DW		 633};
634
635static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
636 .i2c_address = 0x60,
637 .osc_clk = 20
638};
78db8547
IL		 639static struct stv0367_config netup_stv0367_config[] = {
640 {
641 .demod_address = 0x1c,
642 .xtal = 27000000,
643 .if_khz = 4500,
644 .if_iq_mode = 0,
645 .ts_mode = 1,
646 .clk_pol = 0,
647 }, {
648 .demod_address = 0x1d,
649 .xtal = 27000000,
650 .if_khz = 4500,
651 .if_iq_mode = 0,
652 .ts_mode = 1,
653 .clk_pol = 0,
654 },
655};
656
657static struct xc5000_config netup_xc5000_config[] = {
658 {
659 .i2c_address = 0x61,
660 .if_khz = 4500,
661 }, {
662 .i2c_address = 0x64,
663 .if_khz = 4500,
664 },
665};
666
722c90eb
SR		 667static struct drxk_config terratec_drxk_config[] = {
668 {
669 .adr = 0x29,
670 .no_i2c_bridge = 1,
671 }, {
672 .adr = 0x2a,
673 .no_i2c_bridge = 1,
674 },
675};
676
677static struct mt2063_config terratec_mt2063_config[] = {
678 {
679 .tuner_address = 0x60,
680 }, {
681 .tuner_address = 0x67,
682 },
683};
684
7c62f5a1 685static const struct tda10071_config hauppauge_tda10071_config = {
41f55d57 686 .demod_i2c_addr = 0x05,
7c62f5a1
MK		 687 .tuner_i2c_addr = 0x54,
688 .i2c_wr_max = 64,
689 .ts_mode = TDA10071_TS_SERIAL,
690 .spec_inv = 0,
691 .xtal = 40444000, /* 40.444 MHz */
692 .pll_multiplier = 20,
693};
694
695static const struct a8293_config hauppauge_a8293_config = {
696 .i2c_addr = 0x0b,
697};
698
ada73eee 699static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
78db8547
IL		 700{
701 struct cx23885_dev *dev = (struct cx23885_dev *)device;
702 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 703 uint32_t mem = 0;
78db8547 704
d164460f 705 mem = cx_read(MC417_RWD);
78db8547
IL		 706 if (read)
707 cx_set(MC417_OEN, ALT_DATA);
708 else {
709 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL		 710 mem &= ~ALT_DATA;
711 mem |= (data & ALT_DATA);
78db8547
IL		 712 }
713
714 if (flag)
d164460f 715 mem |= ALT_AD_RG;
78db8547 716 else
d164460f 717 mem &= ~ALT_AD_RG;
78db8547 718
d164460f 719 mem &= ~ALT_CS;
78db8547 720 if (read)
d164460f 721 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 722 else
d164460f
AO		 723 mem = (mem & ~ALT_WR) | ALT_RD;
724
725 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL		 726
727 for (;;) {
728 mem = cx_read(MC417_RWD);
729 if ((mem & ALT_RDY) == 0)
730 break;
731 if (time_after(jiffies, timeout))
732 break;
733 udelay(1);
734 }
735
736 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
737 if (read)
738 return mem & ALT_DATA;
739
740 return 0;
741};
ea5697fe 742
d19770e5
ST		 743static int dvb_register(struct cx23885_tsport *port)
744{
745 struct cx23885_dev *dev = port->dev;
493b7127 746 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL		 747 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
748 int mfe_shared = 0; /* bus not shared by default */
5a23b076 749 int ret;
363c35fc 750
f972e0bd 751 /* Get the first frontend */
92abe9ee 752 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 753 if (!fe0)
754 return -EINVAL;
d19770e5
ST		 755
756 /* init struct videobuf_dvb */
363c35fc 757 fe0->dvb.name = dev->name;
d19770e5 758
78db8547
IL		 759 /* multi-frontend gate control is undefined or defaults to fe0 */
760 port->frontends.gate = 0;
761
762 /* Sets the gate control callback to be used by i2c command calls */
763 port->gate_ctrl = cx23885_dvb_gate_ctrl;
764
d19770e5
ST		 765 /* init frontend */
766 switch (dev->board) {
a77743bc 767 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 768 i2c_bus = &dev->i2c_bus[0];
363c35fc 769 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 770 &hauppauge_generic_config,
f139fa71 771 &i2c_bus->i2c_adap);
363c35fc
ST		 772 if (fe0->dvb.frontend != NULL) {
773 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 774 &i2c_bus->i2c_adap,
86184e06 775 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 776 }
777 break;
a5dbf457 778 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 779 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 780 i2c_bus = &dev->i2c_bus[0];
781 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 782 &hauppauge_lgdt3305_config,
a5dbf457
MK		 783 &i2c_bus->i2c_adap);
784 if (fe0->dvb.frontend != NULL) {
785 dvb_attach(tda18271_attach, fe0->dvb.frontend,
786 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 787 &hauppauge_hvr127x_config);
a5dbf457 788 }
15472faf
MCC		 789 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
790 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
a5dbf457 791 break;
19bc5796 792 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 793 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK		 794 i2c_bus = &dev->i2c_bus[0];
795 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
796 &hcw_s5h1411_config,
797 &i2c_bus->i2c_adap);
798 if (fe0->dvb.frontend != NULL) {
799 dvb_attach(tda18271_attach, fe0->dvb.frontend,
800 0x60, &dev->i2c_bus[1].i2c_adap,
801 &hauppauge_tda18271_config);
802 }
0ac60acb
DH		 803
804 tda18271_attach(&dev->ts1.analog_fe,
805 0x60, &dev->i2c_bus[1].i2c_adap,
806 &hauppauge_tda18271_config);
807
19bc5796 808 break;
3ba71d21
MK		 809 case CX23885_BOARD_HAUPPAUGE_HVR1800:
810 i2c_bus = &dev->i2c_bus[0];
92abe9ee 811 switch (alt_tuner) {
3ba71d21 812 case 1:
363c35fc 813 fe0->dvb.frontend =
3ba71d21
MK		 814 dvb_attach(s5h1409_attach,
815 &hauppauge_ezqam_config,
816 &i2c_bus->i2c_adap);
363c35fc
ST		 817 if (fe0->dvb.frontend != NULL) {
818 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 819 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 820 &tda829x_no_probe);
363c35fc 821 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 822 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 823 &hauppauge_tda18271_config);
3ba71d21
MK		 824 }
825 break;
826 case 0:
827 default:
363c35fc 828 fe0->dvb.frontend =
3ba71d21
MK		 829 dvb_attach(s5h1409_attach,
830 &hauppauge_generic_config,
831 &i2c_bus->i2c_adap);
363c35fc
ST		 832 if (fe0->dvb.frontend != NULL)
833 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 834 &i2c_bus->i2c_adap,
835 &hauppauge_generic_tunerconfig, 0);
836 break;
837 }
838 break;
fc959bef 839 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 840 i2c_bus = &dev->i2c_bus[0];
363c35fc 841 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 842 &hauppauge_hvr1800lp_config,
f139fa71 843 &i2c_bus->i2c_adap);
363c35fc
ST		 844 if (fe0->dvb.frontend != NULL) {
845 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 846 &i2c_bus->i2c_adap,
fc959bef
ST		 847 &hauppauge_generic_tunerconfig, 0);
848 }
849 break;
9bc37caa 850 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 851 i2c_bus = &dev->i2c_bus[0];
363c35fc 852 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 853 &fusionhdtv_5_express,
f139fa71 854 &i2c_bus->i2c_adap);
363c35fc
ST		 855 if (fe0->dvb.frontend != NULL) {
856 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 857 &i2c_bus->i2c_adap, 0x61,
858 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 859 }
860 break;
d1987d55
ST		 861 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
862 i2c_bus = &dev->i2c_bus[1];
363c35fc 863 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 864 &hauppauge_hvr1500q_config,
865 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 866 if (fe0->dvb.frontend != NULL)
867 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 868 &i2c_bus->i2c_adap,
869 &hauppauge_hvr1500q_tunerconfig);
d1987d55 870 break;
07b4a835
MK		 871 case CX23885_BOARD_HAUPPAUGE_HVR1500:
872 i2c_bus = &dev->i2c_bus[1];
363c35fc 873 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 874 &hauppauge_hvr1500_config,
875 &dev->i2c_bus[0].i2c_adap);
363c35fc 876 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 877 struct dvb_frontend *fe;
878 struct xc2028_config cfg = {
879 .i2c_adap = &i2c_bus->i2c_adap,
880 .i2c_addr = 0x61,
07b4a835
MK		 881 };
882 static struct xc2028_ctrl ctl = {
ef80bfeb 883 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 884 .max_len = 64,
52c3d29c 885 .demod = XC3028_FE_OREN538,
07b4a835
MK		 886 };
887
888 fe = dvb_attach(xc2028_attach,
363c35fc 889 fe0->dvb.frontend, &cfg);
07b4a835
MK		 890 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
891 fe->ops.tuner_ops.set_config(fe, &ctl);
892 }
893 break;
b3ea0166 894 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 895 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 896 i2c_bus = &dev->i2c_bus[0];
363c35fc 897 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 898 &hauppauge_hvr1200_config,
899 &i2c_bus->i2c_adap);
363c35fc
ST		 900 if (fe0->dvb.frontend != NULL) {
901 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 902 &dev->i2c_bus[1].i2c_adap, 0x42,
903 &tda829x_no_probe);
363c35fc 904 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 905 0x60, &dev->i2c_bus[1].i2c_adap,
906 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 907 }
908 break;
909 case CX23885_BOARD_HAUPPAUGE_HVR1210:
910 i2c_bus = &dev->i2c_bus[0];
911 fe0->dvb.frontend = dvb_attach(tda10048_attach,
912 &hauppauge_hvr1210_config,
913 &i2c_bus->i2c_adap);
914 if (fe0->dvb.frontend != NULL) {
915 dvb_attach(tda18271_attach, fe0->dvb.frontend,
916 0x60, &dev->i2c_bus[1].i2c_adap,
917 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 918 }
919 break;
66762373
ST		 920 case CX23885_BOARD_HAUPPAUGE_HVR1400:
921 i2c_bus = &dev->i2c_bus[0];
363c35fc 922 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 923 &i2c_bus->i2c_adap,
924 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 925 if (fe0->dvb.frontend != NULL) {
66762373
ST		 926 struct dvb_frontend *fe;
927 struct xc2028_config cfg = {
928 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
929 .i2c_addr = 0x64,
66762373
ST		 930 };
931 static struct xc2028_ctrl ctl = {
ef80bfeb 932 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 933 .max_len = 64,
9bed77ee 934 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST		 935 /* This is true for all demods with
936 v36 firmware? */
0975fc68 937 .type = XC2028_D2633,
66762373
ST		 938 };
939
940 fe = dvb_attach(xc2028_attach,
363c35fc 941 fe0->dvb.frontend, &cfg);
66762373
ST		 942 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
943 fe->ops.tuner_ops.set_config(fe, &ctl);
944 }
945 break;
335377b7
MK		 946 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
947 i2c_bus = &dev->i2c_bus[port->nr - 1];
948
363c35fc 949 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 950 &dvico_s5h1409_config,
951 &i2c_bus->i2c_adap);
363c35fc
ST		 952 if (fe0->dvb.frontend == NULL)
953 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 954 &dvico_s5h1411_config,
955 &i2c_bus->i2c_adap);
363c35fc
ST		 956 if (fe0->dvb.frontend != NULL)
957 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 958 &i2c_bus->i2c_adap,
959 &dvico_xc5000_tunerconfig);
335377b7 960 break;
aef2d186
ST		 961 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
962 i2c_bus = &dev->i2c_bus[port->nr - 1];
963
363c35fc 964 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 965 &dvico_fusionhdtv_xc3028,
966 &i2c_bus->i2c_adap);
363c35fc 967 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 968 struct dvb_frontend *fe;
969 struct xc2028_config cfg = {
970 .i2c_adap = &i2c_bus->i2c_adap,
971 .i2c_addr = 0x61,
aef2d186
ST		 972 };
973 static struct xc2028_ctrl ctl = {
ef80bfeb 974 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 975 .max_len = 64,
976 .demod = XC3028_FE_ZARLINK456,
977 };
978
363c35fc 979 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 980 &cfg);
981 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
982 fe->ops.tuner_ops.set_config(fe, &ctl);
983 }
984 break;
985 }
4c56b04a 986 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 987 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 988 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 989 i2c_bus = &dev->i2c_bus[0];
990
363c35fc 991 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 992 &dvico_fusionhdtv_xc3028,
993 &i2c_bus->i2c_adap);
363c35fc 994 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 995 struct dvb_frontend *fe;
996 struct xc2028_config cfg = {
997 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
998 .i2c_addr = 0x61,
4c56b04a
ST		 999 };
1000 static struct xc2028_ctrl ctl = {
ef80bfeb 1001 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 1002 .max_len = 64,
1003 .demod = XC3028_FE_ZARLINK456,
1004 };
1005
363c35fc 1006 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 1007 &cfg);
1008 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1009 fe->ops.tuner_ops.set_config(fe, &ctl);
1010 }
96318d0c 1011 break;
0cf8af57 1012 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1013 i2c_bus = &dev->i2c_bus[0];
1014
1015 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1016 &dvico_fusionhdtv_xc3028,
1017 &i2c_bus->i2c_adap);
1018 if (fe0->dvb.frontend != NULL) {
1019 struct dvb_frontend *fe;
1020 struct xc4000_config cfg = {
1021 .i2c_address = 0x61,
1022 .default_pm = 0,
1023 .dvb_amplitude = 134,
1024 .set_smoothedcvbs = 1,
1025 .if_khz = 4560
1026 };
1027
1028 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1029 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS		 1030 if (!fe) {
1031 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1032 dev->name);
1033 goto frontend_detach;
1034 }
0cf8af57 1035 }
1036 break;
96318d0c 1037 case CX23885_BOARD_TBS_6920:
09ea33e5 1038 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL		 1039
1040 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL		 1041 &tbs_cx24116_config,
1042 &i2c_bus->i2c_adap);
96318d0c 1043 if (fe0->dvb.frontend != NULL)
09ea33e5 1044 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1045
579943f5
IL		 1046 break;
1047 case CX23885_BOARD_TEVII_S470:
1048 i2c_bus = &dev->i2c_bus[1];
1049
09ea33e5
IL		 1050 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1051 &tevii_ds3000_config,
1052 &i2c_bus->i2c_adap);
73f0af44
KD		 1053 if (fe0->dvb.frontend != NULL) {
1054 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1055 &tevii_ts2020_config, &i2c_bus->i2c_adap);
09ea33e5 1056 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
73f0af44 1057 }
579943f5 1058
4c56b04a 1059 break;
c9b8b04b
IL		 1060 case CX23885_BOARD_DVBWORLD_2005:
1061 i2c_bus = &dev->i2c_bus[1];
1062
1063 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1064 &dvbworld_cx24116_config,
1065 &i2c_bus->i2c_adap);
1066 break;
5a23b076
IL		 1067 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1068 i2c_bus = &dev->i2c_bus[0];
1069 switch (port->nr) {
1070 /* port B */
1071 case 1:
1072 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1073 &netup_stv0900_config,
1074 &i2c_bus->i2c_adap, 0);
1075 if (fe0->dvb.frontend != NULL) {
1076 if (dvb_attach(stv6110_attach,
1077 fe0->dvb.frontend,
1078 &netup_stv6110_tunerconfig_a,
1079 &i2c_bus->i2c_adap)) {
1080 if (!dvb_attach(lnbh24_attach,
1081 fe0->dvb.frontend,
1082 &i2c_bus->i2c_adap,
9329fb5b
AO		 1083 LNBH24_PCL | LNBH24_TTX,
1084 LNBH24_TEN, 0x09))
5a23b076
IL		 1085 printk(KERN_ERR
1086 "No LNBH24 found!\n");
1087
1088 }
1089 }
1090 break;
1091 /* port C */
1092 case 2:
1093 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1094 &netup_stv0900_config,
1095 &i2c_bus->i2c_adap, 1);
1096 if (fe0->dvb.frontend != NULL) {
1097 if (dvb_attach(stv6110_attach,
1098 fe0->dvb.frontend,
1099 &netup_stv6110_tunerconfig_b,
1100 &i2c_bus->i2c_adap)) {
1101 if (!dvb_attach(lnbh24_attach,
1102 fe0->dvb.frontend,
1103 &i2c_bus->i2c_adap,
9329fb5b
AO		 1104 LNBH24_PCL | LNBH24_TTX,
1105 LNBH24_TEN, 0x0a))
5a23b076
IL		 1106 printk(KERN_ERR
1107 "No LNBH24 found!\n");
1108
1109 }
1110 }
1111 break;
1112 }
1113 break;
493b7127
DW		 1114 case CX23885_BOARD_MYGICA_X8506:
1115 i2c_bus = &dev->i2c_bus[0];
1116 i2c_bus2 = &dev->i2c_bus[1];
1117 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1118 &mygica_x8506_lgs8gl5_config,
1119 &i2c_bus->i2c_adap);
1120 if (fe0->dvb.frontend != NULL) {
1121 dvb_attach(xc5000_attach,
1122 fe0->dvb.frontend,
1123 &i2c_bus2->i2c_adap,
1124 &mygica_x8506_xc5000_config);
1125 }
15472faf 1126 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
493b7127 1127 break;
0d1b5265
MCC		 1128 case CX23885_BOARD_MYGICA_X8507:
1129 i2c_bus = &dev->i2c_bus[0];
1130 i2c_bus2 = &dev->i2c_bus[1];
1131 fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
1132 &mygica_x8507_mb86a20s_config,
1133 &i2c_bus->i2c_adap);
1134 if (fe0->dvb.frontend != NULL) {
1135 dvb_attach(xc5000_attach,
1136 fe0->dvb.frontend,
1137 &i2c_bus2->i2c_adap,
1138 &mygica_x8507_xc5000_config);
1139 }
1140 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
1141 break;
2365b2d3
DW		 1142 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1143 i2c_bus = &dev->i2c_bus[0];
1144 i2c_bus2 = &dev->i2c_bus[1];
1145 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1146 &magicpro_prohdtve2_lgs8g75_config,
1147 &i2c_bus->i2c_adap);
1148 if (fe0->dvb.frontend != NULL) {
1149 dvb_attach(xc5000_attach,
1150 fe0->dvb.frontend,
1151 &i2c_bus2->i2c_adap,
1152 &magicpro_prohdtve2_xc5000_config);
1153 }
15472faf 1154 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
2365b2d3 1155 break;
13697380 1156 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST		 1157 i2c_bus = &dev->i2c_bus[0];
1158 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1159 &hcw_s5h1411_config,
1160 &i2c_bus->i2c_adap);
1161 if (fe0->dvb.frontend != NULL)
1162 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1163 0x60, &dev->i2c_bus[0].i2c_adap,
1164 &hauppauge_tda18271_config);
1165
1166 tda18271_attach(&dev->ts1.analog_fe,
1167 0x60, &dev->i2c_bus[1].i2c_adap,
1168 &hauppauge_tda18271_config);
1169
1170 break;
aee0b24c 1171 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1172 i2c_bus = &dev->i2c_bus[0];
1173 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1174 &hcw_s5h1411_config,
1175 &i2c_bus->i2c_adap);
1176 if (fe0->dvb.frontend != NULL)
1177 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1178 0x60, &dev->i2c_bus[0].i2c_adap,
1179 &hauppauge_tda18271_config);
1180 break;
ea5697fe
DW		 1181 case CX23885_BOARD_MYGICA_X8558PRO:
1182 switch (port->nr) {
1183 /* port B */
1184 case 1:
1185 i2c_bus = &dev->i2c_bus[0];
1186 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1187 &mygica_x8558pro_atbm8830_cfg1,
1188 &i2c_bus->i2c_adap);
1189 if (fe0->dvb.frontend != NULL) {
1190 dvb_attach(max2165_attach,
1191 fe0->dvb.frontend,
1192 &i2c_bus->i2c_adap,
1193 &mygic_x8558pro_max2165_cfg1);
1194 }
1195 break;
1196 /* port C */
1197 case 2:
1198 i2c_bus = &dev->i2c_bus[1];
1199 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1200 &mygica_x8558pro_atbm8830_cfg2,
1201 &i2c_bus->i2c_adap);
1202 if (fe0->dvb.frontend != NULL) {
1203 dvb_attach(max2165_attach,
1204 fe0->dvb.frontend,
1205 &i2c_bus->i2c_adap,
1206 &mygic_x8558pro_max2165_cfg2);
1207 }
1208 break;
1209 }
1210 break;
78db8547
IL		 1211 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1212 i2c_bus = &dev->i2c_bus[0];
1213 mfe_shared = 1;/* MFE */
1214 port->frontends.gate = 0;/* not clear for me yet */
1215 /* ports B, C */
1216 /* MFE frontend 1 DVB-T */
1217 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1218 &netup_stv0367_config[port->nr - 1],
1219 &i2c_bus->i2c_adap);
4174ebf5 1220 if (fe0->dvb.frontend != NULL) {
78db8547
IL		 1221 if (NULL == dvb_attach(xc5000_attach,
1222 fe0->dvb.frontend,
1223 &i2c_bus->i2c_adap,
1224 &netup_xc5000_config[port->nr - 1]))
1225 goto frontend_detach;
4174ebf5
AO		 1226 /* load xc5000 firmware */
1227 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1228 }
78db8547
IL		 1229 /* MFE frontend 2 */
1230 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1231 if (fe1 == NULL)
1232 goto frontend_detach;
1233 /* DVB-C init */
1234 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1235 &netup_stv0367_config[port->nr - 1],
1236 &i2c_bus->i2c_adap);
1237 if (fe1->dvb.frontend != NULL) {
1238 fe1->dvb.frontend->id = 1;
1239 if (NULL == dvb_attach(xc5000_attach,
1240 fe1->dvb.frontend,
1241 &i2c_bus->i2c_adap,
1242 &netup_xc5000_config[port->nr - 1]))
1243 goto frontend_detach;
1244 }
1245 break;
722c90eb
SR		 1246 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1247 i2c_bus = &dev->i2c_bus[0];
1248 i2c_bus2 = &dev->i2c_bus[1];
1249
1250 switch (port->nr) {
1251 /* port b */
1252 case 1:
1253 fe0->dvb.frontend = dvb_attach(drxk_attach,
1254 &terratec_drxk_config[0],
1255 &i2c_bus->i2c_adap);
1256 if (fe0->dvb.frontend != NULL) {
1257 if (!dvb_attach(mt2063_attach,
1258 fe0->dvb.frontend,
1259 &terratec_mt2063_config[0],
1260 &i2c_bus2->i2c_adap))
1261 goto frontend_detach;
1262 }
1263 break;
1264 /* port c */
1265 case 2:
1266 fe0->dvb.frontend = dvb_attach(drxk_attach,
1267 &terratec_drxk_config[1],
1268 &i2c_bus->i2c_adap);
1269 if (fe0->dvb.frontend != NULL) {
1270 if (!dvb_attach(mt2063_attach,
1271 fe0->dvb.frontend,
1272 &terratec_mt2063_config[1],
1273 &i2c_bus2->i2c_adap))
1274 goto frontend_detach;
1275 }
1276 break;
1277 }
1278 break;
7b134e85
IL		 1279 case CX23885_BOARD_TEVII_S471:
1280 i2c_bus = &dev->i2c_bus[1];
1281
1282 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1283 &tevii_ds3000_config,
1284 &i2c_bus->i2c_adap);
b43ea806
JK		 1285 if (fe0->dvb.frontend != NULL) {
1286 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1287 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1288 }
7b134e85 1289 break;
f667190b
MB		 1290 case CX23885_BOARD_PROF_8000:
1291 i2c_bus = &dev->i2c_bus[0];
1292
1293 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1294 &prof_8000_stv090x_config,
1295 &i2c_bus->i2c_adap,
1296 STV090x_DEMODULATOR_0);
1297 if (fe0->dvb.frontend != NULL) {
1298 if (!dvb_attach(stb6100_attach,
1299 fe0->dvb.frontend,
1300 &prof_8000_stb6100_config,
1301 &i2c_bus->i2c_adap))
1302 goto frontend_detach;
1303
1304 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1305 }
1306 break;
7c62f5a1
MK		 1307 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1308 i2c_bus = &dev->i2c_bus[0];
1309 fe0->dvb.frontend = dvb_attach(tda10071_attach,
1310 &hauppauge_tda10071_config,
1311 &i2c_bus->i2c_adap);
1312 if (fe0->dvb.frontend != NULL) {
1313 dvb_attach(a8293_attach, fe0->dvb.frontend,
1314 &i2c_bus->i2c_adap,
1315 &hauppauge_a8293_config);
1316 }
1317 break;
d19770e5 1318 default:
9c8ced51
ST		 1319 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1320 " isn't supported yet\n",
d19770e5
ST		 1321 dev->name);
1322 break;
1323 }
78db8547
IL		 1324
1325 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1326 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL		 1327 dev->name);
1328 goto frontend_detach;
d19770e5 1329 }
78db8547 1330
d7cba043 1331 /* define general-purpose callback pointer */
363c35fc 1332 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL		 1333 if (fe1)
1334 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1335#if 0
1336 /* Ensure all frontends negotiate bus access */
1337 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1338 if (fe1)
1339 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1340#endif
d19770e5
ST		 1341
1342 /* Put the analog decoder in standby to keep it quiet */
622b828a 1343 call_all(dev, core, s_power, 0);
d19770e5 1344
363c35fc
ST		 1345 if (fe0->dvb.frontend->ops.analog_ops.standby)
1346 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1347
d19770e5 1348 /* register everything */
5a23b076 1349 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1350 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1351 if (ret)
78db8547 1352 goto frontend_detach;
363c35fc 1353
5a23b076
IL		 1354 /* init CI & MAC */
1355 switch (dev->board) {
1356 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1357 static struct netup_card_info cinfo;
1358
1359 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1360 memcpy(port->frontends.adapter.proposed_mac,
1361 cinfo.port[port->nr - 1].mac, 6);
be395157 1362 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1363 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL		 1364
1365 netup_ci_init(port);
1366 break;
1367 }
78db8547
IL		 1368 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1369 struct altera_ci_config netup_ci_cfg = {
1370 .dev = dev,/* magic number to identify*/
1371 .adapter = &port->frontends.adapter,/* for CI */
1372 .demux = &fe0->dvb.demux,/* for hw pid filter */
1373 .fpga_rw = netup_altera_fpga_rw,
1374 };
1375
1376 altera_ci_init(&netup_ci_cfg, port->nr);
1377 break;
1378 }
16bfdaa4
PG		 1379 case CX23885_BOARD_TEVII_S470: {
1380 u8 eeprom[256]; /* 24C02 i2c eeprom */
1381
1382 if (port->nr != 1)
1383 break;
1384
1385 /* Read entire EEPROM */
1386 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1387 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1388 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG		 1389 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1390 break;
1391 }
5a23b076
IL		 1392 }
1393
1394 return ret;
78db8547
IL		 1395
1396frontend_detach:
1397 port->gate_ctrl = NULL;
1398 videobuf_dvb_dealloc_frontends(&port->frontends);
1399 return -EINVAL;
d19770e5
ST		 1400}
1401
1402int cx23885_dvb_register(struct cx23885_tsport *port)
1403{
363c35fc
ST		 1404
1405 struct videobuf_dvb_frontend *fe0;
d19770e5 1406 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 1407 int err, i;
1408
1409 /* Here we need to allocate the correct number of frontends,
af901ca1 1410 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 1411 * no cx23885 boards support this - yet. But, if we don't modify this
1412 * code then the second frontend would never be allocated (later)
1413 * and fail with error before the attach in dvb_register().
1414 * Without these changes we risk an OOPS later. The changes here
1415 * are for safety, and should provide a good foundation for the
1416 * future addition of any multi-frontend cx23885 based boards.
1417 */
1418 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1419 port->num_frontends);
d19770e5 1420
eb0c58bb 1421 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1422 if (videobuf_dvb_alloc_frontend(
9c8ced51 1423 &port->frontends, i) == NULL) {
eb0c58bb
ST		 1424 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1425 return -ENOMEM;
1426 }
1427
1428 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1429 if (!fe0)
1430 err = -EINVAL;
363c35fc 1431
eb0c58bb 1432 dprintk(1, "%s\n", __func__);
9c8ced51 1433 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 1434 dev->board,
1435 dev->name,
1436 dev->pci_bus,
1437 dev->pci_slot);
d19770e5 1438
eb0c58bb 1439 err = -ENODEV;
d19770e5 1440
eb0c58bb
ST		 1441 /* dvb stuff */
1442 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 1443 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1444 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1445 &dev->pci->dev, &port->slock,
44a6481d 1446 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1447 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1448 }
d19770e5
ST		 1449 err = dvb_register(port);
1450 if (err != 0)
9c8ced51
ST		 1451 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1452 __func__, err);
d19770e5 1453
d19770e5
ST		 1454 return err;
1455}
1456
1457int cx23885_dvb_unregister(struct cx23885_tsport *port)
1458{
363c35fc
ST		 1459 struct videobuf_dvb_frontend *fe0;
1460
eb0c58bb
ST		 1461 /* FIXME: in an error condition where the we have
1462 * an expected number of frontends (attach problem)
1463 * then this might not clean up correctly, if 1
1464 * is invalid.
1465 * This comment only applies to future boards IF they
1466 * implement MFE support.
1467 */
92abe9ee 1468 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1469 if (fe0 && fe0->dvb.frontend)
363c35fc 1470 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1471
afd96668
HV		 1472 switch (port->dev->board) {
1473 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1474 netup_ci_exit(port);
1475 break;
78db8547
IL		 1476 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1477 altera_ci_release(port->dev, port->nr);
1478 break;
afd96668 1479 }
5a23b076 1480
78db8547
IL		 1481 port->gate_ctrl = NULL;
1482
d19770e5
ST		 1483 return 0;
1484}
44a6481d 1485
Linux kernel - Deliverables
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