Commit | Line | Data |
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d19770e5 ST |
1 | /* |
2 | * Driver for the Conexant CX23885 PCIe bridge | |
3 | * | |
6d897616 | 4 | * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> |
d19770e5 ST |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/fs.h> | |
26 | #include <linux/kthread.h> | |
27 | #include <linux/file.h> | |
28 | #include <linux/suspend.h> | |
29 | ||
30 | #include "cx23885.h" | |
d19770e5 ST |
31 | #include <media/v4l2-common.h> |
32 | ||
5a23b076 | 33 | #include "dvb_ca_en50221.h" |
d19770e5 | 34 | #include "s5h1409.h" |
52b50450 | 35 | #include "s5h1411.h" |
d19770e5 | 36 | #include "mt2131.h" |
3ba71d21 | 37 | #include "tda8290.h" |
4041f1a5 | 38 | #include "tda18271.h" |
9bc37caa | 39 | #include "lgdt330x.h" |
0cf8af57 | 40 | #include "xc4000.h" |
d1987d55 | 41 | #include "xc5000.h" |
ea5697fe | 42 | #include "max2165.h" |
b3ea0166 | 43 | #include "tda10048.h" |
07b4a835 | 44 | #include "tuner-xc2028.h" |
827855d3 | 45 | #include "tuner-simple.h" |
66762373 ST |
46 | #include "dib7000p.h" |
47 | #include "dibx000_common.h" | |
aef2d186 | 48 | #include "zl10353.h" |
5a23b076 | 49 | #include "stv0900.h" |
f867c3f4 | 50 | #include "stv0900_reg.h" |
5a23b076 IL |
51 | #include "stv6110.h" |
52 | #include "lnbh24.h" | |
96318d0c | 53 | #include "cx24116.h" |
5a23b076 | 54 | #include "cimax2.h" |
493b7127 | 55 | #include "lgs8gxx.h" |
5a23b076 IL |
56 | #include "netup-eeprom.h" |
57 | #include "netup-init.h" | |
a5dbf457 | 58 | #include "lgdt3305.h" |
ea5697fe | 59 | #include "atbm8830.h" |
09ea33e5 IL |
60 | #include "ds3000.h" |
61 | #include "cx23885-f300.h" | |
78db8547 IL |
62 | #include "altera-ci.h" |
63 | #include "stv0367.h" | |
722c90eb SR |
64 | #include "drxk.h" |
65 | #include "mt2063.h" | |
d19770e5 | 66 | |
4513fc69 | 67 | static unsigned int debug; |
d19770e5 | 68 | |
4513fc69 ST |
69 | #define dprintk(level, fmt, arg...)\ |
70 | do { if (debug >= level)\ | |
71 | printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ | |
72 | } while (0) | |
d19770e5 ST |
73 | |
74 | /* ------------------------------------------------------------------ */ | |
75 | ||
3ba71d21 MK |
76 | static unsigned int alt_tuner; |
77 | module_param(alt_tuner, int, 0644); | |
78 | MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration"); | |
79 | ||
78e92006 JG |
80 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
81 | ||
3ba71d21 MK |
82 | /* ------------------------------------------------------------------ */ |
83 | ||
d19770e5 ST |
84 | static int dvb_buf_setup(struct videobuf_queue *q, |
85 | unsigned int *count, unsigned int *size) | |
86 | { | |
87 | struct cx23885_tsport *port = q->priv_data; | |
88 | ||
89 | port->ts_packet_size = 188 * 4; | |
90 | port->ts_packet_count = 32; | |
91 | ||
92 | *size = port->ts_packet_size * port->ts_packet_count; | |
93 | *count = 32; | |
94 | return 0; | |
95 | } | |
96 | ||
44a6481d MK |
97 | static int dvb_buf_prepare(struct videobuf_queue *q, |
98 | struct videobuf_buffer *vb, enum v4l2_field field) | |
d19770e5 ST |
99 | { |
100 | struct cx23885_tsport *port = q->priv_data; | |
9c8ced51 | 101 | return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field); |
d19770e5 ST |
102 | } |
103 | ||
104 | static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
105 | { | |
106 | struct cx23885_tsport *port = q->priv_data; | |
9c8ced51 | 107 | cx23885_buf_queue(port, (struct cx23885_buffer *)vb); |
d19770e5 ST |
108 | } |
109 | ||
44a6481d MK |
110 | static void dvb_buf_release(struct videobuf_queue *q, |
111 | struct videobuf_buffer *vb) | |
d19770e5 | 112 | { |
9c8ced51 | 113 | cx23885_free_buffer(q, (struct cx23885_buffer *)vb); |
d19770e5 ST |
114 | } |
115 | ||
a7d44baa MCC |
116 | static int cx23885_dvb_set_frontend(struct dvb_frontend *fe); |
117 | ||
78db8547 IL |
118 | static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open) |
119 | { | |
120 | struct videobuf_dvb_frontends *f; | |
121 | struct videobuf_dvb_frontend *fe; | |
122 | ||
123 | f = &port->frontends; | |
124 | ||
125 | if (f->gate <= 1) /* undefined or fe0 */ | |
126 | fe = videobuf_dvb_get_frontend(f, 1); | |
127 | else | |
128 | fe = videobuf_dvb_get_frontend(f, f->gate); | |
129 | ||
130 | if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl) | |
131 | fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open); | |
a7d44baa MCC |
132 | |
133 | /* | |
134 | * FIXME: Improve this path to avoid calling the | |
135 | * cx23885_dvb_set_frontend() every time it passes here. | |
136 | */ | |
137 | cx23885_dvb_set_frontend(fe->dvb.frontend); | |
78db8547 IL |
138 | } |
139 | ||
d19770e5 ST |
140 | static struct videobuf_queue_ops dvb_qops = { |
141 | .buf_setup = dvb_buf_setup, | |
142 | .buf_prepare = dvb_buf_prepare, | |
143 | .buf_queue = dvb_buf_queue, | |
144 | .buf_release = dvb_buf_release, | |
145 | }; | |
146 | ||
86184e06 | 147 | static struct s5h1409_config hauppauge_generic_config = { |
fc959bef ST |
148 | .demod_address = 0x32 >> 1, |
149 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
150 | .gpio = S5H1409_GPIO_ON, | |
2b03238a | 151 | .qam_if = 44000, |
fc959bef | 152 | .inversion = S5H1409_INVERSION_OFF, |
dfc1c08a ST |
153 | .status_mode = S5H1409_DEMODLOCKING, |
154 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
fc959bef ST |
155 | }; |
156 | ||
b3ea0166 ST |
157 | static struct tda10048_config hauppauge_hvr1200_config = { |
158 | .demod_address = 0x10 >> 1, | |
159 | .output_mode = TDA10048_SERIAL_OUTPUT, | |
160 | .fwbulkwritelen = TDA10048_BULKWRITE_200, | |
484d9e05 | 161 | .inversion = TDA10048_INVERSION_ON, |
8816bef5 ST |
162 | .dtv6_if_freq_khz = TDA10048_IF_3300, |
163 | .dtv7_if_freq_khz = TDA10048_IF_3800, | |
164 | .dtv8_if_freq_khz = TDA10048_IF_4300, | |
484d9e05 | 165 | .clk_freq_khz = TDA10048_CLK_16000, |
b3ea0166 ST |
166 | }; |
167 | ||
6b926eca MK |
168 | static struct tda10048_config hauppauge_hvr1210_config = { |
169 | .demod_address = 0x10 >> 1, | |
170 | .output_mode = TDA10048_SERIAL_OUTPUT, | |
171 | .fwbulkwritelen = TDA10048_BULKWRITE_200, | |
172 | .inversion = TDA10048_INVERSION_ON, | |
c27586e4 MK |
173 | .dtv6_if_freq_khz = TDA10048_IF_3300, |
174 | .dtv7_if_freq_khz = TDA10048_IF_3500, | |
175 | .dtv8_if_freq_khz = TDA10048_IF_4000, | |
6b926eca MK |
176 | .clk_freq_khz = TDA10048_CLK_16000, |
177 | }; | |
178 | ||
3ba71d21 MK |
179 | static struct s5h1409_config hauppauge_ezqam_config = { |
180 | .demod_address = 0x32 >> 1, | |
181 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
182 | .gpio = S5H1409_GPIO_OFF, | |
183 | .qam_if = 4000, | |
184 | .inversion = S5H1409_INVERSION_ON, | |
dfc1c08a ST |
185 | .status_mode = S5H1409_DEMODLOCKING, |
186 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
3ba71d21 MK |
187 | }; |
188 | ||
fc959bef | 189 | static struct s5h1409_config hauppauge_hvr1800lp_config = { |
d19770e5 ST |
190 | .demod_address = 0x32 >> 1, |
191 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
192 | .gpio = S5H1409_GPIO_OFF, | |
2b03238a | 193 | .qam_if = 44000, |
fe475163 | 194 | .inversion = S5H1409_INVERSION_OFF, |
dfc1c08a ST |
195 | .status_mode = S5H1409_DEMODLOCKING, |
196 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
d19770e5 ST |
197 | }; |
198 | ||
07b4a835 MK |
199 | static struct s5h1409_config hauppauge_hvr1500_config = { |
200 | .demod_address = 0x32 >> 1, | |
201 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
202 | .gpio = S5H1409_GPIO_OFF, | |
203 | .inversion = S5H1409_INVERSION_OFF, | |
dfc1c08a ST |
204 | .status_mode = S5H1409_DEMODLOCKING, |
205 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
07b4a835 MK |
206 | }; |
207 | ||
86184e06 | 208 | static struct mt2131_config hauppauge_generic_tunerconfig = { |
a77743bc ST |
209 | 0x61 |
210 | }; | |
211 | ||
9bc37caa MK |
212 | static struct lgdt330x_config fusionhdtv_5_express = { |
213 | .demod_address = 0x0e, | |
214 | .demod_chip = LGDT3303, | |
215 | .serial_mpeg = 0x40, | |
216 | }; | |
217 | ||
d1987d55 ST |
218 | static struct s5h1409_config hauppauge_hvr1500q_config = { |
219 | .demod_address = 0x32 >> 1, | |
220 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
221 | .gpio = S5H1409_GPIO_ON, | |
222 | .qam_if = 44000, | |
223 | .inversion = S5H1409_INVERSION_OFF, | |
dfc1c08a ST |
224 | .status_mode = S5H1409_DEMODLOCKING, |
225 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
d1987d55 ST |
226 | }; |
227 | ||
335377b7 MK |
228 | static struct s5h1409_config dvico_s5h1409_config = { |
229 | .demod_address = 0x32 >> 1, | |
230 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
231 | .gpio = S5H1409_GPIO_ON, | |
232 | .qam_if = 44000, | |
233 | .inversion = S5H1409_INVERSION_OFF, | |
234 | .status_mode = S5H1409_DEMODLOCKING, | |
235 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
236 | }; | |
237 | ||
52b50450 MK |
238 | static struct s5h1411_config dvico_s5h1411_config = { |
239 | .output_mode = S5H1411_SERIAL_OUTPUT, | |
240 | .gpio = S5H1411_GPIO_ON, | |
241 | .qam_if = S5H1411_IF_44000, | |
242 | .vsb_if = S5H1411_IF_44000, | |
243 | .inversion = S5H1411_INVERSION_OFF, | |
244 | .status_mode = S5H1411_DEMODLOCKING, | |
245 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
246 | }; | |
247 | ||
19bc5796 MK |
248 | static struct s5h1411_config hcw_s5h1411_config = { |
249 | .output_mode = S5H1411_SERIAL_OUTPUT, | |
250 | .gpio = S5H1411_GPIO_OFF, | |
251 | .vsb_if = S5H1411_IF_44000, | |
252 | .qam_if = S5H1411_IF_4000, | |
253 | .inversion = S5H1411_INVERSION_ON, | |
254 | .status_mode = S5H1411_DEMODLOCKING, | |
255 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
256 | }; | |
257 | ||
d1987d55 | 258 | static struct xc5000_config hauppauge_hvr1500q_tunerconfig = { |
e12671cf ST |
259 | .i2c_address = 0x61, |
260 | .if_khz = 5380, | |
d1987d55 ST |
261 | }; |
262 | ||
335377b7 MK |
263 | static struct xc5000_config dvico_xc5000_tunerconfig = { |
264 | .i2c_address = 0x64, | |
265 | .if_khz = 5380, | |
335377b7 MK |
266 | }; |
267 | ||
4041f1a5 MK |
268 | static struct tda829x_config tda829x_no_probe = { |
269 | .probe_tuner = TDA829X_DONT_PROBE, | |
270 | }; | |
271 | ||
f21e0d7f | 272 | static struct tda18271_std_map hauppauge_tda18271_std_map = { |
c0dc0c11 MK |
273 | .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, |
274 | .if_lvl = 6, .rfagc_top = 0x37 }, | |
275 | .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, | |
276 | .if_lvl = 6, .rfagc_top = 0x37 }, | |
f21e0d7f MK |
277 | }; |
278 | ||
b34cdc36 MK |
279 | static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = { |
280 | .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4, | |
281 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
282 | .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5, | |
283 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
284 | .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6, | |
285 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
286 | }; | |
287 | ||
f21e0d7f MK |
288 | static struct tda18271_config hauppauge_tda18271_config = { |
289 | .std_map = &hauppauge_tda18271_std_map, | |
290 | .gate = TDA18271_GATE_ANALOG, | |
04a68baa | 291 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
f21e0d7f MK |
292 | }; |
293 | ||
b3ea0166 | 294 | static struct tda18271_config hauppauge_hvr1200_tuner_config = { |
b34cdc36 | 295 | .std_map = &hauppauge_hvr1200_tda18271_std_map, |
b3ea0166 | 296 | .gate = TDA18271_GATE_ANALOG, |
04a68baa | 297 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
b3ea0166 ST |
298 | }; |
299 | ||
6b926eca MK |
300 | static struct tda18271_config hauppauge_hvr1210_tuner_config = { |
301 | .gate = TDA18271_GATE_DIGITAL, | |
04a68baa | 302 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
6b926eca MK |
303 | }; |
304 | ||
247bc540 | 305 | static struct tda18271_std_map hauppauge_hvr127x_std_map = { |
a5dbf457 MK |
306 | .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4, |
307 | .if_lvl = 1, .rfagc_top = 0x58 }, | |
308 | .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5, | |
309 | .if_lvl = 1, .rfagc_top = 0x58 }, | |
310 | }; | |
311 | ||
247bc540 MK |
312 | static struct tda18271_config hauppauge_hvr127x_config = { |
313 | .std_map = &hauppauge_hvr127x_std_map, | |
04a68baa | 314 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
a5dbf457 MK |
315 | }; |
316 | ||
247bc540 | 317 | static struct lgdt3305_config hauppauge_lgdt3305_config = { |
a5dbf457 MK |
318 | .i2c_addr = 0x0e, |
319 | .mpeg_mode = LGDT3305_MPEG_SERIAL, | |
320 | .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, | |
321 | .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, | |
322 | .deny_i2c_rptr = 1, | |
323 | .spectral_inversion = 1, | |
324 | .qam_if_khz = 4000, | |
325 | .vsb_if_khz = 3250, | |
326 | }; | |
327 | ||
b1721d0d | 328 | static struct dibx000_agc_config xc3028_agc_config = { |
66762373 ST |
329 | BAND_VHF | BAND_UHF, /* band_caps */ |
330 | ||
331 | /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, | |
332 | * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, | |
333 | * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, | |
334 | * P_agc_nb_est=2, P_agc_write=0 | |
335 | */ | |
336 | (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | | |
337 | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */ | |
338 | ||
339 | 712, /* inv_gain */ | |
340 | 21, /* time_stabiliz */ | |
341 | ||
342 | 0, /* alpha_level */ | |
343 | 118, /* thlock */ | |
344 | ||
345 | 0, /* wbd_inv */ | |
346 | 2867, /* wbd_ref */ | |
347 | 0, /* wbd_sel */ | |
348 | 2, /* wbd_alpha */ | |
349 | ||
350 | 0, /* agc1_max */ | |
351 | 0, /* agc1_min */ | |
352 | 39718, /* agc2_max */ | |
353 | 9930, /* agc2_min */ | |
354 | 0, /* agc1_pt1 */ | |
355 | 0, /* agc1_pt2 */ | |
356 | 0, /* agc1_pt3 */ | |
357 | 0, /* agc1_slope1 */ | |
358 | 0, /* agc1_slope2 */ | |
359 | 0, /* agc2_pt1 */ | |
360 | 128, /* agc2_pt2 */ | |
361 | 29, /* agc2_slope1 */ | |
362 | 29, /* agc2_slope2 */ | |
363 | ||
364 | 17, /* alpha_mant */ | |
365 | 27, /* alpha_exp */ | |
366 | 23, /* beta_mant */ | |
367 | 51, /* beta_exp */ | |
368 | ||
369 | 1, /* perform_agc_softsplit */ | |
370 | }; | |
371 | ||
372 | /* PLL Configuration for COFDM BW_MHz = 8.000000 | |
373 | * With external clock = 30.000000 */ | |
b1721d0d | 374 | static struct dibx000_bandwidth_config xc3028_bw_config = { |
66762373 ST |
375 | 60000, /* internal */ |
376 | 30000, /* sampling */ | |
377 | 1, /* pll_cfg: prediv */ | |
378 | 8, /* pll_cfg: ratio */ | |
379 | 3, /* pll_cfg: range */ | |
380 | 1, /* pll_cfg: reset */ | |
381 | 0, /* pll_cfg: bypass */ | |
382 | 0, /* misc: refdiv */ | |
383 | 0, /* misc: bypclk_div */ | |
384 | 1, /* misc: IO_CLK_en_core */ | |
385 | 1, /* misc: ADClkSrc */ | |
386 | 0, /* misc: modulo */ | |
387 | (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */ | |
388 | (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */ | |
389 | 20452225, /* timf */ | |
390 | 30000000 /* xtal_hz */ | |
391 | }; | |
392 | ||
393 | static struct dib7000p_config hauppauge_hvr1400_dib7000_config = { | |
394 | .output_mpeg2_in_188_bytes = 1, | |
395 | .hostbus_diversity = 1, | |
396 | .tuner_is_baseband = 0, | |
397 | .update_lna = NULL, | |
398 | ||
399 | .agc_config_count = 1, | |
400 | .agc = &xc3028_agc_config, | |
401 | .bw = &xc3028_bw_config, | |
402 | ||
403 | .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS, | |
404 | .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES, | |
405 | .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS, | |
406 | ||
407 | .pwm_freq_div = 0, | |
408 | .agc_control = NULL, | |
409 | .spur_protect = 0, | |
410 | ||
411 | .output_mode = OUTMODE_MPEG2_SERIAL, | |
412 | }; | |
413 | ||
aef2d186 ST |
414 | static struct zl10353_config dvico_fusionhdtv_xc3028 = { |
415 | .demod_address = 0x0f, | |
416 | .if2 = 45600, | |
417 | .no_tuner = 1, | |
d4dc673d | 418 | .disable_i2c_gate_ctrl = 1, |
aef2d186 ST |
419 | }; |
420 | ||
f867c3f4 IL |
421 | static struct stv0900_reg stv0900_ts_regs[] = { |
422 | { R0900_TSGENERAL, 0x00 }, | |
423 | { R0900_P1_TSSPEED, 0x40 }, | |
424 | { R0900_P2_TSSPEED, 0x40 }, | |
425 | { R0900_P1_TSCFGM, 0xc0 }, | |
426 | { R0900_P2_TSCFGM, 0xc0 }, | |
427 | { R0900_P1_TSCFGH, 0xe0 }, | |
428 | { R0900_P2_TSCFGH, 0xe0 }, | |
429 | { R0900_P1_TSCFGL, 0x20 }, | |
430 | { R0900_P2_TSCFGL, 0x20 }, | |
431 | { 0xffff, 0xff }, /* terminate */ | |
432 | }; | |
433 | ||
5a23b076 IL |
434 | static struct stv0900_config netup_stv0900_config = { |
435 | .demod_address = 0x68, | |
29372a8d | 436 | .demod_mode = 1, /* dual */ |
644c7ef0 | 437 | .xtal = 8000000, |
5a23b076 IL |
438 | .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */ |
439 | .diseqc_mode = 2,/* 2/3 PWM */ | |
f867c3f4 | 440 | .ts_config_regs = stv0900_ts_regs, |
5a23b076 IL |
441 | .tun1_maddress = 0,/* 0x60 */ |
442 | .tun2_maddress = 3,/* 0x63 */ | |
443 | .tun1_adc = 1,/* 1 Vpp */ | |
444 | .tun2_adc = 1,/* 1 Vpp */ | |
445 | }; | |
446 | ||
447 | static struct stv6110_config netup_stv6110_tunerconfig_a = { | |
448 | .i2c_address = 0x60, | |
644c7ef0 AO |
449 | .mclk = 16000000, |
450 | .clk_div = 1, | |
873688cd | 451 | .gain = 8, /* +16 dB - maximum gain */ |
5a23b076 IL |
452 | }; |
453 | ||
454 | static struct stv6110_config netup_stv6110_tunerconfig_b = { | |
455 | .i2c_address = 0x63, | |
644c7ef0 AO |
456 | .mclk = 16000000, |
457 | .clk_div = 1, | |
873688cd | 458 | .gain = 8, /* +16 dB - maximum gain */ |
5a23b076 IL |
459 | }; |
460 | ||
96318d0c | 461 | static struct cx24116_config tbs_cx24116_config = { |
09ea33e5 | 462 | .demod_address = 0x55, |
96318d0c IL |
463 | }; |
464 | ||
09ea33e5 IL |
465 | static struct ds3000_config tevii_ds3000_config = { |
466 | .demod_address = 0x68, | |
579943f5 IL |
467 | }; |
468 | ||
c9b8b04b IL |
469 | static struct cx24116_config dvbworld_cx24116_config = { |
470 | .demod_address = 0x05, | |
471 | }; | |
472 | ||
493b7127 DW |
473 | static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = { |
474 | .prod = LGS8GXX_PROD_LGS8GL5, | |
475 | .demod_address = 0x19, | |
476 | .serial_ts = 0, | |
477 | .ts_clk_pol = 1, | |
478 | .ts_clk_gated = 1, | |
479 | .if_clk_freq = 30400, /* 30.4 MHz */ | |
480 | .if_freq = 5380, /* 5.38 MHz */ | |
481 | .if_neg_center = 1, | |
482 | .ext_adc = 0, | |
483 | .adc_signed = 0, | |
484 | .if_neg_edge = 0, | |
485 | }; | |
486 | ||
487 | static struct xc5000_config mygica_x8506_xc5000_config = { | |
488 | .i2c_address = 0x61, | |
489 | .if_khz = 5380, | |
490 | }; | |
491 | ||
a7d44baa | 492 | static int cx23885_dvb_set_frontend(struct dvb_frontend *fe) |
f35b9e80 | 493 | { |
a7d44baa | 494 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
f35b9e80 MK |
495 | struct cx23885_tsport *port = fe->dvb->priv; |
496 | struct cx23885_dev *dev = port->dev; | |
497 | ||
498 | switch (dev->board) { | |
499 | case CX23885_BOARD_HAUPPAUGE_HVR1275: | |
a7d44baa | 500 | switch (p->modulation) { |
f35b9e80 MK |
501 | case VSB_8: |
502 | cx23885_gpio_clear(dev, GPIO_5); | |
503 | break; | |
504 | case QAM_64: | |
505 | case QAM_256: | |
506 | default: | |
507 | cx23885_gpio_set(dev, GPIO_5); | |
508 | break; | |
509 | } | |
510 | break; | |
6f0d8c02 DW |
511 | case CX23885_BOARD_MYGICA_X8506: |
512 | case CX23885_BOARD_MAGICPRO_PROHDTVE2: | |
513 | /* Select Digital TV */ | |
514 | cx23885_gpio_set(dev, GPIO_0); | |
515 | break; | |
f35b9e80 | 516 | } |
5bdd3962 | 517 | return 0; |
f35b9e80 MK |
518 | } |
519 | ||
2365b2d3 DW |
520 | static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = { |
521 | .prod = LGS8GXX_PROD_LGS8G75, | |
522 | .demod_address = 0x19, | |
523 | .serial_ts = 0, | |
524 | .ts_clk_pol = 1, | |
525 | .ts_clk_gated = 1, | |
526 | .if_clk_freq = 30400, /* 30.4 MHz */ | |
527 | .if_freq = 6500, /* 6.50 MHz */ | |
528 | .if_neg_center = 1, | |
529 | .ext_adc = 0, | |
530 | .adc_signed = 1, | |
531 | .adc_vpp = 2, /* 1.6 Vpp */ | |
532 | .if_neg_edge = 1, | |
533 | }; | |
534 | ||
535 | static struct xc5000_config magicpro_prohdtve2_xc5000_config = { | |
536 | .i2c_address = 0x61, | |
537 | .if_khz = 6500, | |
538 | }; | |
539 | ||
ea5697fe DW |
540 | static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = { |
541 | .prod = ATBM8830_PROD_8830, | |
542 | .demod_address = 0x44, | |
543 | .serial_ts = 0, | |
544 | .ts_sampling_edge = 1, | |
545 | .ts_clk_gated = 0, | |
546 | .osc_clk_freq = 30400, /* in kHz */ | |
547 | .if_freq = 0, /* zero IF */ | |
548 | .zif_swap_iq = 1, | |
c245c75c DW |
549 | .agc_min = 0x2E, |
550 | .agc_max = 0xFF, | |
551 | .agc_hold_loop = 0, | |
ea5697fe DW |
552 | }; |
553 | ||
554 | static struct max2165_config mygic_x8558pro_max2165_cfg1 = { | |
555 | .i2c_address = 0x60, | |
556 | .osc_clk = 20 | |
557 | }; | |
558 | ||
559 | static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = { | |
560 | .prod = ATBM8830_PROD_8830, | |
561 | .demod_address = 0x44, | |
562 | .serial_ts = 1, | |
563 | .ts_sampling_edge = 1, | |
564 | .ts_clk_gated = 0, | |
565 | .osc_clk_freq = 30400, /* in kHz */ | |
566 | .if_freq = 0, /* zero IF */ | |
567 | .zif_swap_iq = 1, | |
c245c75c DW |
568 | .agc_min = 0x2E, |
569 | .agc_max = 0xFF, | |
570 | .agc_hold_loop = 0, | |
ea5697fe DW |
571 | }; |
572 | ||
573 | static struct max2165_config mygic_x8558pro_max2165_cfg2 = { | |
574 | .i2c_address = 0x60, | |
575 | .osc_clk = 20 | |
576 | }; | |
78db8547 IL |
577 | static struct stv0367_config netup_stv0367_config[] = { |
578 | { | |
579 | .demod_address = 0x1c, | |
580 | .xtal = 27000000, | |
581 | .if_khz = 4500, | |
582 | .if_iq_mode = 0, | |
583 | .ts_mode = 1, | |
584 | .clk_pol = 0, | |
585 | }, { | |
586 | .demod_address = 0x1d, | |
587 | .xtal = 27000000, | |
588 | .if_khz = 4500, | |
589 | .if_iq_mode = 0, | |
590 | .ts_mode = 1, | |
591 | .clk_pol = 0, | |
592 | }, | |
593 | }; | |
594 | ||
595 | static struct xc5000_config netup_xc5000_config[] = { | |
596 | { | |
597 | .i2c_address = 0x61, | |
598 | .if_khz = 4500, | |
599 | }, { | |
600 | .i2c_address = 0x64, | |
601 | .if_khz = 4500, | |
602 | }, | |
603 | }; | |
604 | ||
722c90eb SR |
605 | static struct drxk_config terratec_drxk_config[] = { |
606 | { | |
607 | .adr = 0x29, | |
608 | .no_i2c_bridge = 1, | |
609 | }, { | |
610 | .adr = 0x2a, | |
611 | .no_i2c_bridge = 1, | |
612 | }, | |
613 | }; | |
614 | ||
615 | static struct mt2063_config terratec_mt2063_config[] = { | |
616 | { | |
617 | .tuner_address = 0x60, | |
618 | }, { | |
619 | .tuner_address = 0x67, | |
620 | }, | |
621 | }; | |
622 | ||
78db8547 IL |
623 | int netup_altera_fpga_rw(void *device, int flag, int data, int read) |
624 | { | |
625 | struct cx23885_dev *dev = (struct cx23885_dev *)device; | |
626 | unsigned long timeout = jiffies + msecs_to_jiffies(1); | |
d164460f | 627 | uint32_t mem = 0; |
78db8547 | 628 | |
d164460f | 629 | mem = cx_read(MC417_RWD); |
78db8547 IL |
630 | if (read) |
631 | cx_set(MC417_OEN, ALT_DATA); | |
632 | else { | |
633 | cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */ | |
78db8547 IL |
634 | mem &= ~ALT_DATA; |
635 | mem |= (data & ALT_DATA); | |
78db8547 IL |
636 | } |
637 | ||
638 | if (flag) | |
d164460f | 639 | mem |= ALT_AD_RG; |
78db8547 | 640 | else |
d164460f | 641 | mem &= ~ALT_AD_RG; |
78db8547 | 642 | |
d164460f | 643 | mem &= ~ALT_CS; |
78db8547 | 644 | if (read) |
d164460f | 645 | mem = (mem & ~ALT_RD) | ALT_WR; |
78db8547 | 646 | else |
d164460f AO |
647 | mem = (mem & ~ALT_WR) | ALT_RD; |
648 | ||
649 | cx_write(MC417_RWD, mem); /* start RW cycle */ | |
78db8547 IL |
650 | |
651 | for (;;) { | |
652 | mem = cx_read(MC417_RWD); | |
653 | if ((mem & ALT_RDY) == 0) | |
654 | break; | |
655 | if (time_after(jiffies, timeout)) | |
656 | break; | |
657 | udelay(1); | |
658 | } | |
659 | ||
660 | cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS); | |
661 | if (read) | |
662 | return mem & ALT_DATA; | |
663 | ||
664 | return 0; | |
665 | }; | |
ea5697fe | 666 | |
d19770e5 ST |
667 | static int dvb_register(struct cx23885_tsport *port) |
668 | { | |
669 | struct cx23885_dev *dev = port->dev; | |
493b7127 | 670 | struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL; |
78db8547 IL |
671 | struct videobuf_dvb_frontend *fe0, *fe1 = NULL; |
672 | int mfe_shared = 0; /* bus not shared by default */ | |
5a23b076 | 673 | int ret; |
363c35fc | 674 | |
f972e0bd | 675 | /* Get the first frontend */ |
92abe9ee | 676 | fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); |
363c35fc ST |
677 | if (!fe0) |
678 | return -EINVAL; | |
d19770e5 ST |
679 | |
680 | /* init struct videobuf_dvb */ | |
363c35fc | 681 | fe0->dvb.name = dev->name; |
d19770e5 | 682 | |
78db8547 IL |
683 | /* multi-frontend gate control is undefined or defaults to fe0 */ |
684 | port->frontends.gate = 0; | |
685 | ||
686 | /* Sets the gate control callback to be used by i2c command calls */ | |
687 | port->gate_ctrl = cx23885_dvb_gate_ctrl; | |
688 | ||
d19770e5 ST |
689 | /* init frontend */ |
690 | switch (dev->board) { | |
a77743bc | 691 | case CX23885_BOARD_HAUPPAUGE_HVR1250: |
f139fa71 | 692 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 693 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
86184e06 | 694 | &hauppauge_generic_config, |
f139fa71 | 695 | &i2c_bus->i2c_adap); |
363c35fc ST |
696 | if (fe0->dvb.frontend != NULL) { |
697 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
f139fa71 | 698 | &i2c_bus->i2c_adap, |
86184e06 | 699 | &hauppauge_generic_tunerconfig, 0); |
d19770e5 ST |
700 | } |
701 | break; | |
a5dbf457 | 702 | case CX23885_BOARD_HAUPPAUGE_HVR1270: |
d099becb | 703 | case CX23885_BOARD_HAUPPAUGE_HVR1275: |
a5dbf457 MK |
704 | i2c_bus = &dev->i2c_bus[0]; |
705 | fe0->dvb.frontend = dvb_attach(lgdt3305_attach, | |
247bc540 | 706 | &hauppauge_lgdt3305_config, |
a5dbf457 MK |
707 | &i2c_bus->i2c_adap); |
708 | if (fe0->dvb.frontend != NULL) { | |
709 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
710 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
247bc540 | 711 | &hauppauge_hvr127x_config); |
a5dbf457 MK |
712 | } |
713 | break; | |
19bc5796 | 714 | case CX23885_BOARD_HAUPPAUGE_HVR1255: |
0ac60acb | 715 | case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: |
19bc5796 MK |
716 | i2c_bus = &dev->i2c_bus[0]; |
717 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
718 | &hcw_s5h1411_config, | |
719 | &i2c_bus->i2c_adap); | |
720 | if (fe0->dvb.frontend != NULL) { | |
721 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
722 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
723 | &hauppauge_tda18271_config); | |
724 | } | |
0ac60acb DH |
725 | |
726 | tda18271_attach(&dev->ts1.analog_fe, | |
727 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
728 | &hauppauge_tda18271_config); | |
729 | ||
19bc5796 | 730 | break; |
3ba71d21 MK |
731 | case CX23885_BOARD_HAUPPAUGE_HVR1800: |
732 | i2c_bus = &dev->i2c_bus[0]; | |
92abe9ee | 733 | switch (alt_tuner) { |
3ba71d21 | 734 | case 1: |
363c35fc | 735 | fe0->dvb.frontend = |
3ba71d21 MK |
736 | dvb_attach(s5h1409_attach, |
737 | &hauppauge_ezqam_config, | |
738 | &i2c_bus->i2c_adap); | |
363c35fc ST |
739 | if (fe0->dvb.frontend != NULL) { |
740 | dvb_attach(tda829x_attach, fe0->dvb.frontend, | |
3ba71d21 | 741 | &dev->i2c_bus[1].i2c_adap, 0x42, |
4041f1a5 | 742 | &tda829x_no_probe); |
363c35fc | 743 | dvb_attach(tda18271_attach, fe0->dvb.frontend, |
4041f1a5 | 744 | 0x60, &dev->i2c_bus[1].i2c_adap, |
f21e0d7f | 745 | &hauppauge_tda18271_config); |
3ba71d21 MK |
746 | } |
747 | break; | |
748 | case 0: | |
749 | default: | |
363c35fc | 750 | fe0->dvb.frontend = |
3ba71d21 MK |
751 | dvb_attach(s5h1409_attach, |
752 | &hauppauge_generic_config, | |
753 | &i2c_bus->i2c_adap); | |
363c35fc ST |
754 | if (fe0->dvb.frontend != NULL) |
755 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
3ba71d21 MK |
756 | &i2c_bus->i2c_adap, |
757 | &hauppauge_generic_tunerconfig, 0); | |
758 | break; | |
759 | } | |
760 | break; | |
fc959bef | 761 | case CX23885_BOARD_HAUPPAUGE_HVR1800lp: |
f139fa71 | 762 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 763 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
fc959bef | 764 | &hauppauge_hvr1800lp_config, |
f139fa71 | 765 | &i2c_bus->i2c_adap); |
363c35fc ST |
766 | if (fe0->dvb.frontend != NULL) { |
767 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
f139fa71 | 768 | &i2c_bus->i2c_adap, |
fc959bef ST |
769 | &hauppauge_generic_tunerconfig, 0); |
770 | } | |
771 | break; | |
9bc37caa | 772 | case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: |
f139fa71 | 773 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 774 | fe0->dvb.frontend = dvb_attach(lgdt330x_attach, |
9bc37caa | 775 | &fusionhdtv_5_express, |
f139fa71 | 776 | &i2c_bus->i2c_adap); |
363c35fc ST |
777 | if (fe0->dvb.frontend != NULL) { |
778 | dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
827855d3 MK |
779 | &i2c_bus->i2c_adap, 0x61, |
780 | TUNER_LG_TDVS_H06XF); | |
9bc37caa MK |
781 | } |
782 | break; | |
d1987d55 ST |
783 | case CX23885_BOARD_HAUPPAUGE_HVR1500Q: |
784 | i2c_bus = &dev->i2c_bus[1]; | |
363c35fc | 785 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
d1987d55 ST |
786 | &hauppauge_hvr1500q_config, |
787 | &dev->i2c_bus[0].i2c_adap); | |
363c35fc ST |
788 | if (fe0->dvb.frontend != NULL) |
789 | dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
30650961 MK |
790 | &i2c_bus->i2c_adap, |
791 | &hauppauge_hvr1500q_tunerconfig); | |
d1987d55 | 792 | break; |
07b4a835 MK |
793 | case CX23885_BOARD_HAUPPAUGE_HVR1500: |
794 | i2c_bus = &dev->i2c_bus[1]; | |
363c35fc | 795 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
07b4a835 MK |
796 | &hauppauge_hvr1500_config, |
797 | &dev->i2c_bus[0].i2c_adap); | |
363c35fc | 798 | if (fe0->dvb.frontend != NULL) { |
07b4a835 MK |
799 | struct dvb_frontend *fe; |
800 | struct xc2028_config cfg = { | |
801 | .i2c_adap = &i2c_bus->i2c_adap, | |
802 | .i2c_addr = 0x61, | |
07b4a835 MK |
803 | }; |
804 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 805 | .fname = XC2028_DEFAULT_FIRMWARE, |
07b4a835 | 806 | .max_len = 64, |
52c3d29c | 807 | .demod = XC3028_FE_OREN538, |
07b4a835 MK |
808 | }; |
809 | ||
810 | fe = dvb_attach(xc2028_attach, | |
363c35fc | 811 | fe0->dvb.frontend, &cfg); |
07b4a835 MK |
812 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) |
813 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
814 | } | |
815 | break; | |
b3ea0166 | 816 | case CX23885_BOARD_HAUPPAUGE_HVR1200: |
a780a31c | 817 | case CX23885_BOARD_HAUPPAUGE_HVR1700: |
b3ea0166 | 818 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 819 | fe0->dvb.frontend = dvb_attach(tda10048_attach, |
b3ea0166 ST |
820 | &hauppauge_hvr1200_config, |
821 | &i2c_bus->i2c_adap); | |
363c35fc ST |
822 | if (fe0->dvb.frontend != NULL) { |
823 | dvb_attach(tda829x_attach, fe0->dvb.frontend, | |
b3ea0166 ST |
824 | &dev->i2c_bus[1].i2c_adap, 0x42, |
825 | &tda829x_no_probe); | |
363c35fc | 826 | dvb_attach(tda18271_attach, fe0->dvb.frontend, |
b3ea0166 ST |
827 | 0x60, &dev->i2c_bus[1].i2c_adap, |
828 | &hauppauge_hvr1200_tuner_config); | |
6b926eca MK |
829 | } |
830 | break; | |
831 | case CX23885_BOARD_HAUPPAUGE_HVR1210: | |
832 | i2c_bus = &dev->i2c_bus[0]; | |
833 | fe0->dvb.frontend = dvb_attach(tda10048_attach, | |
834 | &hauppauge_hvr1210_config, | |
835 | &i2c_bus->i2c_adap); | |
836 | if (fe0->dvb.frontend != NULL) { | |
837 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
838 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
839 | &hauppauge_hvr1210_tuner_config); | |
b3ea0166 ST |
840 | } |
841 | break; | |
66762373 ST |
842 | case CX23885_BOARD_HAUPPAUGE_HVR1400: |
843 | i2c_bus = &dev->i2c_bus[0]; | |
363c35fc | 844 | fe0->dvb.frontend = dvb_attach(dib7000p_attach, |
66762373 ST |
845 | &i2c_bus->i2c_adap, |
846 | 0x12, &hauppauge_hvr1400_dib7000_config); | |
363c35fc | 847 | if (fe0->dvb.frontend != NULL) { |
66762373 ST |
848 | struct dvb_frontend *fe; |
849 | struct xc2028_config cfg = { | |
850 | .i2c_adap = &dev->i2c_bus[1].i2c_adap, | |
851 | .i2c_addr = 0x64, | |
66762373 ST |
852 | }; |
853 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 854 | .fname = XC3028L_DEFAULT_FIRMWARE, |
66762373 | 855 | .max_len = 64, |
9bed77ee | 856 | .demod = XC3028_FE_DIBCOM52, |
9c8ced51 ST |
857 | /* This is true for all demods with |
858 | v36 firmware? */ | |
0975fc68 | 859 | .type = XC2028_D2633, |
66762373 ST |
860 | }; |
861 | ||
862 | fe = dvb_attach(xc2028_attach, | |
363c35fc | 863 | fe0->dvb.frontend, &cfg); |
66762373 ST |
864 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) |
865 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
866 | } | |
867 | break; | |
335377b7 MK |
868 | case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: |
869 | i2c_bus = &dev->i2c_bus[port->nr - 1]; | |
870 | ||
363c35fc | 871 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
335377b7 MK |
872 | &dvico_s5h1409_config, |
873 | &i2c_bus->i2c_adap); | |
363c35fc ST |
874 | if (fe0->dvb.frontend == NULL) |
875 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
52b50450 MK |
876 | &dvico_s5h1411_config, |
877 | &i2c_bus->i2c_adap); | |
363c35fc ST |
878 | if (fe0->dvb.frontend != NULL) |
879 | dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
30650961 MK |
880 | &i2c_bus->i2c_adap, |
881 | &dvico_xc5000_tunerconfig); | |
335377b7 | 882 | break; |
aef2d186 ST |
883 | case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: { |
884 | i2c_bus = &dev->i2c_bus[port->nr - 1]; | |
885 | ||
363c35fc | 886 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
aef2d186 ST |
887 | &dvico_fusionhdtv_xc3028, |
888 | &i2c_bus->i2c_adap); | |
363c35fc | 889 | if (fe0->dvb.frontend != NULL) { |
aef2d186 ST |
890 | struct dvb_frontend *fe; |
891 | struct xc2028_config cfg = { | |
892 | .i2c_adap = &i2c_bus->i2c_adap, | |
893 | .i2c_addr = 0x61, | |
aef2d186 ST |
894 | }; |
895 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 896 | .fname = XC2028_DEFAULT_FIRMWARE, |
aef2d186 ST |
897 | .max_len = 64, |
898 | .demod = XC3028_FE_ZARLINK456, | |
899 | }; | |
900 | ||
363c35fc | 901 | fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, |
aef2d186 ST |
902 | &cfg); |
903 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) | |
904 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
905 | } | |
906 | break; | |
907 | } | |
4c56b04a | 908 | case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: |
9bb1b7e8 | 909 | case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: |
34e383dd | 910 | case CX23885_BOARD_COMPRO_VIDEOMATE_E800: |
4c56b04a ST |
911 | i2c_bus = &dev->i2c_bus[0]; |
912 | ||
363c35fc | 913 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
4c56b04a ST |
914 | &dvico_fusionhdtv_xc3028, |
915 | &i2c_bus->i2c_adap); | |
363c35fc | 916 | if (fe0->dvb.frontend != NULL) { |
4c56b04a ST |
917 | struct dvb_frontend *fe; |
918 | struct xc2028_config cfg = { | |
919 | .i2c_adap = &dev->i2c_bus[1].i2c_adap, | |
920 | .i2c_addr = 0x61, | |
4c56b04a ST |
921 | }; |
922 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 923 | .fname = XC2028_DEFAULT_FIRMWARE, |
4c56b04a ST |
924 | .max_len = 64, |
925 | .demod = XC3028_FE_ZARLINK456, | |
926 | }; | |
927 | ||
363c35fc | 928 | fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, |
4c56b04a ST |
929 | &cfg); |
930 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) | |
931 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
932 | } | |
96318d0c | 933 | break; |
0cf8af57 | 934 | case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: |
935 | i2c_bus = &dev->i2c_bus[0]; | |
936 | ||
937 | fe0->dvb.frontend = dvb_attach(zl10353_attach, | |
938 | &dvico_fusionhdtv_xc3028, | |
939 | &i2c_bus->i2c_adap); | |
940 | if (fe0->dvb.frontend != NULL) { | |
941 | struct dvb_frontend *fe; | |
942 | struct xc4000_config cfg = { | |
943 | .i2c_address = 0x61, | |
944 | .default_pm = 0, | |
945 | .dvb_amplitude = 134, | |
946 | .set_smoothedcvbs = 1, | |
947 | .if_khz = 4560 | |
948 | }; | |
949 | ||
950 | fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, | |
951 | &dev->i2c_bus[1].i2c_adap, &cfg); | |
a7c8aada MS |
952 | if (!fe) { |
953 | printk(KERN_ERR "%s/2: xc4000 attach failed\n", | |
954 | dev->name); | |
955 | goto frontend_detach; | |
956 | } | |
0cf8af57 | 957 | } |
958 | break; | |
96318d0c | 959 | case CX23885_BOARD_TBS_6920: |
09ea33e5 | 960 | i2c_bus = &dev->i2c_bus[1]; |
96318d0c IL |
961 | |
962 | fe0->dvb.frontend = dvb_attach(cx24116_attach, | |
09ea33e5 IL |
963 | &tbs_cx24116_config, |
964 | &i2c_bus->i2c_adap); | |
96318d0c | 965 | if (fe0->dvb.frontend != NULL) |
09ea33e5 | 966 | fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; |
96318d0c | 967 | |
579943f5 IL |
968 | break; |
969 | case CX23885_BOARD_TEVII_S470: | |
970 | i2c_bus = &dev->i2c_bus[1]; | |
971 | ||
09ea33e5 IL |
972 | fe0->dvb.frontend = dvb_attach(ds3000_attach, |
973 | &tevii_ds3000_config, | |
974 | &i2c_bus->i2c_adap); | |
579943f5 | 975 | if (fe0->dvb.frontend != NULL) |
09ea33e5 | 976 | fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; |
579943f5 | 977 | |
4c56b04a | 978 | break; |
c9b8b04b IL |
979 | case CX23885_BOARD_DVBWORLD_2005: |
980 | i2c_bus = &dev->i2c_bus[1]; | |
981 | ||
982 | fe0->dvb.frontend = dvb_attach(cx24116_attach, | |
983 | &dvbworld_cx24116_config, | |
984 | &i2c_bus->i2c_adap); | |
985 | break; | |
5a23b076 IL |
986 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: |
987 | i2c_bus = &dev->i2c_bus[0]; | |
988 | switch (port->nr) { | |
989 | /* port B */ | |
990 | case 1: | |
991 | fe0->dvb.frontend = dvb_attach(stv0900_attach, | |
992 | &netup_stv0900_config, | |
993 | &i2c_bus->i2c_adap, 0); | |
994 | if (fe0->dvb.frontend != NULL) { | |
995 | if (dvb_attach(stv6110_attach, | |
996 | fe0->dvb.frontend, | |
997 | &netup_stv6110_tunerconfig_a, | |
998 | &i2c_bus->i2c_adap)) { | |
999 | if (!dvb_attach(lnbh24_attach, | |
1000 | fe0->dvb.frontend, | |
1001 | &i2c_bus->i2c_adap, | |
9329fb5b AO |
1002 | LNBH24_PCL | LNBH24_TTX, |
1003 | LNBH24_TEN, 0x09)) | |
5a23b076 IL |
1004 | printk(KERN_ERR |
1005 | "No LNBH24 found!\n"); | |
1006 | ||
1007 | } | |
1008 | } | |
1009 | break; | |
1010 | /* port C */ | |
1011 | case 2: | |
1012 | fe0->dvb.frontend = dvb_attach(stv0900_attach, | |
1013 | &netup_stv0900_config, | |
1014 | &i2c_bus->i2c_adap, 1); | |
1015 | if (fe0->dvb.frontend != NULL) { | |
1016 | if (dvb_attach(stv6110_attach, | |
1017 | fe0->dvb.frontend, | |
1018 | &netup_stv6110_tunerconfig_b, | |
1019 | &i2c_bus->i2c_adap)) { | |
1020 | if (!dvb_attach(lnbh24_attach, | |
1021 | fe0->dvb.frontend, | |
1022 | &i2c_bus->i2c_adap, | |
9329fb5b AO |
1023 | LNBH24_PCL | LNBH24_TTX, |
1024 | LNBH24_TEN, 0x0a)) | |
5a23b076 IL |
1025 | printk(KERN_ERR |
1026 | "No LNBH24 found!\n"); | |
1027 | ||
1028 | } | |
1029 | } | |
1030 | break; | |
1031 | } | |
1032 | break; | |
493b7127 DW |
1033 | case CX23885_BOARD_MYGICA_X8506: |
1034 | i2c_bus = &dev->i2c_bus[0]; | |
1035 | i2c_bus2 = &dev->i2c_bus[1]; | |
1036 | fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, | |
1037 | &mygica_x8506_lgs8gl5_config, | |
1038 | &i2c_bus->i2c_adap); | |
1039 | if (fe0->dvb.frontend != NULL) { | |
1040 | dvb_attach(xc5000_attach, | |
1041 | fe0->dvb.frontend, | |
1042 | &i2c_bus2->i2c_adap, | |
1043 | &mygica_x8506_xc5000_config); | |
1044 | } | |
1045 | break; | |
2365b2d3 DW |
1046 | case CX23885_BOARD_MAGICPRO_PROHDTVE2: |
1047 | i2c_bus = &dev->i2c_bus[0]; | |
1048 | i2c_bus2 = &dev->i2c_bus[1]; | |
1049 | fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, | |
1050 | &magicpro_prohdtve2_lgs8g75_config, | |
1051 | &i2c_bus->i2c_adap); | |
1052 | if (fe0->dvb.frontend != NULL) { | |
1053 | dvb_attach(xc5000_attach, | |
1054 | fe0->dvb.frontend, | |
1055 | &i2c_bus2->i2c_adap, | |
1056 | &magicpro_prohdtve2_xc5000_config); | |
1057 | } | |
1058 | break; | |
13697380 | 1059 | case CX23885_BOARD_HAUPPAUGE_HVR1850: |
35045137 ST |
1060 | i2c_bus = &dev->i2c_bus[0]; |
1061 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
1062 | &hcw_s5h1411_config, | |
1063 | &i2c_bus->i2c_adap); | |
1064 | if (fe0->dvb.frontend != NULL) | |
1065 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
1066 | 0x60, &dev->i2c_bus[0].i2c_adap, | |
1067 | &hauppauge_tda18271_config); | |
1068 | ||
1069 | tda18271_attach(&dev->ts1.analog_fe, | |
1070 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
1071 | &hauppauge_tda18271_config); | |
1072 | ||
1073 | break; | |
aee0b24c | 1074 | case CX23885_BOARD_HAUPPAUGE_HVR1290: |
13697380 ST |
1075 | i2c_bus = &dev->i2c_bus[0]; |
1076 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
1077 | &hcw_s5h1411_config, | |
1078 | &i2c_bus->i2c_adap); | |
1079 | if (fe0->dvb.frontend != NULL) | |
1080 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
1081 | 0x60, &dev->i2c_bus[0].i2c_adap, | |
1082 | &hauppauge_tda18271_config); | |
1083 | break; | |
ea5697fe DW |
1084 | case CX23885_BOARD_MYGICA_X8558PRO: |
1085 | switch (port->nr) { | |
1086 | /* port B */ | |
1087 | case 1: | |
1088 | i2c_bus = &dev->i2c_bus[0]; | |
1089 | fe0->dvb.frontend = dvb_attach(atbm8830_attach, | |
1090 | &mygica_x8558pro_atbm8830_cfg1, | |
1091 | &i2c_bus->i2c_adap); | |
1092 | if (fe0->dvb.frontend != NULL) { | |
1093 | dvb_attach(max2165_attach, | |
1094 | fe0->dvb.frontend, | |
1095 | &i2c_bus->i2c_adap, | |
1096 | &mygic_x8558pro_max2165_cfg1); | |
1097 | } | |
1098 | break; | |
1099 | /* port C */ | |
1100 | case 2: | |
1101 | i2c_bus = &dev->i2c_bus[1]; | |
1102 | fe0->dvb.frontend = dvb_attach(atbm8830_attach, | |
1103 | &mygica_x8558pro_atbm8830_cfg2, | |
1104 | &i2c_bus->i2c_adap); | |
1105 | if (fe0->dvb.frontend != NULL) { | |
1106 | dvb_attach(max2165_attach, | |
1107 | fe0->dvb.frontend, | |
1108 | &i2c_bus->i2c_adap, | |
1109 | &mygic_x8558pro_max2165_cfg2); | |
1110 | } | |
1111 | break; | |
1112 | } | |
1113 | break; | |
78db8547 IL |
1114 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: |
1115 | i2c_bus = &dev->i2c_bus[0]; | |
1116 | mfe_shared = 1;/* MFE */ | |
1117 | port->frontends.gate = 0;/* not clear for me yet */ | |
1118 | /* ports B, C */ | |
1119 | /* MFE frontend 1 DVB-T */ | |
1120 | fe0->dvb.frontend = dvb_attach(stv0367ter_attach, | |
1121 | &netup_stv0367_config[port->nr - 1], | |
1122 | &i2c_bus->i2c_adap); | |
4174ebf5 | 1123 | if (fe0->dvb.frontend != NULL) { |
78db8547 IL |
1124 | if (NULL == dvb_attach(xc5000_attach, |
1125 | fe0->dvb.frontend, | |
1126 | &i2c_bus->i2c_adap, | |
1127 | &netup_xc5000_config[port->nr - 1])) | |
1128 | goto frontend_detach; | |
4174ebf5 AO |
1129 | /* load xc5000 firmware */ |
1130 | fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend); | |
1131 | } | |
78db8547 IL |
1132 | /* MFE frontend 2 */ |
1133 | fe1 = videobuf_dvb_get_frontend(&port->frontends, 2); | |
1134 | if (fe1 == NULL) | |
1135 | goto frontend_detach; | |
1136 | /* DVB-C init */ | |
1137 | fe1->dvb.frontend = dvb_attach(stv0367cab_attach, | |
1138 | &netup_stv0367_config[port->nr - 1], | |
1139 | &i2c_bus->i2c_adap); | |
1140 | if (fe1->dvb.frontend != NULL) { | |
1141 | fe1->dvb.frontend->id = 1; | |
1142 | if (NULL == dvb_attach(xc5000_attach, | |
1143 | fe1->dvb.frontend, | |
1144 | &i2c_bus->i2c_adap, | |
1145 | &netup_xc5000_config[port->nr - 1])) | |
1146 | goto frontend_detach; | |
1147 | } | |
1148 | break; | |
722c90eb SR |
1149 | case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: |
1150 | i2c_bus = &dev->i2c_bus[0]; | |
1151 | i2c_bus2 = &dev->i2c_bus[1]; | |
1152 | ||
1153 | switch (port->nr) { | |
1154 | /* port b */ | |
1155 | case 1: | |
1156 | fe0->dvb.frontend = dvb_attach(drxk_attach, | |
1157 | &terratec_drxk_config[0], | |
1158 | &i2c_bus->i2c_adap); | |
1159 | if (fe0->dvb.frontend != NULL) { | |
1160 | if (!dvb_attach(mt2063_attach, | |
1161 | fe0->dvb.frontend, | |
1162 | &terratec_mt2063_config[0], | |
1163 | &i2c_bus2->i2c_adap)) | |
1164 | goto frontend_detach; | |
1165 | } | |
1166 | break; | |
1167 | /* port c */ | |
1168 | case 2: | |
1169 | fe0->dvb.frontend = dvb_attach(drxk_attach, | |
1170 | &terratec_drxk_config[1], | |
1171 | &i2c_bus->i2c_adap); | |
1172 | if (fe0->dvb.frontend != NULL) { | |
1173 | if (!dvb_attach(mt2063_attach, | |
1174 | fe0->dvb.frontend, | |
1175 | &terratec_mt2063_config[1], | |
1176 | &i2c_bus2->i2c_adap)) | |
1177 | goto frontend_detach; | |
1178 | } | |
1179 | break; | |
1180 | } | |
1181 | break; | |
7b134e85 IL |
1182 | case CX23885_BOARD_TEVII_S471: |
1183 | i2c_bus = &dev->i2c_bus[1]; | |
1184 | ||
1185 | fe0->dvb.frontend = dvb_attach(ds3000_attach, | |
1186 | &tevii_ds3000_config, | |
1187 | &i2c_bus->i2c_adap); | |
1188 | break; | |
d19770e5 | 1189 | default: |
9c8ced51 ST |
1190 | printk(KERN_INFO "%s: The frontend of your DVB/ATSC card " |
1191 | " isn't supported yet\n", | |
d19770e5 ST |
1192 | dev->name); |
1193 | break; | |
1194 | } | |
78db8547 IL |
1195 | |
1196 | if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) { | |
9c8ced51 | 1197 | printk(KERN_ERR "%s: frontend initialization failed\n", |
78db8547 IL |
1198 | dev->name); |
1199 | goto frontend_detach; | |
d19770e5 | 1200 | } |
78db8547 | 1201 | |
d7cba043 | 1202 | /* define general-purpose callback pointer */ |
363c35fc | 1203 | fe0->dvb.frontend->callback = cx23885_tuner_callback; |
78db8547 IL |
1204 | if (fe1) |
1205 | fe1->dvb.frontend->callback = cx23885_tuner_callback; | |
1206 | #if 0 | |
1207 | /* Ensure all frontends negotiate bus access */ | |
1208 | fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; | |
1209 | if (fe1) | |
1210 | fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; | |
1211 | #endif | |
d19770e5 ST |
1212 | |
1213 | /* Put the analog decoder in standby to keep it quiet */ | |
622b828a | 1214 | call_all(dev, core, s_power, 0); |
d19770e5 | 1215 | |
363c35fc ST |
1216 | if (fe0->dvb.frontend->ops.analog_ops.standby) |
1217 | fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend); | |
3ba71d21 | 1218 | |
d19770e5 | 1219 | /* register everything */ |
5a23b076 | 1220 | ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port, |
9adf6132 | 1221 | &dev->pci->dev, adapter_nr, mfe_shared); |
bee30192 | 1222 | if (ret) |
78db8547 | 1223 | goto frontend_detach; |
363c35fc | 1224 | |
5a23b076 IL |
1225 | /* init CI & MAC */ |
1226 | switch (dev->board) { | |
1227 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: { | |
1228 | static struct netup_card_info cinfo; | |
1229 | ||
1230 | netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); | |
1231 | memcpy(port->frontends.adapter.proposed_mac, | |
1232 | cinfo.port[port->nr - 1].mac, 6); | |
be395157 | 1233 | printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n", |
1234 | port->nr, port->frontends.adapter.proposed_mac); | |
5a23b076 IL |
1235 | |
1236 | netup_ci_init(port); | |
1237 | break; | |
1238 | } | |
78db8547 IL |
1239 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { |
1240 | struct altera_ci_config netup_ci_cfg = { | |
1241 | .dev = dev,/* magic number to identify*/ | |
1242 | .adapter = &port->frontends.adapter,/* for CI */ | |
1243 | .demux = &fe0->dvb.demux,/* for hw pid filter */ | |
1244 | .fpga_rw = netup_altera_fpga_rw, | |
1245 | }; | |
1246 | ||
1247 | altera_ci_init(&netup_ci_cfg, port->nr); | |
1248 | break; | |
1249 | } | |
16bfdaa4 PG |
1250 | case CX23885_BOARD_TEVII_S470: { |
1251 | u8 eeprom[256]; /* 24C02 i2c eeprom */ | |
1252 | ||
1253 | if (port->nr != 1) | |
1254 | break; | |
1255 | ||
1256 | /* Read entire EEPROM */ | |
1257 | dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; | |
1258 | tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); | |
5cac1f66 | 1259 | printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0); |
16bfdaa4 PG |
1260 | memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6); |
1261 | break; | |
1262 | } | |
5a23b076 IL |
1263 | } |
1264 | ||
1265 | return ret; | |
78db8547 IL |
1266 | |
1267 | frontend_detach: | |
1268 | port->gate_ctrl = NULL; | |
1269 | videobuf_dvb_dealloc_frontends(&port->frontends); | |
1270 | return -EINVAL; | |
d19770e5 ST |
1271 | } |
1272 | ||
1273 | int cx23885_dvb_register(struct cx23885_tsport *port) | |
1274 | { | |
363c35fc ST |
1275 | |
1276 | struct videobuf_dvb_frontend *fe0; | |
d19770e5 | 1277 | struct cx23885_dev *dev = port->dev; |
eb0c58bb ST |
1278 | int err, i; |
1279 | ||
1280 | /* Here we need to allocate the correct number of frontends, | |
af901ca1 | 1281 | * as reflected in the cards struct. The reality is that currently |
eb0c58bb ST |
1282 | * no cx23885 boards support this - yet. But, if we don't modify this |
1283 | * code then the second frontend would never be allocated (later) | |
1284 | * and fail with error before the attach in dvb_register(). | |
1285 | * Without these changes we risk an OOPS later. The changes here | |
1286 | * are for safety, and should provide a good foundation for the | |
1287 | * future addition of any multi-frontend cx23885 based boards. | |
1288 | */ | |
1289 | printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, | |
1290 | port->num_frontends); | |
d19770e5 | 1291 | |
eb0c58bb | 1292 | for (i = 1; i <= port->num_frontends; i++) { |
96b7a1a8 | 1293 | if (videobuf_dvb_alloc_frontend( |
9c8ced51 | 1294 | &port->frontends, i) == NULL) { |
eb0c58bb ST |
1295 | printk(KERN_ERR "%s() failed to alloc\n", __func__); |
1296 | return -ENOMEM; | |
1297 | } | |
1298 | ||
1299 | fe0 = videobuf_dvb_get_frontend(&port->frontends, i); | |
1300 | if (!fe0) | |
1301 | err = -EINVAL; | |
363c35fc | 1302 | |
eb0c58bb | 1303 | dprintk(1, "%s\n", __func__); |
9c8ced51 | 1304 | dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n", |
eb0c58bb ST |
1305 | dev->board, |
1306 | dev->name, | |
1307 | dev->pci_bus, | |
1308 | dev->pci_slot); | |
d19770e5 | 1309 | |
eb0c58bb | 1310 | err = -ENODEV; |
d19770e5 | 1311 | |
eb0c58bb ST |
1312 | /* dvb stuff */ |
1313 | /* We have to init the queue for each frontend on a port. */ | |
9c8ced51 ST |
1314 | printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name); |
1315 | videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops, | |
1316 | &dev->pci->dev, &port->slock, | |
44a6481d | 1317 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP, |
08bff03e | 1318 | sizeof(struct cx23885_buffer), port, NULL); |
eb0c58bb | 1319 | } |
d19770e5 ST |
1320 | err = dvb_register(port); |
1321 | if (err != 0) | |
9c8ced51 ST |
1322 | printk(KERN_ERR "%s() dvb_register failed err = %d\n", |
1323 | __func__, err); | |
d19770e5 | 1324 | |
d19770e5 ST |
1325 | return err; |
1326 | } | |
1327 | ||
1328 | int cx23885_dvb_unregister(struct cx23885_tsport *port) | |
1329 | { | |
363c35fc ST |
1330 | struct videobuf_dvb_frontend *fe0; |
1331 | ||
eb0c58bb ST |
1332 | /* FIXME: in an error condition where the we have |
1333 | * an expected number of frontends (attach problem) | |
1334 | * then this might not clean up correctly, if 1 | |
1335 | * is invalid. | |
1336 | * This comment only applies to future boards IF they | |
1337 | * implement MFE support. | |
1338 | */ | |
92abe9ee | 1339 | fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); |
e66131ce | 1340 | if (fe0 && fe0->dvb.frontend) |
363c35fc | 1341 | videobuf_dvb_unregister_bus(&port->frontends); |
d19770e5 | 1342 | |
afd96668 HV |
1343 | switch (port->dev->board) { |
1344 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: | |
1345 | netup_ci_exit(port); | |
1346 | break; | |
78db8547 IL |
1347 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: |
1348 | altera_ci_release(port->dev, port->nr); | |
1349 | break; | |
afd96668 | 1350 | } |
5a23b076 | 1351 | |
78db8547 IL |
1352 | port->gate_ctrl = NULL; |
1353 | ||
d19770e5 ST |
1354 | return 0; |
1355 | } | |
44a6481d | 1356 |