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[media] ds3000: lock led procedure added
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
ST		 46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
5a23b076
IL		 51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
5a23b076 54#include "cimax2.h"
493b7127 55#include "lgs8gxx.h"
5a23b076
IL		 56#include "netup-eeprom.h"
57#include "netup-init.h"
a5dbf457 58#include "lgdt3305.h"
ea5697fe 59#include "atbm8830.h"
73f0af44 60#include "ts2020.h"
09ea33e5
IL		 61#include "ds3000.h"
62#include "cx23885-f300.h"
78db8547
IL		 63#include "altera-ci.h"
64#include "stv0367.h"
722c90eb
SR		 65#include "drxk.h"
66#include "mt2063.h"
f667190b
MB		 67#include "stv090x.h"
68#include "stb6100.h"
69#include "stb6100_cfg.h"
7c62f5a1
MK		 70#include "tda10071.h"
71#include "a8293.h"
d19770e5 72
4513fc69 73static unsigned int debug;
d19770e5 74
4513fc69
ST		 75#define dprintk(level, fmt, arg...)\
76 do { if (debug >= level)\
77 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
78 } while (0)
d19770e5
ST		 79
80/* ------------------------------------------------------------------ */
81
3ba71d21
MK		 82static unsigned int alt_tuner;
83module_param(alt_tuner, int, 0644);
84MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
85
78e92006
JG		 86DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
87
3ba71d21
MK		 88/* ------------------------------------------------------------------ */
89
d19770e5
ST		 90static int dvb_buf_setup(struct videobuf_queue *q,
91 unsigned int *count, unsigned int *size)
92{
93 struct cx23885_tsport *port = q->priv_data;
94
95 port->ts_packet_size = 188 * 4;
96 port->ts_packet_count = 32;
97
98 *size = port->ts_packet_size * port->ts_packet_count;
99 *count = 32;
100 return 0;
101}
102
44a6481d
MK		 103static int dvb_buf_prepare(struct videobuf_queue *q,
104 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 105{
106 struct cx23885_tsport *port = q->priv_data;
9c8ced51 107 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 108}
109
110static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
111{
112 struct cx23885_tsport *port = q->priv_data;
9c8ced51 113 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 114}
115
44a6481d
MK		 116static void dvb_buf_release(struct videobuf_queue *q,
117 struct videobuf_buffer *vb)
d19770e5 118{
9c8ced51 119 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 120}
121
a7d44baa
MCC		 122static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
123
78db8547
IL		 124static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
125{
126 struct videobuf_dvb_frontends *f;
127 struct videobuf_dvb_frontend *fe;
128
129 f = &port->frontends;
130
131 if (f->gate <= 1) /* undefined or fe0 */
132 fe = videobuf_dvb_get_frontend(f, 1);
133 else
134 fe = videobuf_dvb_get_frontend(f, f->gate);
135
136 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
137 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
a7d44baa
MCC		 138
139 /*
140 * FIXME: Improve this path to avoid calling the
141 * cx23885_dvb_set_frontend() every time it passes here.
142 */
143 cx23885_dvb_set_frontend(fe->dvb.frontend);
78db8547
IL		 144}
145
d19770e5
ST		 146static struct videobuf_queue_ops dvb_qops = {
147 .buf_setup = dvb_buf_setup,
148 .buf_prepare = dvb_buf_prepare,
149 .buf_queue = dvb_buf_queue,
150 .buf_release = dvb_buf_release,
151};
152
86184e06 153static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 154 .demod_address = 0x32 >> 1,
155 .output_mode = S5H1409_SERIAL_OUTPUT,
156 .gpio = S5H1409_GPIO_ON,
2b03238a 157 .qam_if = 44000,
fc959bef 158 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 159 .status_mode = S5H1409_DEMODLOCKING,
160 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 161};
162
b3ea0166
ST		 163static struct tda10048_config hauppauge_hvr1200_config = {
164 .demod_address = 0x10 >> 1,
165 .output_mode = TDA10048_SERIAL_OUTPUT,
166 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 167 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 168 .dtv6_if_freq_khz = TDA10048_IF_3300,
169 .dtv7_if_freq_khz = TDA10048_IF_3800,
170 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 171 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 172};
173
6b926eca
MK		 174static struct tda10048_config hauppauge_hvr1210_config = {
175 .demod_address = 0x10 >> 1,
176 .output_mode = TDA10048_SERIAL_OUTPUT,
177 .fwbulkwritelen = TDA10048_BULKWRITE_200,
178 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 179 .dtv6_if_freq_khz = TDA10048_IF_3300,
180 .dtv7_if_freq_khz = TDA10048_IF_3500,
181 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 182 .clk_freq_khz = TDA10048_CLK_16000,
183};
184
3ba71d21
MK		 185static struct s5h1409_config hauppauge_ezqam_config = {
186 .demod_address = 0x32 >> 1,
187 .output_mode = S5H1409_SERIAL_OUTPUT,
188 .gpio = S5H1409_GPIO_OFF,
189 .qam_if = 4000,
190 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 191 .status_mode = S5H1409_DEMODLOCKING,
192 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 193};
194
fc959bef 195static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 196 .demod_address = 0x32 >> 1,
197 .output_mode = S5H1409_SERIAL_OUTPUT,
198 .gpio = S5H1409_GPIO_OFF,
2b03238a 199 .qam_if = 44000,
fe475163 200 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 201 .status_mode = S5H1409_DEMODLOCKING,
202 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 203};
204
07b4a835
MK		 205static struct s5h1409_config hauppauge_hvr1500_config = {
206 .demod_address = 0x32 >> 1,
207 .output_mode = S5H1409_SERIAL_OUTPUT,
208 .gpio = S5H1409_GPIO_OFF,
209 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 210 .status_mode = S5H1409_DEMODLOCKING,
211 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 212};
213
86184e06 214static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 215 0x61
216};
217
9bc37caa
MK		 218static struct lgdt330x_config fusionhdtv_5_express = {
219 .demod_address = 0x0e,
220 .demod_chip = LGDT3303,
221 .serial_mpeg = 0x40,
222};
223
d1987d55
ST		 224static struct s5h1409_config hauppauge_hvr1500q_config = {
225 .demod_address = 0x32 >> 1,
226 .output_mode = S5H1409_SERIAL_OUTPUT,
227 .gpio = S5H1409_GPIO_ON,
228 .qam_if = 44000,
229 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 230 .status_mode = S5H1409_DEMODLOCKING,
231 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 232};
233
335377b7
MK		 234static struct s5h1409_config dvico_s5h1409_config = {
235 .demod_address = 0x32 >> 1,
236 .output_mode = S5H1409_SERIAL_OUTPUT,
237 .gpio = S5H1409_GPIO_ON,
238 .qam_if = 44000,
239 .inversion = S5H1409_INVERSION_OFF,
240 .status_mode = S5H1409_DEMODLOCKING,
241 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
242};
243
52b50450
MK		 244static struct s5h1411_config dvico_s5h1411_config = {
245 .output_mode = S5H1411_SERIAL_OUTPUT,
246 .gpio = S5H1411_GPIO_ON,
247 .qam_if = S5H1411_IF_44000,
248 .vsb_if = S5H1411_IF_44000,
249 .inversion = S5H1411_INVERSION_OFF,
250 .status_mode = S5H1411_DEMODLOCKING,
251 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
252};
253
19bc5796
MK		 254static struct s5h1411_config hcw_s5h1411_config = {
255 .output_mode = S5H1411_SERIAL_OUTPUT,
256 .gpio = S5H1411_GPIO_OFF,
257 .vsb_if = S5H1411_IF_44000,
258 .qam_if = S5H1411_IF_4000,
259 .inversion = S5H1411_INVERSION_ON,
260 .status_mode = S5H1411_DEMODLOCKING,
261 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
262};
263
d1987d55 264static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 265 .i2c_address = 0x61,
266 .if_khz = 5380,
d1987d55
ST		 267};
268
335377b7
MK		 269static struct xc5000_config dvico_xc5000_tunerconfig = {
270 .i2c_address = 0x64,
271 .if_khz = 5380,
335377b7
MK		 272};
273
4041f1a5
MK		 274static struct tda829x_config tda829x_no_probe = {
275 .probe_tuner = TDA829X_DONT_PROBE,
276};
277
f21e0d7f 278static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 279 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
280 .if_lvl = 6, .rfagc_top = 0x37 },
281 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
282 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 283};
284
b34cdc36
MK		 285static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
286 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
287 .if_lvl = 1, .rfagc_top = 0x37, },
288 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
289 .if_lvl = 1, .rfagc_top = 0x37, },
290 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
291 .if_lvl = 1, .rfagc_top = 0x37, },
292};
293
f21e0d7f
MK		 294static struct tda18271_config hauppauge_tda18271_config = {
295 .std_map = &hauppauge_tda18271_std_map,
296 .gate = TDA18271_GATE_ANALOG,
04a68baa 297 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 298};
299
b3ea0166 300static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 301 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 302 .gate = TDA18271_GATE_ANALOG,
04a68baa 303 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 304};
305
6b926eca
MK		 306static struct tda18271_config hauppauge_hvr1210_tuner_config = {
307 .gate = TDA18271_GATE_DIGITAL,
04a68baa 308 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 309};
310
247bc540 311static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 312 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
313 .if_lvl = 1, .rfagc_top = 0x58 },
314 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
315 .if_lvl = 1, .rfagc_top = 0x58 },
316};
317
247bc540
MK		 318static struct tda18271_config hauppauge_hvr127x_config = {
319 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 320 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 321};
322
247bc540 323static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 324 .i2c_addr = 0x0e,
325 .mpeg_mode = LGDT3305_MPEG_SERIAL,
326 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
327 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
328 .deny_i2c_rptr = 1,
329 .spectral_inversion = 1,
330 .qam_if_khz = 4000,
331 .vsb_if_khz = 3250,
332};
333
b1721d0d 334static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 335 BAND_VHF | BAND_UHF, /* band_caps */
336
337 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
338 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
339 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
340 * P_agc_nb_est=2, P_agc_write=0
341 */
342 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
343 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
344
345 712, /* inv_gain */
346 21, /* time_stabiliz */
347
348 0, /* alpha_level */
349 118, /* thlock */
350
351 0, /* wbd_inv */
352 2867, /* wbd_ref */
353 0, /* wbd_sel */
354 2, /* wbd_alpha */
355
356 0, /* agc1_max */
357 0, /* agc1_min */
358 39718, /* agc2_max */
359 9930, /* agc2_min */
360 0, /* agc1_pt1 */
361 0, /* agc1_pt2 */
362 0, /* agc1_pt3 */
363 0, /* agc1_slope1 */
364 0, /* agc1_slope2 */
365 0, /* agc2_pt1 */
366 128, /* agc2_pt2 */
367 29, /* agc2_slope1 */
368 29, /* agc2_slope2 */
369
370 17, /* alpha_mant */
371 27, /* alpha_exp */
372 23, /* beta_mant */
373 51, /* beta_exp */
374
375 1, /* perform_agc_softsplit */
376};
377
378/* PLL Configuration for COFDM BW_MHz = 8.000000
379 * With external clock = 30.000000 */
b1721d0d 380static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 381 60000, /* internal */
382 30000, /* sampling */
383 1, /* pll_cfg: prediv */
384 8, /* pll_cfg: ratio */
385 3, /* pll_cfg: range */
386 1, /* pll_cfg: reset */
387 0, /* pll_cfg: bypass */
388 0, /* misc: refdiv */
389 0, /* misc: bypclk_div */
390 1, /* misc: IO_CLK_en_core */
391 1, /* misc: ADClkSrc */
392 0, /* misc: modulo */
393 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
394 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
395 20452225, /* timf */
396 30000000 /* xtal_hz */
397};
398
399static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
400 .output_mpeg2_in_188_bytes = 1,
401 .hostbus_diversity = 1,
402 .tuner_is_baseband = 0,
403 .update_lna = NULL,
404
405 .agc_config_count = 1,
406 .agc = &xc3028_agc_config,
407 .bw = &xc3028_bw_config,
408
409 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
410 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
411 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
412
413 .pwm_freq_div = 0,
414 .agc_control = NULL,
415 .spur_protect = 0,
416
417 .output_mode = OUTMODE_MPEG2_SERIAL,
418};
419
aef2d186
ST		 420static struct zl10353_config dvico_fusionhdtv_xc3028 = {
421 .demod_address = 0x0f,
422 .if2 = 45600,
423 .no_tuner = 1,
d4dc673d 424 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 425};
426
f867c3f4
IL		 427static struct stv0900_reg stv0900_ts_regs[] = {
428 { R0900_TSGENERAL, 0x00 },
429 { R0900_P1_TSSPEED, 0x40 },
430 { R0900_P2_TSSPEED, 0x40 },
431 { R0900_P1_TSCFGM, 0xc0 },
432 { R0900_P2_TSCFGM, 0xc0 },
433 { R0900_P1_TSCFGH, 0xe0 },
434 { R0900_P2_TSCFGH, 0xe0 },
435 { R0900_P1_TSCFGL, 0x20 },
436 { R0900_P2_TSCFGL, 0x20 },
437 { 0xffff, 0xff }, /* terminate */
438};
439
5a23b076
IL		 440static struct stv0900_config netup_stv0900_config = {
441 .demod_address = 0x68,
29372a8d 442 .demod_mode = 1, /* dual */
644c7ef0 443 .xtal = 8000000,
5a23b076
IL		 444 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
445 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 446 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 447 .tun1_maddress = 0,/* 0x60 */
448 .tun2_maddress = 3,/* 0x63 */
449 .tun1_adc = 1,/* 1 Vpp */
450 .tun2_adc = 1,/* 1 Vpp */
451};
452
453static struct stv6110_config netup_stv6110_tunerconfig_a = {
454 .i2c_address = 0x60,
644c7ef0
AO		 455 .mclk = 16000000,
456 .clk_div = 1,
873688cd 457 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 458};
459
460static struct stv6110_config netup_stv6110_tunerconfig_b = {
461 .i2c_address = 0x63,
644c7ef0
AO		 462 .mclk = 16000000,
463 .clk_div = 1,
873688cd 464 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 465};
466
96318d0c 467static struct cx24116_config tbs_cx24116_config = {
09ea33e5 468 .demod_address = 0x55,
96318d0c
IL		 469};
470
09ea33e5
IL		 471static struct ds3000_config tevii_ds3000_config = {
472 .demod_address = 0x68,
579943f5
IL		 473};
474
73f0af44
KD		 475static struct ts2020_config tevii_ts2020_config = {
476 .tuner_address = 0x60,
477};
478
c9b8b04b
IL		 479static struct cx24116_config dvbworld_cx24116_config = {
480 .demod_address = 0x05,
481};
482
493b7127
DW		 483static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
484 .prod = LGS8GXX_PROD_LGS8GL5,
485 .demod_address = 0x19,
486 .serial_ts = 0,
487 .ts_clk_pol = 1,
488 .ts_clk_gated = 1,
489 .if_clk_freq = 30400, /* 30.4 MHz */
490 .if_freq = 5380, /* 5.38 MHz */
491 .if_neg_center = 1,
492 .ext_adc = 0,
493 .adc_signed = 0,
494 .if_neg_edge = 0,
495};
496
497static struct xc5000_config mygica_x8506_xc5000_config = {
498 .i2c_address = 0x61,
499 .if_khz = 5380,
500};
501
f667190b
MB		 502static struct stv090x_config prof_8000_stv090x_config = {
503 .device = STV0903,
504 .demod_mode = STV090x_SINGLE,
505 .clk_mode = STV090x_CLK_EXT,
506 .xtal = 27000000,
507 .address = 0x6A,
508 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
509 .repeater_level = STV090x_RPTLEVEL_64,
510 .adc1_range = STV090x_ADC_2Vpp,
511 .diseqc_envelope_mode = false,
512
513 .tuner_get_frequency = stb6100_get_frequency,
514 .tuner_set_frequency = stb6100_set_frequency,
515 .tuner_set_bandwidth = stb6100_set_bandwidth,
516 .tuner_get_bandwidth = stb6100_get_bandwidth,
517};
518
519static struct stb6100_config prof_8000_stb6100_config = {
520 .tuner_address = 0x60,
521 .refclock = 27000000,
522};
523
524static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
525{
526 struct cx23885_tsport *port = fe->dvb->priv;
527 struct cx23885_dev *dev = port->dev;
528
529 if (voltage == SEC_VOLTAGE_18)
530 cx_write(MC417_RWD, 0x00001e00);
531 else if (voltage == SEC_VOLTAGE_13)
532 cx_write(MC417_RWD, 0x00001a00);
533 else
534 cx_write(MC417_RWD, 0x00001800);
535 return 0;
536}
537
a7d44baa 538static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 539{
a7d44baa 540 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK		 541 struct cx23885_tsport *port = fe->dvb->priv;
542 struct cx23885_dev *dev = port->dev;
543
544 switch (dev->board) {
545 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 546 switch (p->modulation) {
f35b9e80
MK		 547 case VSB_8:
548 cx23885_gpio_clear(dev, GPIO_5);
549 break;
550 case QAM_64:
551 case QAM_256:
552 default:
553 cx23885_gpio_set(dev, GPIO_5);
554 break;
555 }
556 break;
6f0d8c02
DW		 557 case CX23885_BOARD_MYGICA_X8506:
558 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
559 /* Select Digital TV */
560 cx23885_gpio_set(dev, GPIO_0);
561 break;
f35b9e80 562 }
5bdd3962 563 return 0;
f35b9e80
MK		 564}
565
2365b2d3
DW		 566static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
567 .prod = LGS8GXX_PROD_LGS8G75,
568 .demod_address = 0x19,
569 .serial_ts = 0,
570 .ts_clk_pol = 1,
571 .ts_clk_gated = 1,
572 .if_clk_freq = 30400, /* 30.4 MHz */
573 .if_freq = 6500, /* 6.50 MHz */
574 .if_neg_center = 1,
575 .ext_adc = 0,
576 .adc_signed = 1,
577 .adc_vpp = 2, /* 1.6 Vpp */
578 .if_neg_edge = 1,
579};
580
581static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
582 .i2c_address = 0x61,
583 .if_khz = 6500,
584};
585
ea5697fe
DW		 586static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
587 .prod = ATBM8830_PROD_8830,
588 .demod_address = 0x44,
589 .serial_ts = 0,
590 .ts_sampling_edge = 1,
591 .ts_clk_gated = 0,
592 .osc_clk_freq = 30400, /* in kHz */
593 .if_freq = 0, /* zero IF */
594 .zif_swap_iq = 1,
c245c75c
DW		 595 .agc_min = 0x2E,
596 .agc_max = 0xFF,
597 .agc_hold_loop = 0,
ea5697fe
DW		 598};
599
600static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
601 .i2c_address = 0x60,
602 .osc_clk = 20
603};
604
605static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
606 .prod = ATBM8830_PROD_8830,
607 .demod_address = 0x44,
608 .serial_ts = 1,
609 .ts_sampling_edge = 1,
610 .ts_clk_gated = 0,
611 .osc_clk_freq = 30400, /* in kHz */
612 .if_freq = 0, /* zero IF */
613 .zif_swap_iq = 1,
c245c75c
DW		 614 .agc_min = 0x2E,
615 .agc_max = 0xFF,
616 .agc_hold_loop = 0,
ea5697fe
DW		 617};
618
619static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
620 .i2c_address = 0x60,
621 .osc_clk = 20
622};
78db8547
IL		 623static struct stv0367_config netup_stv0367_config[] = {
624 {
625 .demod_address = 0x1c,
626 .xtal = 27000000,
627 .if_khz = 4500,
628 .if_iq_mode = 0,
629 .ts_mode = 1,
630 .clk_pol = 0,
631 }, {
632 .demod_address = 0x1d,
633 .xtal = 27000000,
634 .if_khz = 4500,
635 .if_iq_mode = 0,
636 .ts_mode = 1,
637 .clk_pol = 0,
638 },
639};
640
641static struct xc5000_config netup_xc5000_config[] = {
642 {
643 .i2c_address = 0x61,
644 .if_khz = 4500,
645 }, {
646 .i2c_address = 0x64,
647 .if_khz = 4500,
648 },
649};
650
722c90eb
SR		 651static struct drxk_config terratec_drxk_config[] = {
652 {
653 .adr = 0x29,
654 .no_i2c_bridge = 1,
655 }, {
656 .adr = 0x2a,
657 .no_i2c_bridge = 1,
658 },
659};
660
661static struct mt2063_config terratec_mt2063_config[] = {
662 {
663 .tuner_address = 0x60,
664 }, {
665 .tuner_address = 0x67,
666 },
667};
668
7c62f5a1 669static const struct tda10071_config hauppauge_tda10071_config = {
41f55d57 670 .demod_i2c_addr = 0x05,
7c62f5a1
MK		 671 .tuner_i2c_addr = 0x54,
672 .i2c_wr_max = 64,
673 .ts_mode = TDA10071_TS_SERIAL,
674 .spec_inv = 0,
675 .xtal = 40444000, /* 40.444 MHz */
676 .pll_multiplier = 20,
677};
678
679static const struct a8293_config hauppauge_a8293_config = {
680 .i2c_addr = 0x0b,
681};
682
ada73eee 683static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
78db8547
IL		 684{
685 struct cx23885_dev *dev = (struct cx23885_dev *)device;
686 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 687 uint32_t mem = 0;
78db8547 688
d164460f 689 mem = cx_read(MC417_RWD);
78db8547
IL		 690 if (read)
691 cx_set(MC417_OEN, ALT_DATA);
692 else {
693 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL		 694 mem &= ~ALT_DATA;
695 mem |= (data & ALT_DATA);
78db8547
IL		 696 }
697
698 if (flag)
d164460f 699 mem |= ALT_AD_RG;
78db8547 700 else
d164460f 701 mem &= ~ALT_AD_RG;
78db8547 702
d164460f 703 mem &= ~ALT_CS;
78db8547 704 if (read)
d164460f 705 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 706 else
d164460f
AO		 707 mem = (mem & ~ALT_WR) | ALT_RD;
708
709 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL		 710
711 for (;;) {
712 mem = cx_read(MC417_RWD);
713 if ((mem & ALT_RDY) == 0)
714 break;
715 if (time_after(jiffies, timeout))
716 break;
717 udelay(1);
718 }
719
720 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
721 if (read)
722 return mem & ALT_DATA;
723
724 return 0;
725};
ea5697fe 726
d19770e5
ST		 727static int dvb_register(struct cx23885_tsport *port)
728{
729 struct cx23885_dev *dev = port->dev;
493b7127 730 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL		 731 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
732 int mfe_shared = 0; /* bus not shared by default */
5a23b076 733 int ret;
363c35fc 734
f972e0bd 735 /* Get the first frontend */
92abe9ee 736 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 737 if (!fe0)
738 return -EINVAL;
d19770e5
ST		 739
740 /* init struct videobuf_dvb */
363c35fc 741 fe0->dvb.name = dev->name;
d19770e5 742
78db8547
IL		 743 /* multi-frontend gate control is undefined or defaults to fe0 */
744 port->frontends.gate = 0;
745
746 /* Sets the gate control callback to be used by i2c command calls */
747 port->gate_ctrl = cx23885_dvb_gate_ctrl;
748
d19770e5
ST		 749 /* init frontend */
750 switch (dev->board) {
a77743bc 751 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 752 i2c_bus = &dev->i2c_bus[0];
363c35fc 753 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 754 &hauppauge_generic_config,
f139fa71 755 &i2c_bus->i2c_adap);
363c35fc
ST		 756 if (fe0->dvb.frontend != NULL) {
757 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 758 &i2c_bus->i2c_adap,
86184e06 759 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 760 }
761 break;
a5dbf457 762 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 763 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 764 i2c_bus = &dev->i2c_bus[0];
765 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 766 &hauppauge_lgdt3305_config,
a5dbf457
MK		 767 &i2c_bus->i2c_adap);
768 if (fe0->dvb.frontend != NULL) {
769 dvb_attach(tda18271_attach, fe0->dvb.frontend,
770 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 771 &hauppauge_hvr127x_config);
a5dbf457
MK		 772 }
773 break;
19bc5796 774 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 775 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK		 776 i2c_bus = &dev->i2c_bus[0];
777 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
778 &hcw_s5h1411_config,
779 &i2c_bus->i2c_adap);
780 if (fe0->dvb.frontend != NULL) {
781 dvb_attach(tda18271_attach, fe0->dvb.frontend,
782 0x60, &dev->i2c_bus[1].i2c_adap,
783 &hauppauge_tda18271_config);
784 }
0ac60acb
DH		 785
786 tda18271_attach(&dev->ts1.analog_fe,
787 0x60, &dev->i2c_bus[1].i2c_adap,
788 &hauppauge_tda18271_config);
789
19bc5796 790 break;
3ba71d21
MK		 791 case CX23885_BOARD_HAUPPAUGE_HVR1800:
792 i2c_bus = &dev->i2c_bus[0];
92abe9ee 793 switch (alt_tuner) {
3ba71d21 794 case 1:
363c35fc 795 fe0->dvb.frontend =
3ba71d21
MK		 796 dvb_attach(s5h1409_attach,
797 &hauppauge_ezqam_config,
798 &i2c_bus->i2c_adap);
363c35fc
ST		 799 if (fe0->dvb.frontend != NULL) {
800 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 801 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 802 &tda829x_no_probe);
363c35fc 803 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 804 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 805 &hauppauge_tda18271_config);
3ba71d21
MK		 806 }
807 break;
808 case 0:
809 default:
363c35fc 810 fe0->dvb.frontend =
3ba71d21
MK		 811 dvb_attach(s5h1409_attach,
812 &hauppauge_generic_config,
813 &i2c_bus->i2c_adap);
363c35fc
ST		 814 if (fe0->dvb.frontend != NULL)
815 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 816 &i2c_bus->i2c_adap,
817 &hauppauge_generic_tunerconfig, 0);
818 break;
819 }
820 break;
fc959bef 821 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 822 i2c_bus = &dev->i2c_bus[0];
363c35fc 823 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 824 &hauppauge_hvr1800lp_config,
f139fa71 825 &i2c_bus->i2c_adap);
363c35fc
ST		 826 if (fe0->dvb.frontend != NULL) {
827 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 828 &i2c_bus->i2c_adap,
fc959bef
ST		 829 &hauppauge_generic_tunerconfig, 0);
830 }
831 break;
9bc37caa 832 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 833 i2c_bus = &dev->i2c_bus[0];
363c35fc 834 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 835 &fusionhdtv_5_express,
f139fa71 836 &i2c_bus->i2c_adap);
363c35fc
ST		 837 if (fe0->dvb.frontend != NULL) {
838 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 839 &i2c_bus->i2c_adap, 0x61,
840 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 841 }
842 break;
d1987d55
ST		 843 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
844 i2c_bus = &dev->i2c_bus[1];
363c35fc 845 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 846 &hauppauge_hvr1500q_config,
847 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 848 if (fe0->dvb.frontend != NULL)
849 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 850 &i2c_bus->i2c_adap,
851 &hauppauge_hvr1500q_tunerconfig);
d1987d55 852 break;
07b4a835
MK		 853 case CX23885_BOARD_HAUPPAUGE_HVR1500:
854 i2c_bus = &dev->i2c_bus[1];
363c35fc 855 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 856 &hauppauge_hvr1500_config,
857 &dev->i2c_bus[0].i2c_adap);
363c35fc 858 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 859 struct dvb_frontend *fe;
860 struct xc2028_config cfg = {
861 .i2c_adap = &i2c_bus->i2c_adap,
862 .i2c_addr = 0x61,
07b4a835
MK		 863 };
864 static struct xc2028_ctrl ctl = {
ef80bfeb 865 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 866 .max_len = 64,
52c3d29c 867 .demod = XC3028_FE_OREN538,
07b4a835
MK		 868 };
869
870 fe = dvb_attach(xc2028_attach,
363c35fc 871 fe0->dvb.frontend, &cfg);
07b4a835
MK		 872 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
873 fe->ops.tuner_ops.set_config(fe, &ctl);
874 }
875 break;
b3ea0166 876 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 877 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 878 i2c_bus = &dev->i2c_bus[0];
363c35fc 879 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 880 &hauppauge_hvr1200_config,
881 &i2c_bus->i2c_adap);
363c35fc
ST		 882 if (fe0->dvb.frontend != NULL) {
883 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 884 &dev->i2c_bus[1].i2c_adap, 0x42,
885 &tda829x_no_probe);
363c35fc 886 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 887 0x60, &dev->i2c_bus[1].i2c_adap,
888 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 889 }
890 break;
891 case CX23885_BOARD_HAUPPAUGE_HVR1210:
892 i2c_bus = &dev->i2c_bus[0];
893 fe0->dvb.frontend = dvb_attach(tda10048_attach,
894 &hauppauge_hvr1210_config,
895 &i2c_bus->i2c_adap);
896 if (fe0->dvb.frontend != NULL) {
897 dvb_attach(tda18271_attach, fe0->dvb.frontend,
898 0x60, &dev->i2c_bus[1].i2c_adap,
899 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 900 }
901 break;
66762373
ST		 902 case CX23885_BOARD_HAUPPAUGE_HVR1400:
903 i2c_bus = &dev->i2c_bus[0];
363c35fc 904 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 905 &i2c_bus->i2c_adap,
906 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 907 if (fe0->dvb.frontend != NULL) {
66762373
ST		 908 struct dvb_frontend *fe;
909 struct xc2028_config cfg = {
910 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
911 .i2c_addr = 0x64,
66762373
ST		 912 };
913 static struct xc2028_ctrl ctl = {
ef80bfeb 914 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 915 .max_len = 64,
9bed77ee 916 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST		 917 /* This is true for all demods with
918 v36 firmware? */
0975fc68 919 .type = XC2028_D2633,
66762373
ST		 920 };
921
922 fe = dvb_attach(xc2028_attach,
363c35fc 923 fe0->dvb.frontend, &cfg);
66762373
ST		 924 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
925 fe->ops.tuner_ops.set_config(fe, &ctl);
926 }
927 break;
335377b7
MK		 928 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
929 i2c_bus = &dev->i2c_bus[port->nr - 1];
930
363c35fc 931 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 932 &dvico_s5h1409_config,
933 &i2c_bus->i2c_adap);
363c35fc
ST		 934 if (fe0->dvb.frontend == NULL)
935 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 936 &dvico_s5h1411_config,
937 &i2c_bus->i2c_adap);
363c35fc
ST		 938 if (fe0->dvb.frontend != NULL)
939 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 940 &i2c_bus->i2c_adap,
941 &dvico_xc5000_tunerconfig);
335377b7 942 break;
aef2d186
ST		 943 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
944 i2c_bus = &dev->i2c_bus[port->nr - 1];
945
363c35fc 946 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 947 &dvico_fusionhdtv_xc3028,
948 &i2c_bus->i2c_adap);
363c35fc 949 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 950 struct dvb_frontend *fe;
951 struct xc2028_config cfg = {
952 .i2c_adap = &i2c_bus->i2c_adap,
953 .i2c_addr = 0x61,
aef2d186
ST		 954 };
955 static struct xc2028_ctrl ctl = {
ef80bfeb 956 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 957 .max_len = 64,
958 .demod = XC3028_FE_ZARLINK456,
959 };
960
363c35fc 961 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 962 &cfg);
963 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
964 fe->ops.tuner_ops.set_config(fe, &ctl);
965 }
966 break;
967 }
4c56b04a 968 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 969 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 970 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 971 i2c_bus = &dev->i2c_bus[0];
972
363c35fc 973 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 974 &dvico_fusionhdtv_xc3028,
975 &i2c_bus->i2c_adap);
363c35fc 976 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 977 struct dvb_frontend *fe;
978 struct xc2028_config cfg = {
979 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
980 .i2c_addr = 0x61,
4c56b04a
ST		 981 };
982 static struct xc2028_ctrl ctl = {
ef80bfeb 983 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 984 .max_len = 64,
985 .demod = XC3028_FE_ZARLINK456,
986 };
987
363c35fc 988 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 989 &cfg);
990 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
991 fe->ops.tuner_ops.set_config(fe, &ctl);
992 }
96318d0c 993 break;
0cf8af57 994 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
995 i2c_bus = &dev->i2c_bus[0];
996
997 fe0->dvb.frontend = dvb_attach(zl10353_attach,
998 &dvico_fusionhdtv_xc3028,
999 &i2c_bus->i2c_adap);
1000 if (fe0->dvb.frontend != NULL) {
1001 struct dvb_frontend *fe;
1002 struct xc4000_config cfg = {
1003 .i2c_address = 0x61,
1004 .default_pm = 0,
1005 .dvb_amplitude = 134,
1006 .set_smoothedcvbs = 1,
1007 .if_khz = 4560
1008 };
1009
1010 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1011 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS		 1012 if (!fe) {
1013 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1014 dev->name);
1015 goto frontend_detach;
1016 }
0cf8af57 1017 }
1018 break;
96318d0c 1019 case CX23885_BOARD_TBS_6920:
09ea33e5 1020 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL		 1021
1022 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL		 1023 &tbs_cx24116_config,
1024 &i2c_bus->i2c_adap);
96318d0c 1025 if (fe0->dvb.frontend != NULL)
09ea33e5 1026 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1027
579943f5
IL		 1028 break;
1029 case CX23885_BOARD_TEVII_S470:
1030 i2c_bus = &dev->i2c_bus[1];
1031
09ea33e5
IL		 1032 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1033 &tevii_ds3000_config,
1034 &i2c_bus->i2c_adap);
73f0af44
KD		 1035 if (fe0->dvb.frontend != NULL) {
1036 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1037 &tevii_ts2020_config, &i2c_bus->i2c_adap);
09ea33e5 1038 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
73f0af44 1039 }
579943f5 1040
4c56b04a 1041 break;
c9b8b04b
IL		 1042 case CX23885_BOARD_DVBWORLD_2005:
1043 i2c_bus = &dev->i2c_bus[1];
1044
1045 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1046 &dvbworld_cx24116_config,
1047 &i2c_bus->i2c_adap);
1048 break;
5a23b076
IL		 1049 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1050 i2c_bus = &dev->i2c_bus[0];
1051 switch (port->nr) {
1052 /* port B */
1053 case 1:
1054 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1055 &netup_stv0900_config,
1056 &i2c_bus->i2c_adap, 0);
1057 if (fe0->dvb.frontend != NULL) {
1058 if (dvb_attach(stv6110_attach,
1059 fe0->dvb.frontend,
1060 &netup_stv6110_tunerconfig_a,
1061 &i2c_bus->i2c_adap)) {
1062 if (!dvb_attach(lnbh24_attach,
1063 fe0->dvb.frontend,
1064 &i2c_bus->i2c_adap,
9329fb5b
AO		 1065 LNBH24_PCL | LNBH24_TTX,
1066 LNBH24_TEN, 0x09))
5a23b076
IL		 1067 printk(KERN_ERR
1068 "No LNBH24 found!\n");
1069
1070 }
1071 }
1072 break;
1073 /* port C */
1074 case 2:
1075 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1076 &netup_stv0900_config,
1077 &i2c_bus->i2c_adap, 1);
1078 if (fe0->dvb.frontend != NULL) {
1079 if (dvb_attach(stv6110_attach,
1080 fe0->dvb.frontend,
1081 &netup_stv6110_tunerconfig_b,
1082 &i2c_bus->i2c_adap)) {
1083 if (!dvb_attach(lnbh24_attach,
1084 fe0->dvb.frontend,
1085 &i2c_bus->i2c_adap,
9329fb5b
AO		 1086 LNBH24_PCL | LNBH24_TTX,
1087 LNBH24_TEN, 0x0a))
5a23b076
IL		 1088 printk(KERN_ERR
1089 "No LNBH24 found!\n");
1090
1091 }
1092 }
1093 break;
1094 }
1095 break;
493b7127
DW		 1096 case CX23885_BOARD_MYGICA_X8506:
1097 i2c_bus = &dev->i2c_bus[0];
1098 i2c_bus2 = &dev->i2c_bus[1];
1099 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1100 &mygica_x8506_lgs8gl5_config,
1101 &i2c_bus->i2c_adap);
1102 if (fe0->dvb.frontend != NULL) {
1103 dvb_attach(xc5000_attach,
1104 fe0->dvb.frontend,
1105 &i2c_bus2->i2c_adap,
1106 &mygica_x8506_xc5000_config);
1107 }
1108 break;
2365b2d3
DW		 1109 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1110 i2c_bus = &dev->i2c_bus[0];
1111 i2c_bus2 = &dev->i2c_bus[1];
1112 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1113 &magicpro_prohdtve2_lgs8g75_config,
1114 &i2c_bus->i2c_adap);
1115 if (fe0->dvb.frontend != NULL) {
1116 dvb_attach(xc5000_attach,
1117 fe0->dvb.frontend,
1118 &i2c_bus2->i2c_adap,
1119 &magicpro_prohdtve2_xc5000_config);
1120 }
1121 break;
13697380 1122 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST		 1123 i2c_bus = &dev->i2c_bus[0];
1124 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1125 &hcw_s5h1411_config,
1126 &i2c_bus->i2c_adap);
1127 if (fe0->dvb.frontend != NULL)
1128 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1129 0x60, &dev->i2c_bus[0].i2c_adap,
1130 &hauppauge_tda18271_config);
1131
1132 tda18271_attach(&dev->ts1.analog_fe,
1133 0x60, &dev->i2c_bus[1].i2c_adap,
1134 &hauppauge_tda18271_config);
1135
1136 break;
aee0b24c 1137 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1138 i2c_bus = &dev->i2c_bus[0];
1139 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1140 &hcw_s5h1411_config,
1141 &i2c_bus->i2c_adap);
1142 if (fe0->dvb.frontend != NULL)
1143 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1144 0x60, &dev->i2c_bus[0].i2c_adap,
1145 &hauppauge_tda18271_config);
1146 break;
ea5697fe
DW		 1147 case CX23885_BOARD_MYGICA_X8558PRO:
1148 switch (port->nr) {
1149 /* port B */
1150 case 1:
1151 i2c_bus = &dev->i2c_bus[0];
1152 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1153 &mygica_x8558pro_atbm8830_cfg1,
1154 &i2c_bus->i2c_adap);
1155 if (fe0->dvb.frontend != NULL) {
1156 dvb_attach(max2165_attach,
1157 fe0->dvb.frontend,
1158 &i2c_bus->i2c_adap,
1159 &mygic_x8558pro_max2165_cfg1);
1160 }
1161 break;
1162 /* port C */
1163 case 2:
1164 i2c_bus = &dev->i2c_bus[1];
1165 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1166 &mygica_x8558pro_atbm8830_cfg2,
1167 &i2c_bus->i2c_adap);
1168 if (fe0->dvb.frontend != NULL) {
1169 dvb_attach(max2165_attach,
1170 fe0->dvb.frontend,
1171 &i2c_bus->i2c_adap,
1172 &mygic_x8558pro_max2165_cfg2);
1173 }
1174 break;
1175 }
1176 break;
78db8547
IL		 1177 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1178 i2c_bus = &dev->i2c_bus[0];
1179 mfe_shared = 1;/* MFE */
1180 port->frontends.gate = 0;/* not clear for me yet */
1181 /* ports B, C */
1182 /* MFE frontend 1 DVB-T */
1183 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1184 &netup_stv0367_config[port->nr - 1],
1185 &i2c_bus->i2c_adap);
4174ebf5 1186 if (fe0->dvb.frontend != NULL) {
78db8547
IL		 1187 if (NULL == dvb_attach(xc5000_attach,
1188 fe0->dvb.frontend,
1189 &i2c_bus->i2c_adap,
1190 &netup_xc5000_config[port->nr - 1]))
1191 goto frontend_detach;
4174ebf5
AO		 1192 /* load xc5000 firmware */
1193 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1194 }
78db8547
IL		 1195 /* MFE frontend 2 */
1196 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1197 if (fe1 == NULL)
1198 goto frontend_detach;
1199 /* DVB-C init */
1200 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1201 &netup_stv0367_config[port->nr - 1],
1202 &i2c_bus->i2c_adap);
1203 if (fe1->dvb.frontend != NULL) {
1204 fe1->dvb.frontend->id = 1;
1205 if (NULL == dvb_attach(xc5000_attach,
1206 fe1->dvb.frontend,
1207 &i2c_bus->i2c_adap,
1208 &netup_xc5000_config[port->nr - 1]))
1209 goto frontend_detach;
1210 }
1211 break;
722c90eb
SR		 1212 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1213 i2c_bus = &dev->i2c_bus[0];
1214 i2c_bus2 = &dev->i2c_bus[1];
1215
1216 switch (port->nr) {
1217 /* port b */
1218 case 1:
1219 fe0->dvb.frontend = dvb_attach(drxk_attach,
1220 &terratec_drxk_config[0],
1221 &i2c_bus->i2c_adap);
1222 if (fe0->dvb.frontend != NULL) {
1223 if (!dvb_attach(mt2063_attach,
1224 fe0->dvb.frontend,
1225 &terratec_mt2063_config[0],
1226 &i2c_bus2->i2c_adap))
1227 goto frontend_detach;
1228 }
1229 break;
1230 /* port c */
1231 case 2:
1232 fe0->dvb.frontend = dvb_attach(drxk_attach,
1233 &terratec_drxk_config[1],
1234 &i2c_bus->i2c_adap);
1235 if (fe0->dvb.frontend != NULL) {
1236 if (!dvb_attach(mt2063_attach,
1237 fe0->dvb.frontend,
1238 &terratec_mt2063_config[1],
1239 &i2c_bus2->i2c_adap))
1240 goto frontend_detach;
1241 }
1242 break;
1243 }
1244 break;
7b134e85
IL		 1245 case CX23885_BOARD_TEVII_S471:
1246 i2c_bus = &dev->i2c_bus[1];
1247
1248 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1249 &tevii_ds3000_config,
1250 &i2c_bus->i2c_adap);
1251 break;
f667190b
MB		 1252 case CX23885_BOARD_PROF_8000:
1253 i2c_bus = &dev->i2c_bus[0];
1254
1255 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1256 &prof_8000_stv090x_config,
1257 &i2c_bus->i2c_adap,
1258 STV090x_DEMODULATOR_0);
1259 if (fe0->dvb.frontend != NULL) {
1260 if (!dvb_attach(stb6100_attach,
1261 fe0->dvb.frontend,
1262 &prof_8000_stb6100_config,
1263 &i2c_bus->i2c_adap))
1264 goto frontend_detach;
1265
1266 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1267 }
1268 break;
7c62f5a1
MK		 1269 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1270 i2c_bus = &dev->i2c_bus[0];
1271 fe0->dvb.frontend = dvb_attach(tda10071_attach,
1272 &hauppauge_tda10071_config,
1273 &i2c_bus->i2c_adap);
1274 if (fe0->dvb.frontend != NULL) {
1275 dvb_attach(a8293_attach, fe0->dvb.frontend,
1276 &i2c_bus->i2c_adap,
1277 &hauppauge_a8293_config);
1278 }
1279 break;
d19770e5 1280 default:
9c8ced51
ST		 1281 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1282 " isn't supported yet\n",
d19770e5
ST		 1283 dev->name);
1284 break;
1285 }
78db8547
IL		 1286
1287 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1288 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL		 1289 dev->name);
1290 goto frontend_detach;
d19770e5 1291 }
78db8547 1292
d7cba043 1293 /* define general-purpose callback pointer */
363c35fc 1294 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL		 1295 if (fe1)
1296 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1297#if 0
1298 /* Ensure all frontends negotiate bus access */
1299 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1300 if (fe1)
1301 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1302#endif
d19770e5
ST		 1303
1304 /* Put the analog decoder in standby to keep it quiet */
622b828a 1305 call_all(dev, core, s_power, 0);
d19770e5 1306
363c35fc
ST		 1307 if (fe0->dvb.frontend->ops.analog_ops.standby)
1308 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1309
d19770e5 1310 /* register everything */
5a23b076 1311 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1312 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1313 if (ret)
78db8547 1314 goto frontend_detach;
363c35fc 1315
5a23b076
IL		 1316 /* init CI & MAC */
1317 switch (dev->board) {
1318 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1319 static struct netup_card_info cinfo;
1320
1321 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1322 memcpy(port->frontends.adapter.proposed_mac,
1323 cinfo.port[port->nr - 1].mac, 6);
be395157 1324 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1325 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL		 1326
1327 netup_ci_init(port);
1328 break;
1329 }
78db8547
IL		 1330 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1331 struct altera_ci_config netup_ci_cfg = {
1332 .dev = dev,/* magic number to identify*/
1333 .adapter = &port->frontends.adapter,/* for CI */
1334 .demux = &fe0->dvb.demux,/* for hw pid filter */
1335 .fpga_rw = netup_altera_fpga_rw,
1336 };
1337
1338 altera_ci_init(&netup_ci_cfg, port->nr);
1339 break;
1340 }
16bfdaa4
PG		 1341 case CX23885_BOARD_TEVII_S470: {
1342 u8 eeprom[256]; /* 24C02 i2c eeprom */
1343
1344 if (port->nr != 1)
1345 break;
1346
1347 /* Read entire EEPROM */
1348 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1349 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1350 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG		 1351 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1352 break;
1353 }
5a23b076
IL		 1354 }
1355
1356 return ret;
78db8547
IL		 1357
1358frontend_detach:
1359 port->gate_ctrl = NULL;
1360 videobuf_dvb_dealloc_frontends(&port->frontends);
1361 return -EINVAL;
d19770e5
ST		 1362}
1363
1364int cx23885_dvb_register(struct cx23885_tsport *port)
1365{
363c35fc
ST		 1366
1367 struct videobuf_dvb_frontend *fe0;
d19770e5 1368 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 1369 int err, i;
1370
1371 /* Here we need to allocate the correct number of frontends,
af901ca1 1372 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 1373 * no cx23885 boards support this - yet. But, if we don't modify this
1374 * code then the second frontend would never be allocated (later)
1375 * and fail with error before the attach in dvb_register().
1376 * Without these changes we risk an OOPS later. The changes here
1377 * are for safety, and should provide a good foundation for the
1378 * future addition of any multi-frontend cx23885 based boards.
1379 */
1380 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1381 port->num_frontends);
d19770e5 1382
eb0c58bb 1383 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1384 if (videobuf_dvb_alloc_frontend(
9c8ced51 1385 &port->frontends, i) == NULL) {
eb0c58bb
ST		 1386 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1387 return -ENOMEM;
1388 }
1389
1390 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1391 if (!fe0)
1392 err = -EINVAL;
363c35fc 1393
eb0c58bb 1394 dprintk(1, "%s\n", __func__);
9c8ced51 1395 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 1396 dev->board,
1397 dev->name,
1398 dev->pci_bus,
1399 dev->pci_slot);
d19770e5 1400
eb0c58bb 1401 err = -ENODEV;
d19770e5 1402
eb0c58bb
ST		 1403 /* dvb stuff */
1404 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 1405 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1406 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1407 &dev->pci->dev, &port->slock,
44a6481d 1408 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1409 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1410 }
d19770e5
ST		 1411 err = dvb_register(port);
1412 if (err != 0)
9c8ced51
ST		 1413 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1414 __func__, err);
d19770e5 1415
d19770e5
ST		 1416 return err;
1417}
1418
1419int cx23885_dvb_unregister(struct cx23885_tsport *port)
1420{
363c35fc
ST		 1421 struct videobuf_dvb_frontend *fe0;
1422
eb0c58bb
ST		 1423 /* FIXME: in an error condition where the we have
1424 * an expected number of frontends (attach problem)
1425 * then this might not clean up correctly, if 1
1426 * is invalid.
1427 * This comment only applies to future boards IF they
1428 * implement MFE support.
1429 */
92abe9ee 1430 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1431 if (fe0 && fe0->dvb.frontend)
363c35fc 1432 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1433
afd96668
HV		 1434 switch (port->dev->board) {
1435 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1436 netup_ci_exit(port);
1437 break;
78db8547
IL		 1438 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1439 altera_ci_release(port->dev, port->nr);
1440 break;
afd96668 1441 }
5a23b076 1442
78db8547
IL		 1443 port->gate_ctrl = NULL;
1444
d19770e5
ST		 1445 return 0;
1446}
44a6481d 1447
Linux kernel - Deliverables
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