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[media] pt3: make pt3_pm_ops() static
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
d19770e5
ST		 16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/fs.h>
22#include <linux/kthread.h>
23#include <linux/file.h>
24#include <linux/suspend.h>
25
26#include "cx23885.h"
d19770e5
ST		 27#include <media/v4l2-common.h>
28
5a23b076 29#include "dvb_ca_en50221.h"
d19770e5 30#include "s5h1409.h"
52b50450 31#include "s5h1411.h"
d19770e5 32#include "mt2131.h"
3ba71d21 33#include "tda8290.h"
4041f1a5 34#include "tda18271.h"
9bc37caa 35#include "lgdt330x.h"
0cf8af57 36#include "xc4000.h"
d1987d55 37#include "xc5000.h"
ea5697fe 38#include "max2165.h"
b3ea0166 39#include "tda10048.h"
07b4a835 40#include "tuner-xc2028.h"
827855d3 41#include "tuner-simple.h"
66762373 42#include "dib7000p.h"
46b21bba 43#include "dib0070.h"
66762373 44#include "dibx000_common.h"
aef2d186 45#include "zl10353.h"
5a23b076 46#include "stv0900.h"
f867c3f4 47#include "stv0900_reg.h"
5a23b076
IL		 48#include "stv6110.h"
49#include "lnbh24.h"
96318d0c 50#include "cx24116.h"
e6001482 51#include "cx24117.h"
5a23b076 52#include "cimax2.h"
493b7127 53#include "lgs8gxx.h"
5a23b076
IL		 54#include "netup-eeprom.h"
55#include "netup-init.h"
a5dbf457 56#include "lgdt3305.h"
ea5697fe 57#include "atbm8830.h"
73f0af44 58#include "ts2020.h"
09ea33e5
IL		 59#include "ds3000.h"
60#include "cx23885-f300.h"
78db8547
IL		 61#include "altera-ci.h"
62#include "stv0367.h"
722c90eb
SR		 63#include "drxk.h"
64#include "mt2063.h"
f667190b
MB		 65#include "stv090x.h"
66#include "stb6100.h"
67#include "stb6100_cfg.h"
7c62f5a1
MK		 68#include "tda10071.h"
69#include "a8293.h"
0d1b5265 70#include "mb86a20s.h"
36efec48 71#include "si2165.h"
d19770e5 72
4513fc69 73static unsigned int debug;
d19770e5 74
4513fc69
ST		 75#define dprintk(level, fmt, arg...)\
76 do { if (debug >= level)\
77 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
78 } while (0)
d19770e5
ST		 79
80/* ------------------------------------------------------------------ */
81
3ba71d21
MK		 82static unsigned int alt_tuner;
83module_param(alt_tuner, int, 0644);
84MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
85
78e92006
JG		 86DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
87
3ba71d21
MK		 88/* ------------------------------------------------------------------ */
89
453afdd9
HV		 90static int queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
91 unsigned int *num_buffers, unsigned int *num_planes,
92 unsigned int sizes[], void *alloc_ctxs[])
d19770e5 93{
453afdd9 94 struct cx23885_tsport *port = q->drv_priv;
d19770e5
ST		 95
96 port->ts_packet_size = 188 * 4;
97 port->ts_packet_count = 32;
453afdd9
HV		 98 *num_planes = 1;
99 sizes[0] = port->ts_packet_size * port->ts_packet_count;
100 *num_buffers = 32;
d19770e5
ST		 101 return 0;
102}
103
453afdd9
HV		 104
105static int buffer_prepare(struct vb2_buffer *vb)
d19770e5 106{
453afdd9
HV		 107 struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
108 struct cx23885_buffer *buf =
109 container_of(vb, struct cx23885_buffer, vb);
110
111 return cx23885_buf_prepare(buf, port);
d19770e5
ST		 112}
113
453afdd9 114static void buffer_finish(struct vb2_buffer *vb)
d19770e5 115{
453afdd9
HV		 116 struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
117 struct cx23885_dev *dev = port->dev;
118 struct cx23885_buffer *buf = container_of(vb,
119 struct cx23885_buffer, vb);
120 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
121
122 cx23885_free_buffer(dev, buf);
123
124 dma_unmap_sg(&dev->pci->dev, sgt->sgl, sgt->nents, DMA_FROM_DEVICE);
d19770e5
ST		 125}
126
453afdd9 127static void buffer_queue(struct vb2_buffer *vb)
d19770e5 128{
453afdd9
HV		 129 struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
130 struct cx23885_buffer *buf = container_of(vb,
131 struct cx23885_buffer, vb);
132
133 cx23885_buf_queue(port, buf);
d19770e5
ST		 134}
135
78db8547
IL		 136static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
137{
453afdd9
HV		 138 struct vb2_dvb_frontends *f;
139 struct vb2_dvb_frontend *fe;
78db8547
IL		 140
141 f = &port->frontends;
142
143 if (f->gate <= 1) /* undefined or fe0 */
453afdd9 144 fe = vb2_dvb_get_frontend(f, 1);
78db8547 145 else
453afdd9 146 fe = vb2_dvb_get_frontend(f, f->gate);
78db8547
IL		 147
148 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
149 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
150}
151
453afdd9
HV		 152static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
153{
154 struct cx23885_tsport *port = q->drv_priv;
155 struct cx23885_dmaqueue *dmaq = &port->mpegq;
156 struct cx23885_buffer *buf = list_entry(dmaq->active.next,
157 struct cx23885_buffer, queue);
158
159 cx23885_start_dma(port, dmaq, buf);
160 return 0;
161}
162
163static void cx23885_stop_streaming(struct vb2_queue *q)
164{
165 struct cx23885_tsport *port = q->drv_priv;
166
167 cx23885_cancel_buffers(port);
168}
169
170static struct vb2_ops dvb_qops = {
171 .queue_setup = queue_setup,
172 .buf_prepare = buffer_prepare,
173 .buf_finish = buffer_finish,
174 .buf_queue = buffer_queue,
175 .wait_prepare = vb2_ops_wait_prepare,
176 .wait_finish = vb2_ops_wait_finish,
177 .start_streaming = cx23885_start_streaming,
178 .stop_streaming = cx23885_stop_streaming,
d19770e5
ST		 179};
180
86184e06 181static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 182 .demod_address = 0x32 >> 1,
183 .output_mode = S5H1409_SERIAL_OUTPUT,
184 .gpio = S5H1409_GPIO_ON,
2b03238a 185 .qam_if = 44000,
fc959bef 186 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 187 .status_mode = S5H1409_DEMODLOCKING,
188 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 189};
190
b3ea0166
ST		 191static struct tda10048_config hauppauge_hvr1200_config = {
192 .demod_address = 0x10 >> 1,
193 .output_mode = TDA10048_SERIAL_OUTPUT,
194 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 195 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 196 .dtv6_if_freq_khz = TDA10048_IF_3300,
197 .dtv7_if_freq_khz = TDA10048_IF_3800,
198 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 199 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 200};
201
6b926eca
MK		 202static struct tda10048_config hauppauge_hvr1210_config = {
203 .demod_address = 0x10 >> 1,
204 .output_mode = TDA10048_SERIAL_OUTPUT,
205 .fwbulkwritelen = TDA10048_BULKWRITE_200,
206 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 207 .dtv6_if_freq_khz = TDA10048_IF_3300,
208 .dtv7_if_freq_khz = TDA10048_IF_3500,
209 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 210 .clk_freq_khz = TDA10048_CLK_16000,
211};
212
3ba71d21
MK		 213static struct s5h1409_config hauppauge_ezqam_config = {
214 .demod_address = 0x32 >> 1,
215 .output_mode = S5H1409_SERIAL_OUTPUT,
216 .gpio = S5H1409_GPIO_OFF,
217 .qam_if = 4000,
218 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 219 .status_mode = S5H1409_DEMODLOCKING,
220 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 221};
222
fc959bef 223static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 224 .demod_address = 0x32 >> 1,
225 .output_mode = S5H1409_SERIAL_OUTPUT,
226 .gpio = S5H1409_GPIO_OFF,
2b03238a 227 .qam_if = 44000,
fe475163 228 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 229 .status_mode = S5H1409_DEMODLOCKING,
230 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 231};
232
07b4a835
MK		 233static struct s5h1409_config hauppauge_hvr1500_config = {
234 .demod_address = 0x32 >> 1,
235 .output_mode = S5H1409_SERIAL_OUTPUT,
236 .gpio = S5H1409_GPIO_OFF,
237 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 238 .status_mode = S5H1409_DEMODLOCKING,
239 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 240};
241
86184e06 242static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 243 0x61
244};
245
9bc37caa
MK		 246static struct lgdt330x_config fusionhdtv_5_express = {
247 .demod_address = 0x0e,
248 .demod_chip = LGDT3303,
249 .serial_mpeg = 0x40,
250};
251
d1987d55
ST		 252static struct s5h1409_config hauppauge_hvr1500q_config = {
253 .demod_address = 0x32 >> 1,
254 .output_mode = S5H1409_SERIAL_OUTPUT,
255 .gpio = S5H1409_GPIO_ON,
256 .qam_if = 44000,
257 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 258 .status_mode = S5H1409_DEMODLOCKING,
259 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 260};
261
335377b7
MK		 262static struct s5h1409_config dvico_s5h1409_config = {
263 .demod_address = 0x32 >> 1,
264 .output_mode = S5H1409_SERIAL_OUTPUT,
265 .gpio = S5H1409_GPIO_ON,
266 .qam_if = 44000,
267 .inversion = S5H1409_INVERSION_OFF,
268 .status_mode = S5H1409_DEMODLOCKING,
269 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
270};
271
52b50450
MK		 272static struct s5h1411_config dvico_s5h1411_config = {
273 .output_mode = S5H1411_SERIAL_OUTPUT,
274 .gpio = S5H1411_GPIO_ON,
275 .qam_if = S5H1411_IF_44000,
276 .vsb_if = S5H1411_IF_44000,
277 .inversion = S5H1411_INVERSION_OFF,
278 .status_mode = S5H1411_DEMODLOCKING,
279 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
280};
281
19bc5796
MK		 282static struct s5h1411_config hcw_s5h1411_config = {
283 .output_mode = S5H1411_SERIAL_OUTPUT,
284 .gpio = S5H1411_GPIO_OFF,
285 .vsb_if = S5H1411_IF_44000,
286 .qam_if = S5H1411_IF_4000,
287 .inversion = S5H1411_INVERSION_ON,
288 .status_mode = S5H1411_DEMODLOCKING,
289 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
290};
291
d1987d55 292static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 293 .i2c_address = 0x61,
294 .if_khz = 5380,
d1987d55
ST		 295};
296
335377b7
MK		 297static struct xc5000_config dvico_xc5000_tunerconfig = {
298 .i2c_address = 0x64,
299 .if_khz = 5380,
335377b7
MK		 300};
301
4041f1a5
MK		 302static struct tda829x_config tda829x_no_probe = {
303 .probe_tuner = TDA829X_DONT_PROBE,
304};
305
f21e0d7f 306static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 307 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
308 .if_lvl = 6, .rfagc_top = 0x37 },
309 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
310 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 311};
312
b34cdc36
MK		 313static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
314 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
315 .if_lvl = 1, .rfagc_top = 0x37, },
316 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
317 .if_lvl = 1, .rfagc_top = 0x37, },
318 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
319 .if_lvl = 1, .rfagc_top = 0x37, },
320};
321
f21e0d7f
MK		 322static struct tda18271_config hauppauge_tda18271_config = {
323 .std_map = &hauppauge_tda18271_std_map,
324 .gate = TDA18271_GATE_ANALOG,
04a68baa 325 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 326};
327
b3ea0166 328static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 329 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 330 .gate = TDA18271_GATE_ANALOG,
04a68baa 331 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 332};
333
6b926eca
MK		 334static struct tda18271_config hauppauge_hvr1210_tuner_config = {
335 .gate = TDA18271_GATE_DIGITAL,
04a68baa 336 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 337};
338
36efec48
MS		 339static struct tda18271_config hauppauge_hvr4400_tuner_config = {
340 .gate = TDA18271_GATE_DIGITAL,
341 .output_opt = TDA18271_OUTPUT_LT_OFF,
342};
343
247bc540 344static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 345 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
346 .if_lvl = 1, .rfagc_top = 0x58 },
347 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
348 .if_lvl = 1, .rfagc_top = 0x58 },
349};
350
247bc540
MK		 351static struct tda18271_config hauppauge_hvr127x_config = {
352 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 353 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 354};
355
247bc540 356static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 357 .i2c_addr = 0x0e,
358 .mpeg_mode = LGDT3305_MPEG_SERIAL,
359 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
360 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
361 .deny_i2c_rptr = 1,
362 .spectral_inversion = 1,
363 .qam_if_khz = 4000,
364 .vsb_if_khz = 3250,
365};
366
b1721d0d 367static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 368 BAND_VHF | BAND_UHF, /* band_caps */
369
370 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
371 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
372 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
373 * P_agc_nb_est=2, P_agc_write=0
374 */
375 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
376 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
377
378 712, /* inv_gain */
379 21, /* time_stabiliz */
380
381 0, /* alpha_level */
382 118, /* thlock */
383
384 0, /* wbd_inv */
385 2867, /* wbd_ref */
386 0, /* wbd_sel */
387 2, /* wbd_alpha */
388
389 0, /* agc1_max */
390 0, /* agc1_min */
391 39718, /* agc2_max */
392 9930, /* agc2_min */
393 0, /* agc1_pt1 */
394 0, /* agc1_pt2 */
395 0, /* agc1_pt3 */
396 0, /* agc1_slope1 */
397 0, /* agc1_slope2 */
398 0, /* agc2_pt1 */
399 128, /* agc2_pt2 */
400 29, /* agc2_slope1 */
401 29, /* agc2_slope2 */
402
403 17, /* alpha_mant */
404 27, /* alpha_exp */
405 23, /* beta_mant */
406 51, /* beta_exp */
407
408 1, /* perform_agc_softsplit */
409};
410
411/* PLL Configuration for COFDM BW_MHz = 8.000000
412 * With external clock = 30.000000 */
b1721d0d 413static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 414 60000, /* internal */
415 30000, /* sampling */
416 1, /* pll_cfg: prediv */
417 8, /* pll_cfg: ratio */
418 3, /* pll_cfg: range */
419 1, /* pll_cfg: reset */
420 0, /* pll_cfg: bypass */
421 0, /* misc: refdiv */
422 0, /* misc: bypclk_div */
423 1, /* misc: IO_CLK_en_core */
424 1, /* misc: ADClkSrc */
425 0, /* misc: modulo */
426 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
427 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
428 20452225, /* timf */
429 30000000 /* xtal_hz */
430};
431
432static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
433 .output_mpeg2_in_188_bytes = 1,
434 .hostbus_diversity = 1,
435 .tuner_is_baseband = 0,
436 .update_lna = NULL,
437
438 .agc_config_count = 1,
439 .agc = &xc3028_agc_config,
440 .bw = &xc3028_bw_config,
441
442 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
443 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
444 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
445
446 .pwm_freq_div = 0,
447 .agc_control = NULL,
448 .spur_protect = 0,
449
450 .output_mode = OUTMODE_MPEG2_SERIAL,
451};
452
aef2d186
ST		 453static struct zl10353_config dvico_fusionhdtv_xc3028 = {
454 .demod_address = 0x0f,
455 .if2 = 45600,
456 .no_tuner = 1,
d4dc673d 457 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 458};
459
f867c3f4
IL		 460static struct stv0900_reg stv0900_ts_regs[] = {
461 { R0900_TSGENERAL, 0x00 },
462 { R0900_P1_TSSPEED, 0x40 },
463 { R0900_P2_TSSPEED, 0x40 },
464 { R0900_P1_TSCFGM, 0xc0 },
465 { R0900_P2_TSCFGM, 0xc0 },
466 { R0900_P1_TSCFGH, 0xe0 },
467 { R0900_P2_TSCFGH, 0xe0 },
468 { R0900_P1_TSCFGL, 0x20 },
469 { R0900_P2_TSCFGL, 0x20 },
470 { 0xffff, 0xff }, /* terminate */
471};
472
5a23b076
IL		 473static struct stv0900_config netup_stv0900_config = {
474 .demod_address = 0x68,
29372a8d 475 .demod_mode = 1, /* dual */
644c7ef0 476 .xtal = 8000000,
5a23b076
IL		 477 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
478 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 479 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 480 .tun1_maddress = 0,/* 0x60 */
481 .tun2_maddress = 3,/* 0x63 */
482 .tun1_adc = 1,/* 1 Vpp */
483 .tun2_adc = 1,/* 1 Vpp */
484};
485
486static struct stv6110_config netup_stv6110_tunerconfig_a = {
487 .i2c_address = 0x60,
644c7ef0
AO		 488 .mclk = 16000000,
489 .clk_div = 1,
873688cd 490 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 491};
492
493static struct stv6110_config netup_stv6110_tunerconfig_b = {
494 .i2c_address = 0x63,
644c7ef0
AO		 495 .mclk = 16000000,
496 .clk_div = 1,
873688cd 497 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 498};
499
96318d0c 500static struct cx24116_config tbs_cx24116_config = {
09ea33e5 501 .demod_address = 0x55,
96318d0c
IL		 502};
503
e6001482
LA		 504static struct cx24117_config tbs_cx24117_config = {
505 .demod_address = 0x55,
506};
507
09ea33e5
IL		 508static struct ds3000_config tevii_ds3000_config = {
509 .demod_address = 0x68,
579943f5
IL		 510};
511
73f0af44
KD		 512static struct ts2020_config tevii_ts2020_config = {
513 .tuner_address = 0x60,
b858c331 514 .clk_out_div = 1,
8d2b0229 515 .frequency_div = 1146000,
73f0af44
KD		 516};
517
c9b8b04b
IL		 518static struct cx24116_config dvbworld_cx24116_config = {
519 .demod_address = 0x05,
520};
521
493b7127
DW		 522static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
523 .prod = LGS8GXX_PROD_LGS8GL5,
524 .demod_address = 0x19,
525 .serial_ts = 0,
526 .ts_clk_pol = 1,
527 .ts_clk_gated = 1,
528 .if_clk_freq = 30400, /* 30.4 MHz */
529 .if_freq = 5380, /* 5.38 MHz */
530 .if_neg_center = 1,
531 .ext_adc = 0,
532 .adc_signed = 0,
533 .if_neg_edge = 0,
534};
535
536static struct xc5000_config mygica_x8506_xc5000_config = {
537 .i2c_address = 0x61,
538 .if_khz = 5380,
539};
540
0d1b5265
MCC		 541static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
542 .demod_address = 0x10,
543};
544
545static struct xc5000_config mygica_x8507_xc5000_config = {
546 .i2c_address = 0x61,
547 .if_khz = 4000,
548};
549
f667190b 550static struct stv090x_config prof_8000_stv090x_config = {
b858c331
IL		 551 .device = STV0903,
552 .demod_mode = STV090x_SINGLE,
553 .clk_mode = STV090x_CLK_EXT,
554 .xtal = 27000000,
555 .address = 0x6A,
556 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
557 .repeater_level = STV090x_RPTLEVEL_64,
558 .adc1_range = STV090x_ADC_2Vpp,
559 .diseqc_envelope_mode = false,
560
561 .tuner_get_frequency = stb6100_get_frequency,
562 .tuner_set_frequency = stb6100_set_frequency,
563 .tuner_set_bandwidth = stb6100_set_bandwidth,
564 .tuner_get_bandwidth = stb6100_get_bandwidth,
f667190b
MB		 565};
566
567static struct stb6100_config prof_8000_stb6100_config = {
568 .tuner_address = 0x60,
569 .refclock = 27000000,
570};
571
572static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
573{
574 struct cx23885_tsport *port = fe->dvb->priv;
575 struct cx23885_dev *dev = port->dev;
576
577 if (voltage == SEC_VOLTAGE_18)
578 cx_write(MC417_RWD, 0x00001e00);
579 else if (voltage == SEC_VOLTAGE_13)
580 cx_write(MC417_RWD, 0x00001a00);
581 else
582 cx_write(MC417_RWD, 0x00001800);
583 return 0;
584}
585
a7d44baa 586static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 587{
a7d44baa 588 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK		 589 struct cx23885_tsport *port = fe->dvb->priv;
590 struct cx23885_dev *dev = port->dev;
591
592 switch (dev->board) {
593 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 594 switch (p->modulation) {
f35b9e80
MK		 595 case VSB_8:
596 cx23885_gpio_clear(dev, GPIO_5);
597 break;
598 case QAM_64:
599 case QAM_256:
600 default:
601 cx23885_gpio_set(dev, GPIO_5);
602 break;
603 }
604 break;
6f0d8c02 605 case CX23885_BOARD_MYGICA_X8506:
0d1b5265 606 case CX23885_BOARD_MYGICA_X8507:
6f0d8c02
DW		 607 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
608 /* Select Digital TV */
609 cx23885_gpio_set(dev, GPIO_0);
610 break;
f35b9e80 611 }
15472faf
MCC		 612
613 /* Call the real set_frontend */
614 if (port->set_frontend)
615 return port->set_frontend(fe);
616
5bdd3962 617 return 0;
f35b9e80
MK		 618}
619
15472faf
MCC		 620static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
621 struct dvb_frontend *fe)
622{
623 port->set_frontend = fe->ops.set_frontend;
624 fe->ops.set_frontend = cx23885_dvb_set_frontend;
625}
626
2365b2d3
DW		 627static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
628 .prod = LGS8GXX_PROD_LGS8G75,
629 .demod_address = 0x19,
630 .serial_ts = 0,
631 .ts_clk_pol = 1,
632 .ts_clk_gated = 1,
633 .if_clk_freq = 30400, /* 30.4 MHz */
634 .if_freq = 6500, /* 6.50 MHz */
635 .if_neg_center = 1,
636 .ext_adc = 0,
637 .adc_signed = 1,
638 .adc_vpp = 2, /* 1.6 Vpp */
639 .if_neg_edge = 1,
640};
641
642static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
643 .i2c_address = 0x61,
644 .if_khz = 6500,
645};
646
ea5697fe
DW		 647static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
648 .prod = ATBM8830_PROD_8830,
649 .demod_address = 0x44,
650 .serial_ts = 0,
651 .ts_sampling_edge = 1,
652 .ts_clk_gated = 0,
653 .osc_clk_freq = 30400, /* in kHz */
654 .if_freq = 0, /* zero IF */
655 .zif_swap_iq = 1,
c245c75c
DW		 656 .agc_min = 0x2E,
657 .agc_max = 0xFF,
658 .agc_hold_loop = 0,
ea5697fe
DW		 659};
660
661static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
662 .i2c_address = 0x60,
663 .osc_clk = 20
664};
665
666static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
667 .prod = ATBM8830_PROD_8830,
668 .demod_address = 0x44,
669 .serial_ts = 1,
670 .ts_sampling_edge = 1,
671 .ts_clk_gated = 0,
672 .osc_clk_freq = 30400, /* in kHz */
673 .if_freq = 0, /* zero IF */
674 .zif_swap_iq = 1,
c245c75c
DW		 675 .agc_min = 0x2E,
676 .agc_max = 0xFF,
677 .agc_hold_loop = 0,
ea5697fe
DW		 678};
679
680static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
681 .i2c_address = 0x60,
682 .osc_clk = 20
683};
78db8547
IL		 684static struct stv0367_config netup_stv0367_config[] = {
685 {
686 .demod_address = 0x1c,
687 .xtal = 27000000,
688 .if_khz = 4500,
689 .if_iq_mode = 0,
690 .ts_mode = 1,
691 .clk_pol = 0,
692 }, {
693 .demod_address = 0x1d,
694 .xtal = 27000000,
695 .if_khz = 4500,
696 .if_iq_mode = 0,
697 .ts_mode = 1,
698 .clk_pol = 0,
699 },
700};
701
702static struct xc5000_config netup_xc5000_config[] = {
703 {
704 .i2c_address = 0x61,
705 .if_khz = 4500,
706 }, {
707 .i2c_address = 0x64,
708 .if_khz = 4500,
709 },
710};
711
722c90eb
SR		 712static struct drxk_config terratec_drxk_config[] = {
713 {
714 .adr = 0x29,
715 .no_i2c_bridge = 1,
716 }, {
717 .adr = 0x2a,
718 .no_i2c_bridge = 1,
719 },
720};
721
722static struct mt2063_config terratec_mt2063_config[] = {
723 {
724 .tuner_address = 0x60,
725 }, {
726 .tuner_address = 0x67,
727 },
728};
729
7c62f5a1 730static const struct tda10071_config hauppauge_tda10071_config = {
41f55d57 731 .demod_i2c_addr = 0x05,
7c62f5a1
MK		 732 .tuner_i2c_addr = 0x54,
733 .i2c_wr_max = 64,
734 .ts_mode = TDA10071_TS_SERIAL,
735 .spec_inv = 0,
736 .xtal = 40444000, /* 40.444 MHz */
737 .pll_multiplier = 20,
738};
739
740static const struct a8293_config hauppauge_a8293_config = {
741 .i2c_addr = 0x0b,
742};
743
36efec48
MS		 744static const struct si2165_config hauppauge_hvr4400_si2165_config = {
745 .i2c_addr = 0x64,
746 .chip_mode = SI2165_MODE_PLL_XTAL,
747 .ref_freq_Hz = 16000000,
748};
749
ada73eee 750static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
78db8547
IL		 751{
752 struct cx23885_dev *dev = (struct cx23885_dev *)device;
753 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 754 uint32_t mem = 0;
78db8547 755
d164460f 756 mem = cx_read(MC417_RWD);
78db8547
IL		 757 if (read)
758 cx_set(MC417_OEN, ALT_DATA);
759 else {
760 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL		 761 mem &= ~ALT_DATA;
762 mem |= (data & ALT_DATA);
78db8547
IL		 763 }
764
765 if (flag)
d164460f 766 mem |= ALT_AD_RG;
78db8547 767 else
d164460f 768 mem &= ~ALT_AD_RG;
78db8547 769
d164460f 770 mem &= ~ALT_CS;
78db8547 771 if (read)
d164460f 772 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 773 else
d164460f
AO		 774 mem = (mem & ~ALT_WR) | ALT_RD;
775
776 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL		 777
778 for (;;) {
779 mem = cx_read(MC417_RWD);
780 if ((mem & ALT_RDY) == 0)
781 break;
782 if (time_after(jiffies, timeout))
783 break;
784 udelay(1);
785 }
786
787 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
788 if (read)
789 return mem & ALT_DATA;
790
791 return 0;
792};
ea5697fe 793
46b21bba
JH		 794static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
795{
796 struct dib7000p_ops *dib7000p_ops = fe->sec_priv;
797
798 return dib7000p_ops->set_gpio(fe, 8, 0, !onoff);
799}
800
801static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff)
802{
803 return 0;
804}
805
806static struct dib0070_config dib7070p_dib0070_config = {
807 .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
808 .reset = dib7070_tuner_reset,
809 .sleep = dib7070_tuner_sleep,
810 .clock_khz = 12000,
46b21bba
JH		 811 .freq_offset_khz_vhf = 550,
812 /* .flip_chip = 1, */
813};
814
815/* DIB7070 generic */
816static struct dibx000_agc_config dib7070_agc_config = {
817 .band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
818
819 /*
820 * P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5,
821 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
822 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0
823 */
824 .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) |
825 (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
826 .inv_gain = 600,
827 .time_stabiliz = 10,
828 .alpha_level = 0,
829 .thlock = 118,
830 .wbd_inv = 0,
831 .wbd_ref = 3530,
832 .wbd_sel = 1,
833 .wbd_alpha = 5,
834 .agc1_max = 65535,
835 .agc1_min = 0,
836 .agc2_max = 65535,
837 .agc2_min = 0,
838 .agc1_pt1 = 0,
839 .agc1_pt2 = 40,
840 .agc1_pt3 = 183,
841 .agc1_slope1 = 206,
842 .agc1_slope2 = 255,
843 .agc2_pt1 = 72,
844 .agc2_pt2 = 152,
845 .agc2_slope1 = 88,
846 .agc2_slope2 = 90,
847 .alpha_mant = 17,
848 .alpha_exp = 27,
849 .beta_mant = 23,
850 .beta_exp = 51,
851 .perform_agc_softsplit = 0,
852};
853
854static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
855 .internal = 60000,
856 .sampling = 15000,
857 .pll_prediv = 1,
858 .pll_ratio = 20,
859 .pll_range = 3,
860 .pll_reset = 1,
861 .pll_bypass = 0,
862 .enable_refdiv = 0,
863 .bypclk_div = 0,
864 .IO_CLK_en_core = 1,
865 .ADClkSrc = 1,
866 .modulo = 2,
867 /* refsel, sel, freq_15k */
868 .sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
869 .ifreq = (0 << 25) | 0,
870 .timf = 20452225,
871 .xtal_hz = 12000000,
872};
873
874static struct dib7000p_config dib7070p_dib7000p_config = {
875 /* .output_mode = OUTMODE_MPEG2_FIFO, */
876 .output_mode = OUTMODE_MPEG2_SERIAL,
877 /* .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK, */
878 .output_mpeg2_in_188_bytes = 1,
879
880 .agc_config_count = 1,
881 .agc = &dib7070_agc_config,
882 .bw = &dib7070_bw_config_12_mhz,
883 .tuner_is_baseband = 1,
884 .spur_protect = 1,
885
886 .gpio_dir = 0xfcef, /* DIB7000P_GPIO_DEFAULT_DIRECTIONS, */
887 .gpio_val = 0x0110, /* DIB7000P_GPIO_DEFAULT_VALUES, */
888 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
889
890 .hostbus_diversity = 1,
891};
892
d19770e5
ST		 893static int dvb_register(struct cx23885_tsport *port)
894{
8abe4a0a 895 struct dib7000p_ops dib7000p_ops;
d19770e5 896 struct cx23885_dev *dev = port->dev;
493b7127 897 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
453afdd9 898 struct vb2_dvb_frontend *fe0, *fe1 = NULL;
78db8547 899 int mfe_shared = 0; /* bus not shared by default */
5a23b076 900 int ret;
363c35fc 901
f972e0bd 902 /* Get the first frontend */
453afdd9 903 fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 904 if (!fe0)
905 return -EINVAL;
d19770e5 906
453afdd9 907 /* init struct vb2_dvb */
363c35fc 908 fe0->dvb.name = dev->name;
d19770e5 909
78db8547
IL		 910 /* multi-frontend gate control is undefined or defaults to fe0 */
911 port->frontends.gate = 0;
912
913 /* Sets the gate control callback to be used by i2c command calls */
914 port->gate_ctrl = cx23885_dvb_gate_ctrl;
915
d19770e5
ST		 916 /* init frontend */
917 switch (dev->board) {
a77743bc 918 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 919 i2c_bus = &dev->i2c_bus[0];
363c35fc 920 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 921 &hauppauge_generic_config,
f139fa71 922 &i2c_bus->i2c_adap);
363c35fc
ST		 923 if (fe0->dvb.frontend != NULL) {
924 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 925 &i2c_bus->i2c_adap,
86184e06 926 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 927 }
928 break;
a5dbf457 929 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 930 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 931 i2c_bus = &dev->i2c_bus[0];
932 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 933 &hauppauge_lgdt3305_config,
a5dbf457
MK		 934 &i2c_bus->i2c_adap);
935 if (fe0->dvb.frontend != NULL) {
936 dvb_attach(tda18271_attach, fe0->dvb.frontend,
937 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 938 &hauppauge_hvr127x_config);
a5dbf457 939 }
15472faf
MCC		 940 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
941 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
a5dbf457 942 break;
19bc5796 943 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 944 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK		 945 i2c_bus = &dev->i2c_bus[0];
946 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
947 &hcw_s5h1411_config,
948 &i2c_bus->i2c_adap);
949 if (fe0->dvb.frontend != NULL) {
950 dvb_attach(tda18271_attach, fe0->dvb.frontend,
951 0x60, &dev->i2c_bus[1].i2c_adap,
952 &hauppauge_tda18271_config);
953 }
0ac60acb
DH		 954
955 tda18271_attach(&dev->ts1.analog_fe,
956 0x60, &dev->i2c_bus[1].i2c_adap,
957 &hauppauge_tda18271_config);
958
19bc5796 959 break;
3ba71d21
MK		 960 case CX23885_BOARD_HAUPPAUGE_HVR1800:
961 i2c_bus = &dev->i2c_bus[0];
92abe9ee 962 switch (alt_tuner) {
3ba71d21 963 case 1:
363c35fc 964 fe0->dvb.frontend =
3ba71d21
MK		 965 dvb_attach(s5h1409_attach,
966 &hauppauge_ezqam_config,
967 &i2c_bus->i2c_adap);
363c35fc
ST		 968 if (fe0->dvb.frontend != NULL) {
969 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 970 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 971 &tda829x_no_probe);
363c35fc 972 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 973 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 974 &hauppauge_tda18271_config);
3ba71d21
MK		 975 }
976 break;
977 case 0:
978 default:
363c35fc 979 fe0->dvb.frontend =
3ba71d21
MK		 980 dvb_attach(s5h1409_attach,
981 &hauppauge_generic_config,
982 &i2c_bus->i2c_adap);
363c35fc
ST		 983 if (fe0->dvb.frontend != NULL)
984 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 985 &i2c_bus->i2c_adap,
986 &hauppauge_generic_tunerconfig, 0);
987 break;
988 }
989 break;
fc959bef 990 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 991 i2c_bus = &dev->i2c_bus[0];
363c35fc 992 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 993 &hauppauge_hvr1800lp_config,
f139fa71 994 &i2c_bus->i2c_adap);
363c35fc
ST		 995 if (fe0->dvb.frontend != NULL) {
996 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 997 &i2c_bus->i2c_adap,
fc959bef
ST		 998 &hauppauge_generic_tunerconfig, 0);
999 }
1000 break;
9bc37caa 1001 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 1002 i2c_bus = &dev->i2c_bus[0];
363c35fc 1003 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 1004 &fusionhdtv_5_express,
f139fa71 1005 &i2c_bus->i2c_adap);
363c35fc
ST		 1006 if (fe0->dvb.frontend != NULL) {
1007 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 1008 &i2c_bus->i2c_adap, 0x61,
1009 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 1010 }
1011 break;
d1987d55
ST		 1012 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1013 i2c_bus = &dev->i2c_bus[1];
363c35fc 1014 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 1015 &hauppauge_hvr1500q_config,
1016 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 1017 if (fe0->dvb.frontend != NULL)
1018 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 1019 &i2c_bus->i2c_adap,
1020 &hauppauge_hvr1500q_tunerconfig);
d1987d55 1021 break;
07b4a835
MK		 1022 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1023 i2c_bus = &dev->i2c_bus[1];
363c35fc 1024 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 1025 &hauppauge_hvr1500_config,
1026 &dev->i2c_bus[0].i2c_adap);
363c35fc 1027 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 1028 struct dvb_frontend *fe;
1029 struct xc2028_config cfg = {
1030 .i2c_adap = &i2c_bus->i2c_adap,
1031 .i2c_addr = 0x61,
07b4a835
MK		 1032 };
1033 static struct xc2028_ctrl ctl = {
ef80bfeb 1034 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 1035 .max_len = 64,
52c3d29c 1036 .demod = XC3028_FE_OREN538,
07b4a835
MK		 1037 };
1038
1039 fe = dvb_attach(xc2028_attach,
363c35fc 1040 fe0->dvb.frontend, &cfg);
07b4a835
MK		 1041 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1042 fe->ops.tuner_ops.set_config(fe, &ctl);
1043 }
1044 break;
b3ea0166 1045 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1046 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 1047 i2c_bus = &dev->i2c_bus[0];
363c35fc 1048 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 1049 &hauppauge_hvr1200_config,
1050 &i2c_bus->i2c_adap);
363c35fc
ST		 1051 if (fe0->dvb.frontend != NULL) {
1052 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 1053 &dev->i2c_bus[1].i2c_adap, 0x42,
1054 &tda829x_no_probe);
363c35fc 1055 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 1056 0x60, &dev->i2c_bus[1].i2c_adap,
1057 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 1058 }
1059 break;
1060 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1061 i2c_bus = &dev->i2c_bus[0];
1062 fe0->dvb.frontend = dvb_attach(tda10048_attach,
1063 &hauppauge_hvr1210_config,
1064 &i2c_bus->i2c_adap);
1065 if (fe0->dvb.frontend != NULL) {
1066 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1067 0x60, &dev->i2c_bus[1].i2c_adap,
1068 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 1069 }
1070 break;
66762373
ST		 1071 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1072 i2c_bus = &dev->i2c_bus[0];
8abe4a0a
MCC		 1073
1074 if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
1075 return -ENODEV;
1076
1077 fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap,
66762373 1078 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 1079 if (fe0->dvb.frontend != NULL) {
66762373
ST		 1080 struct dvb_frontend *fe;
1081 struct xc2028_config cfg = {
1082 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
1083 .i2c_addr = 0x64,
66762373
ST		 1084 };
1085 static struct xc2028_ctrl ctl = {
ef80bfeb 1086 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 1087 .max_len = 64,
9bed77ee 1088 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST		 1089 /* This is true for all demods with
1090 v36 firmware? */
0975fc68 1091 .type = XC2028_D2633,
66762373
ST		 1092 };
1093
1094 fe = dvb_attach(xc2028_attach,
363c35fc 1095 fe0->dvb.frontend, &cfg);
66762373
ST		 1096 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1097 fe->ops.tuner_ops.set_config(fe, &ctl);
1098 }
1099 break;
335377b7
MK		 1100 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1101 i2c_bus = &dev->i2c_bus[port->nr - 1];
1102
363c35fc 1103 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 1104 &dvico_s5h1409_config,
1105 &i2c_bus->i2c_adap);
363c35fc
ST		 1106 if (fe0->dvb.frontend == NULL)
1107 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 1108 &dvico_s5h1411_config,
1109 &i2c_bus->i2c_adap);
363c35fc
ST		 1110 if (fe0->dvb.frontend != NULL)
1111 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 1112 &i2c_bus->i2c_adap,
1113 &dvico_xc5000_tunerconfig);
335377b7 1114 break;
aef2d186
ST		 1115 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
1116 i2c_bus = &dev->i2c_bus[port->nr - 1];
1117
363c35fc 1118 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 1119 &dvico_fusionhdtv_xc3028,
1120 &i2c_bus->i2c_adap);
363c35fc 1121 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 1122 struct dvb_frontend *fe;
1123 struct xc2028_config cfg = {
1124 .i2c_adap = &i2c_bus->i2c_adap,
1125 .i2c_addr = 0x61,
aef2d186
ST		 1126 };
1127 static struct xc2028_ctrl ctl = {
ef80bfeb 1128 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 1129 .max_len = 64,
1130 .demod = XC3028_FE_ZARLINK456,
1131 };
1132
363c35fc 1133 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 1134 &cfg);
1135 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1136 fe->ops.tuner_ops.set_config(fe, &ctl);
1137 }
1138 break;
46b21bba
JH		 1139 }
1140 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: {
1141 i2c_bus = &dev->i2c_bus[port->nr - 1];
1142 /* cxusb_ctrl_msg(adap->dev, CMD_DIGITAL, NULL, 0, NULL, 0); */
1143 /* cxusb_bluebird_gpio_pulse(adap->dev, 0x02, 1); */
1144
1145 if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
1146 return -ENODEV;
1147
1148 if (dib7000p_ops.i2c_enumeration(&i2c_bus->i2c_adap, 1, 0x12, &dib7070p_dib7000p_config) < 0) {
1149 printk(KERN_WARNING "Unable to enumerate dib7000p\n");
1150 return -ENODEV;
1151 }
1152 fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, 0x80, &dib7070p_dib7000p_config);
1153 if (fe0->dvb.frontend != NULL) {
1154 struct i2c_adapter *tun_i2c;
1155
1156 fe0->dvb.frontend->sec_priv = kmalloc(sizeof(dib7000p_ops), GFP_KERNEL);
1157 memcpy(fe0->dvb.frontend->sec_priv, &dib7000p_ops, sizeof(dib7000p_ops));
1158 tun_i2c = dib7000p_ops.get_i2c_master(fe0->dvb.frontend, DIBX000_I2C_INTERFACE_TUNER, 1);
1159 if (!dvb_attach(dib0070_attach, fe0->dvb.frontend, tun_i2c, &dib7070p_dib0070_config))
1160 return -ENODEV;
1161 }
1162 break;
aef2d186 1163 }
4c56b04a 1164 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 1165 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 1166 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 1167 i2c_bus = &dev->i2c_bus[0];
1168
363c35fc 1169 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 1170 &dvico_fusionhdtv_xc3028,
1171 &i2c_bus->i2c_adap);
363c35fc 1172 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 1173 struct dvb_frontend *fe;
1174 struct xc2028_config cfg = {
1175 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
1176 .i2c_addr = 0x61,
4c56b04a
ST		 1177 };
1178 static struct xc2028_ctrl ctl = {
ef80bfeb 1179 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 1180 .max_len = 64,
1181 .demod = XC3028_FE_ZARLINK456,
1182 };
1183
363c35fc 1184 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 1185 &cfg);
1186 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1187 fe->ops.tuner_ops.set_config(fe, &ctl);
1188 }
96318d0c 1189 break;
0cf8af57 1190 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1191 i2c_bus = &dev->i2c_bus[0];
1192
1193 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1194 &dvico_fusionhdtv_xc3028,
1195 &i2c_bus->i2c_adap);
1196 if (fe0->dvb.frontend != NULL) {
1197 struct dvb_frontend *fe;
1198 struct xc4000_config cfg = {
1199 .i2c_address = 0x61,
1200 .default_pm = 0,
1201 .dvb_amplitude = 134,
1202 .set_smoothedcvbs = 1,
1203 .if_khz = 4560
1204 };
1205
1206 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1207 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS		 1208 if (!fe) {
1209 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1210 dev->name);
1211 goto frontend_detach;
1212 }
0cf8af57 1213 }
1214 break;
96318d0c 1215 case CX23885_BOARD_TBS_6920:
09ea33e5 1216 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL		 1217
1218 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL		 1219 &tbs_cx24116_config,
1220 &i2c_bus->i2c_adap);
96318d0c 1221 if (fe0->dvb.frontend != NULL)
09ea33e5 1222 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1223
579943f5 1224 break;
e6001482
LA		 1225 case CX23885_BOARD_TBS_6980:
1226 case CX23885_BOARD_TBS_6981:
1227 i2c_bus = &dev->i2c_bus[1];
1228
1229 switch (port->nr) {
1230 /* PORT B */
1231 case 1:
1232 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1233 &tbs_cx24117_config,
d10e8280 1234 &i2c_bus->i2c_adap);
e6001482
LA		 1235 break;
1236 /* PORT C */
1237 case 2:
e6001482
LA		 1238 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1239 &tbs_cx24117_config,
d10e8280 1240 &i2c_bus->i2c_adap);
e6001482
LA		 1241 break;
1242 }
1243 break;
579943f5
IL		 1244 case CX23885_BOARD_TEVII_S470:
1245 i2c_bus = &dev->i2c_bus[1];
1246
09ea33e5
IL		 1247 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1248 &tevii_ds3000_config,
1249 &i2c_bus->i2c_adap);
73f0af44
KD		 1250 if (fe0->dvb.frontend != NULL) {
1251 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1252 &tevii_ts2020_config, &i2c_bus->i2c_adap);
09ea33e5 1253 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
73f0af44 1254 }
579943f5 1255
4c56b04a 1256 break;
c9b8b04b
IL		 1257 case CX23885_BOARD_DVBWORLD_2005:
1258 i2c_bus = &dev->i2c_bus[1];
1259
1260 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1261 &dvbworld_cx24116_config,
1262 &i2c_bus->i2c_adap);
1263 break;
5a23b076
IL		 1264 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1265 i2c_bus = &dev->i2c_bus[0];
1266 switch (port->nr) {
1267 /* port B */
1268 case 1:
1269 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1270 &netup_stv0900_config,
1271 &i2c_bus->i2c_adap, 0);
1272 if (fe0->dvb.frontend != NULL) {
1273 if (dvb_attach(stv6110_attach,
1274 fe0->dvb.frontend,
1275 &netup_stv6110_tunerconfig_a,
1276 &i2c_bus->i2c_adap)) {
1277 if (!dvb_attach(lnbh24_attach,
1278 fe0->dvb.frontend,
1279 &i2c_bus->i2c_adap,
9329fb5b
AO		 1280 LNBH24_PCL | LNBH24_TTX,
1281 LNBH24_TEN, 0x09))
5a23b076
IL		 1282 printk(KERN_ERR
1283 "No LNBH24 found!\n");
1284
1285 }
1286 }
1287 break;
1288 /* port C */
1289 case 2:
1290 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1291 &netup_stv0900_config,
1292 &i2c_bus->i2c_adap, 1);
1293 if (fe0->dvb.frontend != NULL) {
1294 if (dvb_attach(stv6110_attach,
1295 fe0->dvb.frontend,
1296 &netup_stv6110_tunerconfig_b,
1297 &i2c_bus->i2c_adap)) {
1298 if (!dvb_attach(lnbh24_attach,
1299 fe0->dvb.frontend,
1300 &i2c_bus->i2c_adap,
9329fb5b
AO		 1301 LNBH24_PCL | LNBH24_TTX,
1302 LNBH24_TEN, 0x0a))
5a23b076
IL		 1303 printk(KERN_ERR
1304 "No LNBH24 found!\n");
1305
1306 }
1307 }
1308 break;
1309 }
1310 break;
493b7127
DW		 1311 case CX23885_BOARD_MYGICA_X8506:
1312 i2c_bus = &dev->i2c_bus[0];
1313 i2c_bus2 = &dev->i2c_bus[1];
1314 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1315 &mygica_x8506_lgs8gl5_config,
1316 &i2c_bus->i2c_adap);
1317 if (fe0->dvb.frontend != NULL) {
1318 dvb_attach(xc5000_attach,
1319 fe0->dvb.frontend,
1320 &i2c_bus2->i2c_adap,
1321 &mygica_x8506_xc5000_config);
1322 }
15472faf 1323 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
493b7127 1324 break;
0d1b5265
MCC		 1325 case CX23885_BOARD_MYGICA_X8507:
1326 i2c_bus = &dev->i2c_bus[0];
1327 i2c_bus2 = &dev->i2c_bus[1];
1328 fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
1329 &mygica_x8507_mb86a20s_config,
1330 &i2c_bus->i2c_adap);
1331 if (fe0->dvb.frontend != NULL) {
1332 dvb_attach(xc5000_attach,
1333 fe0->dvb.frontend,
1334 &i2c_bus2->i2c_adap,
1335 &mygica_x8507_xc5000_config);
1336 }
1337 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
1338 break;
2365b2d3
DW		 1339 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1340 i2c_bus = &dev->i2c_bus[0];
1341 i2c_bus2 = &dev->i2c_bus[1];
1342 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1343 &magicpro_prohdtve2_lgs8g75_config,
1344 &i2c_bus->i2c_adap);
1345 if (fe0->dvb.frontend != NULL) {
1346 dvb_attach(xc5000_attach,
1347 fe0->dvb.frontend,
1348 &i2c_bus2->i2c_adap,
1349 &magicpro_prohdtve2_xc5000_config);
1350 }
15472faf 1351 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
2365b2d3 1352 break;
13697380 1353 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST		 1354 i2c_bus = &dev->i2c_bus[0];
1355 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1356 &hcw_s5h1411_config,
1357 &i2c_bus->i2c_adap);
1358 if (fe0->dvb.frontend != NULL)
1359 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1360 0x60, &dev->i2c_bus[0].i2c_adap,
1361 &hauppauge_tda18271_config);
1362
1363 tda18271_attach(&dev->ts1.analog_fe,
1364 0x60, &dev->i2c_bus[1].i2c_adap,
1365 &hauppauge_tda18271_config);
1366
1367 break;
aee0b24c 1368 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1369 i2c_bus = &dev->i2c_bus[0];
1370 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1371 &hcw_s5h1411_config,
1372 &i2c_bus->i2c_adap);
1373 if (fe0->dvb.frontend != NULL)
1374 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1375 0x60, &dev->i2c_bus[0].i2c_adap,
1376 &hauppauge_tda18271_config);
1377 break;
ea5697fe
DW		 1378 case CX23885_BOARD_MYGICA_X8558PRO:
1379 switch (port->nr) {
1380 /* port B */
1381 case 1:
1382 i2c_bus = &dev->i2c_bus[0];
1383 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1384 &mygica_x8558pro_atbm8830_cfg1,
1385 &i2c_bus->i2c_adap);
1386 if (fe0->dvb.frontend != NULL) {
1387 dvb_attach(max2165_attach,
1388 fe0->dvb.frontend,
1389 &i2c_bus->i2c_adap,
1390 &mygic_x8558pro_max2165_cfg1);
1391 }
1392 break;
1393 /* port C */
1394 case 2:
1395 i2c_bus = &dev->i2c_bus[1];
1396 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1397 &mygica_x8558pro_atbm8830_cfg2,
1398 &i2c_bus->i2c_adap);
1399 if (fe0->dvb.frontend != NULL) {
1400 dvb_attach(max2165_attach,
1401 fe0->dvb.frontend,
1402 &i2c_bus->i2c_adap,
1403 &mygic_x8558pro_max2165_cfg2);
1404 }
1405 break;
1406 }
1407 break;
78db8547
IL		 1408 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1409 i2c_bus = &dev->i2c_bus[0];
1410 mfe_shared = 1;/* MFE */
1411 port->frontends.gate = 0;/* not clear for me yet */
1412 /* ports B, C */
1413 /* MFE frontend 1 DVB-T */
1414 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1415 &netup_stv0367_config[port->nr - 1],
1416 &i2c_bus->i2c_adap);
4174ebf5 1417 if (fe0->dvb.frontend != NULL) {
78db8547
IL		 1418 if (NULL == dvb_attach(xc5000_attach,
1419 fe0->dvb.frontend,
1420 &i2c_bus->i2c_adap,
1421 &netup_xc5000_config[port->nr - 1]))
1422 goto frontend_detach;
4174ebf5
AO		 1423 /* load xc5000 firmware */
1424 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1425 }
78db8547 1426 /* MFE frontend 2 */
453afdd9 1427 fe1 = vb2_dvb_get_frontend(&port->frontends, 2);
78db8547
IL		 1428 if (fe1 == NULL)
1429 goto frontend_detach;
1430 /* DVB-C init */
1431 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1432 &netup_stv0367_config[port->nr - 1],
1433 &i2c_bus->i2c_adap);
1434 if (fe1->dvb.frontend != NULL) {
1435 fe1->dvb.frontend->id = 1;
1436 if (NULL == dvb_attach(xc5000_attach,
1437 fe1->dvb.frontend,
1438 &i2c_bus->i2c_adap,
1439 &netup_xc5000_config[port->nr - 1]))
1440 goto frontend_detach;
1441 }
1442 break;
722c90eb
SR		 1443 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1444 i2c_bus = &dev->i2c_bus[0];
1445 i2c_bus2 = &dev->i2c_bus[1];
1446
1447 switch (port->nr) {
1448 /* port b */
1449 case 1:
1450 fe0->dvb.frontend = dvb_attach(drxk_attach,
1451 &terratec_drxk_config[0],
1452 &i2c_bus->i2c_adap);
1453 if (fe0->dvb.frontend != NULL) {
1454 if (!dvb_attach(mt2063_attach,
1455 fe0->dvb.frontend,
1456 &terratec_mt2063_config[0],
1457 &i2c_bus2->i2c_adap))
1458 goto frontend_detach;
1459 }
1460 break;
1461 /* port c */
1462 case 2:
1463 fe0->dvb.frontend = dvb_attach(drxk_attach,
1464 &terratec_drxk_config[1],
1465 &i2c_bus->i2c_adap);
1466 if (fe0->dvb.frontend != NULL) {
1467 if (!dvb_attach(mt2063_attach,
1468 fe0->dvb.frontend,
1469 &terratec_mt2063_config[1],
1470 &i2c_bus2->i2c_adap))
1471 goto frontend_detach;
1472 }
1473 break;
1474 }
1475 break;
7b134e85
IL		 1476 case CX23885_BOARD_TEVII_S471:
1477 i2c_bus = &dev->i2c_bus[1];
1478
1479 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1480 &tevii_ds3000_config,
1481 &i2c_bus->i2c_adap);
b43ea806
JK		 1482 if (fe0->dvb.frontend != NULL) {
1483 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1484 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1485 }
7b134e85 1486 break;
f667190b
MB		 1487 case CX23885_BOARD_PROF_8000:
1488 i2c_bus = &dev->i2c_bus[0];
1489
1490 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1491 &prof_8000_stv090x_config,
1492 &i2c_bus->i2c_adap,
1493 STV090x_DEMODULATOR_0);
1494 if (fe0->dvb.frontend != NULL) {
1495 if (!dvb_attach(stb6100_attach,
1496 fe0->dvb.frontend,
1497 &prof_8000_stb6100_config,
1498 &i2c_bus->i2c_adap))
1499 goto frontend_detach;
1500
1501 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1502 }
1503 break;
7c62f5a1
MK		 1504 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1505 i2c_bus = &dev->i2c_bus[0];
36efec48
MS		 1506 i2c_bus2 = &dev->i2c_bus[1];
1507 switch (port->nr) {
1508 /* port b */
1509 case 1:
1510 fe0->dvb.frontend = dvb_attach(tda10071_attach,
7c62f5a1
MK		 1511 &hauppauge_tda10071_config,
1512 &i2c_bus->i2c_adap);
36efec48
MS		 1513 if (fe0->dvb.frontend != NULL) {
1514 if (!dvb_attach(a8293_attach, fe0->dvb.frontend,
1515 &i2c_bus->i2c_adap,
1516 &hauppauge_a8293_config))
1517 goto frontend_detach;
1518 }
1519 break;
1520 /* port c */
1521 case 2:
1522 fe0->dvb.frontend = dvb_attach(si2165_attach,
1523 &hauppauge_hvr4400_si2165_config,
1524 &i2c_bus->i2c_adap);
1525 if (fe0->dvb.frontend != NULL) {
711c3119 1526 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
36efec48
MS		 1527 if (!dvb_attach(tda18271_attach,
1528 fe0->dvb.frontend,
1529 0x60, &i2c_bus2->i2c_adap,
1530 &hauppauge_hvr4400_tuner_config))
1531 goto frontend_detach;
1532 }
1533 break;
7c62f5a1
MK		 1534 }
1535 break;
d19770e5 1536 default:
9c8ced51
ST		 1537 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1538 " isn't supported yet\n",
d19770e5
ST		 1539 dev->name);
1540 break;
1541 }
78db8547
IL		 1542
1543 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1544 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL		 1545 dev->name);
1546 goto frontend_detach;
d19770e5 1547 }
78db8547 1548
d7cba043 1549 /* define general-purpose callback pointer */
363c35fc 1550 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL		 1551 if (fe1)
1552 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1553#if 0
1554 /* Ensure all frontends negotiate bus access */
1555 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1556 if (fe1)
1557 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1558#endif
d19770e5
ST		 1559
1560 /* Put the analog decoder in standby to keep it quiet */
622b828a 1561 call_all(dev, core, s_power, 0);
d19770e5 1562
363c35fc
ST		 1563 if (fe0->dvb.frontend->ops.analog_ops.standby)
1564 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1565
d19770e5 1566 /* register everything */
453afdd9 1567 ret = vb2_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1568 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1569 if (ret)
78db8547 1570 goto frontend_detach;
363c35fc 1571
5a23b076
IL		 1572 /* init CI & MAC */
1573 switch (dev->board) {
1574 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1575 static struct netup_card_info cinfo;
1576
1577 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1578 memcpy(port->frontends.adapter.proposed_mac,
1579 cinfo.port[port->nr - 1].mac, 6);
be395157 1580 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1581 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL		 1582
1583 netup_ci_init(port);
1584 break;
1585 }
78db8547
IL		 1586 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1587 struct altera_ci_config netup_ci_cfg = {
1588 .dev = dev,/* magic number to identify*/
1589 .adapter = &port->frontends.adapter,/* for CI */
1590 .demux = &fe0->dvb.demux,/* for hw pid filter */
1591 .fpga_rw = netup_altera_fpga_rw,
1592 };
1593
1594 altera_ci_init(&netup_ci_cfg, port->nr);
1595 break;
1596 }
16bfdaa4
PG		 1597 case CX23885_BOARD_TEVII_S470: {
1598 u8 eeprom[256]; /* 24C02 i2c eeprom */
1599
1600 if (port->nr != 1)
1601 break;
1602
1603 /* Read entire EEPROM */
1604 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1605 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1606 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG		 1607 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1608 break;
1609 }
5a23b076
IL		 1610 }
1611
1612 return ret;
78db8547
IL		 1613
1614frontend_detach:
1615 port->gate_ctrl = NULL;
453afdd9 1616 vb2_dvb_dealloc_frontends(&port->frontends);
78db8547 1617 return -EINVAL;
d19770e5
ST		 1618}
1619
1620int cx23885_dvb_register(struct cx23885_tsport *port)
1621{
363c35fc 1622
453afdd9 1623 struct vb2_dvb_frontend *fe0;
d19770e5 1624 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 1625 int err, i;
1626
1627 /* Here we need to allocate the correct number of frontends,
af901ca1 1628 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 1629 * no cx23885 boards support this - yet. But, if we don't modify this
1630 * code then the second frontend would never be allocated (later)
1631 * and fail with error before the attach in dvb_register().
1632 * Without these changes we risk an OOPS later. The changes here
1633 * are for safety, and should provide a good foundation for the
1634 * future addition of any multi-frontend cx23885 based boards.
1635 */
1636 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1637 port->num_frontends);
d19770e5 1638
eb0c58bb 1639 for (i = 1; i <= port->num_frontends; i++) {
453afdd9
HV		 1640 struct vb2_queue *q;
1641
1642 if (vb2_dvb_alloc_frontend(
9c8ced51 1643 &port->frontends, i) == NULL) {
eb0c58bb
ST		 1644 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1645 return -ENOMEM;
1646 }
1647
453afdd9 1648 fe0 = vb2_dvb_get_frontend(&port->frontends, i);
eb0c58bb
ST		 1649 if (!fe0)
1650 err = -EINVAL;
363c35fc 1651
eb0c58bb 1652 dprintk(1, "%s\n", __func__);
9c8ced51 1653 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 1654 dev->board,
1655 dev->name,
1656 dev->pci_bus,
1657 dev->pci_slot);
d19770e5 1658
eb0c58bb 1659 err = -ENODEV;
d19770e5 1660
eb0c58bb
ST		 1661 /* dvb stuff */
1662 /* We have to init the queue for each frontend on a port. */
9c8ced51 1663 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
453afdd9
HV		 1664 q = &fe0->dvb.dvbq;
1665 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1666 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1667 q->gfp_flags = GFP_DMA32;
1668 q->min_buffers_needed = 2;
1669 q->drv_priv = port;
1670 q->buf_struct_size = sizeof(struct cx23885_buffer);
1671 q->ops = &dvb_qops;
1672 q->mem_ops = &vb2_dma_sg_memops;
1673 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1674 q->lock = &dev->lock;
1675
1676 err = vb2_queue_init(q);
1677 if (err < 0)
1678 return err;
eb0c58bb 1679 }
d19770e5
ST		 1680 err = dvb_register(port);
1681 if (err != 0)
9c8ced51
ST		 1682 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1683 __func__, err);
d19770e5 1684
d19770e5
ST		 1685 return err;
1686}
1687
1688int cx23885_dvb_unregister(struct cx23885_tsport *port)
1689{
453afdd9 1690 struct vb2_dvb_frontend *fe0;
363c35fc 1691
eb0c58bb
ST		 1692 /* FIXME: in an error condition where the we have
1693 * an expected number of frontends (attach problem)
1694 * then this might not clean up correctly, if 1
1695 * is invalid.
1696 * This comment only applies to future boards IF they
1697 * implement MFE support.
1698 */
453afdd9 1699 fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
e66131ce 1700 if (fe0 && fe0->dvb.frontend)
453afdd9 1701 vb2_dvb_unregister_bus(&port->frontends);
d19770e5 1702
afd96668
HV		 1703 switch (port->dev->board) {
1704 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1705 netup_ci_exit(port);
1706 break;
78db8547
IL		 1707 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1708 altera_ci_release(port->dev, port->nr);
1709 break;
afd96668 1710 }
5a23b076 1711
78db8547
IL		 1712 port->gate_ctrl = NULL;
1713
d19770e5
ST		 1714 return 0;
1715}
Linux kernel - Deliverables
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