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[media] cx23885: add support for TechnoTrend CT2-4500 CI
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
d19770e5
ST		 16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/device.h>
21#include <linux/fs.h>
22#include <linux/kthread.h>
23#include <linux/file.h>
24#include <linux/suspend.h>
25
26#include "cx23885.h"
d19770e5
ST		 27#include <media/v4l2-common.h>
28
5a23b076 29#include "dvb_ca_en50221.h"
d19770e5 30#include "s5h1409.h"
52b50450 31#include "s5h1411.h"
d19770e5 32#include "mt2131.h"
3ba71d21 33#include "tda8290.h"
4041f1a5 34#include "tda18271.h"
9bc37caa 35#include "lgdt330x.h"
0cf8af57 36#include "xc4000.h"
d1987d55 37#include "xc5000.h"
ea5697fe 38#include "max2165.h"
b3ea0166 39#include "tda10048.h"
07b4a835 40#include "tuner-xc2028.h"
827855d3 41#include "tuner-simple.h"
66762373 42#include "dib7000p.h"
46b21bba 43#include "dib0070.h"
66762373 44#include "dibx000_common.h"
aef2d186 45#include "zl10353.h"
5a23b076 46#include "stv0900.h"
f867c3f4 47#include "stv0900_reg.h"
5a23b076
IL		 48#include "stv6110.h"
49#include "lnbh24.h"
96318d0c 50#include "cx24116.h"
e6001482 51#include "cx24117.h"
5a23b076 52#include "cimax2.h"
493b7127 53#include "lgs8gxx.h"
5a23b076
IL		 54#include "netup-eeprom.h"
55#include "netup-init.h"
a5dbf457 56#include "lgdt3305.h"
ea5697fe 57#include "atbm8830.h"
73f0af44 58#include "ts2020.h"
09ea33e5
IL		 59#include "ds3000.h"
60#include "cx23885-f300.h"
78db8547
IL		 61#include "altera-ci.h"
62#include "stv0367.h"
722c90eb
SR		 63#include "drxk.h"
64#include "mt2063.h"
f667190b
MB		 65#include "stv090x.h"
66#include "stb6100.h"
67#include "stb6100_cfg.h"
7c62f5a1
MK		 68#include "tda10071.h"
69#include "a8293.h"
0d1b5265 70#include "mb86a20s.h"
36efec48 71#include "si2165.h"
29442266
OS		 72#include "si2168.h"
73#include "si2157.h"
24e77409 74#include "sp2.h"
29442266
OS		 75#include "m88ds3103.h"
76#include "m88ts2022.h"
d19770e5 77
4513fc69 78static unsigned int debug;
d19770e5 79
4513fc69
ST		 80#define dprintk(level, fmt, arg...)\
81 do { if (debug >= level)\
82 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
83 } while (0)
d19770e5
ST		 84
85/* ------------------------------------------------------------------ */
86
3ba71d21
MK		 87static unsigned int alt_tuner;
88module_param(alt_tuner, int, 0644);
89MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
90
78e92006
JG		 91DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
92
3ba71d21
MK		 93/* ------------------------------------------------------------------ */
94
453afdd9
HV		 95static int queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt,
96 unsigned int *num_buffers, unsigned int *num_planes,
97 unsigned int sizes[], void *alloc_ctxs[])
d19770e5 98{
453afdd9 99 struct cx23885_tsport *port = q->drv_priv;
d19770e5
ST		 100
101 port->ts_packet_size = 188 * 4;
102 port->ts_packet_count = 32;
453afdd9
HV		 103 *num_planes = 1;
104 sizes[0] = port->ts_packet_size * port->ts_packet_count;
105 *num_buffers = 32;
d19770e5
ST		 106 return 0;
107}
108
453afdd9
HV		 109
110static int buffer_prepare(struct vb2_buffer *vb)
d19770e5 111{
453afdd9
HV		 112 struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
113 struct cx23885_buffer *buf =
114 container_of(vb, struct cx23885_buffer, vb);
115
116 return cx23885_buf_prepare(buf, port);
d19770e5
ST		 117}
118
453afdd9 119static void buffer_finish(struct vb2_buffer *vb)
d19770e5 120{
453afdd9
HV		 121 struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
122 struct cx23885_dev *dev = port->dev;
123 struct cx23885_buffer *buf = container_of(vb,
124 struct cx23885_buffer, vb);
125 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
126
127 cx23885_free_buffer(dev, buf);
128
129 dma_unmap_sg(&dev->pci->dev, sgt->sgl, sgt->nents, DMA_FROM_DEVICE);
d19770e5
ST		 130}
131
453afdd9 132static void buffer_queue(struct vb2_buffer *vb)
d19770e5 133{
453afdd9
HV		 134 struct cx23885_tsport *port = vb->vb2_queue->drv_priv;
135 struct cx23885_buffer *buf = container_of(vb,
136 struct cx23885_buffer, vb);
137
138 cx23885_buf_queue(port, buf);
d19770e5
ST		 139}
140
78db8547
IL		 141static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
142{
453afdd9
HV		 143 struct vb2_dvb_frontends *f;
144 struct vb2_dvb_frontend *fe;
78db8547
IL		 145
146 f = &port->frontends;
147
148 if (f->gate <= 1) /* undefined or fe0 */
453afdd9 149 fe = vb2_dvb_get_frontend(f, 1);
78db8547 150 else
453afdd9 151 fe = vb2_dvb_get_frontend(f, f->gate);
78db8547
IL		 152
153 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
154 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
155}
156
453afdd9
HV		 157static int cx23885_start_streaming(struct vb2_queue *q, unsigned int count)
158{
159 struct cx23885_tsport *port = q->drv_priv;
160 struct cx23885_dmaqueue *dmaq = &port->mpegq;
161 struct cx23885_buffer *buf = list_entry(dmaq->active.next,
162 struct cx23885_buffer, queue);
163
164 cx23885_start_dma(port, dmaq, buf);
165 return 0;
166}
167
168static void cx23885_stop_streaming(struct vb2_queue *q)
169{
170 struct cx23885_tsport *port = q->drv_priv;
171
172 cx23885_cancel_buffers(port);
173}
174
175static struct vb2_ops dvb_qops = {
176 .queue_setup = queue_setup,
177 .buf_prepare = buffer_prepare,
178 .buf_finish = buffer_finish,
179 .buf_queue = buffer_queue,
180 .wait_prepare = vb2_ops_wait_prepare,
181 .wait_finish = vb2_ops_wait_finish,
182 .start_streaming = cx23885_start_streaming,
183 .stop_streaming = cx23885_stop_streaming,
d19770e5
ST		 184};
185
86184e06 186static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 187 .demod_address = 0x32 >> 1,
188 .output_mode = S5H1409_SERIAL_OUTPUT,
189 .gpio = S5H1409_GPIO_ON,
2b03238a 190 .qam_if = 44000,
fc959bef 191 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 192 .status_mode = S5H1409_DEMODLOCKING,
193 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 194};
195
b3ea0166
ST		 196static struct tda10048_config hauppauge_hvr1200_config = {
197 .demod_address = 0x10 >> 1,
198 .output_mode = TDA10048_SERIAL_OUTPUT,
199 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 200 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 201 .dtv6_if_freq_khz = TDA10048_IF_3300,
202 .dtv7_if_freq_khz = TDA10048_IF_3800,
203 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 204 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 205};
206
6b926eca
MK		 207static struct tda10048_config hauppauge_hvr1210_config = {
208 .demod_address = 0x10 >> 1,
209 .output_mode = TDA10048_SERIAL_OUTPUT,
210 .fwbulkwritelen = TDA10048_BULKWRITE_200,
211 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 212 .dtv6_if_freq_khz = TDA10048_IF_3300,
213 .dtv7_if_freq_khz = TDA10048_IF_3500,
214 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 215 .clk_freq_khz = TDA10048_CLK_16000,
216};
217
3ba71d21
MK		 218static struct s5h1409_config hauppauge_ezqam_config = {
219 .demod_address = 0x32 >> 1,
220 .output_mode = S5H1409_SERIAL_OUTPUT,
221 .gpio = S5H1409_GPIO_OFF,
222 .qam_if = 4000,
223 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 224 .status_mode = S5H1409_DEMODLOCKING,
225 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 226};
227
fc959bef 228static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 229 .demod_address = 0x32 >> 1,
230 .output_mode = S5H1409_SERIAL_OUTPUT,
231 .gpio = S5H1409_GPIO_OFF,
2b03238a 232 .qam_if = 44000,
fe475163 233 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 234 .status_mode = S5H1409_DEMODLOCKING,
235 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 236};
237
07b4a835
MK		 238static struct s5h1409_config hauppauge_hvr1500_config = {
239 .demod_address = 0x32 >> 1,
240 .output_mode = S5H1409_SERIAL_OUTPUT,
241 .gpio = S5H1409_GPIO_OFF,
242 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 243 .status_mode = S5H1409_DEMODLOCKING,
244 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 245};
246
86184e06 247static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 248 0x61
249};
250
9bc37caa
MK		 251static struct lgdt330x_config fusionhdtv_5_express = {
252 .demod_address = 0x0e,
253 .demod_chip = LGDT3303,
254 .serial_mpeg = 0x40,
255};
256
d1987d55
ST		 257static struct s5h1409_config hauppauge_hvr1500q_config = {
258 .demod_address = 0x32 >> 1,
259 .output_mode = S5H1409_SERIAL_OUTPUT,
260 .gpio = S5H1409_GPIO_ON,
261 .qam_if = 44000,
262 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 263 .status_mode = S5H1409_DEMODLOCKING,
264 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 265};
266
335377b7
MK		 267static struct s5h1409_config dvico_s5h1409_config = {
268 .demod_address = 0x32 >> 1,
269 .output_mode = S5H1409_SERIAL_OUTPUT,
270 .gpio = S5H1409_GPIO_ON,
271 .qam_if = 44000,
272 .inversion = S5H1409_INVERSION_OFF,
273 .status_mode = S5H1409_DEMODLOCKING,
274 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
275};
276
52b50450
MK		 277static struct s5h1411_config dvico_s5h1411_config = {
278 .output_mode = S5H1411_SERIAL_OUTPUT,
279 .gpio = S5H1411_GPIO_ON,
280 .qam_if = S5H1411_IF_44000,
281 .vsb_if = S5H1411_IF_44000,
282 .inversion = S5H1411_INVERSION_OFF,
283 .status_mode = S5H1411_DEMODLOCKING,
284 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
285};
286
19bc5796
MK		 287static struct s5h1411_config hcw_s5h1411_config = {
288 .output_mode = S5H1411_SERIAL_OUTPUT,
289 .gpio = S5H1411_GPIO_OFF,
290 .vsb_if = S5H1411_IF_44000,
291 .qam_if = S5H1411_IF_4000,
292 .inversion = S5H1411_INVERSION_ON,
293 .status_mode = S5H1411_DEMODLOCKING,
294 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
295};
296
d1987d55 297static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 298 .i2c_address = 0x61,
299 .if_khz = 5380,
d1987d55
ST		 300};
301
335377b7
MK		 302static struct xc5000_config dvico_xc5000_tunerconfig = {
303 .i2c_address = 0x64,
304 .if_khz = 5380,
335377b7
MK		 305};
306
4041f1a5
MK		 307static struct tda829x_config tda829x_no_probe = {
308 .probe_tuner = TDA829X_DONT_PROBE,
309};
310
f21e0d7f 311static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 312 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
313 .if_lvl = 6, .rfagc_top = 0x37 },
314 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
315 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 316};
317
b34cdc36
MK		 318static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
319 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
320 .if_lvl = 1, .rfagc_top = 0x37, },
321 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
322 .if_lvl = 1, .rfagc_top = 0x37, },
323 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
324 .if_lvl = 1, .rfagc_top = 0x37, },
325};
326
f21e0d7f
MK		 327static struct tda18271_config hauppauge_tda18271_config = {
328 .std_map = &hauppauge_tda18271_std_map,
329 .gate = TDA18271_GATE_ANALOG,
04a68baa 330 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 331};
332
b3ea0166 333static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 334 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 335 .gate = TDA18271_GATE_ANALOG,
04a68baa 336 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 337};
338
6b926eca
MK		 339static struct tda18271_config hauppauge_hvr1210_tuner_config = {
340 .gate = TDA18271_GATE_DIGITAL,
04a68baa 341 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 342};
343
36efec48
MS		 344static struct tda18271_config hauppauge_hvr4400_tuner_config = {
345 .gate = TDA18271_GATE_DIGITAL,
346 .output_opt = TDA18271_OUTPUT_LT_OFF,
347};
348
247bc540 349static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 350 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
351 .if_lvl = 1, .rfagc_top = 0x58 },
352 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
353 .if_lvl = 1, .rfagc_top = 0x58 },
354};
355
247bc540
MK		 356static struct tda18271_config hauppauge_hvr127x_config = {
357 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 358 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 359};
360
247bc540 361static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 362 .i2c_addr = 0x0e,
363 .mpeg_mode = LGDT3305_MPEG_SERIAL,
364 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
365 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
366 .deny_i2c_rptr = 1,
367 .spectral_inversion = 1,
368 .qam_if_khz = 4000,
369 .vsb_if_khz = 3250,
370};
371
b1721d0d 372static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 373 BAND_VHF | BAND_UHF, /* band_caps */
374
375 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
376 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
377 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
378 * P_agc_nb_est=2, P_agc_write=0
379 */
380 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
381 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
382
383 712, /* inv_gain */
384 21, /* time_stabiliz */
385
386 0, /* alpha_level */
387 118, /* thlock */
388
389 0, /* wbd_inv */
390 2867, /* wbd_ref */
391 0, /* wbd_sel */
392 2, /* wbd_alpha */
393
394 0, /* agc1_max */
395 0, /* agc1_min */
396 39718, /* agc2_max */
397 9930, /* agc2_min */
398 0, /* agc1_pt1 */
399 0, /* agc1_pt2 */
400 0, /* agc1_pt3 */
401 0, /* agc1_slope1 */
402 0, /* agc1_slope2 */
403 0, /* agc2_pt1 */
404 128, /* agc2_pt2 */
405 29, /* agc2_slope1 */
406 29, /* agc2_slope2 */
407
408 17, /* alpha_mant */
409 27, /* alpha_exp */
410 23, /* beta_mant */
411 51, /* beta_exp */
412
413 1, /* perform_agc_softsplit */
414};
415
416/* PLL Configuration for COFDM BW_MHz = 8.000000
417 * With external clock = 30.000000 */
b1721d0d 418static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 419 60000, /* internal */
420 30000, /* sampling */
421 1, /* pll_cfg: prediv */
422 8, /* pll_cfg: ratio */
423 3, /* pll_cfg: range */
424 1, /* pll_cfg: reset */
425 0, /* pll_cfg: bypass */
426 0, /* misc: refdiv */
427 0, /* misc: bypclk_div */
428 1, /* misc: IO_CLK_en_core */
429 1, /* misc: ADClkSrc */
430 0, /* misc: modulo */
431 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
432 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
433 20452225, /* timf */
434 30000000 /* xtal_hz */
435};
436
437static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
438 .output_mpeg2_in_188_bytes = 1,
439 .hostbus_diversity = 1,
440 .tuner_is_baseband = 0,
441 .update_lna = NULL,
442
443 .agc_config_count = 1,
444 .agc = &xc3028_agc_config,
445 .bw = &xc3028_bw_config,
446
447 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
448 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
449 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
450
451 .pwm_freq_div = 0,
452 .agc_control = NULL,
453 .spur_protect = 0,
454
455 .output_mode = OUTMODE_MPEG2_SERIAL,
456};
457
aef2d186
ST		 458static struct zl10353_config dvico_fusionhdtv_xc3028 = {
459 .demod_address = 0x0f,
460 .if2 = 45600,
461 .no_tuner = 1,
d4dc673d 462 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 463};
464
f867c3f4
IL		 465static struct stv0900_reg stv0900_ts_regs[] = {
466 { R0900_TSGENERAL, 0x00 },
467 { R0900_P1_TSSPEED, 0x40 },
468 { R0900_P2_TSSPEED, 0x40 },
469 { R0900_P1_TSCFGM, 0xc0 },
470 { R0900_P2_TSCFGM, 0xc0 },
471 { R0900_P1_TSCFGH, 0xe0 },
472 { R0900_P2_TSCFGH, 0xe0 },
473 { R0900_P1_TSCFGL, 0x20 },
474 { R0900_P2_TSCFGL, 0x20 },
475 { 0xffff, 0xff }, /* terminate */
476};
477
5a23b076
IL		 478static struct stv0900_config netup_stv0900_config = {
479 .demod_address = 0x68,
29372a8d 480 .demod_mode = 1, /* dual */
644c7ef0 481 .xtal = 8000000,
5a23b076
IL		 482 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
483 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 484 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 485 .tun1_maddress = 0,/* 0x60 */
486 .tun2_maddress = 3,/* 0x63 */
487 .tun1_adc = 1,/* 1 Vpp */
488 .tun2_adc = 1,/* 1 Vpp */
489};
490
491static struct stv6110_config netup_stv6110_tunerconfig_a = {
492 .i2c_address = 0x60,
644c7ef0
AO		 493 .mclk = 16000000,
494 .clk_div = 1,
873688cd 495 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 496};
497
498static struct stv6110_config netup_stv6110_tunerconfig_b = {
499 .i2c_address = 0x63,
644c7ef0
AO		 500 .mclk = 16000000,
501 .clk_div = 1,
873688cd 502 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 503};
504
96318d0c 505static struct cx24116_config tbs_cx24116_config = {
09ea33e5 506 .demod_address = 0x55,
96318d0c
IL		 507};
508
e6001482
LA		 509static struct cx24117_config tbs_cx24117_config = {
510 .demod_address = 0x55,
511};
512
09ea33e5
IL		 513static struct ds3000_config tevii_ds3000_config = {
514 .demod_address = 0x68,
579943f5
IL		 515};
516
73f0af44
KD		 517static struct ts2020_config tevii_ts2020_config = {
518 .tuner_address = 0x60,
b858c331 519 .clk_out_div = 1,
8d2b0229 520 .frequency_div = 1146000,
73f0af44
KD		 521};
522
c9b8b04b
IL		 523static struct cx24116_config dvbworld_cx24116_config = {
524 .demod_address = 0x05,
525};
526
493b7127
DW		 527static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
528 .prod = LGS8GXX_PROD_LGS8GL5,
529 .demod_address = 0x19,
530 .serial_ts = 0,
531 .ts_clk_pol = 1,
532 .ts_clk_gated = 1,
533 .if_clk_freq = 30400, /* 30.4 MHz */
534 .if_freq = 5380, /* 5.38 MHz */
535 .if_neg_center = 1,
536 .ext_adc = 0,
537 .adc_signed = 0,
538 .if_neg_edge = 0,
539};
540
541static struct xc5000_config mygica_x8506_xc5000_config = {
542 .i2c_address = 0x61,
543 .if_khz = 5380,
544};
545
0d1b5265
MCC		 546static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
547 .demod_address = 0x10,
548};
549
550static struct xc5000_config mygica_x8507_xc5000_config = {
551 .i2c_address = 0x61,
552 .if_khz = 4000,
553};
554
f667190b 555static struct stv090x_config prof_8000_stv090x_config = {
b858c331
IL		 556 .device = STV0903,
557 .demod_mode = STV090x_SINGLE,
558 .clk_mode = STV090x_CLK_EXT,
559 .xtal = 27000000,
560 .address = 0x6A,
561 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
562 .repeater_level = STV090x_RPTLEVEL_64,
563 .adc1_range = STV090x_ADC_2Vpp,
564 .diseqc_envelope_mode = false,
565
566 .tuner_get_frequency = stb6100_get_frequency,
567 .tuner_set_frequency = stb6100_set_frequency,
568 .tuner_set_bandwidth = stb6100_set_bandwidth,
569 .tuner_get_bandwidth = stb6100_get_bandwidth,
f667190b
MB		 570};
571
572static struct stb6100_config prof_8000_stb6100_config = {
573 .tuner_address = 0x60,
574 .refclock = 27000000,
575};
576
577static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
578{
579 struct cx23885_tsport *port = fe->dvb->priv;
580 struct cx23885_dev *dev = port->dev;
581
582 if (voltage == SEC_VOLTAGE_18)
583 cx_write(MC417_RWD, 0x00001e00);
584 else if (voltage == SEC_VOLTAGE_13)
585 cx_write(MC417_RWD, 0x00001a00);
586 else
587 cx_write(MC417_RWD, 0x00001800);
588 return 0;
589}
590
29442266
OS		 591static int dvbsky_t9580_set_voltage(struct dvb_frontend *fe,
592 fe_sec_voltage_t voltage)
593{
594 struct cx23885_tsport *port = fe->dvb->priv;
595 struct cx23885_dev *dev = port->dev;
596
597 cx23885_gpio_enable(dev, GPIO_0 | GPIO_1, 1);
598
599 switch (voltage) {
600 case SEC_VOLTAGE_13:
601 cx23885_gpio_set(dev, GPIO_1);
602 cx23885_gpio_clear(dev, GPIO_0);
603 break;
604 case SEC_VOLTAGE_18:
605 cx23885_gpio_set(dev, GPIO_1);
606 cx23885_gpio_set(dev, GPIO_0);
607 break;
608 case SEC_VOLTAGE_OFF:
609 cx23885_gpio_clear(dev, GPIO_1);
610 cx23885_gpio_clear(dev, GPIO_0);
611 break;
612 }
613
614 /* call the frontend set_voltage function */
615 port->fe_set_voltage(fe, voltage);
616
617 return 0;
618}
619
24e77409
OS		 620static int cx23885_sp2_ci_ctrl(void *priv, u8 read, int addr,
621 u8 data, int *mem)
622{
623 /* MC417 */
624 #define SP2_DATA 0x000000ff
625 #define SP2_WR 0x00008000
626 #define SP2_RD 0x00004000
627 #define SP2_ACK 0x00001000
628 #define SP2_ADHI 0x00000800
629 #define SP2_ADLO 0x00000400
630 #define SP2_CS1 0x00000200
631 #define SP2_CS0 0x00000100
632 #define SP2_EN_ALL 0x00001000
633 #define SP2_CTRL_OFF (SP2_CS1 | SP2_CS0 | SP2_WR | SP2_RD)
634
635 struct cx23885_tsport *port = priv;
636 struct cx23885_dev *dev = port->dev;
637 int ret;
0e6c7b01 638 int tmp = 0;
24e77409
OS		 639 unsigned long timeout;
640
641 mutex_lock(&dev->gpio_lock);
642
643 /* write addr */
644 cx_write(MC417_OEN, SP2_EN_ALL);
645 cx_write(MC417_RWD, SP2_CTRL_OFF |
646 SP2_ADLO | (0xff & addr));
647 cx_clear(MC417_RWD, SP2_ADLO);
648 cx_write(MC417_RWD, SP2_CTRL_OFF |
649 SP2_ADHI | (0xff & (addr >> 8)));
650 cx_clear(MC417_RWD, SP2_ADHI);
651
652 if (read)
653 /* data in */
654 cx_write(MC417_OEN, SP2_EN_ALL | SP2_DATA);
655 else
656 /* data out */
657 cx_write(MC417_RWD, SP2_CTRL_OFF | data);
658
659 /* chip select 0 */
660 cx_clear(MC417_RWD, SP2_CS0);
661
662 /* read/write */
663 cx_clear(MC417_RWD, (read) ? SP2_RD : SP2_WR);
664
665 /* wait for a maximum of 1 msec */
666 timeout = jiffies + msecs_to_jiffies(1);
667 while (!time_after(jiffies, timeout)) {
668 tmp = cx_read(MC417_RWD);
669 if ((tmp & SP2_ACK) == 0)
670 break;
671 usleep_range(50, 100);
672 }
673
674 cx_set(MC417_RWD, SP2_CTRL_OFF);
675 *mem = tmp & 0xff;
676
677 mutex_unlock(&dev->gpio_lock);
678
679 if (!read) {
680 if (*mem < 0) {
681 ret = -EREMOTEIO;
682 goto err;
683 }
684 }
685
686 return 0;
687err:
688 return ret;
689}
690
a7d44baa 691static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 692{
a7d44baa 693 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK		 694 struct cx23885_tsport *port = fe->dvb->priv;
695 struct cx23885_dev *dev = port->dev;
696
697 switch (dev->board) {
698 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 699 switch (p->modulation) {
f35b9e80
MK		 700 case VSB_8:
701 cx23885_gpio_clear(dev, GPIO_5);
702 break;
703 case QAM_64:
704 case QAM_256:
705 default:
706 cx23885_gpio_set(dev, GPIO_5);
707 break;
708 }
709 break;
6f0d8c02 710 case CX23885_BOARD_MYGICA_X8506:
0d1b5265 711 case CX23885_BOARD_MYGICA_X8507:
6f0d8c02
DW		 712 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
713 /* Select Digital TV */
714 cx23885_gpio_set(dev, GPIO_0);
715 break;
f35b9e80 716 }
15472faf
MCC		 717
718 /* Call the real set_frontend */
719 if (port->set_frontend)
720 return port->set_frontend(fe);
721
5bdd3962 722 return 0;
f35b9e80
MK		 723}
724
15472faf
MCC		 725static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
726 struct dvb_frontend *fe)
727{
728 port->set_frontend = fe->ops.set_frontend;
729 fe->ops.set_frontend = cx23885_dvb_set_frontend;
730}
731
2365b2d3
DW		 732static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
733 .prod = LGS8GXX_PROD_LGS8G75,
734 .demod_address = 0x19,
735 .serial_ts = 0,
736 .ts_clk_pol = 1,
737 .ts_clk_gated = 1,
738 .if_clk_freq = 30400, /* 30.4 MHz */
739 .if_freq = 6500, /* 6.50 MHz */
740 .if_neg_center = 1,
741 .ext_adc = 0,
742 .adc_signed = 1,
743 .adc_vpp = 2, /* 1.6 Vpp */
744 .if_neg_edge = 1,
745};
746
747static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
748 .i2c_address = 0x61,
749 .if_khz = 6500,
750};
751
ea5697fe
DW		 752static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
753 .prod = ATBM8830_PROD_8830,
754 .demod_address = 0x44,
755 .serial_ts = 0,
756 .ts_sampling_edge = 1,
757 .ts_clk_gated = 0,
758 .osc_clk_freq = 30400, /* in kHz */
759 .if_freq = 0, /* zero IF */
760 .zif_swap_iq = 1,
c245c75c
DW		 761 .agc_min = 0x2E,
762 .agc_max = 0xFF,
763 .agc_hold_loop = 0,
ea5697fe
DW		 764};
765
766static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
767 .i2c_address = 0x60,
768 .osc_clk = 20
769};
770
771static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
772 .prod = ATBM8830_PROD_8830,
773 .demod_address = 0x44,
774 .serial_ts = 1,
775 .ts_sampling_edge = 1,
776 .ts_clk_gated = 0,
777 .osc_clk_freq = 30400, /* in kHz */
778 .if_freq = 0, /* zero IF */
779 .zif_swap_iq = 1,
c245c75c
DW		 780 .agc_min = 0x2E,
781 .agc_max = 0xFF,
782 .agc_hold_loop = 0,
ea5697fe
DW		 783};
784
785static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
786 .i2c_address = 0x60,
787 .osc_clk = 20
788};
78db8547
IL		 789static struct stv0367_config netup_stv0367_config[] = {
790 {
791 .demod_address = 0x1c,
792 .xtal = 27000000,
793 .if_khz = 4500,
794 .if_iq_mode = 0,
795 .ts_mode = 1,
796 .clk_pol = 0,
797 }, {
798 .demod_address = 0x1d,
799 .xtal = 27000000,
800 .if_khz = 4500,
801 .if_iq_mode = 0,
802 .ts_mode = 1,
803 .clk_pol = 0,
804 },
805};
806
807static struct xc5000_config netup_xc5000_config[] = {
808 {
809 .i2c_address = 0x61,
810 .if_khz = 4500,
811 }, {
812 .i2c_address = 0x64,
813 .if_khz = 4500,
814 },
815};
816
722c90eb
SR		 817static struct drxk_config terratec_drxk_config[] = {
818 {
819 .adr = 0x29,
820 .no_i2c_bridge = 1,
821 }, {
822 .adr = 0x2a,
823 .no_i2c_bridge = 1,
824 },
825};
826
827static struct mt2063_config terratec_mt2063_config[] = {
828 {
829 .tuner_address = 0x60,
830 }, {
831 .tuner_address = 0x67,
832 },
833};
834
7c62f5a1 835static const struct tda10071_config hauppauge_tda10071_config = {
41f55d57 836 .demod_i2c_addr = 0x05,
7c62f5a1
MK		 837 .tuner_i2c_addr = 0x54,
838 .i2c_wr_max = 64,
839 .ts_mode = TDA10071_TS_SERIAL,
840 .spec_inv = 0,
841 .xtal = 40444000, /* 40.444 MHz */
842 .pll_multiplier = 20,
843};
844
845static const struct a8293_config hauppauge_a8293_config = {
846 .i2c_addr = 0x0b,
847};
848
36efec48
MS		 849static const struct si2165_config hauppauge_hvr4400_si2165_config = {
850 .i2c_addr = 0x64,
851 .chip_mode = SI2165_MODE_PLL_XTAL,
852 .ref_freq_Hz = 16000000,
853};
854
29442266
OS		 855static const struct m88ds3103_config dvbsky_t9580_m88ds3103_config = {
856 .i2c_addr = 0x68,
857 .clock = 27000000,
858 .i2c_wr_max = 33,
859 .clock_out = 0,
860 .ts_mode = M88DS3103_TS_PARALLEL,
861 .ts_clk = 16000,
862 .ts_clk_pol = 1,
863 .lnb_en_pol = 1,
864 .lnb_hv_pol = 0,
865 .agc = 0x99,
866};
867
0e6c7b01 868static const struct m88ds3103_config dvbsky_s950c_m88ds3103_config = {
869 .i2c_addr = 0x68,
870 .clock = 27000000,
871 .i2c_wr_max = 33,
872 .clock_out = 0,
873 .ts_mode = M88DS3103_TS_CI,
874 .ts_clk = 10000,
875 .ts_clk_pol = 1,
876 .lnb_en_pol = 1,
877 .lnb_hv_pol = 0,
878 .agc = 0x99,
879};
880
ada73eee 881static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
78db8547
IL		 882{
883 struct cx23885_dev *dev = (struct cx23885_dev *)device;
884 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 885 uint32_t mem = 0;
78db8547 886
d164460f 887 mem = cx_read(MC417_RWD);
78db8547
IL		 888 if (read)
889 cx_set(MC417_OEN, ALT_DATA);
890 else {
891 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL		 892 mem &= ~ALT_DATA;
893 mem |= (data & ALT_DATA);
78db8547
IL		 894 }
895
896 if (flag)
d164460f 897 mem |= ALT_AD_RG;
78db8547 898 else
d164460f 899 mem &= ~ALT_AD_RG;
78db8547 900
d164460f 901 mem &= ~ALT_CS;
78db8547 902 if (read)
d164460f 903 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 904 else
d164460f
AO		 905 mem = (mem & ~ALT_WR) | ALT_RD;
906
907 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL		 908
909 for (;;) {
910 mem = cx_read(MC417_RWD);
911 if ((mem & ALT_RDY) == 0)
912 break;
913 if (time_after(jiffies, timeout))
914 break;
915 udelay(1);
916 }
917
918 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
919 if (read)
920 return mem & ALT_DATA;
921
922 return 0;
923};
ea5697fe 924
46b21bba
JH		 925static int dib7070_tuner_reset(struct dvb_frontend *fe, int onoff)
926{
927 struct dib7000p_ops *dib7000p_ops = fe->sec_priv;
928
929 return dib7000p_ops->set_gpio(fe, 8, 0, !onoff);
930}
931
932static int dib7070_tuner_sleep(struct dvb_frontend *fe, int onoff)
933{
934 return 0;
935}
936
937static struct dib0070_config dib7070p_dib0070_config = {
938 .i2c_address = DEFAULT_DIB0070_I2C_ADDRESS,
939 .reset = dib7070_tuner_reset,
940 .sleep = dib7070_tuner_sleep,
941 .clock_khz = 12000,
46b21bba
JH		 942 .freq_offset_khz_vhf = 550,
943 /* .flip_chip = 1, */
944};
945
946/* DIB7070 generic */
947static struct dibx000_agc_config dib7070_agc_config = {
948 .band_caps = BAND_UHF | BAND_VHF | BAND_LBAND | BAND_SBAND,
949
950 /*
951 * P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=5,
952 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, P_agc_inh_dc_rv_est=0,
953 * P_agc_time_est=3, P_agc_freeze=0, P_agc_nb_est=5, P_agc_write=0
954 */
955 .setup = (0 << 15) | (0 << 14) | (5 << 11) | (0 << 10) | (0 << 9) |
956 (0 << 8) | (3 << 5) | (0 << 4) | (5 << 1) | (0 << 0),
957 .inv_gain = 600,
958 .time_stabiliz = 10,
959 .alpha_level = 0,
960 .thlock = 118,
961 .wbd_inv = 0,
962 .wbd_ref = 3530,
963 .wbd_sel = 1,
964 .wbd_alpha = 5,
965 .agc1_max = 65535,
966 .agc1_min = 0,
967 .agc2_max = 65535,
968 .agc2_min = 0,
969 .agc1_pt1 = 0,
970 .agc1_pt2 = 40,
971 .agc1_pt3 = 183,
972 .agc1_slope1 = 206,
973 .agc1_slope2 = 255,
974 .agc2_pt1 = 72,
975 .agc2_pt2 = 152,
976 .agc2_slope1 = 88,
977 .agc2_slope2 = 90,
978 .alpha_mant = 17,
979 .alpha_exp = 27,
980 .beta_mant = 23,
981 .beta_exp = 51,
982 .perform_agc_softsplit = 0,
983};
984
985static struct dibx000_bandwidth_config dib7070_bw_config_12_mhz = {
986 .internal = 60000,
987 .sampling = 15000,
988 .pll_prediv = 1,
989 .pll_ratio = 20,
990 .pll_range = 3,
991 .pll_reset = 1,
992 .pll_bypass = 0,
993 .enable_refdiv = 0,
994 .bypclk_div = 0,
995 .IO_CLK_en_core = 1,
996 .ADClkSrc = 1,
997 .modulo = 2,
998 /* refsel, sel, freq_15k */
999 .sad_cfg = (3 << 14) | (1 << 12) | (524 << 0),
1000 .ifreq = (0 << 25) | 0,
1001 .timf = 20452225,
1002 .xtal_hz = 12000000,
1003};
1004
1005static struct dib7000p_config dib7070p_dib7000p_config = {
1006 /* .output_mode = OUTMODE_MPEG2_FIFO, */
1007 .output_mode = OUTMODE_MPEG2_SERIAL,
1008 /* .output_mode = OUTMODE_MPEG2_PAR_GATED_CLK, */
1009 .output_mpeg2_in_188_bytes = 1,
1010
1011 .agc_config_count = 1,
1012 .agc = &dib7070_agc_config,
1013 .bw = &dib7070_bw_config_12_mhz,
1014 .tuner_is_baseband = 1,
1015 .spur_protect = 1,
1016
1017 .gpio_dir = 0xfcef, /* DIB7000P_GPIO_DEFAULT_DIRECTIONS, */
1018 .gpio_val = 0x0110, /* DIB7000P_GPIO_DEFAULT_VALUES, */
1019 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
1020
1021 .hostbus_diversity = 1,
1022};
1023
d19770e5
ST		 1024static int dvb_register(struct cx23885_tsport *port)
1025{
8abe4a0a 1026 struct dib7000p_ops dib7000p_ops;
d19770e5 1027 struct cx23885_dev *dev = port->dev;
493b7127 1028 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
453afdd9 1029 struct vb2_dvb_frontend *fe0, *fe1 = NULL;
29442266
OS		 1030 struct si2168_config si2168_config;
1031 struct si2157_config si2157_config;
24e77409 1032 struct sp2_config sp2_config;
29442266
OS		 1033 struct m88ts2022_config m88ts2022_config;
1034 struct i2c_board_info info;
1035 struct i2c_adapter *adapter;
0e6c7b01 1036 struct i2c_client *client_demod = NULL, *client_tuner = NULL, *client_ci = NULL;
78db8547 1037 int mfe_shared = 0; /* bus not shared by default */
5a23b076 1038 int ret;
363c35fc 1039
f972e0bd 1040 /* Get the first frontend */
453afdd9 1041 fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 1042 if (!fe0)
1043 return -EINVAL;
d19770e5 1044
453afdd9 1045 /* init struct vb2_dvb */
363c35fc 1046 fe0->dvb.name = dev->name;
d19770e5 1047
78db8547
IL		 1048 /* multi-frontend gate control is undefined or defaults to fe0 */
1049 port->frontends.gate = 0;
1050
1051 /* Sets the gate control callback to be used by i2c command calls */
1052 port->gate_ctrl = cx23885_dvb_gate_ctrl;
1053
d19770e5
ST		 1054 /* init frontend */
1055 switch (dev->board) {
a77743bc 1056 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 1057 i2c_bus = &dev->i2c_bus[0];
363c35fc 1058 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 1059 &hauppauge_generic_config,
f139fa71 1060 &i2c_bus->i2c_adap);
363c35fc
ST		 1061 if (fe0->dvb.frontend != NULL) {
1062 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 1063 &i2c_bus->i2c_adap,
86184e06 1064 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 1065 }
1066 break;
a5dbf457 1067 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 1068 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 1069 i2c_bus = &dev->i2c_bus[0];
1070 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 1071 &hauppauge_lgdt3305_config,
a5dbf457
MK		 1072 &i2c_bus->i2c_adap);
1073 if (fe0->dvb.frontend != NULL) {
1074 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1075 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 1076 &hauppauge_hvr127x_config);
a5dbf457 1077 }
15472faf
MCC		 1078 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
1079 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
a5dbf457 1080 break;
19bc5796 1081 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 1082 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK		 1083 i2c_bus = &dev->i2c_bus[0];
1084 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1085 &hcw_s5h1411_config,
1086 &i2c_bus->i2c_adap);
1087 if (fe0->dvb.frontend != NULL) {
1088 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1089 0x60, &dev->i2c_bus[1].i2c_adap,
1090 &hauppauge_tda18271_config);
1091 }
0ac60acb
DH		 1092
1093 tda18271_attach(&dev->ts1.analog_fe,
1094 0x60, &dev->i2c_bus[1].i2c_adap,
1095 &hauppauge_tda18271_config);
1096
19bc5796 1097 break;
3ba71d21
MK		 1098 case CX23885_BOARD_HAUPPAUGE_HVR1800:
1099 i2c_bus = &dev->i2c_bus[0];
92abe9ee 1100 switch (alt_tuner) {
3ba71d21 1101 case 1:
363c35fc 1102 fe0->dvb.frontend =
3ba71d21
MK		 1103 dvb_attach(s5h1409_attach,
1104 &hauppauge_ezqam_config,
1105 &i2c_bus->i2c_adap);
363c35fc
ST		 1106 if (fe0->dvb.frontend != NULL) {
1107 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 1108 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 1109 &tda829x_no_probe);
363c35fc 1110 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 1111 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 1112 &hauppauge_tda18271_config);
3ba71d21
MK		 1113 }
1114 break;
1115 case 0:
1116 default:
363c35fc 1117 fe0->dvb.frontend =
3ba71d21
MK		 1118 dvb_attach(s5h1409_attach,
1119 &hauppauge_generic_config,
1120 &i2c_bus->i2c_adap);
363c35fc
ST		 1121 if (fe0->dvb.frontend != NULL)
1122 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 1123 &i2c_bus->i2c_adap,
1124 &hauppauge_generic_tunerconfig, 0);
1125 break;
1126 }
1127 break;
fc959bef 1128 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 1129 i2c_bus = &dev->i2c_bus[0];
363c35fc 1130 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 1131 &hauppauge_hvr1800lp_config,
f139fa71 1132 &i2c_bus->i2c_adap);
363c35fc
ST		 1133 if (fe0->dvb.frontend != NULL) {
1134 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 1135 &i2c_bus->i2c_adap,
fc959bef
ST		 1136 &hauppauge_generic_tunerconfig, 0);
1137 }
1138 break;
9bc37caa 1139 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 1140 i2c_bus = &dev->i2c_bus[0];
363c35fc 1141 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 1142 &fusionhdtv_5_express,
f139fa71 1143 &i2c_bus->i2c_adap);
363c35fc
ST		 1144 if (fe0->dvb.frontend != NULL) {
1145 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 1146 &i2c_bus->i2c_adap, 0x61,
1147 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 1148 }
1149 break;
d1987d55
ST		 1150 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
1151 i2c_bus = &dev->i2c_bus[1];
363c35fc 1152 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 1153 &hauppauge_hvr1500q_config,
1154 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 1155 if (fe0->dvb.frontend != NULL)
1156 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 1157 &i2c_bus->i2c_adap,
1158 &hauppauge_hvr1500q_tunerconfig);
d1987d55 1159 break;
07b4a835
MK		 1160 case CX23885_BOARD_HAUPPAUGE_HVR1500:
1161 i2c_bus = &dev->i2c_bus[1];
363c35fc 1162 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 1163 &hauppauge_hvr1500_config,
1164 &dev->i2c_bus[0].i2c_adap);
363c35fc 1165 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 1166 struct dvb_frontend *fe;
1167 struct xc2028_config cfg = {
1168 .i2c_adap = &i2c_bus->i2c_adap,
1169 .i2c_addr = 0x61,
07b4a835
MK		 1170 };
1171 static struct xc2028_ctrl ctl = {
ef80bfeb 1172 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 1173 .max_len = 64,
52c3d29c 1174 .demod = XC3028_FE_OREN538,
07b4a835
MK		 1175 };
1176
1177 fe = dvb_attach(xc2028_attach,
363c35fc 1178 fe0->dvb.frontend, &cfg);
07b4a835
MK		 1179 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1180 fe->ops.tuner_ops.set_config(fe, &ctl);
1181 }
1182 break;
b3ea0166 1183 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 1184 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 1185 i2c_bus = &dev->i2c_bus[0];
363c35fc 1186 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 1187 &hauppauge_hvr1200_config,
1188 &i2c_bus->i2c_adap);
363c35fc
ST		 1189 if (fe0->dvb.frontend != NULL) {
1190 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 1191 &dev->i2c_bus[1].i2c_adap, 0x42,
1192 &tda829x_no_probe);
363c35fc 1193 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 1194 0x60, &dev->i2c_bus[1].i2c_adap,
1195 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 1196 }
1197 break;
1198 case CX23885_BOARD_HAUPPAUGE_HVR1210:
1199 i2c_bus = &dev->i2c_bus[0];
1200 fe0->dvb.frontend = dvb_attach(tda10048_attach,
1201 &hauppauge_hvr1210_config,
1202 &i2c_bus->i2c_adap);
1203 if (fe0->dvb.frontend != NULL) {
1204 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1205 0x60, &dev->i2c_bus[1].i2c_adap,
1206 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 1207 }
1208 break;
66762373
ST		 1209 case CX23885_BOARD_HAUPPAUGE_HVR1400:
1210 i2c_bus = &dev->i2c_bus[0];
8abe4a0a
MCC		 1211
1212 if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
1213 return -ENODEV;
1214
1215 fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap,
66762373 1216 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 1217 if (fe0->dvb.frontend != NULL) {
66762373
ST		 1218 struct dvb_frontend *fe;
1219 struct xc2028_config cfg = {
1220 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
1221 .i2c_addr = 0x64,
66762373
ST		 1222 };
1223 static struct xc2028_ctrl ctl = {
ef80bfeb 1224 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 1225 .max_len = 64,
9bed77ee 1226 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST		 1227 /* This is true for all demods with
1228 v36 firmware? */
0975fc68 1229 .type = XC2028_D2633,
66762373
ST		 1230 };
1231
1232 fe = dvb_attach(xc2028_attach,
363c35fc 1233 fe0->dvb.frontend, &cfg);
66762373
ST		 1234 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1235 fe->ops.tuner_ops.set_config(fe, &ctl);
1236 }
1237 break;
335377b7
MK		 1238 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
1239 i2c_bus = &dev->i2c_bus[port->nr - 1];
1240
363c35fc 1241 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 1242 &dvico_s5h1409_config,
1243 &i2c_bus->i2c_adap);
363c35fc
ST		 1244 if (fe0->dvb.frontend == NULL)
1245 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 1246 &dvico_s5h1411_config,
1247 &i2c_bus->i2c_adap);
363c35fc
ST		 1248 if (fe0->dvb.frontend != NULL)
1249 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 1250 &i2c_bus->i2c_adap,
1251 &dvico_xc5000_tunerconfig);
335377b7 1252 break;
aef2d186
ST		 1253 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
1254 i2c_bus = &dev->i2c_bus[port->nr - 1];
1255
363c35fc 1256 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 1257 &dvico_fusionhdtv_xc3028,
1258 &i2c_bus->i2c_adap);
363c35fc 1259 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 1260 struct dvb_frontend *fe;
1261 struct xc2028_config cfg = {
1262 .i2c_adap = &i2c_bus->i2c_adap,
1263 .i2c_addr = 0x61,
aef2d186
ST		 1264 };
1265 static struct xc2028_ctrl ctl = {
ef80bfeb 1266 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 1267 .max_len = 64,
1268 .demod = XC3028_FE_ZARLINK456,
1269 };
1270
363c35fc 1271 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 1272 &cfg);
1273 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1274 fe->ops.tuner_ops.set_config(fe, &ctl);
1275 }
1276 break;
46b21bba
JH		 1277 }
1278 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2: {
1279 i2c_bus = &dev->i2c_bus[port->nr - 1];
1280 /* cxusb_ctrl_msg(adap->dev, CMD_DIGITAL, NULL, 0, NULL, 0); */
1281 /* cxusb_bluebird_gpio_pulse(adap->dev, 0x02, 1); */
1282
1283 if (!dvb_attach(dib7000p_attach, &dib7000p_ops))
1284 return -ENODEV;
1285
1286 if (dib7000p_ops.i2c_enumeration(&i2c_bus->i2c_adap, 1, 0x12, &dib7070p_dib7000p_config) < 0) {
1287 printk(KERN_WARNING "Unable to enumerate dib7000p\n");
1288 return -ENODEV;
1289 }
1290 fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, 0x80, &dib7070p_dib7000p_config);
1291 if (fe0->dvb.frontend != NULL) {
1292 struct i2c_adapter *tun_i2c;
1293
1294 fe0->dvb.frontend->sec_priv = kmalloc(sizeof(dib7000p_ops), GFP_KERNEL);
1295 memcpy(fe0->dvb.frontend->sec_priv, &dib7000p_ops, sizeof(dib7000p_ops));
1296 tun_i2c = dib7000p_ops.get_i2c_master(fe0->dvb.frontend, DIBX000_I2C_INTERFACE_TUNER, 1);
1297 if (!dvb_attach(dib0070_attach, fe0->dvb.frontend, tun_i2c, &dib7070p_dib0070_config))
1298 return -ENODEV;
1299 }
1300 break;
aef2d186 1301 }
4c56b04a 1302 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 1303 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 1304 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 1305 i2c_bus = &dev->i2c_bus[0];
1306
363c35fc 1307 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 1308 &dvico_fusionhdtv_xc3028,
1309 &i2c_bus->i2c_adap);
363c35fc 1310 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 1311 struct dvb_frontend *fe;
1312 struct xc2028_config cfg = {
1313 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
1314 .i2c_addr = 0x61,
4c56b04a
ST		 1315 };
1316 static struct xc2028_ctrl ctl = {
ef80bfeb 1317 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 1318 .max_len = 64,
1319 .demod = XC3028_FE_ZARLINK456,
1320 };
1321
363c35fc 1322 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 1323 &cfg);
1324 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1325 fe->ops.tuner_ops.set_config(fe, &ctl);
1326 }
96318d0c 1327 break;
0cf8af57 1328 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1329 i2c_bus = &dev->i2c_bus[0];
1330
1331 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1332 &dvico_fusionhdtv_xc3028,
1333 &i2c_bus->i2c_adap);
1334 if (fe0->dvb.frontend != NULL) {
1335 struct dvb_frontend *fe;
1336 struct xc4000_config cfg = {
1337 .i2c_address = 0x61,
1338 .default_pm = 0,
1339 .dvb_amplitude = 134,
1340 .set_smoothedcvbs = 1,
1341 .if_khz = 4560
1342 };
1343
1344 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1345 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS		 1346 if (!fe) {
1347 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1348 dev->name);
1349 goto frontend_detach;
1350 }
0cf8af57 1351 }
1352 break;
96318d0c 1353 case CX23885_BOARD_TBS_6920:
09ea33e5 1354 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL		 1355
1356 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL		 1357 &tbs_cx24116_config,
1358 &i2c_bus->i2c_adap);
96318d0c 1359 if (fe0->dvb.frontend != NULL)
09ea33e5 1360 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1361
579943f5 1362 break;
e6001482
LA		 1363 case CX23885_BOARD_TBS_6980:
1364 case CX23885_BOARD_TBS_6981:
1365 i2c_bus = &dev->i2c_bus[1];
1366
1367 switch (port->nr) {
1368 /* PORT B */
1369 case 1:
1370 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1371 &tbs_cx24117_config,
d10e8280 1372 &i2c_bus->i2c_adap);
e6001482
LA		 1373 break;
1374 /* PORT C */
1375 case 2:
e6001482
LA		 1376 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1377 &tbs_cx24117_config,
d10e8280 1378 &i2c_bus->i2c_adap);
e6001482
LA		 1379 break;
1380 }
1381 break;
579943f5
IL		 1382 case CX23885_BOARD_TEVII_S470:
1383 i2c_bus = &dev->i2c_bus[1];
1384
09ea33e5
IL		 1385 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1386 &tevii_ds3000_config,
1387 &i2c_bus->i2c_adap);
73f0af44
KD		 1388 if (fe0->dvb.frontend != NULL) {
1389 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1390 &tevii_ts2020_config, &i2c_bus->i2c_adap);
09ea33e5 1391 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
73f0af44 1392 }
579943f5 1393
4c56b04a 1394 break;
c9b8b04b
IL		 1395 case CX23885_BOARD_DVBWORLD_2005:
1396 i2c_bus = &dev->i2c_bus[1];
1397
1398 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1399 &dvbworld_cx24116_config,
1400 &i2c_bus->i2c_adap);
1401 break;
5a23b076
IL		 1402 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1403 i2c_bus = &dev->i2c_bus[0];
1404 switch (port->nr) {
1405 /* port B */
1406 case 1:
1407 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1408 &netup_stv0900_config,
1409 &i2c_bus->i2c_adap, 0);
1410 if (fe0->dvb.frontend != NULL) {
1411 if (dvb_attach(stv6110_attach,
1412 fe0->dvb.frontend,
1413 &netup_stv6110_tunerconfig_a,
1414 &i2c_bus->i2c_adap)) {
1415 if (!dvb_attach(lnbh24_attach,
1416 fe0->dvb.frontend,
1417 &i2c_bus->i2c_adap,
9329fb5b
AO		 1418 LNBH24_PCL | LNBH24_TTX,
1419 LNBH24_TEN, 0x09))
5a23b076
IL		 1420 printk(KERN_ERR
1421 "No LNBH24 found!\n");
1422
1423 }
1424 }
1425 break;
1426 /* port C */
1427 case 2:
1428 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1429 &netup_stv0900_config,
1430 &i2c_bus->i2c_adap, 1);
1431 if (fe0->dvb.frontend != NULL) {
1432 if (dvb_attach(stv6110_attach,
1433 fe0->dvb.frontend,
1434 &netup_stv6110_tunerconfig_b,
1435 &i2c_bus->i2c_adap)) {
1436 if (!dvb_attach(lnbh24_attach,
1437 fe0->dvb.frontend,
1438 &i2c_bus->i2c_adap,
9329fb5b
AO		 1439 LNBH24_PCL | LNBH24_TTX,
1440 LNBH24_TEN, 0x0a))
5a23b076
IL		 1441 printk(KERN_ERR
1442 "No LNBH24 found!\n");
1443
1444 }
1445 }
1446 break;
1447 }
1448 break;
493b7127
DW		 1449 case CX23885_BOARD_MYGICA_X8506:
1450 i2c_bus = &dev->i2c_bus[0];
1451 i2c_bus2 = &dev->i2c_bus[1];
1452 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1453 &mygica_x8506_lgs8gl5_config,
1454 &i2c_bus->i2c_adap);
1455 if (fe0->dvb.frontend != NULL) {
1456 dvb_attach(xc5000_attach,
1457 fe0->dvb.frontend,
1458 &i2c_bus2->i2c_adap,
1459 &mygica_x8506_xc5000_config);
1460 }
15472faf 1461 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
493b7127 1462 break;
0d1b5265
MCC		 1463 case CX23885_BOARD_MYGICA_X8507:
1464 i2c_bus = &dev->i2c_bus[0];
1465 i2c_bus2 = &dev->i2c_bus[1];
1466 fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
1467 &mygica_x8507_mb86a20s_config,
1468 &i2c_bus->i2c_adap);
1469 if (fe0->dvb.frontend != NULL) {
1470 dvb_attach(xc5000_attach,
1471 fe0->dvb.frontend,
1472 &i2c_bus2->i2c_adap,
1473 &mygica_x8507_xc5000_config);
1474 }
1475 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
1476 break;
2365b2d3
DW		 1477 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1478 i2c_bus = &dev->i2c_bus[0];
1479 i2c_bus2 = &dev->i2c_bus[1];
1480 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1481 &magicpro_prohdtve2_lgs8g75_config,
1482 &i2c_bus->i2c_adap);
1483 if (fe0->dvb.frontend != NULL) {
1484 dvb_attach(xc5000_attach,
1485 fe0->dvb.frontend,
1486 &i2c_bus2->i2c_adap,
1487 &magicpro_prohdtve2_xc5000_config);
1488 }
15472faf 1489 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
2365b2d3 1490 break;
13697380 1491 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST		 1492 i2c_bus = &dev->i2c_bus[0];
1493 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1494 &hcw_s5h1411_config,
1495 &i2c_bus->i2c_adap);
1496 if (fe0->dvb.frontend != NULL)
1497 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1498 0x60, &dev->i2c_bus[0].i2c_adap,
1499 &hauppauge_tda18271_config);
1500
1501 tda18271_attach(&dev->ts1.analog_fe,
1502 0x60, &dev->i2c_bus[1].i2c_adap,
1503 &hauppauge_tda18271_config);
1504
1505 break;
aee0b24c 1506 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1507 i2c_bus = &dev->i2c_bus[0];
1508 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1509 &hcw_s5h1411_config,
1510 &i2c_bus->i2c_adap);
1511 if (fe0->dvb.frontend != NULL)
1512 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1513 0x60, &dev->i2c_bus[0].i2c_adap,
1514 &hauppauge_tda18271_config);
1515 break;
ea5697fe
DW		 1516 case CX23885_BOARD_MYGICA_X8558PRO:
1517 switch (port->nr) {
1518 /* port B */
1519 case 1:
1520 i2c_bus = &dev->i2c_bus[0];
1521 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1522 &mygica_x8558pro_atbm8830_cfg1,
1523 &i2c_bus->i2c_adap);
1524 if (fe0->dvb.frontend != NULL) {
1525 dvb_attach(max2165_attach,
1526 fe0->dvb.frontend,
1527 &i2c_bus->i2c_adap,
1528 &mygic_x8558pro_max2165_cfg1);
1529 }
1530 break;
1531 /* port C */
1532 case 2:
1533 i2c_bus = &dev->i2c_bus[1];
1534 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1535 &mygica_x8558pro_atbm8830_cfg2,
1536 &i2c_bus->i2c_adap);
1537 if (fe0->dvb.frontend != NULL) {
1538 dvb_attach(max2165_attach,
1539 fe0->dvb.frontend,
1540 &i2c_bus->i2c_adap,
1541 &mygic_x8558pro_max2165_cfg2);
1542 }
1543 break;
1544 }
1545 break;
78db8547
IL		 1546 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1547 i2c_bus = &dev->i2c_bus[0];
1548 mfe_shared = 1;/* MFE */
1549 port->frontends.gate = 0;/* not clear for me yet */
1550 /* ports B, C */
1551 /* MFE frontend 1 DVB-T */
1552 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1553 &netup_stv0367_config[port->nr - 1],
1554 &i2c_bus->i2c_adap);
4174ebf5 1555 if (fe0->dvb.frontend != NULL) {
78db8547
IL		 1556 if (NULL == dvb_attach(xc5000_attach,
1557 fe0->dvb.frontend,
1558 &i2c_bus->i2c_adap,
1559 &netup_xc5000_config[port->nr - 1]))
1560 goto frontend_detach;
4174ebf5
AO		 1561 /* load xc5000 firmware */
1562 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1563 }
78db8547 1564 /* MFE frontend 2 */
453afdd9 1565 fe1 = vb2_dvb_get_frontend(&port->frontends, 2);
78db8547
IL		 1566 if (fe1 == NULL)
1567 goto frontend_detach;
1568 /* DVB-C init */
1569 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1570 &netup_stv0367_config[port->nr - 1],
1571 &i2c_bus->i2c_adap);
1572 if (fe1->dvb.frontend != NULL) {
1573 fe1->dvb.frontend->id = 1;
1574 if (NULL == dvb_attach(xc5000_attach,
1575 fe1->dvb.frontend,
1576 &i2c_bus->i2c_adap,
1577 &netup_xc5000_config[port->nr - 1]))
1578 goto frontend_detach;
1579 }
1580 break;
722c90eb
SR		 1581 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1582 i2c_bus = &dev->i2c_bus[0];
1583 i2c_bus2 = &dev->i2c_bus[1];
1584
1585 switch (port->nr) {
1586 /* port b */
1587 case 1:
1588 fe0->dvb.frontend = dvb_attach(drxk_attach,
1589 &terratec_drxk_config[0],
1590 &i2c_bus->i2c_adap);
1591 if (fe0->dvb.frontend != NULL) {
1592 if (!dvb_attach(mt2063_attach,
1593 fe0->dvb.frontend,
1594 &terratec_mt2063_config[0],
1595 &i2c_bus2->i2c_adap))
1596 goto frontend_detach;
1597 }
1598 break;
1599 /* port c */
1600 case 2:
1601 fe0->dvb.frontend = dvb_attach(drxk_attach,
1602 &terratec_drxk_config[1],
1603 &i2c_bus->i2c_adap);
1604 if (fe0->dvb.frontend != NULL) {
1605 if (!dvb_attach(mt2063_attach,
1606 fe0->dvb.frontend,
1607 &terratec_mt2063_config[1],
1608 &i2c_bus2->i2c_adap))
1609 goto frontend_detach;
1610 }
1611 break;
1612 }
1613 break;
7b134e85
IL		 1614 case CX23885_BOARD_TEVII_S471:
1615 i2c_bus = &dev->i2c_bus[1];
1616
1617 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1618 &tevii_ds3000_config,
1619 &i2c_bus->i2c_adap);
b43ea806
JK		 1620 if (fe0->dvb.frontend != NULL) {
1621 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1622 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1623 }
7b134e85 1624 break;
f667190b
MB		 1625 case CX23885_BOARD_PROF_8000:
1626 i2c_bus = &dev->i2c_bus[0];
1627
1628 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1629 &prof_8000_stv090x_config,
1630 &i2c_bus->i2c_adap,
1631 STV090x_DEMODULATOR_0);
1632 if (fe0->dvb.frontend != NULL) {
1633 if (!dvb_attach(stb6100_attach,
1634 fe0->dvb.frontend,
1635 &prof_8000_stb6100_config,
1636 &i2c_bus->i2c_adap))
1637 goto frontend_detach;
1638
1639 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1640 }
1641 break;
7c62f5a1
MK		 1642 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1643 i2c_bus = &dev->i2c_bus[0];
36efec48
MS		 1644 i2c_bus2 = &dev->i2c_bus[1];
1645 switch (port->nr) {
1646 /* port b */
1647 case 1:
1648 fe0->dvb.frontend = dvb_attach(tda10071_attach,
7c62f5a1
MK		 1649 &hauppauge_tda10071_config,
1650 &i2c_bus->i2c_adap);
36efec48
MS		 1651 if (fe0->dvb.frontend != NULL) {
1652 if (!dvb_attach(a8293_attach, fe0->dvb.frontend,
1653 &i2c_bus->i2c_adap,
1654 &hauppauge_a8293_config))
1655 goto frontend_detach;
1656 }
1657 break;
1658 /* port c */
1659 case 2:
1660 fe0->dvb.frontend = dvb_attach(si2165_attach,
1661 &hauppauge_hvr4400_si2165_config,
1662 &i2c_bus->i2c_adap);
1663 if (fe0->dvb.frontend != NULL) {
711c3119 1664 fe0->dvb.frontend->ops.i2c_gate_ctrl = NULL;
36efec48
MS		 1665 if (!dvb_attach(tda18271_attach,
1666 fe0->dvb.frontend,
1667 0x60, &i2c_bus2->i2c_adap,
1668 &hauppauge_hvr4400_tuner_config))
1669 goto frontend_detach;
1670 }
1671 break;
7c62f5a1
MK		 1672 }
1673 break;
29442266
OS		 1674 case CX23885_BOARD_DVBSKY_T9580:
1675 i2c_bus = &dev->i2c_bus[0];
1676 i2c_bus2 = &dev->i2c_bus[1];
1677 switch (port->nr) {
1678 /* port b - satellite */
1679 case 1:
1680 /* attach frontend */
1681 fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
1682 &dvbsky_t9580_m88ds3103_config,
1683 &i2c_bus2->i2c_adap, &adapter);
1684 if (fe0->dvb.frontend == NULL)
1685 break;
1686
1687 /* attach tuner */
143800a5 1688 memset(&m88ts2022_config, 0, sizeof(m88ts2022_config));
29442266
OS		 1689 m88ts2022_config.fe = fe0->dvb.frontend;
1690 m88ts2022_config.clock = 27000000;
1691 memset(&info, 0, sizeof(struct i2c_board_info));
1692 strlcpy(info.type, "m88ts2022", I2C_NAME_SIZE);
1693 info.addr = 0x60;
1694 info.platform_data = &m88ts2022_config;
1695 request_module(info.type);
1696 client_tuner = i2c_new_device(adapter, &info);
1697 if (client_tuner == NULL ||
1698 client_tuner->dev.driver == NULL)
1699 goto frontend_detach;
1700 if (!try_module_get(client_tuner->dev.driver->owner)) {
1701 i2c_unregister_device(client_tuner);
1702 goto frontend_detach;
1703 }
1704
1705 /* delegate signal strength measurement to tuner */
1706 fe0->dvb.frontend->ops.read_signal_strength =
1707 fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
1708
1709 /*
1710 * for setting the voltage we need to set GPIOs on
1711 * the card.
1712 */
1713 port->fe_set_voltage =
1714 fe0->dvb.frontend->ops.set_voltage;
1715 fe0->dvb.frontend->ops.set_voltage =
1716 dvbsky_t9580_set_voltage;
1717
1718 port->i2c_client_tuner = client_tuner;
1719
1720 break;
1721 /* port c - terrestrial/cable */
1722 case 2:
1723 /* attach frontend */
143800a5 1724 memset(&si2168_config, 0, sizeof(si2168_config));
29442266
OS		 1725 si2168_config.i2c_adapter = &adapter;
1726 si2168_config.fe = &fe0->dvb.frontend;
1727 si2168_config.ts_mode = SI2168_TS_SERIAL;
1728 memset(&info, 0, sizeof(struct i2c_board_info));
1729 strlcpy(info.type, "si2168", I2C_NAME_SIZE);
1730 info.addr = 0x64;
1731 info.platform_data = &si2168_config;
1732 request_module(info.type);
1733 client_demod = i2c_new_device(&i2c_bus->i2c_adap, &info);
1734 if (client_demod == NULL ||
1735 client_demod->dev.driver == NULL)
1736 goto frontend_detach;
1737 if (!try_module_get(client_demod->dev.driver->owner)) {
1738 i2c_unregister_device(client_demod);
1739 goto frontend_detach;
1740 }
1741 port->i2c_client_demod = client_demod;
1742
1743 /* attach tuner */
143800a5 1744 memset(&si2157_config, 0, sizeof(si2157_config));
29442266
OS		 1745 si2157_config.fe = fe0->dvb.frontend;
1746 memset(&info, 0, sizeof(struct i2c_board_info));
1747 strlcpy(info.type, "si2157", I2C_NAME_SIZE);
1748 info.addr = 0x60;
1749 info.platform_data = &si2157_config;
1750 request_module(info.type);
1751 client_tuner = i2c_new_device(adapter, &info);
1752 if (client_tuner == NULL ||
1753 client_tuner->dev.driver == NULL) {
1754 module_put(client_demod->dev.driver->owner);
1755 i2c_unregister_device(client_demod);
1756 goto frontend_detach;
1757 }
1758 if (!try_module_get(client_tuner->dev.driver->owner)) {
1759 i2c_unregister_device(client_tuner);
1760 module_put(client_demod->dev.driver->owner);
1761 i2c_unregister_device(client_demod);
1762 goto frontend_detach;
1763 }
1764 port->i2c_client_tuner = client_tuner;
1765 break;
1766 }
1767 break;
82c10276 1768 case CX23885_BOARD_DVBSKY_T980C:
61b103e8 1769 case CX23885_BOARD_TT_CT2_4500_CI:
82c10276 1770 i2c_bus = &dev->i2c_bus[1];
24e77409 1771 i2c_bus2 = &dev->i2c_bus[0];
82c10276
OS		 1772
1773 /* attach frontend */
1774 memset(&si2168_config, 0, sizeof(si2168_config));
1775 si2168_config.i2c_adapter = &adapter;
1776 si2168_config.fe = &fe0->dvb.frontend;
1777 si2168_config.ts_mode = SI2168_TS_PARALLEL;
1778 memset(&info, 0, sizeof(struct i2c_board_info));
1779 strlcpy(info.type, "si2168", I2C_NAME_SIZE);
1780 info.addr = 0x64;
1781 info.platform_data = &si2168_config;
1782 request_module(info.type);
1783 client_demod = i2c_new_device(&i2c_bus->i2c_adap, &info);
1784 if (client_demod == NULL ||
1785 client_demod->dev.driver == NULL)
1786 goto frontend_detach;
1787 if (!try_module_get(client_demod->dev.driver->owner)) {
1788 i2c_unregister_device(client_demod);
1789 goto frontend_detach;
1790 }
1791 port->i2c_client_demod = client_demod;
1792
1793 /* attach tuner */
1794 memset(&si2157_config, 0, sizeof(si2157_config));
1795 si2157_config.fe = fe0->dvb.frontend;
1796 memset(&info, 0, sizeof(struct i2c_board_info));
1797 strlcpy(info.type, "si2157", I2C_NAME_SIZE);
1798 info.addr = 0x60;
1799 info.platform_data = &si2157_config;
1800 request_module(info.type);
1801 client_tuner = i2c_new_device(adapter, &info);
1802 if (client_tuner == NULL ||
1803 client_tuner->dev.driver == NULL) {
1804 module_put(client_demod->dev.driver->owner);
1805 i2c_unregister_device(client_demod);
1806 goto frontend_detach;
1807 }
1808 if (!try_module_get(client_tuner->dev.driver->owner)) {
1809 i2c_unregister_device(client_tuner);
1810 module_put(client_demod->dev.driver->owner);
1811 i2c_unregister_device(client_demod);
1812 goto frontend_detach;
1813 }
0e6c7b01 1814 port->i2c_client_tuner = client_tuner;
1815 break;
1816 case CX23885_BOARD_DVBSKY_S950C:
1817 i2c_bus = &dev->i2c_bus[1];
1818 i2c_bus2 = &dev->i2c_bus[0];
1819
1820 /* attach frontend */
1821 fe0->dvb.frontend = dvb_attach(m88ds3103_attach,
1822 &dvbsky_s950c_m88ds3103_config,
1823 &i2c_bus->i2c_adap, &adapter);
1824 if (fe0->dvb.frontend == NULL)
1825 break;
1826
1827 /* attach tuner */
1828 memset(&m88ts2022_config, 0, sizeof(m88ts2022_config));
1829 m88ts2022_config.fe = fe0->dvb.frontend;
1830 m88ts2022_config.clock = 27000000;
1831 memset(&info, 0, sizeof(struct i2c_board_info));
1832 strlcpy(info.type, "m88ts2022", I2C_NAME_SIZE);
1833 info.addr = 0x60;
1834 info.platform_data = &m88ts2022_config;
1835 request_module(info.type);
1836 client_tuner = i2c_new_device(adapter, &info);
1837 if (client_tuner == NULL ||
1838 client_tuner->dev.driver == NULL)
1839 goto frontend_detach;
1840 if (!try_module_get(client_tuner->dev.driver->owner)) {
1841 i2c_unregister_device(client_tuner);
1842 goto frontend_detach;
1843 }
1844
1845 /* delegate signal strength measurement to tuner */
1846 fe0->dvb.frontend->ops.read_signal_strength =
1847 fe0->dvb.frontend->ops.tuner_ops.get_rf_strength;
1848
82c10276
OS		 1849 port->i2c_client_tuner = client_tuner;
1850 break;
d19770e5 1851 default:
9c8ced51
ST		 1852 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1853 " isn't supported yet\n",
d19770e5
ST		 1854 dev->name);
1855 break;
1856 }
78db8547
IL		 1857
1858 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1859 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL		 1860 dev->name);
1861 goto frontend_detach;
d19770e5 1862 }
78db8547 1863
d7cba043 1864 /* define general-purpose callback pointer */
363c35fc 1865 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL		 1866 if (fe1)
1867 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1868#if 0
1869 /* Ensure all frontends negotiate bus access */
1870 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1871 if (fe1)
1872 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1873#endif
d19770e5
ST		 1874
1875 /* Put the analog decoder in standby to keep it quiet */
622b828a 1876 call_all(dev, core, s_power, 0);
d19770e5 1877
363c35fc
ST		 1878 if (fe0->dvb.frontend->ops.analog_ops.standby)
1879 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1880
d19770e5 1881 /* register everything */
453afdd9 1882 ret = vb2_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1883 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1884 if (ret)
78db8547 1885 goto frontend_detach;
363c35fc 1886
5a23b076
IL		 1887 /* init CI & MAC */
1888 switch (dev->board) {
1889 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1890 static struct netup_card_info cinfo;
1891
1892 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1893 memcpy(port->frontends.adapter.proposed_mac,
1894 cinfo.port[port->nr - 1].mac, 6);
be395157 1895 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1896 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL		 1897
1898 netup_ci_init(port);
1899 break;
1900 }
78db8547
IL		 1901 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1902 struct altera_ci_config netup_ci_cfg = {
1903 .dev = dev,/* magic number to identify*/
1904 .adapter = &port->frontends.adapter,/* for CI */
1905 .demux = &fe0->dvb.demux,/* for hw pid filter */
1906 .fpga_rw = netup_altera_fpga_rw,
1907 };
1908
1909 altera_ci_init(&netup_ci_cfg, port->nr);
1910 break;
1911 }
16bfdaa4
PG		 1912 case CX23885_BOARD_TEVII_S470: {
1913 u8 eeprom[256]; /* 24C02 i2c eeprom */
1914
1915 if (port->nr != 1)
1916 break;
1917
1918 /* Read entire EEPROM */
1919 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1920 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1921 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG		 1922 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1923 break;
1924 }
29442266
OS		 1925 case CX23885_BOARD_DVBSKY_T9580: {
1926 u8 eeprom[256]; /* 24C02 i2c eeprom */
1927
1928 if (port->nr > 2)
1929 break;
1930
1931 /* Read entire EEPROM */
1932 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1933 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
1934 sizeof(eeprom));
1935 printk(KERN_INFO "DVBSky T9580 port %d MAC address: %pM\n",
1936 port->nr, eeprom + 0xc0 + (port->nr-1) * 8);
1937 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0 +
1938 (port->nr-1) * 8, 6);
1939 break;
1940 }
0e6c7b01 1941 case CX23885_BOARD_DVBSKY_S950C:
61b103e8
OS		 1942 case CX23885_BOARD_DVBSKY_T980C:
1943 case CX23885_BOARD_TT_CT2_4500_CI: {
82c10276
OS		 1944 u8 eeprom[256]; /* 24C02 i2c eeprom */
1945
24e77409
OS		 1946 /* attach CI */
1947 memset(&sp2_config, 0, sizeof(sp2_config));
1948 sp2_config.dvb_adap = &port->frontends.adapter;
1949 sp2_config.priv = port;
1950 sp2_config.ci_control = cx23885_sp2_ci_ctrl;
1951 memset(&info, 0, sizeof(struct i2c_board_info));
1952 strlcpy(info.type, "sp2", I2C_NAME_SIZE);
1953 info.addr = 0x40;
1954 info.platform_data = &sp2_config;
1955 request_module(info.type);
1956 client_ci = i2c_new_device(&i2c_bus2->i2c_adap, &info);
1957 if (client_ci == NULL ||
1958 client_ci->dev.driver == NULL) {
0e6c7b01 1959 if (client_tuner) {
1960 module_put(client_tuner->dev.driver->owner);
1961 i2c_unregister_device(client_tuner);
1962 }
1963 if (client_demod) {
1964 module_put(client_demod->dev.driver->owner);
1965 i2c_unregister_device(client_demod);
1966 }
24e77409
OS		 1967 goto frontend_detach;
1968 }
1969 if (!try_module_get(client_ci->dev.driver->owner)) {
1970 i2c_unregister_device(client_ci);
0e6c7b01 1971 if (client_tuner) {
1972 module_put(client_tuner->dev.driver->owner);
1973 i2c_unregister_device(client_tuner);
1974 }
1975 if (client_demod) {
1976 module_put(client_demod->dev.driver->owner);
1977 i2c_unregister_device(client_demod);
1978 }
24e77409
OS		 1979 goto frontend_detach;
1980 }
1981 port->i2c_client_ci = client_ci;
1982
82c10276
OS		 1983 if (port->nr != 1)
1984 break;
1985
1986 /* Read entire EEPROM */
1987 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1988 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom,
1989 sizeof(eeprom));
61b103e8
OS		 1990 printk(KERN_INFO "%s MAC address: %pM\n",
1991 cx23885_boards[dev->board].name, eeprom + 0xc0);
82c10276
OS		 1992 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xc0, 6);
1993 break;
1994 }
5a23b076
IL		 1995 }
1996
1997 return ret;
78db8547
IL		 1998
1999frontend_detach:
2000 port->gate_ctrl = NULL;
453afdd9 2001 vb2_dvb_dealloc_frontends(&port->frontends);
78db8547 2002 return -EINVAL;
d19770e5
ST		 2003}
2004
2005int cx23885_dvb_register(struct cx23885_tsport *port)
2006{
363c35fc 2007
453afdd9 2008 struct vb2_dvb_frontend *fe0;
d19770e5 2009 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 2010 int err, i;
2011
2012 /* Here we need to allocate the correct number of frontends,
af901ca1 2013 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 2014 * no cx23885 boards support this - yet. But, if we don't modify this
2015 * code then the second frontend would never be allocated (later)
2016 * and fail with error before the attach in dvb_register().
2017 * Without these changes we risk an OOPS later. The changes here
2018 * are for safety, and should provide a good foundation for the
2019 * future addition of any multi-frontend cx23885 based boards.
2020 */
2021 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
2022 port->num_frontends);
d19770e5 2023
eb0c58bb 2024 for (i = 1; i <= port->num_frontends; i++) {
453afdd9
HV		 2025 struct vb2_queue *q;
2026
2027 if (vb2_dvb_alloc_frontend(
9c8ced51 2028 &port->frontends, i) == NULL) {
eb0c58bb
ST		 2029 printk(KERN_ERR "%s() failed to alloc\n", __func__);
2030 return -ENOMEM;
2031 }
2032
453afdd9 2033 fe0 = vb2_dvb_get_frontend(&port->frontends, i);
eb0c58bb
ST		 2034 if (!fe0)
2035 err = -EINVAL;
363c35fc 2036
eb0c58bb 2037 dprintk(1, "%s\n", __func__);
9c8ced51 2038 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 2039 dev->board,
2040 dev->name,
2041 dev->pci_bus,
2042 dev->pci_slot);
d19770e5 2043
eb0c58bb 2044 err = -ENODEV;
d19770e5 2045
eb0c58bb
ST		 2046 /* dvb stuff */
2047 /* We have to init the queue for each frontend on a port. */
9c8ced51 2048 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
453afdd9
HV		 2049 q = &fe0->dvb.dvbq;
2050 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
2051 q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
2052 q->gfp_flags = GFP_DMA32;
2053 q->min_buffers_needed = 2;
2054 q->drv_priv = port;
2055 q->buf_struct_size = sizeof(struct cx23885_buffer);
2056 q->ops = &dvb_qops;
2057 q->mem_ops = &vb2_dma_sg_memops;
2058 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
2059 q->lock = &dev->lock;
2060
2061 err = vb2_queue_init(q);
2062 if (err < 0)
2063 return err;
eb0c58bb 2064 }
d19770e5
ST		 2065 err = dvb_register(port);
2066 if (err != 0)
9c8ced51
ST		 2067 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
2068 __func__, err);
d19770e5 2069
d19770e5
ST		 2070 return err;
2071}
2072
2073int cx23885_dvb_unregister(struct cx23885_tsport *port)
2074{
453afdd9 2075 struct vb2_dvb_frontend *fe0;
b0b12e63
OS		 2076 struct i2c_client *client;
2077
e450de45
OS		 2078 /* remove I2C client for CI */
2079 client = port->i2c_client_ci;
2080 if (client) {
2081 module_put(client->dev.driver->owner);
2082 i2c_unregister_device(client);
2083 }
2084
b0b12e63
OS		 2085 /* remove I2C client for tuner */
2086 client = port->i2c_client_tuner;
2087 if (client) {
2088 module_put(client->dev.driver->owner);
2089 i2c_unregister_device(client);
2090 }
2091
2092 /* remove I2C client for demodulator */
2093 client = port->i2c_client_demod;
2094 if (client) {
2095 module_put(client->dev.driver->owner);
2096 i2c_unregister_device(client);
2097 }
363c35fc 2098
453afdd9 2099 fe0 = vb2_dvb_get_frontend(&port->frontends, 1);
b0b12e63 2100
e66131ce 2101 if (fe0 && fe0->dvb.frontend)
453afdd9 2102 vb2_dvb_unregister_bus(&port->frontends);
d19770e5 2103
afd96668
HV		 2104 switch (port->dev->board) {
2105 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
2106 netup_ci_exit(port);
2107 break;
78db8547
IL		 2108 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
2109 altera_ci_release(port->dev, port->nr);
2110 break;
afd96668 2111 }
5a23b076 2112
78db8547
IL		 2113 port->gate_ctrl = NULL;
2114
d19770e5
ST		 2115 return 0;
2116}
Linux kernel - Deliverables
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