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[media] ts2020: add ts2020 tuner driver
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
ST		 46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
5a23b076
IL		 51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
5a23b076 54#include "cimax2.h"
493b7127 55#include "lgs8gxx.h"
5a23b076
IL		 56#include "netup-eeprom.h"
57#include "netup-init.h"
a5dbf457 58#include "lgdt3305.h"
ea5697fe 59#include "atbm8830.h"
09ea33e5
IL		 60#include "ds3000.h"
61#include "cx23885-f300.h"
78db8547
IL		 62#include "altera-ci.h"
63#include "stv0367.h"
722c90eb
SR		 64#include "drxk.h"
65#include "mt2063.h"
f667190b
MB		 66#include "stv090x.h"
67#include "stb6100.h"
68#include "stb6100_cfg.h"
7c62f5a1
MK		 69#include "tda10071.h"
70#include "a8293.h"
d19770e5 71
4513fc69 72static unsigned int debug;
d19770e5 73
4513fc69
ST		 74#define dprintk(level, fmt, arg...)\
75 do { if (debug >= level)\
76 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
77 } while (0)
d19770e5
ST		 78
79/* ------------------------------------------------------------------ */
80
3ba71d21
MK		 81static unsigned int alt_tuner;
82module_param(alt_tuner, int, 0644);
83MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
84
78e92006
JG		 85DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
86
3ba71d21
MK		 87/* ------------------------------------------------------------------ */
88
d19770e5
ST		 89static int dvb_buf_setup(struct videobuf_queue *q,
90 unsigned int *count, unsigned int *size)
91{
92 struct cx23885_tsport *port = q->priv_data;
93
94 port->ts_packet_size = 188 * 4;
95 port->ts_packet_count = 32;
96
97 *size = port->ts_packet_size * port->ts_packet_count;
98 *count = 32;
99 return 0;
100}
101
44a6481d
MK		 102static int dvb_buf_prepare(struct videobuf_queue *q,
103 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 104{
105 struct cx23885_tsport *port = q->priv_data;
9c8ced51 106 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 107}
108
109static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
110{
111 struct cx23885_tsport *port = q->priv_data;
9c8ced51 112 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 113}
114
44a6481d
MK		 115static void dvb_buf_release(struct videobuf_queue *q,
116 struct videobuf_buffer *vb)
d19770e5 117{
9c8ced51 118 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 119}
120
a7d44baa
MCC		 121static int cx23885_dvb_set_frontend(struct dvb_frontend *fe);
122
78db8547
IL		 123static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
124{
125 struct videobuf_dvb_frontends *f;
126 struct videobuf_dvb_frontend *fe;
127
128 f = &port->frontends;
129
130 if (f->gate <= 1) /* undefined or fe0 */
131 fe = videobuf_dvb_get_frontend(f, 1);
132 else
133 fe = videobuf_dvb_get_frontend(f, f->gate);
134
135 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
136 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
a7d44baa
MCC		 137
138 /*
139 * FIXME: Improve this path to avoid calling the
140 * cx23885_dvb_set_frontend() every time it passes here.
141 */
142 cx23885_dvb_set_frontend(fe->dvb.frontend);
78db8547
IL		 143}
144
d19770e5
ST		 145static struct videobuf_queue_ops dvb_qops = {
146 .buf_setup = dvb_buf_setup,
147 .buf_prepare = dvb_buf_prepare,
148 .buf_queue = dvb_buf_queue,
149 .buf_release = dvb_buf_release,
150};
151
86184e06 152static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 153 .demod_address = 0x32 >> 1,
154 .output_mode = S5H1409_SERIAL_OUTPUT,
155 .gpio = S5H1409_GPIO_ON,
2b03238a 156 .qam_if = 44000,
fc959bef 157 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 158 .status_mode = S5H1409_DEMODLOCKING,
159 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 160};
161
b3ea0166
ST		 162static struct tda10048_config hauppauge_hvr1200_config = {
163 .demod_address = 0x10 >> 1,
164 .output_mode = TDA10048_SERIAL_OUTPUT,
165 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 166 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 167 .dtv6_if_freq_khz = TDA10048_IF_3300,
168 .dtv7_if_freq_khz = TDA10048_IF_3800,
169 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 170 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 171};
172
6b926eca
MK		 173static struct tda10048_config hauppauge_hvr1210_config = {
174 .demod_address = 0x10 >> 1,
175 .output_mode = TDA10048_SERIAL_OUTPUT,
176 .fwbulkwritelen = TDA10048_BULKWRITE_200,
177 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 178 .dtv6_if_freq_khz = TDA10048_IF_3300,
179 .dtv7_if_freq_khz = TDA10048_IF_3500,
180 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 181 .clk_freq_khz = TDA10048_CLK_16000,
182};
183
3ba71d21
MK		 184static struct s5h1409_config hauppauge_ezqam_config = {
185 .demod_address = 0x32 >> 1,
186 .output_mode = S5H1409_SERIAL_OUTPUT,
187 .gpio = S5H1409_GPIO_OFF,
188 .qam_if = 4000,
189 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 190 .status_mode = S5H1409_DEMODLOCKING,
191 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 192};
193
fc959bef 194static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 195 .demod_address = 0x32 >> 1,
196 .output_mode = S5H1409_SERIAL_OUTPUT,
197 .gpio = S5H1409_GPIO_OFF,
2b03238a 198 .qam_if = 44000,
fe475163 199 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 200 .status_mode = S5H1409_DEMODLOCKING,
201 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 202};
203
07b4a835
MK		 204static struct s5h1409_config hauppauge_hvr1500_config = {
205 .demod_address = 0x32 >> 1,
206 .output_mode = S5H1409_SERIAL_OUTPUT,
207 .gpio = S5H1409_GPIO_OFF,
208 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 209 .status_mode = S5H1409_DEMODLOCKING,
210 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 211};
212
86184e06 213static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 214 0x61
215};
216
9bc37caa
MK		 217static struct lgdt330x_config fusionhdtv_5_express = {
218 .demod_address = 0x0e,
219 .demod_chip = LGDT3303,
220 .serial_mpeg = 0x40,
221};
222
d1987d55
ST		 223static struct s5h1409_config hauppauge_hvr1500q_config = {
224 .demod_address = 0x32 >> 1,
225 .output_mode = S5H1409_SERIAL_OUTPUT,
226 .gpio = S5H1409_GPIO_ON,
227 .qam_if = 44000,
228 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 229 .status_mode = S5H1409_DEMODLOCKING,
230 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 231};
232
335377b7
MK		 233static struct s5h1409_config dvico_s5h1409_config = {
234 .demod_address = 0x32 >> 1,
235 .output_mode = S5H1409_SERIAL_OUTPUT,
236 .gpio = S5H1409_GPIO_ON,
237 .qam_if = 44000,
238 .inversion = S5H1409_INVERSION_OFF,
239 .status_mode = S5H1409_DEMODLOCKING,
240 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
241};
242
52b50450
MK		 243static struct s5h1411_config dvico_s5h1411_config = {
244 .output_mode = S5H1411_SERIAL_OUTPUT,
245 .gpio = S5H1411_GPIO_ON,
246 .qam_if = S5H1411_IF_44000,
247 .vsb_if = S5H1411_IF_44000,
248 .inversion = S5H1411_INVERSION_OFF,
249 .status_mode = S5H1411_DEMODLOCKING,
250 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
251};
252
19bc5796
MK		 253static struct s5h1411_config hcw_s5h1411_config = {
254 .output_mode = S5H1411_SERIAL_OUTPUT,
255 .gpio = S5H1411_GPIO_OFF,
256 .vsb_if = S5H1411_IF_44000,
257 .qam_if = S5H1411_IF_4000,
258 .inversion = S5H1411_INVERSION_ON,
259 .status_mode = S5H1411_DEMODLOCKING,
260 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
261};
262
d1987d55 263static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 264 .i2c_address = 0x61,
265 .if_khz = 5380,
d1987d55
ST		 266};
267
335377b7
MK		 268static struct xc5000_config dvico_xc5000_tunerconfig = {
269 .i2c_address = 0x64,
270 .if_khz = 5380,
335377b7
MK		 271};
272
4041f1a5
MK		 273static struct tda829x_config tda829x_no_probe = {
274 .probe_tuner = TDA829X_DONT_PROBE,
275};
276
f21e0d7f 277static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 278 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
279 .if_lvl = 6, .rfagc_top = 0x37 },
280 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
281 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 282};
283
b34cdc36
MK		 284static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
285 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
286 .if_lvl = 1, .rfagc_top = 0x37, },
287 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
288 .if_lvl = 1, .rfagc_top = 0x37, },
289 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
290 .if_lvl = 1, .rfagc_top = 0x37, },
291};
292
f21e0d7f
MK		 293static struct tda18271_config hauppauge_tda18271_config = {
294 .std_map = &hauppauge_tda18271_std_map,
295 .gate = TDA18271_GATE_ANALOG,
04a68baa 296 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 297};
298
b3ea0166 299static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 300 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 301 .gate = TDA18271_GATE_ANALOG,
04a68baa 302 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 303};
304
6b926eca
MK		 305static struct tda18271_config hauppauge_hvr1210_tuner_config = {
306 .gate = TDA18271_GATE_DIGITAL,
04a68baa 307 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 308};
309
247bc540 310static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 311 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
312 .if_lvl = 1, .rfagc_top = 0x58 },
313 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
314 .if_lvl = 1, .rfagc_top = 0x58 },
315};
316
247bc540
MK		 317static struct tda18271_config hauppauge_hvr127x_config = {
318 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 319 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 320};
321
247bc540 322static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 323 .i2c_addr = 0x0e,
324 .mpeg_mode = LGDT3305_MPEG_SERIAL,
325 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
326 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
327 .deny_i2c_rptr = 1,
328 .spectral_inversion = 1,
329 .qam_if_khz = 4000,
330 .vsb_if_khz = 3250,
331};
332
b1721d0d 333static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 334 BAND_VHF | BAND_UHF, /* band_caps */
335
336 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
337 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
338 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
339 * P_agc_nb_est=2, P_agc_write=0
340 */
341 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
342 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
343
344 712, /* inv_gain */
345 21, /* time_stabiliz */
346
347 0, /* alpha_level */
348 118, /* thlock */
349
350 0, /* wbd_inv */
351 2867, /* wbd_ref */
352 0, /* wbd_sel */
353 2, /* wbd_alpha */
354
355 0, /* agc1_max */
356 0, /* agc1_min */
357 39718, /* agc2_max */
358 9930, /* agc2_min */
359 0, /* agc1_pt1 */
360 0, /* agc1_pt2 */
361 0, /* agc1_pt3 */
362 0, /* agc1_slope1 */
363 0, /* agc1_slope2 */
364 0, /* agc2_pt1 */
365 128, /* agc2_pt2 */
366 29, /* agc2_slope1 */
367 29, /* agc2_slope2 */
368
369 17, /* alpha_mant */
370 27, /* alpha_exp */
371 23, /* beta_mant */
372 51, /* beta_exp */
373
374 1, /* perform_agc_softsplit */
375};
376
377/* PLL Configuration for COFDM BW_MHz = 8.000000
378 * With external clock = 30.000000 */
b1721d0d 379static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 380 60000, /* internal */
381 30000, /* sampling */
382 1, /* pll_cfg: prediv */
383 8, /* pll_cfg: ratio */
384 3, /* pll_cfg: range */
385 1, /* pll_cfg: reset */
386 0, /* pll_cfg: bypass */
387 0, /* misc: refdiv */
388 0, /* misc: bypclk_div */
389 1, /* misc: IO_CLK_en_core */
390 1, /* misc: ADClkSrc */
391 0, /* misc: modulo */
392 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
393 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
394 20452225, /* timf */
395 30000000 /* xtal_hz */
396};
397
398static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
399 .output_mpeg2_in_188_bytes = 1,
400 .hostbus_diversity = 1,
401 .tuner_is_baseband = 0,
402 .update_lna = NULL,
403
404 .agc_config_count = 1,
405 .agc = &xc3028_agc_config,
406 .bw = &xc3028_bw_config,
407
408 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
409 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
410 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
411
412 .pwm_freq_div = 0,
413 .agc_control = NULL,
414 .spur_protect = 0,
415
416 .output_mode = OUTMODE_MPEG2_SERIAL,
417};
418
aef2d186
ST		 419static struct zl10353_config dvico_fusionhdtv_xc3028 = {
420 .demod_address = 0x0f,
421 .if2 = 45600,
422 .no_tuner = 1,
d4dc673d 423 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 424};
425
f867c3f4
IL		 426static struct stv0900_reg stv0900_ts_regs[] = {
427 { R0900_TSGENERAL, 0x00 },
428 { R0900_P1_TSSPEED, 0x40 },
429 { R0900_P2_TSSPEED, 0x40 },
430 { R0900_P1_TSCFGM, 0xc0 },
431 { R0900_P2_TSCFGM, 0xc0 },
432 { R0900_P1_TSCFGH, 0xe0 },
433 { R0900_P2_TSCFGH, 0xe0 },
434 { R0900_P1_TSCFGL, 0x20 },
435 { R0900_P2_TSCFGL, 0x20 },
436 { 0xffff, 0xff }, /* terminate */
437};
438
5a23b076
IL		 439static struct stv0900_config netup_stv0900_config = {
440 .demod_address = 0x68,
29372a8d 441 .demod_mode = 1, /* dual */
644c7ef0 442 .xtal = 8000000,
5a23b076
IL		 443 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
444 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 445 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 446 .tun1_maddress = 0,/* 0x60 */
447 .tun2_maddress = 3,/* 0x63 */
448 .tun1_adc = 1,/* 1 Vpp */
449 .tun2_adc = 1,/* 1 Vpp */
450};
451
452static struct stv6110_config netup_stv6110_tunerconfig_a = {
453 .i2c_address = 0x60,
644c7ef0
AO		 454 .mclk = 16000000,
455 .clk_div = 1,
873688cd 456 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 457};
458
459static struct stv6110_config netup_stv6110_tunerconfig_b = {
460 .i2c_address = 0x63,
644c7ef0
AO		 461 .mclk = 16000000,
462 .clk_div = 1,
873688cd 463 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 464};
465
96318d0c 466static struct cx24116_config tbs_cx24116_config = {
09ea33e5 467 .demod_address = 0x55,
96318d0c
IL		 468};
469
09ea33e5
IL		 470static struct ds3000_config tevii_ds3000_config = {
471 .demod_address = 0x68,
579943f5
IL		 472};
473
c9b8b04b
IL		 474static struct cx24116_config dvbworld_cx24116_config = {
475 .demod_address = 0x05,
476};
477
493b7127
DW		 478static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
479 .prod = LGS8GXX_PROD_LGS8GL5,
480 .demod_address = 0x19,
481 .serial_ts = 0,
482 .ts_clk_pol = 1,
483 .ts_clk_gated = 1,
484 .if_clk_freq = 30400, /* 30.4 MHz */
485 .if_freq = 5380, /* 5.38 MHz */
486 .if_neg_center = 1,
487 .ext_adc = 0,
488 .adc_signed = 0,
489 .if_neg_edge = 0,
490};
491
492static struct xc5000_config mygica_x8506_xc5000_config = {
493 .i2c_address = 0x61,
494 .if_khz = 5380,
495};
496
f667190b
MB		 497static struct stv090x_config prof_8000_stv090x_config = {
498 .device = STV0903,
499 .demod_mode = STV090x_SINGLE,
500 .clk_mode = STV090x_CLK_EXT,
501 .xtal = 27000000,
502 .address = 0x6A,
503 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
504 .repeater_level = STV090x_RPTLEVEL_64,
505 .adc1_range = STV090x_ADC_2Vpp,
506 .diseqc_envelope_mode = false,
507
508 .tuner_get_frequency = stb6100_get_frequency,
509 .tuner_set_frequency = stb6100_set_frequency,
510 .tuner_set_bandwidth = stb6100_set_bandwidth,
511 .tuner_get_bandwidth = stb6100_get_bandwidth,
512};
513
514static struct stb6100_config prof_8000_stb6100_config = {
515 .tuner_address = 0x60,
516 .refclock = 27000000,
517};
518
519static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
520{
521 struct cx23885_tsport *port = fe->dvb->priv;
522 struct cx23885_dev *dev = port->dev;
523
524 if (voltage == SEC_VOLTAGE_18)
525 cx_write(MC417_RWD, 0x00001e00);
526 else if (voltage == SEC_VOLTAGE_13)
527 cx_write(MC417_RWD, 0x00001a00);
528 else
529 cx_write(MC417_RWD, 0x00001800);
530 return 0;
531}
532
a7d44baa 533static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 534{
a7d44baa 535 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK		 536 struct cx23885_tsport *port = fe->dvb->priv;
537 struct cx23885_dev *dev = port->dev;
538
539 switch (dev->board) {
540 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 541 switch (p->modulation) {
f35b9e80
MK		 542 case VSB_8:
543 cx23885_gpio_clear(dev, GPIO_5);
544 break;
545 case QAM_64:
546 case QAM_256:
547 default:
548 cx23885_gpio_set(dev, GPIO_5);
549 break;
550 }
551 break;
6f0d8c02
DW		 552 case CX23885_BOARD_MYGICA_X8506:
553 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
554 /* Select Digital TV */
555 cx23885_gpio_set(dev, GPIO_0);
556 break;
f35b9e80 557 }
5bdd3962 558 return 0;
f35b9e80
MK		 559}
560
2365b2d3
DW		 561static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
562 .prod = LGS8GXX_PROD_LGS8G75,
563 .demod_address = 0x19,
564 .serial_ts = 0,
565 .ts_clk_pol = 1,
566 .ts_clk_gated = 1,
567 .if_clk_freq = 30400, /* 30.4 MHz */
568 .if_freq = 6500, /* 6.50 MHz */
569 .if_neg_center = 1,
570 .ext_adc = 0,
571 .adc_signed = 1,
572 .adc_vpp = 2, /* 1.6 Vpp */
573 .if_neg_edge = 1,
574};
575
576static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
577 .i2c_address = 0x61,
578 .if_khz = 6500,
579};
580
ea5697fe
DW		 581static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
582 .prod = ATBM8830_PROD_8830,
583 .demod_address = 0x44,
584 .serial_ts = 0,
585 .ts_sampling_edge = 1,
586 .ts_clk_gated = 0,
587 .osc_clk_freq = 30400, /* in kHz */
588 .if_freq = 0, /* zero IF */
589 .zif_swap_iq = 1,
c245c75c
DW		 590 .agc_min = 0x2E,
591 .agc_max = 0xFF,
592 .agc_hold_loop = 0,
ea5697fe
DW		 593};
594
595static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
596 .i2c_address = 0x60,
597 .osc_clk = 20
598};
599
600static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
601 .prod = ATBM8830_PROD_8830,
602 .demod_address = 0x44,
603 .serial_ts = 1,
604 .ts_sampling_edge = 1,
605 .ts_clk_gated = 0,
606 .osc_clk_freq = 30400, /* in kHz */
607 .if_freq = 0, /* zero IF */
608 .zif_swap_iq = 1,
c245c75c
DW		 609 .agc_min = 0x2E,
610 .agc_max = 0xFF,
611 .agc_hold_loop = 0,
ea5697fe
DW		 612};
613
614static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
615 .i2c_address = 0x60,
616 .osc_clk = 20
617};
78db8547
IL		 618static struct stv0367_config netup_stv0367_config[] = {
619 {
620 .demod_address = 0x1c,
621 .xtal = 27000000,
622 .if_khz = 4500,
623 .if_iq_mode = 0,
624 .ts_mode = 1,
625 .clk_pol = 0,
626 }, {
627 .demod_address = 0x1d,
628 .xtal = 27000000,
629 .if_khz = 4500,
630 .if_iq_mode = 0,
631 .ts_mode = 1,
632 .clk_pol = 0,
633 },
634};
635
636static struct xc5000_config netup_xc5000_config[] = {
637 {
638 .i2c_address = 0x61,
639 .if_khz = 4500,
640 }, {
641 .i2c_address = 0x64,
642 .if_khz = 4500,
643 },
644};
645
722c90eb
SR		 646static struct drxk_config terratec_drxk_config[] = {
647 {
648 .adr = 0x29,
649 .no_i2c_bridge = 1,
650 }, {
651 .adr = 0x2a,
652 .no_i2c_bridge = 1,
653 },
654};
655
656static struct mt2063_config terratec_mt2063_config[] = {
657 {
658 .tuner_address = 0x60,
659 }, {
660 .tuner_address = 0x67,
661 },
662};
663
7c62f5a1 664static const struct tda10071_config hauppauge_tda10071_config = {
41f55d57 665 .demod_i2c_addr = 0x05,
7c62f5a1
MK		 666 .tuner_i2c_addr = 0x54,
667 .i2c_wr_max = 64,
668 .ts_mode = TDA10071_TS_SERIAL,
669 .spec_inv = 0,
670 .xtal = 40444000, /* 40.444 MHz */
671 .pll_multiplier = 20,
672};
673
674static const struct a8293_config hauppauge_a8293_config = {
675 .i2c_addr = 0x0b,
676};
677
ada73eee 678static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
78db8547
IL		 679{
680 struct cx23885_dev *dev = (struct cx23885_dev *)device;
681 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 682 uint32_t mem = 0;
78db8547 683
d164460f 684 mem = cx_read(MC417_RWD);
78db8547
IL		 685 if (read)
686 cx_set(MC417_OEN, ALT_DATA);
687 else {
688 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL		 689 mem &= ~ALT_DATA;
690 mem |= (data & ALT_DATA);
78db8547
IL		 691 }
692
693 if (flag)
d164460f 694 mem |= ALT_AD_RG;
78db8547 695 else
d164460f 696 mem &= ~ALT_AD_RG;
78db8547 697
d164460f 698 mem &= ~ALT_CS;
78db8547 699 if (read)
d164460f 700 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 701 else
d164460f
AO		 702 mem = (mem & ~ALT_WR) | ALT_RD;
703
704 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL		 705
706 for (;;) {
707 mem = cx_read(MC417_RWD);
708 if ((mem & ALT_RDY) == 0)
709 break;
710 if (time_after(jiffies, timeout))
711 break;
712 udelay(1);
713 }
714
715 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
716 if (read)
717 return mem & ALT_DATA;
718
719 return 0;
720};
ea5697fe 721
d19770e5
ST		 722static int dvb_register(struct cx23885_tsport *port)
723{
724 struct cx23885_dev *dev = port->dev;
493b7127 725 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL		 726 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
727 int mfe_shared = 0; /* bus not shared by default */
5a23b076 728 int ret;
363c35fc 729
f972e0bd 730 /* Get the first frontend */
92abe9ee 731 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 732 if (!fe0)
733 return -EINVAL;
d19770e5
ST		 734
735 /* init struct videobuf_dvb */
363c35fc 736 fe0->dvb.name = dev->name;
d19770e5 737
78db8547
IL		 738 /* multi-frontend gate control is undefined or defaults to fe0 */
739 port->frontends.gate = 0;
740
741 /* Sets the gate control callback to be used by i2c command calls */
742 port->gate_ctrl = cx23885_dvb_gate_ctrl;
743
d19770e5
ST		 744 /* init frontend */
745 switch (dev->board) {
a77743bc 746 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 747 i2c_bus = &dev->i2c_bus[0];
363c35fc 748 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 749 &hauppauge_generic_config,
f139fa71 750 &i2c_bus->i2c_adap);
363c35fc
ST		 751 if (fe0->dvb.frontend != NULL) {
752 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 753 &i2c_bus->i2c_adap,
86184e06 754 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 755 }
756 break;
a5dbf457 757 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 758 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 759 i2c_bus = &dev->i2c_bus[0];
760 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 761 &hauppauge_lgdt3305_config,
a5dbf457
MK		 762 &i2c_bus->i2c_adap);
763 if (fe0->dvb.frontend != NULL) {
764 dvb_attach(tda18271_attach, fe0->dvb.frontend,
765 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 766 &hauppauge_hvr127x_config);
a5dbf457
MK		 767 }
768 break;
19bc5796 769 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 770 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK		 771 i2c_bus = &dev->i2c_bus[0];
772 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
773 &hcw_s5h1411_config,
774 &i2c_bus->i2c_adap);
775 if (fe0->dvb.frontend != NULL) {
776 dvb_attach(tda18271_attach, fe0->dvb.frontend,
777 0x60, &dev->i2c_bus[1].i2c_adap,
778 &hauppauge_tda18271_config);
779 }
0ac60acb
DH		 780
781 tda18271_attach(&dev->ts1.analog_fe,
782 0x60, &dev->i2c_bus[1].i2c_adap,
783 &hauppauge_tda18271_config);
784
19bc5796 785 break;
3ba71d21
MK		 786 case CX23885_BOARD_HAUPPAUGE_HVR1800:
787 i2c_bus = &dev->i2c_bus[0];
92abe9ee 788 switch (alt_tuner) {
3ba71d21 789 case 1:
363c35fc 790 fe0->dvb.frontend =
3ba71d21
MK		 791 dvb_attach(s5h1409_attach,
792 &hauppauge_ezqam_config,
793 &i2c_bus->i2c_adap);
363c35fc
ST		 794 if (fe0->dvb.frontend != NULL) {
795 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 796 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 797 &tda829x_no_probe);
363c35fc 798 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 799 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 800 &hauppauge_tda18271_config);
3ba71d21
MK		 801 }
802 break;
803 case 0:
804 default:
363c35fc 805 fe0->dvb.frontend =
3ba71d21
MK		 806 dvb_attach(s5h1409_attach,
807 &hauppauge_generic_config,
808 &i2c_bus->i2c_adap);
363c35fc
ST		 809 if (fe0->dvb.frontend != NULL)
810 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 811 &i2c_bus->i2c_adap,
812 &hauppauge_generic_tunerconfig, 0);
813 break;
814 }
815 break;
fc959bef 816 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 817 i2c_bus = &dev->i2c_bus[0];
363c35fc 818 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 819 &hauppauge_hvr1800lp_config,
f139fa71 820 &i2c_bus->i2c_adap);
363c35fc
ST		 821 if (fe0->dvb.frontend != NULL) {
822 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 823 &i2c_bus->i2c_adap,
fc959bef
ST		 824 &hauppauge_generic_tunerconfig, 0);
825 }
826 break;
9bc37caa 827 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 828 i2c_bus = &dev->i2c_bus[0];
363c35fc 829 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 830 &fusionhdtv_5_express,
f139fa71 831 &i2c_bus->i2c_adap);
363c35fc
ST		 832 if (fe0->dvb.frontend != NULL) {
833 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 834 &i2c_bus->i2c_adap, 0x61,
835 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 836 }
837 break;
d1987d55
ST		 838 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
839 i2c_bus = &dev->i2c_bus[1];
363c35fc 840 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 841 &hauppauge_hvr1500q_config,
842 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 843 if (fe0->dvb.frontend != NULL)
844 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 845 &i2c_bus->i2c_adap,
846 &hauppauge_hvr1500q_tunerconfig);
d1987d55 847 break;
07b4a835
MK		 848 case CX23885_BOARD_HAUPPAUGE_HVR1500:
849 i2c_bus = &dev->i2c_bus[1];
363c35fc 850 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 851 &hauppauge_hvr1500_config,
852 &dev->i2c_bus[0].i2c_adap);
363c35fc 853 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 854 struct dvb_frontend *fe;
855 struct xc2028_config cfg = {
856 .i2c_adap = &i2c_bus->i2c_adap,
857 .i2c_addr = 0x61,
07b4a835
MK		 858 };
859 static struct xc2028_ctrl ctl = {
ef80bfeb 860 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 861 .max_len = 64,
52c3d29c 862 .demod = XC3028_FE_OREN538,
07b4a835
MK		 863 };
864
865 fe = dvb_attach(xc2028_attach,
363c35fc 866 fe0->dvb.frontend, &cfg);
07b4a835
MK		 867 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
868 fe->ops.tuner_ops.set_config(fe, &ctl);
869 }
870 break;
b3ea0166 871 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 872 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 873 i2c_bus = &dev->i2c_bus[0];
363c35fc 874 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 875 &hauppauge_hvr1200_config,
876 &i2c_bus->i2c_adap);
363c35fc
ST		 877 if (fe0->dvb.frontend != NULL) {
878 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 879 &dev->i2c_bus[1].i2c_adap, 0x42,
880 &tda829x_no_probe);
363c35fc 881 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 882 0x60, &dev->i2c_bus[1].i2c_adap,
883 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 884 }
885 break;
886 case CX23885_BOARD_HAUPPAUGE_HVR1210:
887 i2c_bus = &dev->i2c_bus[0];
888 fe0->dvb.frontend = dvb_attach(tda10048_attach,
889 &hauppauge_hvr1210_config,
890 &i2c_bus->i2c_adap);
891 if (fe0->dvb.frontend != NULL) {
892 dvb_attach(tda18271_attach, fe0->dvb.frontend,
893 0x60, &dev->i2c_bus[1].i2c_adap,
894 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 895 }
896 break;
66762373
ST		 897 case CX23885_BOARD_HAUPPAUGE_HVR1400:
898 i2c_bus = &dev->i2c_bus[0];
363c35fc 899 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 900 &i2c_bus->i2c_adap,
901 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 902 if (fe0->dvb.frontend != NULL) {
66762373
ST		 903 struct dvb_frontend *fe;
904 struct xc2028_config cfg = {
905 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
906 .i2c_addr = 0x64,
66762373
ST		 907 };
908 static struct xc2028_ctrl ctl = {
ef80bfeb 909 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 910 .max_len = 64,
9bed77ee 911 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST		 912 /* This is true for all demods with
913 v36 firmware? */
0975fc68 914 .type = XC2028_D2633,
66762373
ST		 915 };
916
917 fe = dvb_attach(xc2028_attach,
363c35fc 918 fe0->dvb.frontend, &cfg);
66762373
ST		 919 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
920 fe->ops.tuner_ops.set_config(fe, &ctl);
921 }
922 break;
335377b7
MK		 923 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
924 i2c_bus = &dev->i2c_bus[port->nr - 1];
925
363c35fc 926 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 927 &dvico_s5h1409_config,
928 &i2c_bus->i2c_adap);
363c35fc
ST		 929 if (fe0->dvb.frontend == NULL)
930 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 931 &dvico_s5h1411_config,
932 &i2c_bus->i2c_adap);
363c35fc
ST		 933 if (fe0->dvb.frontend != NULL)
934 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 935 &i2c_bus->i2c_adap,
936 &dvico_xc5000_tunerconfig);
335377b7 937 break;
aef2d186
ST		 938 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
939 i2c_bus = &dev->i2c_bus[port->nr - 1];
940
363c35fc 941 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 942 &dvico_fusionhdtv_xc3028,
943 &i2c_bus->i2c_adap);
363c35fc 944 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 945 struct dvb_frontend *fe;
946 struct xc2028_config cfg = {
947 .i2c_adap = &i2c_bus->i2c_adap,
948 .i2c_addr = 0x61,
aef2d186
ST		 949 };
950 static struct xc2028_ctrl ctl = {
ef80bfeb 951 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 952 .max_len = 64,
953 .demod = XC3028_FE_ZARLINK456,
954 };
955
363c35fc 956 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 957 &cfg);
958 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
959 fe->ops.tuner_ops.set_config(fe, &ctl);
960 }
961 break;
962 }
4c56b04a 963 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 964 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 965 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 966 i2c_bus = &dev->i2c_bus[0];
967
363c35fc 968 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 969 &dvico_fusionhdtv_xc3028,
970 &i2c_bus->i2c_adap);
363c35fc 971 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 972 struct dvb_frontend *fe;
973 struct xc2028_config cfg = {
974 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
975 .i2c_addr = 0x61,
4c56b04a
ST		 976 };
977 static struct xc2028_ctrl ctl = {
ef80bfeb 978 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 979 .max_len = 64,
980 .demod = XC3028_FE_ZARLINK456,
981 };
982
363c35fc 983 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 984 &cfg);
985 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
986 fe->ops.tuner_ops.set_config(fe, &ctl);
987 }
96318d0c 988 break;
0cf8af57 989 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
990 i2c_bus = &dev->i2c_bus[0];
991
992 fe0->dvb.frontend = dvb_attach(zl10353_attach,
993 &dvico_fusionhdtv_xc3028,
994 &i2c_bus->i2c_adap);
995 if (fe0->dvb.frontend != NULL) {
996 struct dvb_frontend *fe;
997 struct xc4000_config cfg = {
998 .i2c_address = 0x61,
999 .default_pm = 0,
1000 .dvb_amplitude = 134,
1001 .set_smoothedcvbs = 1,
1002 .if_khz = 4560
1003 };
1004
1005 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1006 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS		 1007 if (!fe) {
1008 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1009 dev->name);
1010 goto frontend_detach;
1011 }
0cf8af57 1012 }
1013 break;
96318d0c 1014 case CX23885_BOARD_TBS_6920:
09ea33e5 1015 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL		 1016
1017 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL		 1018 &tbs_cx24116_config,
1019 &i2c_bus->i2c_adap);
96318d0c 1020 if (fe0->dvb.frontend != NULL)
09ea33e5 1021 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1022
579943f5
IL		 1023 break;
1024 case CX23885_BOARD_TEVII_S470:
1025 i2c_bus = &dev->i2c_bus[1];
1026
09ea33e5
IL		 1027 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1028 &tevii_ds3000_config,
1029 &i2c_bus->i2c_adap);
579943f5 1030 if (fe0->dvb.frontend != NULL)
09ea33e5 1031 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
579943f5 1032
4c56b04a 1033 break;
c9b8b04b
IL		 1034 case CX23885_BOARD_DVBWORLD_2005:
1035 i2c_bus = &dev->i2c_bus[1];
1036
1037 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1038 &dvbworld_cx24116_config,
1039 &i2c_bus->i2c_adap);
1040 break;
5a23b076
IL		 1041 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1042 i2c_bus = &dev->i2c_bus[0];
1043 switch (port->nr) {
1044 /* port B */
1045 case 1:
1046 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1047 &netup_stv0900_config,
1048 &i2c_bus->i2c_adap, 0);
1049 if (fe0->dvb.frontend != NULL) {
1050 if (dvb_attach(stv6110_attach,
1051 fe0->dvb.frontend,
1052 &netup_stv6110_tunerconfig_a,
1053 &i2c_bus->i2c_adap)) {
1054 if (!dvb_attach(lnbh24_attach,
1055 fe0->dvb.frontend,
1056 &i2c_bus->i2c_adap,
9329fb5b
AO		 1057 LNBH24_PCL | LNBH24_TTX,
1058 LNBH24_TEN, 0x09))
5a23b076
IL		 1059 printk(KERN_ERR
1060 "No LNBH24 found!\n");
1061
1062 }
1063 }
1064 break;
1065 /* port C */
1066 case 2:
1067 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1068 &netup_stv0900_config,
1069 &i2c_bus->i2c_adap, 1);
1070 if (fe0->dvb.frontend != NULL) {
1071 if (dvb_attach(stv6110_attach,
1072 fe0->dvb.frontend,
1073 &netup_stv6110_tunerconfig_b,
1074 &i2c_bus->i2c_adap)) {
1075 if (!dvb_attach(lnbh24_attach,
1076 fe0->dvb.frontend,
1077 &i2c_bus->i2c_adap,
9329fb5b
AO		 1078 LNBH24_PCL | LNBH24_TTX,
1079 LNBH24_TEN, 0x0a))
5a23b076
IL		 1080 printk(KERN_ERR
1081 "No LNBH24 found!\n");
1082
1083 }
1084 }
1085 break;
1086 }
1087 break;
493b7127
DW		 1088 case CX23885_BOARD_MYGICA_X8506:
1089 i2c_bus = &dev->i2c_bus[0];
1090 i2c_bus2 = &dev->i2c_bus[1];
1091 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1092 &mygica_x8506_lgs8gl5_config,
1093 &i2c_bus->i2c_adap);
1094 if (fe0->dvb.frontend != NULL) {
1095 dvb_attach(xc5000_attach,
1096 fe0->dvb.frontend,
1097 &i2c_bus2->i2c_adap,
1098 &mygica_x8506_xc5000_config);
1099 }
1100 break;
2365b2d3
DW		 1101 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1102 i2c_bus = &dev->i2c_bus[0];
1103 i2c_bus2 = &dev->i2c_bus[1];
1104 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1105 &magicpro_prohdtve2_lgs8g75_config,
1106 &i2c_bus->i2c_adap);
1107 if (fe0->dvb.frontend != NULL) {
1108 dvb_attach(xc5000_attach,
1109 fe0->dvb.frontend,
1110 &i2c_bus2->i2c_adap,
1111 &magicpro_prohdtve2_xc5000_config);
1112 }
1113 break;
13697380 1114 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST		 1115 i2c_bus = &dev->i2c_bus[0];
1116 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1117 &hcw_s5h1411_config,
1118 &i2c_bus->i2c_adap);
1119 if (fe0->dvb.frontend != NULL)
1120 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1121 0x60, &dev->i2c_bus[0].i2c_adap,
1122 &hauppauge_tda18271_config);
1123
1124 tda18271_attach(&dev->ts1.analog_fe,
1125 0x60, &dev->i2c_bus[1].i2c_adap,
1126 &hauppauge_tda18271_config);
1127
1128 break;
aee0b24c 1129 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1130 i2c_bus = &dev->i2c_bus[0];
1131 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1132 &hcw_s5h1411_config,
1133 &i2c_bus->i2c_adap);
1134 if (fe0->dvb.frontend != NULL)
1135 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1136 0x60, &dev->i2c_bus[0].i2c_adap,
1137 &hauppauge_tda18271_config);
1138 break;
ea5697fe
DW		 1139 case CX23885_BOARD_MYGICA_X8558PRO:
1140 switch (port->nr) {
1141 /* port B */
1142 case 1:
1143 i2c_bus = &dev->i2c_bus[0];
1144 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1145 &mygica_x8558pro_atbm8830_cfg1,
1146 &i2c_bus->i2c_adap);
1147 if (fe0->dvb.frontend != NULL) {
1148 dvb_attach(max2165_attach,
1149 fe0->dvb.frontend,
1150 &i2c_bus->i2c_adap,
1151 &mygic_x8558pro_max2165_cfg1);
1152 }
1153 break;
1154 /* port C */
1155 case 2:
1156 i2c_bus = &dev->i2c_bus[1];
1157 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1158 &mygica_x8558pro_atbm8830_cfg2,
1159 &i2c_bus->i2c_adap);
1160 if (fe0->dvb.frontend != NULL) {
1161 dvb_attach(max2165_attach,
1162 fe0->dvb.frontend,
1163 &i2c_bus->i2c_adap,
1164 &mygic_x8558pro_max2165_cfg2);
1165 }
1166 break;
1167 }
1168 break;
78db8547
IL		 1169 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1170 i2c_bus = &dev->i2c_bus[0];
1171 mfe_shared = 1;/* MFE */
1172 port->frontends.gate = 0;/* not clear for me yet */
1173 /* ports B, C */
1174 /* MFE frontend 1 DVB-T */
1175 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1176 &netup_stv0367_config[port->nr - 1],
1177 &i2c_bus->i2c_adap);
4174ebf5 1178 if (fe0->dvb.frontend != NULL) {
78db8547
IL		 1179 if (NULL == dvb_attach(xc5000_attach,
1180 fe0->dvb.frontend,
1181 &i2c_bus->i2c_adap,
1182 &netup_xc5000_config[port->nr - 1]))
1183 goto frontend_detach;
4174ebf5
AO		 1184 /* load xc5000 firmware */
1185 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1186 }
78db8547
IL		 1187 /* MFE frontend 2 */
1188 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1189 if (fe1 == NULL)
1190 goto frontend_detach;
1191 /* DVB-C init */
1192 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1193 &netup_stv0367_config[port->nr - 1],
1194 &i2c_bus->i2c_adap);
1195 if (fe1->dvb.frontend != NULL) {
1196 fe1->dvb.frontend->id = 1;
1197 if (NULL == dvb_attach(xc5000_attach,
1198 fe1->dvb.frontend,
1199 &i2c_bus->i2c_adap,
1200 &netup_xc5000_config[port->nr - 1]))
1201 goto frontend_detach;
1202 }
1203 break;
722c90eb
SR		 1204 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1205 i2c_bus = &dev->i2c_bus[0];
1206 i2c_bus2 = &dev->i2c_bus[1];
1207
1208 switch (port->nr) {
1209 /* port b */
1210 case 1:
1211 fe0->dvb.frontend = dvb_attach(drxk_attach,
1212 &terratec_drxk_config[0],
1213 &i2c_bus->i2c_adap);
1214 if (fe0->dvb.frontend != NULL) {
1215 if (!dvb_attach(mt2063_attach,
1216 fe0->dvb.frontend,
1217 &terratec_mt2063_config[0],
1218 &i2c_bus2->i2c_adap))
1219 goto frontend_detach;
1220 }
1221 break;
1222 /* port c */
1223 case 2:
1224 fe0->dvb.frontend = dvb_attach(drxk_attach,
1225 &terratec_drxk_config[1],
1226 &i2c_bus->i2c_adap);
1227 if (fe0->dvb.frontend != NULL) {
1228 if (!dvb_attach(mt2063_attach,
1229 fe0->dvb.frontend,
1230 &terratec_mt2063_config[1],
1231 &i2c_bus2->i2c_adap))
1232 goto frontend_detach;
1233 }
1234 break;
1235 }
1236 break;
7b134e85
IL		 1237 case CX23885_BOARD_TEVII_S471:
1238 i2c_bus = &dev->i2c_bus[1];
1239
1240 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1241 &tevii_ds3000_config,
1242 &i2c_bus->i2c_adap);
1243 break;
f667190b
MB		 1244 case CX23885_BOARD_PROF_8000:
1245 i2c_bus = &dev->i2c_bus[0];
1246
1247 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1248 &prof_8000_stv090x_config,
1249 &i2c_bus->i2c_adap,
1250 STV090x_DEMODULATOR_0);
1251 if (fe0->dvb.frontend != NULL) {
1252 if (!dvb_attach(stb6100_attach,
1253 fe0->dvb.frontend,
1254 &prof_8000_stb6100_config,
1255 &i2c_bus->i2c_adap))
1256 goto frontend_detach;
1257
1258 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1259 }
1260 break;
7c62f5a1
MK		 1261 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1262 i2c_bus = &dev->i2c_bus[0];
1263 fe0->dvb.frontend = dvb_attach(tda10071_attach,
1264 &hauppauge_tda10071_config,
1265 &i2c_bus->i2c_adap);
1266 if (fe0->dvb.frontend != NULL) {
1267 dvb_attach(a8293_attach, fe0->dvb.frontend,
1268 &i2c_bus->i2c_adap,
1269 &hauppauge_a8293_config);
1270 }
1271 break;
d19770e5 1272 default:
9c8ced51
ST		 1273 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1274 " isn't supported yet\n",
d19770e5
ST		 1275 dev->name);
1276 break;
1277 }
78db8547
IL		 1278
1279 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1280 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL		 1281 dev->name);
1282 goto frontend_detach;
d19770e5 1283 }
78db8547 1284
d7cba043 1285 /* define general-purpose callback pointer */
363c35fc 1286 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL		 1287 if (fe1)
1288 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1289#if 0
1290 /* Ensure all frontends negotiate bus access */
1291 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1292 if (fe1)
1293 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1294#endif
d19770e5
ST		 1295
1296 /* Put the analog decoder in standby to keep it quiet */
622b828a 1297 call_all(dev, core, s_power, 0);
d19770e5 1298
363c35fc
ST		 1299 if (fe0->dvb.frontend->ops.analog_ops.standby)
1300 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1301
d19770e5 1302 /* register everything */
5a23b076 1303 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1304 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1305 if (ret)
78db8547 1306 goto frontend_detach;
363c35fc 1307
5a23b076
IL		 1308 /* init CI & MAC */
1309 switch (dev->board) {
1310 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1311 static struct netup_card_info cinfo;
1312
1313 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1314 memcpy(port->frontends.adapter.proposed_mac,
1315 cinfo.port[port->nr - 1].mac, 6);
be395157 1316 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1317 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL		 1318
1319 netup_ci_init(port);
1320 break;
1321 }
78db8547
IL		 1322 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1323 struct altera_ci_config netup_ci_cfg = {
1324 .dev = dev,/* magic number to identify*/
1325 .adapter = &port->frontends.adapter,/* for CI */
1326 .demux = &fe0->dvb.demux,/* for hw pid filter */
1327 .fpga_rw = netup_altera_fpga_rw,
1328 };
1329
1330 altera_ci_init(&netup_ci_cfg, port->nr);
1331 break;
1332 }
16bfdaa4
PG		 1333 case CX23885_BOARD_TEVII_S470: {
1334 u8 eeprom[256]; /* 24C02 i2c eeprom */
1335
1336 if (port->nr != 1)
1337 break;
1338
1339 /* Read entire EEPROM */
1340 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1341 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1342 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG		 1343 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1344 break;
1345 }
5a23b076
IL		 1346 }
1347
1348 return ret;
78db8547
IL		 1349
1350frontend_detach:
1351 port->gate_ctrl = NULL;
1352 videobuf_dvb_dealloc_frontends(&port->frontends);
1353 return -EINVAL;
d19770e5
ST		 1354}
1355
1356int cx23885_dvb_register(struct cx23885_tsport *port)
1357{
363c35fc
ST		 1358
1359 struct videobuf_dvb_frontend *fe0;
d19770e5 1360 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 1361 int err, i;
1362
1363 /* Here we need to allocate the correct number of frontends,
af901ca1 1364 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 1365 * no cx23885 boards support this - yet. But, if we don't modify this
1366 * code then the second frontend would never be allocated (later)
1367 * and fail with error before the attach in dvb_register().
1368 * Without these changes we risk an OOPS later. The changes here
1369 * are for safety, and should provide a good foundation for the
1370 * future addition of any multi-frontend cx23885 based boards.
1371 */
1372 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1373 port->num_frontends);
d19770e5 1374
eb0c58bb 1375 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1376 if (videobuf_dvb_alloc_frontend(
9c8ced51 1377 &port->frontends, i) == NULL) {
eb0c58bb
ST		 1378 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1379 return -ENOMEM;
1380 }
1381
1382 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1383 if (!fe0)
1384 err = -EINVAL;
363c35fc 1385
eb0c58bb 1386 dprintk(1, "%s\n", __func__);
9c8ced51 1387 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 1388 dev->board,
1389 dev->name,
1390 dev->pci_bus,
1391 dev->pci_slot);
d19770e5 1392
eb0c58bb 1393 err = -ENODEV;
d19770e5 1394
eb0c58bb
ST		 1395 /* dvb stuff */
1396 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 1397 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1398 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1399 &dev->pci->dev, &port->slock,
44a6481d 1400 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1401 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1402 }
d19770e5
ST		 1403 err = dvb_register(port);
1404 if (err != 0)
9c8ced51
ST		 1405 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1406 __func__, err);
d19770e5 1407
d19770e5
ST		 1408 return err;
1409}
1410
1411int cx23885_dvb_unregister(struct cx23885_tsport *port)
1412{
363c35fc
ST		 1413 struct videobuf_dvb_frontend *fe0;
1414
eb0c58bb
ST		 1415 /* FIXME: in an error condition where the we have
1416 * an expected number of frontends (attach problem)
1417 * then this might not clean up correctly, if 1
1418 * is invalid.
1419 * This comment only applies to future boards IF they
1420 * implement MFE support.
1421 */
92abe9ee 1422 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1423 if (fe0 && fe0->dvb.frontend)
363c35fc 1424 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1425
afd96668
HV		 1426 switch (port->dev->board) {
1427 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1428 netup_ci_exit(port);
1429 break;
78db8547
IL		 1430 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1431 altera_ci_release(port->dev, port->nr);
1432 break;
afd96668 1433 }
5a23b076 1434
78db8547
IL		 1435 port->gate_ctrl = NULL;
1436
d19770e5
ST		 1437 return 0;
1438}
44a6481d 1439
Linux kernel - Deliverables
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