Commit | Line | Data |
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d19770e5 ST |
1 | /* |
2 | * Driver for the Conexant CX23885 PCIe bridge | |
3 | * | |
6d897616 | 4 | * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org> |
d19770e5 ST |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/device.h> | |
25 | #include <linux/fs.h> | |
26 | #include <linux/kthread.h> | |
27 | #include <linux/file.h> | |
28 | #include <linux/suspend.h> | |
29 | ||
30 | #include "cx23885.h" | |
d19770e5 ST |
31 | #include <media/v4l2-common.h> |
32 | ||
5a23b076 | 33 | #include "dvb_ca_en50221.h" |
d19770e5 | 34 | #include "s5h1409.h" |
52b50450 | 35 | #include "s5h1411.h" |
d19770e5 | 36 | #include "mt2131.h" |
3ba71d21 | 37 | #include "tda8290.h" |
4041f1a5 | 38 | #include "tda18271.h" |
9bc37caa | 39 | #include "lgdt330x.h" |
0cf8af57 | 40 | #include "xc4000.h" |
d1987d55 | 41 | #include "xc5000.h" |
ea5697fe | 42 | #include "max2165.h" |
b3ea0166 | 43 | #include "tda10048.h" |
07b4a835 | 44 | #include "tuner-xc2028.h" |
827855d3 | 45 | #include "tuner-simple.h" |
66762373 ST |
46 | #include "dib7000p.h" |
47 | #include "dibx000_common.h" | |
aef2d186 | 48 | #include "zl10353.h" |
5a23b076 | 49 | #include "stv0900.h" |
f867c3f4 | 50 | #include "stv0900_reg.h" |
5a23b076 IL |
51 | #include "stv6110.h" |
52 | #include "lnbh24.h" | |
96318d0c | 53 | #include "cx24116.h" |
e6001482 | 54 | #include "cx24117.h" |
5a23b076 | 55 | #include "cimax2.h" |
493b7127 | 56 | #include "lgs8gxx.h" |
5a23b076 IL |
57 | #include "netup-eeprom.h" |
58 | #include "netup-init.h" | |
a5dbf457 | 59 | #include "lgdt3305.h" |
ea5697fe | 60 | #include "atbm8830.h" |
73f0af44 | 61 | #include "ts2020.h" |
09ea33e5 IL |
62 | #include "ds3000.h" |
63 | #include "cx23885-f300.h" | |
78db8547 IL |
64 | #include "altera-ci.h" |
65 | #include "stv0367.h" | |
722c90eb SR |
66 | #include "drxk.h" |
67 | #include "mt2063.h" | |
f667190b MB |
68 | #include "stv090x.h" |
69 | #include "stb6100.h" | |
70 | #include "stb6100_cfg.h" | |
7c62f5a1 MK |
71 | #include "tda10071.h" |
72 | #include "a8293.h" | |
0d1b5265 | 73 | #include "mb86a20s.h" |
d19770e5 | 74 | |
4513fc69 | 75 | static unsigned int debug; |
d19770e5 | 76 | |
4513fc69 ST |
77 | #define dprintk(level, fmt, arg...)\ |
78 | do { if (debug >= level)\ | |
79 | printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\ | |
80 | } while (0) | |
d19770e5 ST |
81 | |
82 | /* ------------------------------------------------------------------ */ | |
83 | ||
3ba71d21 MK |
84 | static unsigned int alt_tuner; |
85 | module_param(alt_tuner, int, 0644); | |
86 | MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration"); | |
87 | ||
78e92006 JG |
88 | DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr); |
89 | ||
3ba71d21 MK |
90 | /* ------------------------------------------------------------------ */ |
91 | ||
d19770e5 ST |
92 | static int dvb_buf_setup(struct videobuf_queue *q, |
93 | unsigned int *count, unsigned int *size) | |
94 | { | |
95 | struct cx23885_tsport *port = q->priv_data; | |
96 | ||
97 | port->ts_packet_size = 188 * 4; | |
98 | port->ts_packet_count = 32; | |
99 | ||
100 | *size = port->ts_packet_size * port->ts_packet_count; | |
101 | *count = 32; | |
102 | return 0; | |
103 | } | |
104 | ||
44a6481d MK |
105 | static int dvb_buf_prepare(struct videobuf_queue *q, |
106 | struct videobuf_buffer *vb, enum v4l2_field field) | |
d19770e5 ST |
107 | { |
108 | struct cx23885_tsport *port = q->priv_data; | |
9c8ced51 | 109 | return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field); |
d19770e5 ST |
110 | } |
111 | ||
112 | static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb) | |
113 | { | |
114 | struct cx23885_tsport *port = q->priv_data; | |
9c8ced51 | 115 | cx23885_buf_queue(port, (struct cx23885_buffer *)vb); |
d19770e5 ST |
116 | } |
117 | ||
44a6481d MK |
118 | static void dvb_buf_release(struct videobuf_queue *q, |
119 | struct videobuf_buffer *vb) | |
d19770e5 | 120 | { |
9c8ced51 | 121 | cx23885_free_buffer(q, (struct cx23885_buffer *)vb); |
d19770e5 ST |
122 | } |
123 | ||
78db8547 IL |
124 | static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open) |
125 | { | |
126 | struct videobuf_dvb_frontends *f; | |
127 | struct videobuf_dvb_frontend *fe; | |
128 | ||
129 | f = &port->frontends; | |
130 | ||
131 | if (f->gate <= 1) /* undefined or fe0 */ | |
132 | fe = videobuf_dvb_get_frontend(f, 1); | |
133 | else | |
134 | fe = videobuf_dvb_get_frontend(f, f->gate); | |
135 | ||
136 | if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl) | |
137 | fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open); | |
138 | } | |
139 | ||
d19770e5 ST |
140 | static struct videobuf_queue_ops dvb_qops = { |
141 | .buf_setup = dvb_buf_setup, | |
142 | .buf_prepare = dvb_buf_prepare, | |
143 | .buf_queue = dvb_buf_queue, | |
144 | .buf_release = dvb_buf_release, | |
145 | }; | |
146 | ||
86184e06 | 147 | static struct s5h1409_config hauppauge_generic_config = { |
fc959bef ST |
148 | .demod_address = 0x32 >> 1, |
149 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
150 | .gpio = S5H1409_GPIO_ON, | |
2b03238a | 151 | .qam_if = 44000, |
fc959bef | 152 | .inversion = S5H1409_INVERSION_OFF, |
dfc1c08a ST |
153 | .status_mode = S5H1409_DEMODLOCKING, |
154 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
fc959bef ST |
155 | }; |
156 | ||
b3ea0166 ST |
157 | static struct tda10048_config hauppauge_hvr1200_config = { |
158 | .demod_address = 0x10 >> 1, | |
159 | .output_mode = TDA10048_SERIAL_OUTPUT, | |
160 | .fwbulkwritelen = TDA10048_BULKWRITE_200, | |
484d9e05 | 161 | .inversion = TDA10048_INVERSION_ON, |
8816bef5 ST |
162 | .dtv6_if_freq_khz = TDA10048_IF_3300, |
163 | .dtv7_if_freq_khz = TDA10048_IF_3800, | |
164 | .dtv8_if_freq_khz = TDA10048_IF_4300, | |
484d9e05 | 165 | .clk_freq_khz = TDA10048_CLK_16000, |
b3ea0166 ST |
166 | }; |
167 | ||
6b926eca MK |
168 | static struct tda10048_config hauppauge_hvr1210_config = { |
169 | .demod_address = 0x10 >> 1, | |
170 | .output_mode = TDA10048_SERIAL_OUTPUT, | |
171 | .fwbulkwritelen = TDA10048_BULKWRITE_200, | |
172 | .inversion = TDA10048_INVERSION_ON, | |
c27586e4 MK |
173 | .dtv6_if_freq_khz = TDA10048_IF_3300, |
174 | .dtv7_if_freq_khz = TDA10048_IF_3500, | |
175 | .dtv8_if_freq_khz = TDA10048_IF_4000, | |
6b926eca MK |
176 | .clk_freq_khz = TDA10048_CLK_16000, |
177 | }; | |
178 | ||
3ba71d21 MK |
179 | static struct s5h1409_config hauppauge_ezqam_config = { |
180 | .demod_address = 0x32 >> 1, | |
181 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
182 | .gpio = S5H1409_GPIO_OFF, | |
183 | .qam_if = 4000, | |
184 | .inversion = S5H1409_INVERSION_ON, | |
dfc1c08a ST |
185 | .status_mode = S5H1409_DEMODLOCKING, |
186 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
3ba71d21 MK |
187 | }; |
188 | ||
fc959bef | 189 | static struct s5h1409_config hauppauge_hvr1800lp_config = { |
d19770e5 ST |
190 | .demod_address = 0x32 >> 1, |
191 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
192 | .gpio = S5H1409_GPIO_OFF, | |
2b03238a | 193 | .qam_if = 44000, |
fe475163 | 194 | .inversion = S5H1409_INVERSION_OFF, |
dfc1c08a ST |
195 | .status_mode = S5H1409_DEMODLOCKING, |
196 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
d19770e5 ST |
197 | }; |
198 | ||
07b4a835 MK |
199 | static struct s5h1409_config hauppauge_hvr1500_config = { |
200 | .demod_address = 0x32 >> 1, | |
201 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
202 | .gpio = S5H1409_GPIO_OFF, | |
203 | .inversion = S5H1409_INVERSION_OFF, | |
dfc1c08a ST |
204 | .status_mode = S5H1409_DEMODLOCKING, |
205 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
07b4a835 MK |
206 | }; |
207 | ||
86184e06 | 208 | static struct mt2131_config hauppauge_generic_tunerconfig = { |
a77743bc ST |
209 | 0x61 |
210 | }; | |
211 | ||
9bc37caa MK |
212 | static struct lgdt330x_config fusionhdtv_5_express = { |
213 | .demod_address = 0x0e, | |
214 | .demod_chip = LGDT3303, | |
215 | .serial_mpeg = 0x40, | |
216 | }; | |
217 | ||
d1987d55 ST |
218 | static struct s5h1409_config hauppauge_hvr1500q_config = { |
219 | .demod_address = 0x32 >> 1, | |
220 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
221 | .gpio = S5H1409_GPIO_ON, | |
222 | .qam_if = 44000, | |
223 | .inversion = S5H1409_INVERSION_OFF, | |
dfc1c08a ST |
224 | .status_mode = S5H1409_DEMODLOCKING, |
225 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
d1987d55 ST |
226 | }; |
227 | ||
335377b7 MK |
228 | static struct s5h1409_config dvico_s5h1409_config = { |
229 | .demod_address = 0x32 >> 1, | |
230 | .output_mode = S5H1409_SERIAL_OUTPUT, | |
231 | .gpio = S5H1409_GPIO_ON, | |
232 | .qam_if = 44000, | |
233 | .inversion = S5H1409_INVERSION_OFF, | |
234 | .status_mode = S5H1409_DEMODLOCKING, | |
235 | .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
236 | }; | |
237 | ||
52b50450 MK |
238 | static struct s5h1411_config dvico_s5h1411_config = { |
239 | .output_mode = S5H1411_SERIAL_OUTPUT, | |
240 | .gpio = S5H1411_GPIO_ON, | |
241 | .qam_if = S5H1411_IF_44000, | |
242 | .vsb_if = S5H1411_IF_44000, | |
243 | .inversion = S5H1411_INVERSION_OFF, | |
244 | .status_mode = S5H1411_DEMODLOCKING, | |
245 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
246 | }; | |
247 | ||
19bc5796 MK |
248 | static struct s5h1411_config hcw_s5h1411_config = { |
249 | .output_mode = S5H1411_SERIAL_OUTPUT, | |
250 | .gpio = S5H1411_GPIO_OFF, | |
251 | .vsb_if = S5H1411_IF_44000, | |
252 | .qam_if = S5H1411_IF_4000, | |
253 | .inversion = S5H1411_INVERSION_ON, | |
254 | .status_mode = S5H1411_DEMODLOCKING, | |
255 | .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, | |
256 | }; | |
257 | ||
d1987d55 | 258 | static struct xc5000_config hauppauge_hvr1500q_tunerconfig = { |
e12671cf ST |
259 | .i2c_address = 0x61, |
260 | .if_khz = 5380, | |
d1987d55 ST |
261 | }; |
262 | ||
335377b7 MK |
263 | static struct xc5000_config dvico_xc5000_tunerconfig = { |
264 | .i2c_address = 0x64, | |
265 | .if_khz = 5380, | |
335377b7 MK |
266 | }; |
267 | ||
4041f1a5 MK |
268 | static struct tda829x_config tda829x_no_probe = { |
269 | .probe_tuner = TDA829X_DONT_PROBE, | |
270 | }; | |
271 | ||
f21e0d7f | 272 | static struct tda18271_std_map hauppauge_tda18271_std_map = { |
c0dc0c11 MK |
273 | .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3, |
274 | .if_lvl = 6, .rfagc_top = 0x37 }, | |
275 | .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0, | |
276 | .if_lvl = 6, .rfagc_top = 0x37 }, | |
f21e0d7f MK |
277 | }; |
278 | ||
b34cdc36 MK |
279 | static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = { |
280 | .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4, | |
281 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
282 | .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5, | |
283 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
284 | .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6, | |
285 | .if_lvl = 1, .rfagc_top = 0x37, }, | |
286 | }; | |
287 | ||
f21e0d7f MK |
288 | static struct tda18271_config hauppauge_tda18271_config = { |
289 | .std_map = &hauppauge_tda18271_std_map, | |
290 | .gate = TDA18271_GATE_ANALOG, | |
04a68baa | 291 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
f21e0d7f MK |
292 | }; |
293 | ||
b3ea0166 | 294 | static struct tda18271_config hauppauge_hvr1200_tuner_config = { |
b34cdc36 | 295 | .std_map = &hauppauge_hvr1200_tda18271_std_map, |
b3ea0166 | 296 | .gate = TDA18271_GATE_ANALOG, |
04a68baa | 297 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
b3ea0166 ST |
298 | }; |
299 | ||
6b926eca MK |
300 | static struct tda18271_config hauppauge_hvr1210_tuner_config = { |
301 | .gate = TDA18271_GATE_DIGITAL, | |
04a68baa | 302 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
6b926eca MK |
303 | }; |
304 | ||
247bc540 | 305 | static struct tda18271_std_map hauppauge_hvr127x_std_map = { |
a5dbf457 MK |
306 | .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4, |
307 | .if_lvl = 1, .rfagc_top = 0x58 }, | |
308 | .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5, | |
309 | .if_lvl = 1, .rfagc_top = 0x58 }, | |
310 | }; | |
311 | ||
247bc540 MK |
312 | static struct tda18271_config hauppauge_hvr127x_config = { |
313 | .std_map = &hauppauge_hvr127x_std_map, | |
04a68baa | 314 | .output_opt = TDA18271_OUTPUT_LT_OFF, |
a5dbf457 MK |
315 | }; |
316 | ||
247bc540 | 317 | static struct lgdt3305_config hauppauge_lgdt3305_config = { |
a5dbf457 MK |
318 | .i2c_addr = 0x0e, |
319 | .mpeg_mode = LGDT3305_MPEG_SERIAL, | |
320 | .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE, | |
321 | .tpvalid_polarity = LGDT3305_TP_VALID_HIGH, | |
322 | .deny_i2c_rptr = 1, | |
323 | .spectral_inversion = 1, | |
324 | .qam_if_khz = 4000, | |
325 | .vsb_if_khz = 3250, | |
326 | }; | |
327 | ||
b1721d0d | 328 | static struct dibx000_agc_config xc3028_agc_config = { |
66762373 ST |
329 | BAND_VHF | BAND_UHF, /* band_caps */ |
330 | ||
331 | /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0, | |
332 | * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0, | |
333 | * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0, | |
334 | * P_agc_nb_est=2, P_agc_write=0 | |
335 | */ | |
336 | (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) | | |
337 | (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */ | |
338 | ||
339 | 712, /* inv_gain */ | |
340 | 21, /* time_stabiliz */ | |
341 | ||
342 | 0, /* alpha_level */ | |
343 | 118, /* thlock */ | |
344 | ||
345 | 0, /* wbd_inv */ | |
346 | 2867, /* wbd_ref */ | |
347 | 0, /* wbd_sel */ | |
348 | 2, /* wbd_alpha */ | |
349 | ||
350 | 0, /* agc1_max */ | |
351 | 0, /* agc1_min */ | |
352 | 39718, /* agc2_max */ | |
353 | 9930, /* agc2_min */ | |
354 | 0, /* agc1_pt1 */ | |
355 | 0, /* agc1_pt2 */ | |
356 | 0, /* agc1_pt3 */ | |
357 | 0, /* agc1_slope1 */ | |
358 | 0, /* agc1_slope2 */ | |
359 | 0, /* agc2_pt1 */ | |
360 | 128, /* agc2_pt2 */ | |
361 | 29, /* agc2_slope1 */ | |
362 | 29, /* agc2_slope2 */ | |
363 | ||
364 | 17, /* alpha_mant */ | |
365 | 27, /* alpha_exp */ | |
366 | 23, /* beta_mant */ | |
367 | 51, /* beta_exp */ | |
368 | ||
369 | 1, /* perform_agc_softsplit */ | |
370 | }; | |
371 | ||
372 | /* PLL Configuration for COFDM BW_MHz = 8.000000 | |
373 | * With external clock = 30.000000 */ | |
b1721d0d | 374 | static struct dibx000_bandwidth_config xc3028_bw_config = { |
66762373 ST |
375 | 60000, /* internal */ |
376 | 30000, /* sampling */ | |
377 | 1, /* pll_cfg: prediv */ | |
378 | 8, /* pll_cfg: ratio */ | |
379 | 3, /* pll_cfg: range */ | |
380 | 1, /* pll_cfg: reset */ | |
381 | 0, /* pll_cfg: bypass */ | |
382 | 0, /* misc: refdiv */ | |
383 | 0, /* misc: bypclk_div */ | |
384 | 1, /* misc: IO_CLK_en_core */ | |
385 | 1, /* misc: ADClkSrc */ | |
386 | 0, /* misc: modulo */ | |
387 | (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */ | |
388 | (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */ | |
389 | 20452225, /* timf */ | |
390 | 30000000 /* xtal_hz */ | |
391 | }; | |
392 | ||
393 | static struct dib7000p_config hauppauge_hvr1400_dib7000_config = { | |
394 | .output_mpeg2_in_188_bytes = 1, | |
395 | .hostbus_diversity = 1, | |
396 | .tuner_is_baseband = 0, | |
397 | .update_lna = NULL, | |
398 | ||
399 | .agc_config_count = 1, | |
400 | .agc = &xc3028_agc_config, | |
401 | .bw = &xc3028_bw_config, | |
402 | ||
403 | .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS, | |
404 | .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES, | |
405 | .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS, | |
406 | ||
407 | .pwm_freq_div = 0, | |
408 | .agc_control = NULL, | |
409 | .spur_protect = 0, | |
410 | ||
411 | .output_mode = OUTMODE_MPEG2_SERIAL, | |
412 | }; | |
413 | ||
aef2d186 ST |
414 | static struct zl10353_config dvico_fusionhdtv_xc3028 = { |
415 | .demod_address = 0x0f, | |
416 | .if2 = 45600, | |
417 | .no_tuner = 1, | |
d4dc673d | 418 | .disable_i2c_gate_ctrl = 1, |
aef2d186 ST |
419 | }; |
420 | ||
f867c3f4 IL |
421 | static struct stv0900_reg stv0900_ts_regs[] = { |
422 | { R0900_TSGENERAL, 0x00 }, | |
423 | { R0900_P1_TSSPEED, 0x40 }, | |
424 | { R0900_P2_TSSPEED, 0x40 }, | |
425 | { R0900_P1_TSCFGM, 0xc0 }, | |
426 | { R0900_P2_TSCFGM, 0xc0 }, | |
427 | { R0900_P1_TSCFGH, 0xe0 }, | |
428 | { R0900_P2_TSCFGH, 0xe0 }, | |
429 | { R0900_P1_TSCFGL, 0x20 }, | |
430 | { R0900_P2_TSCFGL, 0x20 }, | |
431 | { 0xffff, 0xff }, /* terminate */ | |
432 | }; | |
433 | ||
5a23b076 IL |
434 | static struct stv0900_config netup_stv0900_config = { |
435 | .demod_address = 0x68, | |
29372a8d | 436 | .demod_mode = 1, /* dual */ |
644c7ef0 | 437 | .xtal = 8000000, |
5a23b076 IL |
438 | .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */ |
439 | .diseqc_mode = 2,/* 2/3 PWM */ | |
f867c3f4 | 440 | .ts_config_regs = stv0900_ts_regs, |
5a23b076 IL |
441 | .tun1_maddress = 0,/* 0x60 */ |
442 | .tun2_maddress = 3,/* 0x63 */ | |
443 | .tun1_adc = 1,/* 1 Vpp */ | |
444 | .tun2_adc = 1,/* 1 Vpp */ | |
445 | }; | |
446 | ||
447 | static struct stv6110_config netup_stv6110_tunerconfig_a = { | |
448 | .i2c_address = 0x60, | |
644c7ef0 AO |
449 | .mclk = 16000000, |
450 | .clk_div = 1, | |
873688cd | 451 | .gain = 8, /* +16 dB - maximum gain */ |
5a23b076 IL |
452 | }; |
453 | ||
454 | static struct stv6110_config netup_stv6110_tunerconfig_b = { | |
455 | .i2c_address = 0x63, | |
644c7ef0 AO |
456 | .mclk = 16000000, |
457 | .clk_div = 1, | |
873688cd | 458 | .gain = 8, /* +16 dB - maximum gain */ |
5a23b076 IL |
459 | }; |
460 | ||
96318d0c | 461 | static struct cx24116_config tbs_cx24116_config = { |
09ea33e5 | 462 | .demod_address = 0x55, |
96318d0c IL |
463 | }; |
464 | ||
e6001482 LA |
465 | static struct cx24117_config tbs_cx24117_config = { |
466 | .demod_address = 0x55, | |
467 | }; | |
468 | ||
09ea33e5 IL |
469 | static struct ds3000_config tevii_ds3000_config = { |
470 | .demod_address = 0x68, | |
579943f5 IL |
471 | }; |
472 | ||
73f0af44 KD |
473 | static struct ts2020_config tevii_ts2020_config = { |
474 | .tuner_address = 0x60, | |
b858c331 | 475 | .clk_out_div = 1, |
8d2b0229 | 476 | .frequency_div = 1146000, |
73f0af44 KD |
477 | }; |
478 | ||
c9b8b04b IL |
479 | static struct cx24116_config dvbworld_cx24116_config = { |
480 | .demod_address = 0x05, | |
481 | }; | |
482 | ||
493b7127 DW |
483 | static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = { |
484 | .prod = LGS8GXX_PROD_LGS8GL5, | |
485 | .demod_address = 0x19, | |
486 | .serial_ts = 0, | |
487 | .ts_clk_pol = 1, | |
488 | .ts_clk_gated = 1, | |
489 | .if_clk_freq = 30400, /* 30.4 MHz */ | |
490 | .if_freq = 5380, /* 5.38 MHz */ | |
491 | .if_neg_center = 1, | |
492 | .ext_adc = 0, | |
493 | .adc_signed = 0, | |
494 | .if_neg_edge = 0, | |
495 | }; | |
496 | ||
497 | static struct xc5000_config mygica_x8506_xc5000_config = { | |
498 | .i2c_address = 0x61, | |
499 | .if_khz = 5380, | |
500 | }; | |
501 | ||
0d1b5265 MCC |
502 | static struct mb86a20s_config mygica_x8507_mb86a20s_config = { |
503 | .demod_address = 0x10, | |
504 | }; | |
505 | ||
506 | static struct xc5000_config mygica_x8507_xc5000_config = { | |
507 | .i2c_address = 0x61, | |
508 | .if_khz = 4000, | |
509 | }; | |
510 | ||
f667190b | 511 | static struct stv090x_config prof_8000_stv090x_config = { |
b858c331 IL |
512 | .device = STV0903, |
513 | .demod_mode = STV090x_SINGLE, | |
514 | .clk_mode = STV090x_CLK_EXT, | |
515 | .xtal = 27000000, | |
516 | .address = 0x6A, | |
517 | .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED, | |
518 | .repeater_level = STV090x_RPTLEVEL_64, | |
519 | .adc1_range = STV090x_ADC_2Vpp, | |
520 | .diseqc_envelope_mode = false, | |
521 | ||
522 | .tuner_get_frequency = stb6100_get_frequency, | |
523 | .tuner_set_frequency = stb6100_set_frequency, | |
524 | .tuner_set_bandwidth = stb6100_set_bandwidth, | |
525 | .tuner_get_bandwidth = stb6100_get_bandwidth, | |
f667190b MB |
526 | }; |
527 | ||
528 | static struct stb6100_config prof_8000_stb6100_config = { | |
529 | .tuner_address = 0x60, | |
530 | .refclock = 27000000, | |
531 | }; | |
532 | ||
533 | static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage) | |
534 | { | |
535 | struct cx23885_tsport *port = fe->dvb->priv; | |
536 | struct cx23885_dev *dev = port->dev; | |
537 | ||
538 | if (voltage == SEC_VOLTAGE_18) | |
539 | cx_write(MC417_RWD, 0x00001e00); | |
540 | else if (voltage == SEC_VOLTAGE_13) | |
541 | cx_write(MC417_RWD, 0x00001a00); | |
542 | else | |
543 | cx_write(MC417_RWD, 0x00001800); | |
544 | return 0; | |
545 | } | |
546 | ||
a7d44baa | 547 | static int cx23885_dvb_set_frontend(struct dvb_frontend *fe) |
f35b9e80 | 548 | { |
a7d44baa | 549 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
f35b9e80 MK |
550 | struct cx23885_tsport *port = fe->dvb->priv; |
551 | struct cx23885_dev *dev = port->dev; | |
552 | ||
553 | switch (dev->board) { | |
554 | case CX23885_BOARD_HAUPPAUGE_HVR1275: | |
a7d44baa | 555 | switch (p->modulation) { |
f35b9e80 MK |
556 | case VSB_8: |
557 | cx23885_gpio_clear(dev, GPIO_5); | |
558 | break; | |
559 | case QAM_64: | |
560 | case QAM_256: | |
561 | default: | |
562 | cx23885_gpio_set(dev, GPIO_5); | |
563 | break; | |
564 | } | |
565 | break; | |
6f0d8c02 | 566 | case CX23885_BOARD_MYGICA_X8506: |
0d1b5265 | 567 | case CX23885_BOARD_MYGICA_X8507: |
6f0d8c02 DW |
568 | case CX23885_BOARD_MAGICPRO_PROHDTVE2: |
569 | /* Select Digital TV */ | |
570 | cx23885_gpio_set(dev, GPIO_0); | |
571 | break; | |
f35b9e80 | 572 | } |
15472faf MCC |
573 | |
574 | /* Call the real set_frontend */ | |
575 | if (port->set_frontend) | |
576 | return port->set_frontend(fe); | |
577 | ||
5bdd3962 | 578 | return 0; |
f35b9e80 MK |
579 | } |
580 | ||
15472faf MCC |
581 | static void cx23885_set_frontend_hook(struct cx23885_tsport *port, |
582 | struct dvb_frontend *fe) | |
583 | { | |
584 | port->set_frontend = fe->ops.set_frontend; | |
585 | fe->ops.set_frontend = cx23885_dvb_set_frontend; | |
586 | } | |
587 | ||
2365b2d3 DW |
588 | static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = { |
589 | .prod = LGS8GXX_PROD_LGS8G75, | |
590 | .demod_address = 0x19, | |
591 | .serial_ts = 0, | |
592 | .ts_clk_pol = 1, | |
593 | .ts_clk_gated = 1, | |
594 | .if_clk_freq = 30400, /* 30.4 MHz */ | |
595 | .if_freq = 6500, /* 6.50 MHz */ | |
596 | .if_neg_center = 1, | |
597 | .ext_adc = 0, | |
598 | .adc_signed = 1, | |
599 | .adc_vpp = 2, /* 1.6 Vpp */ | |
600 | .if_neg_edge = 1, | |
601 | }; | |
602 | ||
603 | static struct xc5000_config magicpro_prohdtve2_xc5000_config = { | |
604 | .i2c_address = 0x61, | |
605 | .if_khz = 6500, | |
606 | }; | |
607 | ||
ea5697fe DW |
608 | static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = { |
609 | .prod = ATBM8830_PROD_8830, | |
610 | .demod_address = 0x44, | |
611 | .serial_ts = 0, | |
612 | .ts_sampling_edge = 1, | |
613 | .ts_clk_gated = 0, | |
614 | .osc_clk_freq = 30400, /* in kHz */ | |
615 | .if_freq = 0, /* zero IF */ | |
616 | .zif_swap_iq = 1, | |
c245c75c DW |
617 | .agc_min = 0x2E, |
618 | .agc_max = 0xFF, | |
619 | .agc_hold_loop = 0, | |
ea5697fe DW |
620 | }; |
621 | ||
622 | static struct max2165_config mygic_x8558pro_max2165_cfg1 = { | |
623 | .i2c_address = 0x60, | |
624 | .osc_clk = 20 | |
625 | }; | |
626 | ||
627 | static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = { | |
628 | .prod = ATBM8830_PROD_8830, | |
629 | .demod_address = 0x44, | |
630 | .serial_ts = 1, | |
631 | .ts_sampling_edge = 1, | |
632 | .ts_clk_gated = 0, | |
633 | .osc_clk_freq = 30400, /* in kHz */ | |
634 | .if_freq = 0, /* zero IF */ | |
635 | .zif_swap_iq = 1, | |
c245c75c DW |
636 | .agc_min = 0x2E, |
637 | .agc_max = 0xFF, | |
638 | .agc_hold_loop = 0, | |
ea5697fe DW |
639 | }; |
640 | ||
641 | static struct max2165_config mygic_x8558pro_max2165_cfg2 = { | |
642 | .i2c_address = 0x60, | |
643 | .osc_clk = 20 | |
644 | }; | |
78db8547 IL |
645 | static struct stv0367_config netup_stv0367_config[] = { |
646 | { | |
647 | .demod_address = 0x1c, | |
648 | .xtal = 27000000, | |
649 | .if_khz = 4500, | |
650 | .if_iq_mode = 0, | |
651 | .ts_mode = 1, | |
652 | .clk_pol = 0, | |
653 | }, { | |
654 | .demod_address = 0x1d, | |
655 | .xtal = 27000000, | |
656 | .if_khz = 4500, | |
657 | .if_iq_mode = 0, | |
658 | .ts_mode = 1, | |
659 | .clk_pol = 0, | |
660 | }, | |
661 | }; | |
662 | ||
663 | static struct xc5000_config netup_xc5000_config[] = { | |
664 | { | |
665 | .i2c_address = 0x61, | |
666 | .if_khz = 4500, | |
667 | }, { | |
668 | .i2c_address = 0x64, | |
669 | .if_khz = 4500, | |
670 | }, | |
671 | }; | |
672 | ||
722c90eb SR |
673 | static struct drxk_config terratec_drxk_config[] = { |
674 | { | |
675 | .adr = 0x29, | |
676 | .no_i2c_bridge = 1, | |
677 | }, { | |
678 | .adr = 0x2a, | |
679 | .no_i2c_bridge = 1, | |
680 | }, | |
681 | }; | |
682 | ||
683 | static struct mt2063_config terratec_mt2063_config[] = { | |
684 | { | |
685 | .tuner_address = 0x60, | |
686 | }, { | |
687 | .tuner_address = 0x67, | |
688 | }, | |
689 | }; | |
690 | ||
7c62f5a1 | 691 | static const struct tda10071_config hauppauge_tda10071_config = { |
41f55d57 | 692 | .demod_i2c_addr = 0x05, |
7c62f5a1 MK |
693 | .tuner_i2c_addr = 0x54, |
694 | .i2c_wr_max = 64, | |
695 | .ts_mode = TDA10071_TS_SERIAL, | |
696 | .spec_inv = 0, | |
697 | .xtal = 40444000, /* 40.444 MHz */ | |
698 | .pll_multiplier = 20, | |
699 | }; | |
700 | ||
701 | static const struct a8293_config hauppauge_a8293_config = { | |
702 | .i2c_addr = 0x0b, | |
703 | }; | |
704 | ||
ada73eee | 705 | static int netup_altera_fpga_rw(void *device, int flag, int data, int read) |
78db8547 IL |
706 | { |
707 | struct cx23885_dev *dev = (struct cx23885_dev *)device; | |
708 | unsigned long timeout = jiffies + msecs_to_jiffies(1); | |
d164460f | 709 | uint32_t mem = 0; |
78db8547 | 710 | |
d164460f | 711 | mem = cx_read(MC417_RWD); |
78db8547 IL |
712 | if (read) |
713 | cx_set(MC417_OEN, ALT_DATA); | |
714 | else { | |
715 | cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */ | |
78db8547 IL |
716 | mem &= ~ALT_DATA; |
717 | mem |= (data & ALT_DATA); | |
78db8547 IL |
718 | } |
719 | ||
720 | if (flag) | |
d164460f | 721 | mem |= ALT_AD_RG; |
78db8547 | 722 | else |
d164460f | 723 | mem &= ~ALT_AD_RG; |
78db8547 | 724 | |
d164460f | 725 | mem &= ~ALT_CS; |
78db8547 | 726 | if (read) |
d164460f | 727 | mem = (mem & ~ALT_RD) | ALT_WR; |
78db8547 | 728 | else |
d164460f AO |
729 | mem = (mem & ~ALT_WR) | ALT_RD; |
730 | ||
731 | cx_write(MC417_RWD, mem); /* start RW cycle */ | |
78db8547 IL |
732 | |
733 | for (;;) { | |
734 | mem = cx_read(MC417_RWD); | |
735 | if ((mem & ALT_RDY) == 0) | |
736 | break; | |
737 | if (time_after(jiffies, timeout)) | |
738 | break; | |
739 | udelay(1); | |
740 | } | |
741 | ||
742 | cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS); | |
743 | if (read) | |
744 | return mem & ALT_DATA; | |
745 | ||
746 | return 0; | |
747 | }; | |
ea5697fe | 748 | |
d19770e5 ST |
749 | static int dvb_register(struct cx23885_tsport *port) |
750 | { | |
8abe4a0a | 751 | struct dib7000p_ops dib7000p_ops; |
d19770e5 | 752 | struct cx23885_dev *dev = port->dev; |
493b7127 | 753 | struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL; |
78db8547 IL |
754 | struct videobuf_dvb_frontend *fe0, *fe1 = NULL; |
755 | int mfe_shared = 0; /* bus not shared by default */ | |
5a23b076 | 756 | int ret; |
363c35fc | 757 | |
f972e0bd | 758 | /* Get the first frontend */ |
92abe9ee | 759 | fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); |
363c35fc ST |
760 | if (!fe0) |
761 | return -EINVAL; | |
d19770e5 ST |
762 | |
763 | /* init struct videobuf_dvb */ | |
363c35fc | 764 | fe0->dvb.name = dev->name; |
d19770e5 | 765 | |
78db8547 IL |
766 | /* multi-frontend gate control is undefined or defaults to fe0 */ |
767 | port->frontends.gate = 0; | |
768 | ||
769 | /* Sets the gate control callback to be used by i2c command calls */ | |
770 | port->gate_ctrl = cx23885_dvb_gate_ctrl; | |
771 | ||
d19770e5 ST |
772 | /* init frontend */ |
773 | switch (dev->board) { | |
a77743bc | 774 | case CX23885_BOARD_HAUPPAUGE_HVR1250: |
f139fa71 | 775 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 776 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
86184e06 | 777 | &hauppauge_generic_config, |
f139fa71 | 778 | &i2c_bus->i2c_adap); |
363c35fc ST |
779 | if (fe0->dvb.frontend != NULL) { |
780 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
f139fa71 | 781 | &i2c_bus->i2c_adap, |
86184e06 | 782 | &hauppauge_generic_tunerconfig, 0); |
d19770e5 ST |
783 | } |
784 | break; | |
a5dbf457 | 785 | case CX23885_BOARD_HAUPPAUGE_HVR1270: |
d099becb | 786 | case CX23885_BOARD_HAUPPAUGE_HVR1275: |
a5dbf457 MK |
787 | i2c_bus = &dev->i2c_bus[0]; |
788 | fe0->dvb.frontend = dvb_attach(lgdt3305_attach, | |
247bc540 | 789 | &hauppauge_lgdt3305_config, |
a5dbf457 MK |
790 | &i2c_bus->i2c_adap); |
791 | if (fe0->dvb.frontend != NULL) { | |
792 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
793 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
247bc540 | 794 | &hauppauge_hvr127x_config); |
a5dbf457 | 795 | } |
15472faf MCC |
796 | if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275) |
797 | cx23885_set_frontend_hook(port, fe0->dvb.frontend); | |
a5dbf457 | 798 | break; |
19bc5796 | 799 | case CX23885_BOARD_HAUPPAUGE_HVR1255: |
0ac60acb | 800 | case CX23885_BOARD_HAUPPAUGE_HVR1255_22111: |
19bc5796 MK |
801 | i2c_bus = &dev->i2c_bus[0]; |
802 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
803 | &hcw_s5h1411_config, | |
804 | &i2c_bus->i2c_adap); | |
805 | if (fe0->dvb.frontend != NULL) { | |
806 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
807 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
808 | &hauppauge_tda18271_config); | |
809 | } | |
0ac60acb DH |
810 | |
811 | tda18271_attach(&dev->ts1.analog_fe, | |
812 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
813 | &hauppauge_tda18271_config); | |
814 | ||
19bc5796 | 815 | break; |
3ba71d21 MK |
816 | case CX23885_BOARD_HAUPPAUGE_HVR1800: |
817 | i2c_bus = &dev->i2c_bus[0]; | |
92abe9ee | 818 | switch (alt_tuner) { |
3ba71d21 | 819 | case 1: |
363c35fc | 820 | fe0->dvb.frontend = |
3ba71d21 MK |
821 | dvb_attach(s5h1409_attach, |
822 | &hauppauge_ezqam_config, | |
823 | &i2c_bus->i2c_adap); | |
363c35fc ST |
824 | if (fe0->dvb.frontend != NULL) { |
825 | dvb_attach(tda829x_attach, fe0->dvb.frontend, | |
3ba71d21 | 826 | &dev->i2c_bus[1].i2c_adap, 0x42, |
4041f1a5 | 827 | &tda829x_no_probe); |
363c35fc | 828 | dvb_attach(tda18271_attach, fe0->dvb.frontend, |
4041f1a5 | 829 | 0x60, &dev->i2c_bus[1].i2c_adap, |
f21e0d7f | 830 | &hauppauge_tda18271_config); |
3ba71d21 MK |
831 | } |
832 | break; | |
833 | case 0: | |
834 | default: | |
363c35fc | 835 | fe0->dvb.frontend = |
3ba71d21 MK |
836 | dvb_attach(s5h1409_attach, |
837 | &hauppauge_generic_config, | |
838 | &i2c_bus->i2c_adap); | |
363c35fc ST |
839 | if (fe0->dvb.frontend != NULL) |
840 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
3ba71d21 MK |
841 | &i2c_bus->i2c_adap, |
842 | &hauppauge_generic_tunerconfig, 0); | |
843 | break; | |
844 | } | |
845 | break; | |
fc959bef | 846 | case CX23885_BOARD_HAUPPAUGE_HVR1800lp: |
f139fa71 | 847 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 848 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
fc959bef | 849 | &hauppauge_hvr1800lp_config, |
f139fa71 | 850 | &i2c_bus->i2c_adap); |
363c35fc ST |
851 | if (fe0->dvb.frontend != NULL) { |
852 | dvb_attach(mt2131_attach, fe0->dvb.frontend, | |
f139fa71 | 853 | &i2c_bus->i2c_adap, |
fc959bef ST |
854 | &hauppauge_generic_tunerconfig, 0); |
855 | } | |
856 | break; | |
9bc37caa | 857 | case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP: |
f139fa71 | 858 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 859 | fe0->dvb.frontend = dvb_attach(lgdt330x_attach, |
9bc37caa | 860 | &fusionhdtv_5_express, |
f139fa71 | 861 | &i2c_bus->i2c_adap); |
363c35fc ST |
862 | if (fe0->dvb.frontend != NULL) { |
863 | dvb_attach(simple_tuner_attach, fe0->dvb.frontend, | |
827855d3 MK |
864 | &i2c_bus->i2c_adap, 0x61, |
865 | TUNER_LG_TDVS_H06XF); | |
9bc37caa MK |
866 | } |
867 | break; | |
d1987d55 ST |
868 | case CX23885_BOARD_HAUPPAUGE_HVR1500Q: |
869 | i2c_bus = &dev->i2c_bus[1]; | |
363c35fc | 870 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
d1987d55 ST |
871 | &hauppauge_hvr1500q_config, |
872 | &dev->i2c_bus[0].i2c_adap); | |
363c35fc ST |
873 | if (fe0->dvb.frontend != NULL) |
874 | dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
30650961 MK |
875 | &i2c_bus->i2c_adap, |
876 | &hauppauge_hvr1500q_tunerconfig); | |
d1987d55 | 877 | break; |
07b4a835 MK |
878 | case CX23885_BOARD_HAUPPAUGE_HVR1500: |
879 | i2c_bus = &dev->i2c_bus[1]; | |
363c35fc | 880 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
07b4a835 MK |
881 | &hauppauge_hvr1500_config, |
882 | &dev->i2c_bus[0].i2c_adap); | |
363c35fc | 883 | if (fe0->dvb.frontend != NULL) { |
07b4a835 MK |
884 | struct dvb_frontend *fe; |
885 | struct xc2028_config cfg = { | |
886 | .i2c_adap = &i2c_bus->i2c_adap, | |
887 | .i2c_addr = 0x61, | |
07b4a835 MK |
888 | }; |
889 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 890 | .fname = XC2028_DEFAULT_FIRMWARE, |
07b4a835 | 891 | .max_len = 64, |
52c3d29c | 892 | .demod = XC3028_FE_OREN538, |
07b4a835 MK |
893 | }; |
894 | ||
895 | fe = dvb_attach(xc2028_attach, | |
363c35fc | 896 | fe0->dvb.frontend, &cfg); |
07b4a835 MK |
897 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) |
898 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
899 | } | |
900 | break; | |
b3ea0166 | 901 | case CX23885_BOARD_HAUPPAUGE_HVR1200: |
a780a31c | 902 | case CX23885_BOARD_HAUPPAUGE_HVR1700: |
b3ea0166 | 903 | i2c_bus = &dev->i2c_bus[0]; |
363c35fc | 904 | fe0->dvb.frontend = dvb_attach(tda10048_attach, |
b3ea0166 ST |
905 | &hauppauge_hvr1200_config, |
906 | &i2c_bus->i2c_adap); | |
363c35fc ST |
907 | if (fe0->dvb.frontend != NULL) { |
908 | dvb_attach(tda829x_attach, fe0->dvb.frontend, | |
b3ea0166 ST |
909 | &dev->i2c_bus[1].i2c_adap, 0x42, |
910 | &tda829x_no_probe); | |
363c35fc | 911 | dvb_attach(tda18271_attach, fe0->dvb.frontend, |
b3ea0166 ST |
912 | 0x60, &dev->i2c_bus[1].i2c_adap, |
913 | &hauppauge_hvr1200_tuner_config); | |
6b926eca MK |
914 | } |
915 | break; | |
916 | case CX23885_BOARD_HAUPPAUGE_HVR1210: | |
917 | i2c_bus = &dev->i2c_bus[0]; | |
918 | fe0->dvb.frontend = dvb_attach(tda10048_attach, | |
919 | &hauppauge_hvr1210_config, | |
920 | &i2c_bus->i2c_adap); | |
921 | if (fe0->dvb.frontend != NULL) { | |
922 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
923 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
924 | &hauppauge_hvr1210_tuner_config); | |
b3ea0166 ST |
925 | } |
926 | break; | |
66762373 ST |
927 | case CX23885_BOARD_HAUPPAUGE_HVR1400: |
928 | i2c_bus = &dev->i2c_bus[0]; | |
8abe4a0a MCC |
929 | |
930 | if (!dvb_attach(dib7000p_attach, &dib7000p_ops)) | |
931 | return -ENODEV; | |
932 | ||
933 | fe0->dvb.frontend = dib7000p_ops.init(&i2c_bus->i2c_adap, | |
66762373 | 934 | 0x12, &hauppauge_hvr1400_dib7000_config); |
363c35fc | 935 | if (fe0->dvb.frontend != NULL) { |
66762373 ST |
936 | struct dvb_frontend *fe; |
937 | struct xc2028_config cfg = { | |
938 | .i2c_adap = &dev->i2c_bus[1].i2c_adap, | |
939 | .i2c_addr = 0x64, | |
66762373 ST |
940 | }; |
941 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 942 | .fname = XC3028L_DEFAULT_FIRMWARE, |
66762373 | 943 | .max_len = 64, |
9bed77ee | 944 | .demod = XC3028_FE_DIBCOM52, |
9c8ced51 ST |
945 | /* This is true for all demods with |
946 | v36 firmware? */ | |
0975fc68 | 947 | .type = XC2028_D2633, |
66762373 ST |
948 | }; |
949 | ||
950 | fe = dvb_attach(xc2028_attach, | |
363c35fc | 951 | fe0->dvb.frontend, &cfg); |
66762373 ST |
952 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) |
953 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
954 | } | |
955 | break; | |
335377b7 MK |
956 | case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP: |
957 | i2c_bus = &dev->i2c_bus[port->nr - 1]; | |
958 | ||
363c35fc | 959 | fe0->dvb.frontend = dvb_attach(s5h1409_attach, |
335377b7 MK |
960 | &dvico_s5h1409_config, |
961 | &i2c_bus->i2c_adap); | |
363c35fc ST |
962 | if (fe0->dvb.frontend == NULL) |
963 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
52b50450 MK |
964 | &dvico_s5h1411_config, |
965 | &i2c_bus->i2c_adap); | |
363c35fc ST |
966 | if (fe0->dvb.frontend != NULL) |
967 | dvb_attach(xc5000_attach, fe0->dvb.frontend, | |
30650961 MK |
968 | &i2c_bus->i2c_adap, |
969 | &dvico_xc5000_tunerconfig); | |
335377b7 | 970 | break; |
aef2d186 ST |
971 | case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: { |
972 | i2c_bus = &dev->i2c_bus[port->nr - 1]; | |
973 | ||
363c35fc | 974 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
aef2d186 ST |
975 | &dvico_fusionhdtv_xc3028, |
976 | &i2c_bus->i2c_adap); | |
363c35fc | 977 | if (fe0->dvb.frontend != NULL) { |
aef2d186 ST |
978 | struct dvb_frontend *fe; |
979 | struct xc2028_config cfg = { | |
980 | .i2c_adap = &i2c_bus->i2c_adap, | |
981 | .i2c_addr = 0x61, | |
aef2d186 ST |
982 | }; |
983 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 984 | .fname = XC2028_DEFAULT_FIRMWARE, |
aef2d186 ST |
985 | .max_len = 64, |
986 | .demod = XC3028_FE_ZARLINK456, | |
987 | }; | |
988 | ||
363c35fc | 989 | fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, |
aef2d186 ST |
990 | &cfg); |
991 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) | |
992 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
993 | } | |
994 | break; | |
995 | } | |
4c56b04a | 996 | case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H: |
9bb1b7e8 | 997 | case CX23885_BOARD_COMPRO_VIDEOMATE_E650F: |
34e383dd | 998 | case CX23885_BOARD_COMPRO_VIDEOMATE_E800: |
4c56b04a ST |
999 | i2c_bus = &dev->i2c_bus[0]; |
1000 | ||
363c35fc | 1001 | fe0->dvb.frontend = dvb_attach(zl10353_attach, |
4c56b04a ST |
1002 | &dvico_fusionhdtv_xc3028, |
1003 | &i2c_bus->i2c_adap); | |
363c35fc | 1004 | if (fe0->dvb.frontend != NULL) { |
4c56b04a ST |
1005 | struct dvb_frontend *fe; |
1006 | struct xc2028_config cfg = { | |
1007 | .i2c_adap = &dev->i2c_bus[1].i2c_adap, | |
1008 | .i2c_addr = 0x61, | |
4c56b04a ST |
1009 | }; |
1010 | static struct xc2028_ctrl ctl = { | |
ef80bfeb | 1011 | .fname = XC2028_DEFAULT_FIRMWARE, |
4c56b04a ST |
1012 | .max_len = 64, |
1013 | .demod = XC3028_FE_ZARLINK456, | |
1014 | }; | |
1015 | ||
363c35fc | 1016 | fe = dvb_attach(xc2028_attach, fe0->dvb.frontend, |
4c56b04a ST |
1017 | &cfg); |
1018 | if (fe != NULL && fe->ops.tuner_ops.set_config != NULL) | |
1019 | fe->ops.tuner_ops.set_config(fe, &ctl); | |
1020 | } | |
96318d0c | 1021 | break; |
0cf8af57 | 1022 | case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000: |
1023 | i2c_bus = &dev->i2c_bus[0]; | |
1024 | ||
1025 | fe0->dvb.frontend = dvb_attach(zl10353_attach, | |
1026 | &dvico_fusionhdtv_xc3028, | |
1027 | &i2c_bus->i2c_adap); | |
1028 | if (fe0->dvb.frontend != NULL) { | |
1029 | struct dvb_frontend *fe; | |
1030 | struct xc4000_config cfg = { | |
1031 | .i2c_address = 0x61, | |
1032 | .default_pm = 0, | |
1033 | .dvb_amplitude = 134, | |
1034 | .set_smoothedcvbs = 1, | |
1035 | .if_khz = 4560 | |
1036 | }; | |
1037 | ||
1038 | fe = dvb_attach(xc4000_attach, fe0->dvb.frontend, | |
1039 | &dev->i2c_bus[1].i2c_adap, &cfg); | |
a7c8aada MS |
1040 | if (!fe) { |
1041 | printk(KERN_ERR "%s/2: xc4000 attach failed\n", | |
1042 | dev->name); | |
1043 | goto frontend_detach; | |
1044 | } | |
0cf8af57 | 1045 | } |
1046 | break; | |
96318d0c | 1047 | case CX23885_BOARD_TBS_6920: |
09ea33e5 | 1048 | i2c_bus = &dev->i2c_bus[1]; |
96318d0c IL |
1049 | |
1050 | fe0->dvb.frontend = dvb_attach(cx24116_attach, | |
09ea33e5 IL |
1051 | &tbs_cx24116_config, |
1052 | &i2c_bus->i2c_adap); | |
96318d0c | 1053 | if (fe0->dvb.frontend != NULL) |
09ea33e5 | 1054 | fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; |
96318d0c | 1055 | |
579943f5 | 1056 | break; |
e6001482 LA |
1057 | case CX23885_BOARD_TBS_6980: |
1058 | case CX23885_BOARD_TBS_6981: | |
1059 | i2c_bus = &dev->i2c_bus[1]; | |
1060 | ||
1061 | switch (port->nr) { | |
1062 | /* PORT B */ | |
1063 | case 1: | |
1064 | fe0->dvb.frontend = dvb_attach(cx24117_attach, | |
1065 | &tbs_cx24117_config, | |
d10e8280 | 1066 | &i2c_bus->i2c_adap); |
e6001482 LA |
1067 | break; |
1068 | /* PORT C */ | |
1069 | case 2: | |
e6001482 LA |
1070 | fe0->dvb.frontend = dvb_attach(cx24117_attach, |
1071 | &tbs_cx24117_config, | |
d10e8280 | 1072 | &i2c_bus->i2c_adap); |
e6001482 LA |
1073 | break; |
1074 | } | |
1075 | break; | |
579943f5 IL |
1076 | case CX23885_BOARD_TEVII_S470: |
1077 | i2c_bus = &dev->i2c_bus[1]; | |
1078 | ||
09ea33e5 IL |
1079 | fe0->dvb.frontend = dvb_attach(ds3000_attach, |
1080 | &tevii_ds3000_config, | |
1081 | &i2c_bus->i2c_adap); | |
73f0af44 KD |
1082 | if (fe0->dvb.frontend != NULL) { |
1083 | dvb_attach(ts2020_attach, fe0->dvb.frontend, | |
1084 | &tevii_ts2020_config, &i2c_bus->i2c_adap); | |
09ea33e5 | 1085 | fe0->dvb.frontend->ops.set_voltage = f300_set_voltage; |
73f0af44 | 1086 | } |
579943f5 | 1087 | |
4c56b04a | 1088 | break; |
c9b8b04b IL |
1089 | case CX23885_BOARD_DVBWORLD_2005: |
1090 | i2c_bus = &dev->i2c_bus[1]; | |
1091 | ||
1092 | fe0->dvb.frontend = dvb_attach(cx24116_attach, | |
1093 | &dvbworld_cx24116_config, | |
1094 | &i2c_bus->i2c_adap); | |
1095 | break; | |
5a23b076 IL |
1096 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: |
1097 | i2c_bus = &dev->i2c_bus[0]; | |
1098 | switch (port->nr) { | |
1099 | /* port B */ | |
1100 | case 1: | |
1101 | fe0->dvb.frontend = dvb_attach(stv0900_attach, | |
1102 | &netup_stv0900_config, | |
1103 | &i2c_bus->i2c_adap, 0); | |
1104 | if (fe0->dvb.frontend != NULL) { | |
1105 | if (dvb_attach(stv6110_attach, | |
1106 | fe0->dvb.frontend, | |
1107 | &netup_stv6110_tunerconfig_a, | |
1108 | &i2c_bus->i2c_adap)) { | |
1109 | if (!dvb_attach(lnbh24_attach, | |
1110 | fe0->dvb.frontend, | |
1111 | &i2c_bus->i2c_adap, | |
9329fb5b AO |
1112 | LNBH24_PCL | LNBH24_TTX, |
1113 | LNBH24_TEN, 0x09)) | |
5a23b076 IL |
1114 | printk(KERN_ERR |
1115 | "No LNBH24 found!\n"); | |
1116 | ||
1117 | } | |
1118 | } | |
1119 | break; | |
1120 | /* port C */ | |
1121 | case 2: | |
1122 | fe0->dvb.frontend = dvb_attach(stv0900_attach, | |
1123 | &netup_stv0900_config, | |
1124 | &i2c_bus->i2c_adap, 1); | |
1125 | if (fe0->dvb.frontend != NULL) { | |
1126 | if (dvb_attach(stv6110_attach, | |
1127 | fe0->dvb.frontend, | |
1128 | &netup_stv6110_tunerconfig_b, | |
1129 | &i2c_bus->i2c_adap)) { | |
1130 | if (!dvb_attach(lnbh24_attach, | |
1131 | fe0->dvb.frontend, | |
1132 | &i2c_bus->i2c_adap, | |
9329fb5b AO |
1133 | LNBH24_PCL | LNBH24_TTX, |
1134 | LNBH24_TEN, 0x0a)) | |
5a23b076 IL |
1135 | printk(KERN_ERR |
1136 | "No LNBH24 found!\n"); | |
1137 | ||
1138 | } | |
1139 | } | |
1140 | break; | |
1141 | } | |
1142 | break; | |
493b7127 DW |
1143 | case CX23885_BOARD_MYGICA_X8506: |
1144 | i2c_bus = &dev->i2c_bus[0]; | |
1145 | i2c_bus2 = &dev->i2c_bus[1]; | |
1146 | fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, | |
1147 | &mygica_x8506_lgs8gl5_config, | |
1148 | &i2c_bus->i2c_adap); | |
1149 | if (fe0->dvb.frontend != NULL) { | |
1150 | dvb_attach(xc5000_attach, | |
1151 | fe0->dvb.frontend, | |
1152 | &i2c_bus2->i2c_adap, | |
1153 | &mygica_x8506_xc5000_config); | |
1154 | } | |
15472faf | 1155 | cx23885_set_frontend_hook(port, fe0->dvb.frontend); |
493b7127 | 1156 | break; |
0d1b5265 MCC |
1157 | case CX23885_BOARD_MYGICA_X8507: |
1158 | i2c_bus = &dev->i2c_bus[0]; | |
1159 | i2c_bus2 = &dev->i2c_bus[1]; | |
1160 | fe0->dvb.frontend = dvb_attach(mb86a20s_attach, | |
1161 | &mygica_x8507_mb86a20s_config, | |
1162 | &i2c_bus->i2c_adap); | |
1163 | if (fe0->dvb.frontend != NULL) { | |
1164 | dvb_attach(xc5000_attach, | |
1165 | fe0->dvb.frontend, | |
1166 | &i2c_bus2->i2c_adap, | |
1167 | &mygica_x8507_xc5000_config); | |
1168 | } | |
1169 | cx23885_set_frontend_hook(port, fe0->dvb.frontend); | |
1170 | break; | |
2365b2d3 DW |
1171 | case CX23885_BOARD_MAGICPRO_PROHDTVE2: |
1172 | i2c_bus = &dev->i2c_bus[0]; | |
1173 | i2c_bus2 = &dev->i2c_bus[1]; | |
1174 | fe0->dvb.frontend = dvb_attach(lgs8gxx_attach, | |
1175 | &magicpro_prohdtve2_lgs8g75_config, | |
1176 | &i2c_bus->i2c_adap); | |
1177 | if (fe0->dvb.frontend != NULL) { | |
1178 | dvb_attach(xc5000_attach, | |
1179 | fe0->dvb.frontend, | |
1180 | &i2c_bus2->i2c_adap, | |
1181 | &magicpro_prohdtve2_xc5000_config); | |
1182 | } | |
15472faf | 1183 | cx23885_set_frontend_hook(port, fe0->dvb.frontend); |
2365b2d3 | 1184 | break; |
13697380 | 1185 | case CX23885_BOARD_HAUPPAUGE_HVR1850: |
35045137 ST |
1186 | i2c_bus = &dev->i2c_bus[0]; |
1187 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
1188 | &hcw_s5h1411_config, | |
1189 | &i2c_bus->i2c_adap); | |
1190 | if (fe0->dvb.frontend != NULL) | |
1191 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
1192 | 0x60, &dev->i2c_bus[0].i2c_adap, | |
1193 | &hauppauge_tda18271_config); | |
1194 | ||
1195 | tda18271_attach(&dev->ts1.analog_fe, | |
1196 | 0x60, &dev->i2c_bus[1].i2c_adap, | |
1197 | &hauppauge_tda18271_config); | |
1198 | ||
1199 | break; | |
aee0b24c | 1200 | case CX23885_BOARD_HAUPPAUGE_HVR1290: |
13697380 ST |
1201 | i2c_bus = &dev->i2c_bus[0]; |
1202 | fe0->dvb.frontend = dvb_attach(s5h1411_attach, | |
1203 | &hcw_s5h1411_config, | |
1204 | &i2c_bus->i2c_adap); | |
1205 | if (fe0->dvb.frontend != NULL) | |
1206 | dvb_attach(tda18271_attach, fe0->dvb.frontend, | |
1207 | 0x60, &dev->i2c_bus[0].i2c_adap, | |
1208 | &hauppauge_tda18271_config); | |
1209 | break; | |
ea5697fe DW |
1210 | case CX23885_BOARD_MYGICA_X8558PRO: |
1211 | switch (port->nr) { | |
1212 | /* port B */ | |
1213 | case 1: | |
1214 | i2c_bus = &dev->i2c_bus[0]; | |
1215 | fe0->dvb.frontend = dvb_attach(atbm8830_attach, | |
1216 | &mygica_x8558pro_atbm8830_cfg1, | |
1217 | &i2c_bus->i2c_adap); | |
1218 | if (fe0->dvb.frontend != NULL) { | |
1219 | dvb_attach(max2165_attach, | |
1220 | fe0->dvb.frontend, | |
1221 | &i2c_bus->i2c_adap, | |
1222 | &mygic_x8558pro_max2165_cfg1); | |
1223 | } | |
1224 | break; | |
1225 | /* port C */ | |
1226 | case 2: | |
1227 | i2c_bus = &dev->i2c_bus[1]; | |
1228 | fe0->dvb.frontend = dvb_attach(atbm8830_attach, | |
1229 | &mygica_x8558pro_atbm8830_cfg2, | |
1230 | &i2c_bus->i2c_adap); | |
1231 | if (fe0->dvb.frontend != NULL) { | |
1232 | dvb_attach(max2165_attach, | |
1233 | fe0->dvb.frontend, | |
1234 | &i2c_bus->i2c_adap, | |
1235 | &mygic_x8558pro_max2165_cfg2); | |
1236 | } | |
1237 | break; | |
1238 | } | |
1239 | break; | |
78db8547 IL |
1240 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: |
1241 | i2c_bus = &dev->i2c_bus[0]; | |
1242 | mfe_shared = 1;/* MFE */ | |
1243 | port->frontends.gate = 0;/* not clear for me yet */ | |
1244 | /* ports B, C */ | |
1245 | /* MFE frontend 1 DVB-T */ | |
1246 | fe0->dvb.frontend = dvb_attach(stv0367ter_attach, | |
1247 | &netup_stv0367_config[port->nr - 1], | |
1248 | &i2c_bus->i2c_adap); | |
4174ebf5 | 1249 | if (fe0->dvb.frontend != NULL) { |
78db8547 IL |
1250 | if (NULL == dvb_attach(xc5000_attach, |
1251 | fe0->dvb.frontend, | |
1252 | &i2c_bus->i2c_adap, | |
1253 | &netup_xc5000_config[port->nr - 1])) | |
1254 | goto frontend_detach; | |
4174ebf5 AO |
1255 | /* load xc5000 firmware */ |
1256 | fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend); | |
1257 | } | |
78db8547 IL |
1258 | /* MFE frontend 2 */ |
1259 | fe1 = videobuf_dvb_get_frontend(&port->frontends, 2); | |
1260 | if (fe1 == NULL) | |
1261 | goto frontend_detach; | |
1262 | /* DVB-C init */ | |
1263 | fe1->dvb.frontend = dvb_attach(stv0367cab_attach, | |
1264 | &netup_stv0367_config[port->nr - 1], | |
1265 | &i2c_bus->i2c_adap); | |
1266 | if (fe1->dvb.frontend != NULL) { | |
1267 | fe1->dvb.frontend->id = 1; | |
1268 | if (NULL == dvb_attach(xc5000_attach, | |
1269 | fe1->dvb.frontend, | |
1270 | &i2c_bus->i2c_adap, | |
1271 | &netup_xc5000_config[port->nr - 1])) | |
1272 | goto frontend_detach; | |
1273 | } | |
1274 | break; | |
722c90eb SR |
1275 | case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL: |
1276 | i2c_bus = &dev->i2c_bus[0]; | |
1277 | i2c_bus2 = &dev->i2c_bus[1]; | |
1278 | ||
1279 | switch (port->nr) { | |
1280 | /* port b */ | |
1281 | case 1: | |
1282 | fe0->dvb.frontend = dvb_attach(drxk_attach, | |
1283 | &terratec_drxk_config[0], | |
1284 | &i2c_bus->i2c_adap); | |
1285 | if (fe0->dvb.frontend != NULL) { | |
1286 | if (!dvb_attach(mt2063_attach, | |
1287 | fe0->dvb.frontend, | |
1288 | &terratec_mt2063_config[0], | |
1289 | &i2c_bus2->i2c_adap)) | |
1290 | goto frontend_detach; | |
1291 | } | |
1292 | break; | |
1293 | /* port c */ | |
1294 | case 2: | |
1295 | fe0->dvb.frontend = dvb_attach(drxk_attach, | |
1296 | &terratec_drxk_config[1], | |
1297 | &i2c_bus->i2c_adap); | |
1298 | if (fe0->dvb.frontend != NULL) { | |
1299 | if (!dvb_attach(mt2063_attach, | |
1300 | fe0->dvb.frontend, | |
1301 | &terratec_mt2063_config[1], | |
1302 | &i2c_bus2->i2c_adap)) | |
1303 | goto frontend_detach; | |
1304 | } | |
1305 | break; | |
1306 | } | |
1307 | break; | |
7b134e85 IL |
1308 | case CX23885_BOARD_TEVII_S471: |
1309 | i2c_bus = &dev->i2c_bus[1]; | |
1310 | ||
1311 | fe0->dvb.frontend = dvb_attach(ds3000_attach, | |
1312 | &tevii_ds3000_config, | |
1313 | &i2c_bus->i2c_adap); | |
b43ea806 JK |
1314 | if (fe0->dvb.frontend != NULL) { |
1315 | dvb_attach(ts2020_attach, fe0->dvb.frontend, | |
1316 | &tevii_ts2020_config, &i2c_bus->i2c_adap); | |
1317 | } | |
7b134e85 | 1318 | break; |
f667190b MB |
1319 | case CX23885_BOARD_PROF_8000: |
1320 | i2c_bus = &dev->i2c_bus[0]; | |
1321 | ||
1322 | fe0->dvb.frontend = dvb_attach(stv090x_attach, | |
1323 | &prof_8000_stv090x_config, | |
1324 | &i2c_bus->i2c_adap, | |
1325 | STV090x_DEMODULATOR_0); | |
1326 | if (fe0->dvb.frontend != NULL) { | |
1327 | if (!dvb_attach(stb6100_attach, | |
1328 | fe0->dvb.frontend, | |
1329 | &prof_8000_stb6100_config, | |
1330 | &i2c_bus->i2c_adap)) | |
1331 | goto frontend_detach; | |
1332 | ||
1333 | fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage; | |
1334 | } | |
1335 | break; | |
7c62f5a1 MK |
1336 | case CX23885_BOARD_HAUPPAUGE_HVR4400: |
1337 | i2c_bus = &dev->i2c_bus[0]; | |
1338 | fe0->dvb.frontend = dvb_attach(tda10071_attach, | |
1339 | &hauppauge_tda10071_config, | |
1340 | &i2c_bus->i2c_adap); | |
1341 | if (fe0->dvb.frontend != NULL) { | |
1342 | dvb_attach(a8293_attach, fe0->dvb.frontend, | |
1343 | &i2c_bus->i2c_adap, | |
1344 | &hauppauge_a8293_config); | |
1345 | } | |
1346 | break; | |
d19770e5 | 1347 | default: |
9c8ced51 ST |
1348 | printk(KERN_INFO "%s: The frontend of your DVB/ATSC card " |
1349 | " isn't supported yet\n", | |
d19770e5 ST |
1350 | dev->name); |
1351 | break; | |
1352 | } | |
78db8547 IL |
1353 | |
1354 | if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) { | |
9c8ced51 | 1355 | printk(KERN_ERR "%s: frontend initialization failed\n", |
78db8547 IL |
1356 | dev->name); |
1357 | goto frontend_detach; | |
d19770e5 | 1358 | } |
78db8547 | 1359 | |
d7cba043 | 1360 | /* define general-purpose callback pointer */ |
363c35fc | 1361 | fe0->dvb.frontend->callback = cx23885_tuner_callback; |
78db8547 IL |
1362 | if (fe1) |
1363 | fe1->dvb.frontend->callback = cx23885_tuner_callback; | |
1364 | #if 0 | |
1365 | /* Ensure all frontends negotiate bus access */ | |
1366 | fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; | |
1367 | if (fe1) | |
1368 | fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl; | |
1369 | #endif | |
d19770e5 ST |
1370 | |
1371 | /* Put the analog decoder in standby to keep it quiet */ | |
622b828a | 1372 | call_all(dev, core, s_power, 0); |
d19770e5 | 1373 | |
363c35fc ST |
1374 | if (fe0->dvb.frontend->ops.analog_ops.standby) |
1375 | fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend); | |
3ba71d21 | 1376 | |
d19770e5 | 1377 | /* register everything */ |
5a23b076 | 1378 | ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port, |
9adf6132 | 1379 | &dev->pci->dev, adapter_nr, mfe_shared); |
bee30192 | 1380 | if (ret) |
78db8547 | 1381 | goto frontend_detach; |
363c35fc | 1382 | |
5a23b076 IL |
1383 | /* init CI & MAC */ |
1384 | switch (dev->board) { | |
1385 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: { | |
1386 | static struct netup_card_info cinfo; | |
1387 | ||
1388 | netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo); | |
1389 | memcpy(port->frontends.adapter.proposed_mac, | |
1390 | cinfo.port[port->nr - 1].mac, 6); | |
be395157 | 1391 | printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n", |
1392 | port->nr, port->frontends.adapter.proposed_mac); | |
5a23b076 IL |
1393 | |
1394 | netup_ci_init(port); | |
1395 | break; | |
1396 | } | |
78db8547 IL |
1397 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: { |
1398 | struct altera_ci_config netup_ci_cfg = { | |
1399 | .dev = dev,/* magic number to identify*/ | |
1400 | .adapter = &port->frontends.adapter,/* for CI */ | |
1401 | .demux = &fe0->dvb.demux,/* for hw pid filter */ | |
1402 | .fpga_rw = netup_altera_fpga_rw, | |
1403 | }; | |
1404 | ||
1405 | altera_ci_init(&netup_ci_cfg, port->nr); | |
1406 | break; | |
1407 | } | |
16bfdaa4 PG |
1408 | case CX23885_BOARD_TEVII_S470: { |
1409 | u8 eeprom[256]; /* 24C02 i2c eeprom */ | |
1410 | ||
1411 | if (port->nr != 1) | |
1412 | break; | |
1413 | ||
1414 | /* Read entire EEPROM */ | |
1415 | dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1; | |
1416 | tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom)); | |
5cac1f66 | 1417 | printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0); |
16bfdaa4 PG |
1418 | memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6); |
1419 | break; | |
1420 | } | |
5a23b076 IL |
1421 | } |
1422 | ||
1423 | return ret; | |
78db8547 IL |
1424 | |
1425 | frontend_detach: | |
1426 | port->gate_ctrl = NULL; | |
1427 | videobuf_dvb_dealloc_frontends(&port->frontends); | |
1428 | return -EINVAL; | |
d19770e5 ST |
1429 | } |
1430 | ||
1431 | int cx23885_dvb_register(struct cx23885_tsport *port) | |
1432 | { | |
363c35fc ST |
1433 | |
1434 | struct videobuf_dvb_frontend *fe0; | |
d19770e5 | 1435 | struct cx23885_dev *dev = port->dev; |
eb0c58bb ST |
1436 | int err, i; |
1437 | ||
1438 | /* Here we need to allocate the correct number of frontends, | |
af901ca1 | 1439 | * as reflected in the cards struct. The reality is that currently |
eb0c58bb ST |
1440 | * no cx23885 boards support this - yet. But, if we don't modify this |
1441 | * code then the second frontend would never be allocated (later) | |
1442 | * and fail with error before the attach in dvb_register(). | |
1443 | * Without these changes we risk an OOPS later. The changes here | |
1444 | * are for safety, and should provide a good foundation for the | |
1445 | * future addition of any multi-frontend cx23885 based boards. | |
1446 | */ | |
1447 | printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__, | |
1448 | port->num_frontends); | |
d19770e5 | 1449 | |
eb0c58bb | 1450 | for (i = 1; i <= port->num_frontends; i++) { |
96b7a1a8 | 1451 | if (videobuf_dvb_alloc_frontend( |
9c8ced51 | 1452 | &port->frontends, i) == NULL) { |
eb0c58bb ST |
1453 | printk(KERN_ERR "%s() failed to alloc\n", __func__); |
1454 | return -ENOMEM; | |
1455 | } | |
1456 | ||
1457 | fe0 = videobuf_dvb_get_frontend(&port->frontends, i); | |
1458 | if (!fe0) | |
1459 | err = -EINVAL; | |
363c35fc | 1460 | |
eb0c58bb | 1461 | dprintk(1, "%s\n", __func__); |
9c8ced51 | 1462 | dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n", |
eb0c58bb ST |
1463 | dev->board, |
1464 | dev->name, | |
1465 | dev->pci_bus, | |
1466 | dev->pci_slot); | |
d19770e5 | 1467 | |
eb0c58bb | 1468 | err = -ENODEV; |
d19770e5 | 1469 | |
eb0c58bb ST |
1470 | /* dvb stuff */ |
1471 | /* We have to init the queue for each frontend on a port. */ | |
9c8ced51 ST |
1472 | printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name); |
1473 | videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops, | |
1474 | &dev->pci->dev, &port->slock, | |
44a6481d | 1475 | V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP, |
08bff03e | 1476 | sizeof(struct cx23885_buffer), port, NULL); |
eb0c58bb | 1477 | } |
d19770e5 ST |
1478 | err = dvb_register(port); |
1479 | if (err != 0) | |
9c8ced51 ST |
1480 | printk(KERN_ERR "%s() dvb_register failed err = %d\n", |
1481 | __func__, err); | |
d19770e5 | 1482 | |
d19770e5 ST |
1483 | return err; |
1484 | } | |
1485 | ||
1486 | int cx23885_dvb_unregister(struct cx23885_tsport *port) | |
1487 | { | |
363c35fc ST |
1488 | struct videobuf_dvb_frontend *fe0; |
1489 | ||
eb0c58bb ST |
1490 | /* FIXME: in an error condition where the we have |
1491 | * an expected number of frontends (attach problem) | |
1492 | * then this might not clean up correctly, if 1 | |
1493 | * is invalid. | |
1494 | * This comment only applies to future boards IF they | |
1495 | * implement MFE support. | |
1496 | */ | |
92abe9ee | 1497 | fe0 = videobuf_dvb_get_frontend(&port->frontends, 1); |
e66131ce | 1498 | if (fe0 && fe0->dvb.frontend) |
363c35fc | 1499 | videobuf_dvb_unregister_bus(&port->frontends); |
d19770e5 | 1500 | |
afd96668 HV |
1501 | switch (port->dev->board) { |
1502 | case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: | |
1503 | netup_ci_exit(port); | |
1504 | break; | |
78db8547 IL |
1505 | case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: |
1506 | altera_ci_release(port->dev, port->nr); | |
1507 | break; | |
afd96668 | 1508 | } |
5a23b076 | 1509 | |
78db8547 IL |
1510 | port->gate_ctrl = NULL; |
1511 | ||
d19770e5 ST |
1512 | return 0; |
1513 | } | |
44a6481d | 1514 |