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[media] mb86a20s: Fix TS parallel mode
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
ST		 31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
ST		 46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
5a23b076
IL		 51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
5a23b076 54#include "cimax2.h"
493b7127 55#include "lgs8gxx.h"
5a23b076
IL		 56#include "netup-eeprom.h"
57#include "netup-init.h"
a5dbf457 58#include "lgdt3305.h"
ea5697fe 59#include "atbm8830.h"
73f0af44 60#include "ts2020.h"
09ea33e5
IL		 61#include "ds3000.h"
62#include "cx23885-f300.h"
78db8547
IL		 63#include "altera-ci.h"
64#include "stv0367.h"
722c90eb
SR		 65#include "drxk.h"
66#include "mt2063.h"
f667190b
MB		 67#include "stv090x.h"
68#include "stb6100.h"
69#include "stb6100_cfg.h"
7c62f5a1
MK		 70#include "tda10071.h"
71#include "a8293.h"
d19770e5 72
4513fc69 73static unsigned int debug;
d19770e5 74
4513fc69
ST		 75#define dprintk(level, fmt, arg...)\
76 do { if (debug >= level)\
77 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
78 } while (0)
d19770e5
ST		 79
80/* ------------------------------------------------------------------ */
81
3ba71d21
MK		 82static unsigned int alt_tuner;
83module_param(alt_tuner, int, 0644);
84MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
85
78e92006
JG		 86DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
87
3ba71d21
MK		 88/* ------------------------------------------------------------------ */
89
d19770e5
ST		 90static int dvb_buf_setup(struct videobuf_queue *q,
91 unsigned int *count, unsigned int *size)
92{
93 struct cx23885_tsport *port = q->priv_data;
94
95 port->ts_packet_size = 188 * 4;
96 port->ts_packet_count = 32;
97
98 *size = port->ts_packet_size * port->ts_packet_count;
99 *count = 32;
100 return 0;
101}
102
44a6481d
MK		 103static int dvb_buf_prepare(struct videobuf_queue *q,
104 struct videobuf_buffer *vb, enum v4l2_field field)
d19770e5
ST		 105{
106 struct cx23885_tsport *port = q->priv_data;
9c8ced51 107 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
d19770e5
ST		 108}
109
110static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
111{
112 struct cx23885_tsport *port = q->priv_data;
9c8ced51 113 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
d19770e5
ST		 114}
115
44a6481d
MK		 116static void dvb_buf_release(struct videobuf_queue *q,
117 struct videobuf_buffer *vb)
d19770e5 118{
9c8ced51 119 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
d19770e5
ST		 120}
121
78db8547
IL		 122static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
123{
124 struct videobuf_dvb_frontends *f;
125 struct videobuf_dvb_frontend *fe;
126
127 f = &port->frontends;
128
129 if (f->gate <= 1) /* undefined or fe0 */
130 fe = videobuf_dvb_get_frontend(f, 1);
131 else
132 fe = videobuf_dvb_get_frontend(f, f->gate);
133
134 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
135 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
136}
137
d19770e5
ST		 138static struct videobuf_queue_ops dvb_qops = {
139 .buf_setup = dvb_buf_setup,
140 .buf_prepare = dvb_buf_prepare,
141 .buf_queue = dvb_buf_queue,
142 .buf_release = dvb_buf_release,
143};
144
86184e06 145static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST		 146 .demod_address = 0x32 >> 1,
147 .output_mode = S5H1409_SERIAL_OUTPUT,
148 .gpio = S5H1409_GPIO_ON,
2b03238a 149 .qam_if = 44000,
fc959bef 150 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 151 .status_mode = S5H1409_DEMODLOCKING,
152 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
fc959bef
ST		 153};
154
b3ea0166
ST		 155static struct tda10048_config hauppauge_hvr1200_config = {
156 .demod_address = 0x10 >> 1,
157 .output_mode = TDA10048_SERIAL_OUTPUT,
158 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 159 .inversion = TDA10048_INVERSION_ON,
8816bef5
ST		 160 .dtv6_if_freq_khz = TDA10048_IF_3300,
161 .dtv7_if_freq_khz = TDA10048_IF_3800,
162 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 163 .clk_freq_khz = TDA10048_CLK_16000,
b3ea0166
ST		 164};
165
6b926eca
MK		 166static struct tda10048_config hauppauge_hvr1210_config = {
167 .demod_address = 0x10 >> 1,
168 .output_mode = TDA10048_SERIAL_OUTPUT,
169 .fwbulkwritelen = TDA10048_BULKWRITE_200,
170 .inversion = TDA10048_INVERSION_ON,
c27586e4
MK		 171 .dtv6_if_freq_khz = TDA10048_IF_3300,
172 .dtv7_if_freq_khz = TDA10048_IF_3500,
173 .dtv8_if_freq_khz = TDA10048_IF_4000,
6b926eca
MK		 174 .clk_freq_khz = TDA10048_CLK_16000,
175};
176
3ba71d21
MK		 177static struct s5h1409_config hauppauge_ezqam_config = {
178 .demod_address = 0x32 >> 1,
179 .output_mode = S5H1409_SERIAL_OUTPUT,
180 .gpio = S5H1409_GPIO_OFF,
181 .qam_if = 4000,
182 .inversion = S5H1409_INVERSION_ON,
dfc1c08a
ST		 183 .status_mode = S5H1409_DEMODLOCKING,
184 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
3ba71d21
MK		 185};
186
fc959bef 187static struct s5h1409_config hauppauge_hvr1800lp_config = {
d19770e5
ST		 188 .demod_address = 0x32 >> 1,
189 .output_mode = S5H1409_SERIAL_OUTPUT,
190 .gpio = S5H1409_GPIO_OFF,
2b03238a 191 .qam_if = 44000,
fe475163 192 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 193 .status_mode = S5H1409_DEMODLOCKING,
194 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d19770e5
ST		 195};
196
07b4a835
MK		 197static struct s5h1409_config hauppauge_hvr1500_config = {
198 .demod_address = 0x32 >> 1,
199 .output_mode = S5H1409_SERIAL_OUTPUT,
200 .gpio = S5H1409_GPIO_OFF,
201 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 202 .status_mode = S5H1409_DEMODLOCKING,
203 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
07b4a835
MK		 204};
205
86184e06 206static struct mt2131_config hauppauge_generic_tunerconfig = {
a77743bc
ST		 207 0x61
208};
209
9bc37caa
MK		 210static struct lgdt330x_config fusionhdtv_5_express = {
211 .demod_address = 0x0e,
212 .demod_chip = LGDT3303,
213 .serial_mpeg = 0x40,
214};
215
d1987d55
ST		 216static struct s5h1409_config hauppauge_hvr1500q_config = {
217 .demod_address = 0x32 >> 1,
218 .output_mode = S5H1409_SERIAL_OUTPUT,
219 .gpio = S5H1409_GPIO_ON,
220 .qam_if = 44000,
221 .inversion = S5H1409_INVERSION_OFF,
dfc1c08a
ST		 222 .status_mode = S5H1409_DEMODLOCKING,
223 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
d1987d55
ST		 224};
225
335377b7
MK		 226static struct s5h1409_config dvico_s5h1409_config = {
227 .demod_address = 0x32 >> 1,
228 .output_mode = S5H1409_SERIAL_OUTPUT,
229 .gpio = S5H1409_GPIO_ON,
230 .qam_if = 44000,
231 .inversion = S5H1409_INVERSION_OFF,
232 .status_mode = S5H1409_DEMODLOCKING,
233 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
234};
235
52b50450
MK		 236static struct s5h1411_config dvico_s5h1411_config = {
237 .output_mode = S5H1411_SERIAL_OUTPUT,
238 .gpio = S5H1411_GPIO_ON,
239 .qam_if = S5H1411_IF_44000,
240 .vsb_if = S5H1411_IF_44000,
241 .inversion = S5H1411_INVERSION_OFF,
242 .status_mode = S5H1411_DEMODLOCKING,
243 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
244};
245
19bc5796
MK		 246static struct s5h1411_config hcw_s5h1411_config = {
247 .output_mode = S5H1411_SERIAL_OUTPUT,
248 .gpio = S5H1411_GPIO_OFF,
249 .vsb_if = S5H1411_IF_44000,
250 .qam_if = S5H1411_IF_4000,
251 .inversion = S5H1411_INVERSION_ON,
252 .status_mode = S5H1411_DEMODLOCKING,
253 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
254};
255
d1987d55 256static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
e12671cf
ST		 257 .i2c_address = 0x61,
258 .if_khz = 5380,
d1987d55
ST		 259};
260
335377b7
MK		 261static struct xc5000_config dvico_xc5000_tunerconfig = {
262 .i2c_address = 0x64,
263 .if_khz = 5380,
335377b7
MK		 264};
265
4041f1a5
MK		 266static struct tda829x_config tda829x_no_probe = {
267 .probe_tuner = TDA829X_DONT_PROBE,
268};
269
f21e0d7f 270static struct tda18271_std_map hauppauge_tda18271_std_map = {
c0dc0c11
MK		 271 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
272 .if_lvl = 6, .rfagc_top = 0x37 },
273 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
274 .if_lvl = 6, .rfagc_top = 0x37 },
f21e0d7f
MK		 275};
276
b34cdc36
MK		 277static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
278 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
279 .if_lvl = 1, .rfagc_top = 0x37, },
280 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
281 .if_lvl = 1, .rfagc_top = 0x37, },
282 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
283 .if_lvl = 1, .rfagc_top = 0x37, },
284};
285
f21e0d7f
MK		 286static struct tda18271_config hauppauge_tda18271_config = {
287 .std_map = &hauppauge_tda18271_std_map,
288 .gate = TDA18271_GATE_ANALOG,
04a68baa 289 .output_opt = TDA18271_OUTPUT_LT_OFF,
f21e0d7f
MK		 290};
291
b3ea0166 292static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 293 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 294 .gate = TDA18271_GATE_ANALOG,
04a68baa 295 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST		 296};
297
6b926eca
MK		 298static struct tda18271_config hauppauge_hvr1210_tuner_config = {
299 .gate = TDA18271_GATE_DIGITAL,
04a68baa 300 .output_opt = TDA18271_OUTPUT_LT_OFF,
6b926eca
MK		 301};
302
247bc540 303static struct tda18271_std_map hauppauge_hvr127x_std_map = {
a5dbf457
MK		 304 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
305 .if_lvl = 1, .rfagc_top = 0x58 },
306 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
307 .if_lvl = 1, .rfagc_top = 0x58 },
308};
309
247bc540
MK		 310static struct tda18271_config hauppauge_hvr127x_config = {
311 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 312 .output_opt = TDA18271_OUTPUT_LT_OFF,
a5dbf457
MK		 313};
314
247bc540 315static struct lgdt3305_config hauppauge_lgdt3305_config = {
a5dbf457
MK		 316 .i2c_addr = 0x0e,
317 .mpeg_mode = LGDT3305_MPEG_SERIAL,
318 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
319 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
320 .deny_i2c_rptr = 1,
321 .spectral_inversion = 1,
322 .qam_if_khz = 4000,
323 .vsb_if_khz = 3250,
324};
325
b1721d0d 326static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST		 327 BAND_VHF | BAND_UHF, /* band_caps */
328
329 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
330 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
331 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
332 * P_agc_nb_est=2, P_agc_write=0
333 */
334 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
335 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
336
337 712, /* inv_gain */
338 21, /* time_stabiliz */
339
340 0, /* alpha_level */
341 118, /* thlock */
342
343 0, /* wbd_inv */
344 2867, /* wbd_ref */
345 0, /* wbd_sel */
346 2, /* wbd_alpha */
347
348 0, /* agc1_max */
349 0, /* agc1_min */
350 39718, /* agc2_max */
351 9930, /* agc2_min */
352 0, /* agc1_pt1 */
353 0, /* agc1_pt2 */
354 0, /* agc1_pt3 */
355 0, /* agc1_slope1 */
356 0, /* agc1_slope2 */
357 0, /* agc2_pt1 */
358 128, /* agc2_pt2 */
359 29, /* agc2_slope1 */
360 29, /* agc2_slope2 */
361
362 17, /* alpha_mant */
363 27, /* alpha_exp */
364 23, /* beta_mant */
365 51, /* beta_exp */
366
367 1, /* perform_agc_softsplit */
368};
369
370/* PLL Configuration for COFDM BW_MHz = 8.000000
371 * With external clock = 30.000000 */
b1721d0d 372static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST		 373 60000, /* internal */
374 30000, /* sampling */
375 1, /* pll_cfg: prediv */
376 8, /* pll_cfg: ratio */
377 3, /* pll_cfg: range */
378 1, /* pll_cfg: reset */
379 0, /* pll_cfg: bypass */
380 0, /* misc: refdiv */
381 0, /* misc: bypclk_div */
382 1, /* misc: IO_CLK_en_core */
383 1, /* misc: ADClkSrc */
384 0, /* misc: modulo */
385 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
386 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
387 20452225, /* timf */
388 30000000 /* xtal_hz */
389};
390
391static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
392 .output_mpeg2_in_188_bytes = 1,
393 .hostbus_diversity = 1,
394 .tuner_is_baseband = 0,
395 .update_lna = NULL,
396
397 .agc_config_count = 1,
398 .agc = &xc3028_agc_config,
399 .bw = &xc3028_bw_config,
400
401 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
402 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
403 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
404
405 .pwm_freq_div = 0,
406 .agc_control = NULL,
407 .spur_protect = 0,
408
409 .output_mode = OUTMODE_MPEG2_SERIAL,
410};
411
aef2d186
ST		 412static struct zl10353_config dvico_fusionhdtv_xc3028 = {
413 .demod_address = 0x0f,
414 .if2 = 45600,
415 .no_tuner = 1,
d4dc673d 416 .disable_i2c_gate_ctrl = 1,
aef2d186
ST		 417};
418
f867c3f4
IL		 419static struct stv0900_reg stv0900_ts_regs[] = {
420 { R0900_TSGENERAL, 0x00 },
421 { R0900_P1_TSSPEED, 0x40 },
422 { R0900_P2_TSSPEED, 0x40 },
423 { R0900_P1_TSCFGM, 0xc0 },
424 { R0900_P2_TSCFGM, 0xc0 },
425 { R0900_P1_TSCFGH, 0xe0 },
426 { R0900_P2_TSCFGH, 0xe0 },
427 { R0900_P1_TSCFGL, 0x20 },
428 { R0900_P2_TSCFGL, 0x20 },
429 { 0xffff, 0xff }, /* terminate */
430};
431
5a23b076
IL		 432static struct stv0900_config netup_stv0900_config = {
433 .demod_address = 0x68,
29372a8d 434 .demod_mode = 1, /* dual */
644c7ef0 435 .xtal = 8000000,
5a23b076
IL		 436 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
437 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 438 .ts_config_regs = stv0900_ts_regs,
5a23b076
IL		 439 .tun1_maddress = 0,/* 0x60 */
440 .tun2_maddress = 3,/* 0x63 */
441 .tun1_adc = 1,/* 1 Vpp */
442 .tun2_adc = 1,/* 1 Vpp */
443};
444
445static struct stv6110_config netup_stv6110_tunerconfig_a = {
446 .i2c_address = 0x60,
644c7ef0
AO		 447 .mclk = 16000000,
448 .clk_div = 1,
873688cd 449 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 450};
451
452static struct stv6110_config netup_stv6110_tunerconfig_b = {
453 .i2c_address = 0x63,
644c7ef0
AO		 454 .mclk = 16000000,
455 .clk_div = 1,
873688cd 456 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL		 457};
458
96318d0c 459static struct cx24116_config tbs_cx24116_config = {
09ea33e5 460 .demod_address = 0x55,
96318d0c
IL		 461};
462
09ea33e5
IL		 463static struct ds3000_config tevii_ds3000_config = {
464 .demod_address = 0x68,
579943f5
IL		 465};
466
73f0af44
KD		 467static struct ts2020_config tevii_ts2020_config = {
468 .tuner_address = 0x60,
b858c331 469 .clk_out_div = 1,
73f0af44
KD		 470};
471
c9b8b04b
IL		 472static struct cx24116_config dvbworld_cx24116_config = {
473 .demod_address = 0x05,
474};
475
493b7127
DW		 476static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
477 .prod = LGS8GXX_PROD_LGS8GL5,
478 .demod_address = 0x19,
479 .serial_ts = 0,
480 .ts_clk_pol = 1,
481 .ts_clk_gated = 1,
482 .if_clk_freq = 30400, /* 30.4 MHz */
483 .if_freq = 5380, /* 5.38 MHz */
484 .if_neg_center = 1,
485 .ext_adc = 0,
486 .adc_signed = 0,
487 .if_neg_edge = 0,
488};
489
490static struct xc5000_config mygica_x8506_xc5000_config = {
491 .i2c_address = 0x61,
492 .if_khz = 5380,
493};
494
f667190b 495static struct stv090x_config prof_8000_stv090x_config = {
b858c331
IL		 496 .device = STV0903,
497 .demod_mode = STV090x_SINGLE,
498 .clk_mode = STV090x_CLK_EXT,
499 .xtal = 27000000,
500 .address = 0x6A,
501 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
502 .repeater_level = STV090x_RPTLEVEL_64,
503 .adc1_range = STV090x_ADC_2Vpp,
504 .diseqc_envelope_mode = false,
505
506 .tuner_get_frequency = stb6100_get_frequency,
507 .tuner_set_frequency = stb6100_set_frequency,
508 .tuner_set_bandwidth = stb6100_set_bandwidth,
509 .tuner_get_bandwidth = stb6100_get_bandwidth,
f667190b
MB		 510};
511
512static struct stb6100_config prof_8000_stb6100_config = {
513 .tuner_address = 0x60,
514 .refclock = 27000000,
515};
516
517static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
518{
519 struct cx23885_tsport *port = fe->dvb->priv;
520 struct cx23885_dev *dev = port->dev;
521
522 if (voltage == SEC_VOLTAGE_18)
523 cx_write(MC417_RWD, 0x00001e00);
524 else if (voltage == SEC_VOLTAGE_13)
525 cx_write(MC417_RWD, 0x00001a00);
526 else
527 cx_write(MC417_RWD, 0x00001800);
528 return 0;
529}
530
a7d44baa 531static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 532{
a7d44baa 533 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK		 534 struct cx23885_tsport *port = fe->dvb->priv;
535 struct cx23885_dev *dev = port->dev;
536
537 switch (dev->board) {
538 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 539 switch (p->modulation) {
f35b9e80
MK		 540 case VSB_8:
541 cx23885_gpio_clear(dev, GPIO_5);
542 break;
543 case QAM_64:
544 case QAM_256:
545 default:
546 cx23885_gpio_set(dev, GPIO_5);
547 break;
548 }
549 break;
6f0d8c02
DW		 550 case CX23885_BOARD_MYGICA_X8506:
551 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
552 /* Select Digital TV */
553 cx23885_gpio_set(dev, GPIO_0);
554 break;
f35b9e80 555 }
15472faf
MCC		 556
557 /* Call the real set_frontend */
558 if (port->set_frontend)
559 return port->set_frontend(fe);
560
5bdd3962 561 return 0;
f35b9e80
MK		 562}
563
15472faf
MCC		 564static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
565 struct dvb_frontend *fe)
566{
567 port->set_frontend = fe->ops.set_frontend;
568 fe->ops.set_frontend = cx23885_dvb_set_frontend;
569}
570
2365b2d3
DW		 571static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
572 .prod = LGS8GXX_PROD_LGS8G75,
573 .demod_address = 0x19,
574 .serial_ts = 0,
575 .ts_clk_pol = 1,
576 .ts_clk_gated = 1,
577 .if_clk_freq = 30400, /* 30.4 MHz */
578 .if_freq = 6500, /* 6.50 MHz */
579 .if_neg_center = 1,
580 .ext_adc = 0,
581 .adc_signed = 1,
582 .adc_vpp = 2, /* 1.6 Vpp */
583 .if_neg_edge = 1,
584};
585
586static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
587 .i2c_address = 0x61,
588 .if_khz = 6500,
589};
590
ea5697fe
DW		 591static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
592 .prod = ATBM8830_PROD_8830,
593 .demod_address = 0x44,
594 .serial_ts = 0,
595 .ts_sampling_edge = 1,
596 .ts_clk_gated = 0,
597 .osc_clk_freq = 30400, /* in kHz */
598 .if_freq = 0, /* zero IF */
599 .zif_swap_iq = 1,
c245c75c
DW		 600 .agc_min = 0x2E,
601 .agc_max = 0xFF,
602 .agc_hold_loop = 0,
ea5697fe
DW		 603};
604
605static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
606 .i2c_address = 0x60,
607 .osc_clk = 20
608};
609
610static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
611 .prod = ATBM8830_PROD_8830,
612 .demod_address = 0x44,
613 .serial_ts = 1,
614 .ts_sampling_edge = 1,
615 .ts_clk_gated = 0,
616 .osc_clk_freq = 30400, /* in kHz */
617 .if_freq = 0, /* zero IF */
618 .zif_swap_iq = 1,
c245c75c
DW		 619 .agc_min = 0x2E,
620 .agc_max = 0xFF,
621 .agc_hold_loop = 0,
ea5697fe
DW		 622};
623
624static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
625 .i2c_address = 0x60,
626 .osc_clk = 20
627};
78db8547
IL		 628static struct stv0367_config netup_stv0367_config[] = {
629 {
630 .demod_address = 0x1c,
631 .xtal = 27000000,
632 .if_khz = 4500,
633 .if_iq_mode = 0,
634 .ts_mode = 1,
635 .clk_pol = 0,
636 }, {
637 .demod_address = 0x1d,
638 .xtal = 27000000,
639 .if_khz = 4500,
640 .if_iq_mode = 0,
641 .ts_mode = 1,
642 .clk_pol = 0,
643 },
644};
645
646static struct xc5000_config netup_xc5000_config[] = {
647 {
648 .i2c_address = 0x61,
649 .if_khz = 4500,
650 }, {
651 .i2c_address = 0x64,
652 .if_khz = 4500,
653 },
654};
655
722c90eb
SR		 656static struct drxk_config terratec_drxk_config[] = {
657 {
658 .adr = 0x29,
659 .no_i2c_bridge = 1,
660 }, {
661 .adr = 0x2a,
662 .no_i2c_bridge = 1,
663 },
664};
665
666static struct mt2063_config terratec_mt2063_config[] = {
667 {
668 .tuner_address = 0x60,
669 }, {
670 .tuner_address = 0x67,
671 },
672};
673
7c62f5a1 674static const struct tda10071_config hauppauge_tda10071_config = {
41f55d57 675 .demod_i2c_addr = 0x05,
7c62f5a1
MK		 676 .tuner_i2c_addr = 0x54,
677 .i2c_wr_max = 64,
678 .ts_mode = TDA10071_TS_SERIAL,
679 .spec_inv = 0,
680 .xtal = 40444000, /* 40.444 MHz */
681 .pll_multiplier = 20,
682};
683
684static const struct a8293_config hauppauge_a8293_config = {
685 .i2c_addr = 0x0b,
686};
687
ada73eee 688static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
78db8547
IL		 689{
690 struct cx23885_dev *dev = (struct cx23885_dev *)device;
691 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 692 uint32_t mem = 0;
78db8547 693
d164460f 694 mem = cx_read(MC417_RWD);
78db8547
IL		 695 if (read)
696 cx_set(MC417_OEN, ALT_DATA);
697 else {
698 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL		 699 mem &= ~ALT_DATA;
700 mem |= (data & ALT_DATA);
78db8547
IL		 701 }
702
703 if (flag)
d164460f 704 mem |= ALT_AD_RG;
78db8547 705 else
d164460f 706 mem &= ~ALT_AD_RG;
78db8547 707
d164460f 708 mem &= ~ALT_CS;
78db8547 709 if (read)
d164460f 710 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 711 else
d164460f
AO		 712 mem = (mem & ~ALT_WR) | ALT_RD;
713
714 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL		 715
716 for (;;) {
717 mem = cx_read(MC417_RWD);
718 if ((mem & ALT_RDY) == 0)
719 break;
720 if (time_after(jiffies, timeout))
721 break;
722 udelay(1);
723 }
724
725 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
726 if (read)
727 return mem & ALT_DATA;
728
729 return 0;
730};
ea5697fe 731
d19770e5
ST		 732static int dvb_register(struct cx23885_tsport *port)
733{
734 struct cx23885_dev *dev = port->dev;
493b7127 735 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL		 736 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
737 int mfe_shared = 0; /* bus not shared by default */
5a23b076 738 int ret;
363c35fc 739
f972e0bd 740 /* Get the first frontend */
92abe9ee 741 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST		 742 if (!fe0)
743 return -EINVAL;
d19770e5
ST		 744
745 /* init struct videobuf_dvb */
363c35fc 746 fe0->dvb.name = dev->name;
d19770e5 747
78db8547
IL		 748 /* multi-frontend gate control is undefined or defaults to fe0 */
749 port->frontends.gate = 0;
750
751 /* Sets the gate control callback to be used by i2c command calls */
752 port->gate_ctrl = cx23885_dvb_gate_ctrl;
753
d19770e5
ST		 754 /* init frontend */
755 switch (dev->board) {
a77743bc 756 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 757 i2c_bus = &dev->i2c_bus[0];
363c35fc 758 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 759 &hauppauge_generic_config,
f139fa71 760 &i2c_bus->i2c_adap);
363c35fc
ST		 761 if (fe0->dvb.frontend != NULL) {
762 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 763 &i2c_bus->i2c_adap,
86184e06 764 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST		 765 }
766 break;
a5dbf457 767 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 768 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK		 769 i2c_bus = &dev->i2c_bus[0];
770 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 771 &hauppauge_lgdt3305_config,
a5dbf457
MK		 772 &i2c_bus->i2c_adap);
773 if (fe0->dvb.frontend != NULL) {
774 dvb_attach(tda18271_attach, fe0->dvb.frontend,
775 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 776 &hauppauge_hvr127x_config);
a5dbf457 777 }
15472faf
MCC		 778 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
779 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
a5dbf457 780 break;
19bc5796 781 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 782 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK		 783 i2c_bus = &dev->i2c_bus[0];
784 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
785 &hcw_s5h1411_config,
786 &i2c_bus->i2c_adap);
787 if (fe0->dvb.frontend != NULL) {
788 dvb_attach(tda18271_attach, fe0->dvb.frontend,
789 0x60, &dev->i2c_bus[1].i2c_adap,
790 &hauppauge_tda18271_config);
791 }
0ac60acb
DH		 792
793 tda18271_attach(&dev->ts1.analog_fe,
794 0x60, &dev->i2c_bus[1].i2c_adap,
795 &hauppauge_tda18271_config);
796
19bc5796 797 break;
3ba71d21
MK		 798 case CX23885_BOARD_HAUPPAUGE_HVR1800:
799 i2c_bus = &dev->i2c_bus[0];
92abe9ee 800 switch (alt_tuner) {
3ba71d21 801 case 1:
363c35fc 802 fe0->dvb.frontend =
3ba71d21
MK		 803 dvb_attach(s5h1409_attach,
804 &hauppauge_ezqam_config,
805 &i2c_bus->i2c_adap);
363c35fc
ST		 806 if (fe0->dvb.frontend != NULL) {
807 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 808 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 809 &tda829x_no_probe);
363c35fc 810 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 811 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 812 &hauppauge_tda18271_config);
3ba71d21
MK		 813 }
814 break;
815 case 0:
816 default:
363c35fc 817 fe0->dvb.frontend =
3ba71d21
MK		 818 dvb_attach(s5h1409_attach,
819 &hauppauge_generic_config,
820 &i2c_bus->i2c_adap);
363c35fc
ST		 821 if (fe0->dvb.frontend != NULL)
822 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK		 823 &i2c_bus->i2c_adap,
824 &hauppauge_generic_tunerconfig, 0);
825 break;
826 }
827 break;
fc959bef 828 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 829 i2c_bus = &dev->i2c_bus[0];
363c35fc 830 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 831 &hauppauge_hvr1800lp_config,
f139fa71 832 &i2c_bus->i2c_adap);
363c35fc
ST		 833 if (fe0->dvb.frontend != NULL) {
834 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 835 &i2c_bus->i2c_adap,
fc959bef
ST		 836 &hauppauge_generic_tunerconfig, 0);
837 }
838 break;
9bc37caa 839 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 840 i2c_bus = &dev->i2c_bus[0];
363c35fc 841 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 842 &fusionhdtv_5_express,
f139fa71 843 &i2c_bus->i2c_adap);
363c35fc
ST		 844 if (fe0->dvb.frontend != NULL) {
845 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK		 846 &i2c_bus->i2c_adap, 0x61,
847 TUNER_LG_TDVS_H06XF);
9bc37caa
MK		 848 }
849 break;
d1987d55
ST		 850 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
851 i2c_bus = &dev->i2c_bus[1];
363c35fc 852 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST		 853 &hauppauge_hvr1500q_config,
854 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST		 855 if (fe0->dvb.frontend != NULL)
856 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 857 &i2c_bus->i2c_adap,
858 &hauppauge_hvr1500q_tunerconfig);
d1987d55 859 break;
07b4a835
MK		 860 case CX23885_BOARD_HAUPPAUGE_HVR1500:
861 i2c_bus = &dev->i2c_bus[1];
363c35fc 862 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK		 863 &hauppauge_hvr1500_config,
864 &dev->i2c_bus[0].i2c_adap);
363c35fc 865 if (fe0->dvb.frontend != NULL) {
07b4a835
MK		 866 struct dvb_frontend *fe;
867 struct xc2028_config cfg = {
868 .i2c_adap = &i2c_bus->i2c_adap,
869 .i2c_addr = 0x61,
07b4a835
MK		 870 };
871 static struct xc2028_ctrl ctl = {
ef80bfeb 872 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 873 .max_len = 64,
52c3d29c 874 .demod = XC3028_FE_OREN538,
07b4a835
MK		 875 };
876
877 fe = dvb_attach(xc2028_attach,
363c35fc 878 fe0->dvb.frontend, &cfg);
07b4a835
MK		 879 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
880 fe->ops.tuner_ops.set_config(fe, &ctl);
881 }
882 break;
b3ea0166 883 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 884 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 885 i2c_bus = &dev->i2c_bus[0];
363c35fc 886 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST		 887 &hauppauge_hvr1200_config,
888 &i2c_bus->i2c_adap);
363c35fc
ST		 889 if (fe0->dvb.frontend != NULL) {
890 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST		 891 &dev->i2c_bus[1].i2c_adap, 0x42,
892 &tda829x_no_probe);
363c35fc 893 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST		 894 0x60, &dev->i2c_bus[1].i2c_adap,
895 &hauppauge_hvr1200_tuner_config);
6b926eca
MK		 896 }
897 break;
898 case CX23885_BOARD_HAUPPAUGE_HVR1210:
899 i2c_bus = &dev->i2c_bus[0];
900 fe0->dvb.frontend = dvb_attach(tda10048_attach,
901 &hauppauge_hvr1210_config,
902 &i2c_bus->i2c_adap);
903 if (fe0->dvb.frontend != NULL) {
904 dvb_attach(tda18271_attach, fe0->dvb.frontend,
905 0x60, &dev->i2c_bus[1].i2c_adap,
906 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST		 907 }
908 break;
66762373
ST		 909 case CX23885_BOARD_HAUPPAUGE_HVR1400:
910 i2c_bus = &dev->i2c_bus[0];
363c35fc 911 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST		 912 &i2c_bus->i2c_adap,
913 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 914 if (fe0->dvb.frontend != NULL) {
66762373
ST		 915 struct dvb_frontend *fe;
916 struct xc2028_config cfg = {
917 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
918 .i2c_addr = 0x64,
66762373
ST		 919 };
920 static struct xc2028_ctrl ctl = {
ef80bfeb 921 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 922 .max_len = 64,
9bed77ee 923 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST		 924 /* This is true for all demods with
925 v36 firmware? */
0975fc68 926 .type = XC2028_D2633,
66762373
ST		 927 };
928
929 fe = dvb_attach(xc2028_attach,
363c35fc 930 fe0->dvb.frontend, &cfg);
66762373
ST		 931 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
932 fe->ops.tuner_ops.set_config(fe, &ctl);
933 }
934 break;
335377b7
MK		 935 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
936 i2c_bus = &dev->i2c_bus[port->nr - 1];
937
363c35fc 938 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK		 939 &dvico_s5h1409_config,
940 &i2c_bus->i2c_adap);
363c35fc
ST		 941 if (fe0->dvb.frontend == NULL)
942 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK		 943 &dvico_s5h1411_config,
944 &i2c_bus->i2c_adap);
363c35fc
ST		 945 if (fe0->dvb.frontend != NULL)
946 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK		 947 &i2c_bus->i2c_adap,
948 &dvico_xc5000_tunerconfig);
335377b7 949 break;
aef2d186
ST		 950 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
951 i2c_bus = &dev->i2c_bus[port->nr - 1];
952
363c35fc 953 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST		 954 &dvico_fusionhdtv_xc3028,
955 &i2c_bus->i2c_adap);
363c35fc 956 if (fe0->dvb.frontend != NULL) {
aef2d186
ST		 957 struct dvb_frontend *fe;
958 struct xc2028_config cfg = {
959 .i2c_adap = &i2c_bus->i2c_adap,
960 .i2c_addr = 0x61,
aef2d186
ST		 961 };
962 static struct xc2028_ctrl ctl = {
ef80bfeb 963 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST		 964 .max_len = 64,
965 .demod = XC3028_FE_ZARLINK456,
966 };
967
363c35fc 968 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST		 969 &cfg);
970 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
971 fe->ops.tuner_ops.set_config(fe, &ctl);
972 }
973 break;
974 }
4c56b04a 975 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 976 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 977 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST		 978 i2c_bus = &dev->i2c_bus[0];
979
363c35fc 980 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST		 981 &dvico_fusionhdtv_xc3028,
982 &i2c_bus->i2c_adap);
363c35fc 983 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST		 984 struct dvb_frontend *fe;
985 struct xc2028_config cfg = {
986 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
987 .i2c_addr = 0x61,
4c56b04a
ST		 988 };
989 static struct xc2028_ctrl ctl = {
ef80bfeb 990 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST		 991 .max_len = 64,
992 .demod = XC3028_FE_ZARLINK456,
993 };
994
363c35fc 995 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST		 996 &cfg);
997 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
998 fe->ops.tuner_ops.set_config(fe, &ctl);
999 }
96318d0c 1000 break;
0cf8af57 1001 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1002 i2c_bus = &dev->i2c_bus[0];
1003
1004 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1005 &dvico_fusionhdtv_xc3028,
1006 &i2c_bus->i2c_adap);
1007 if (fe0->dvb.frontend != NULL) {
1008 struct dvb_frontend *fe;
1009 struct xc4000_config cfg = {
1010 .i2c_address = 0x61,
1011 .default_pm = 0,
1012 .dvb_amplitude = 134,
1013 .set_smoothedcvbs = 1,
1014 .if_khz = 4560
1015 };
1016
1017 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1018 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS		 1019 if (!fe) {
1020 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1021 dev->name);
1022 goto frontend_detach;
1023 }
0cf8af57 1024 }
1025 break;
96318d0c 1026 case CX23885_BOARD_TBS_6920:
09ea33e5 1027 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL		 1028
1029 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL		 1030 &tbs_cx24116_config,
1031 &i2c_bus->i2c_adap);
96318d0c 1032 if (fe0->dvb.frontend != NULL)
09ea33e5 1033 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1034
579943f5
IL		 1035 break;
1036 case CX23885_BOARD_TEVII_S470:
1037 i2c_bus = &dev->i2c_bus[1];
1038
09ea33e5
IL		 1039 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1040 &tevii_ds3000_config,
1041 &i2c_bus->i2c_adap);
73f0af44
KD		 1042 if (fe0->dvb.frontend != NULL) {
1043 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1044 &tevii_ts2020_config, &i2c_bus->i2c_adap);
09ea33e5 1045 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
73f0af44 1046 }
579943f5 1047
4c56b04a 1048 break;
c9b8b04b
IL		 1049 case CX23885_BOARD_DVBWORLD_2005:
1050 i2c_bus = &dev->i2c_bus[1];
1051
1052 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1053 &dvbworld_cx24116_config,
1054 &i2c_bus->i2c_adap);
1055 break;
5a23b076
IL		 1056 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1057 i2c_bus = &dev->i2c_bus[0];
1058 switch (port->nr) {
1059 /* port B */
1060 case 1:
1061 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1062 &netup_stv0900_config,
1063 &i2c_bus->i2c_adap, 0);
1064 if (fe0->dvb.frontend != NULL) {
1065 if (dvb_attach(stv6110_attach,
1066 fe0->dvb.frontend,
1067 &netup_stv6110_tunerconfig_a,
1068 &i2c_bus->i2c_adap)) {
1069 if (!dvb_attach(lnbh24_attach,
1070 fe0->dvb.frontend,
1071 &i2c_bus->i2c_adap,
9329fb5b
AO		 1072 LNBH24_PCL | LNBH24_TTX,
1073 LNBH24_TEN, 0x09))
5a23b076
IL		 1074 printk(KERN_ERR
1075 "No LNBH24 found!\n");
1076
1077 }
1078 }
1079 break;
1080 /* port C */
1081 case 2:
1082 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1083 &netup_stv0900_config,
1084 &i2c_bus->i2c_adap, 1);
1085 if (fe0->dvb.frontend != NULL) {
1086 if (dvb_attach(stv6110_attach,
1087 fe0->dvb.frontend,
1088 &netup_stv6110_tunerconfig_b,
1089 &i2c_bus->i2c_adap)) {
1090 if (!dvb_attach(lnbh24_attach,
1091 fe0->dvb.frontend,
1092 &i2c_bus->i2c_adap,
9329fb5b
AO		 1093 LNBH24_PCL | LNBH24_TTX,
1094 LNBH24_TEN, 0x0a))
5a23b076
IL		 1095 printk(KERN_ERR
1096 "No LNBH24 found!\n");
1097
1098 }
1099 }
1100 break;
1101 }
1102 break;
493b7127
DW		 1103 case CX23885_BOARD_MYGICA_X8506:
1104 i2c_bus = &dev->i2c_bus[0];
1105 i2c_bus2 = &dev->i2c_bus[1];
1106 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1107 &mygica_x8506_lgs8gl5_config,
1108 &i2c_bus->i2c_adap);
1109 if (fe0->dvb.frontend != NULL) {
1110 dvb_attach(xc5000_attach,
1111 fe0->dvb.frontend,
1112 &i2c_bus2->i2c_adap,
1113 &mygica_x8506_xc5000_config);
1114 }
15472faf 1115 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
493b7127 1116 break;
2365b2d3
DW		 1117 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1118 i2c_bus = &dev->i2c_bus[0];
1119 i2c_bus2 = &dev->i2c_bus[1];
1120 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1121 &magicpro_prohdtve2_lgs8g75_config,
1122 &i2c_bus->i2c_adap);
1123 if (fe0->dvb.frontend != NULL) {
1124 dvb_attach(xc5000_attach,
1125 fe0->dvb.frontend,
1126 &i2c_bus2->i2c_adap,
1127 &magicpro_prohdtve2_xc5000_config);
1128 }
15472faf 1129 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
2365b2d3 1130 break;
13697380 1131 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST		 1132 i2c_bus = &dev->i2c_bus[0];
1133 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1134 &hcw_s5h1411_config,
1135 &i2c_bus->i2c_adap);
1136 if (fe0->dvb.frontend != NULL)
1137 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1138 0x60, &dev->i2c_bus[0].i2c_adap,
1139 &hauppauge_tda18271_config);
1140
1141 tda18271_attach(&dev->ts1.analog_fe,
1142 0x60, &dev->i2c_bus[1].i2c_adap,
1143 &hauppauge_tda18271_config);
1144
1145 break;
aee0b24c 1146 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST		 1147 i2c_bus = &dev->i2c_bus[0];
1148 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1149 &hcw_s5h1411_config,
1150 &i2c_bus->i2c_adap);
1151 if (fe0->dvb.frontend != NULL)
1152 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1153 0x60, &dev->i2c_bus[0].i2c_adap,
1154 &hauppauge_tda18271_config);
1155 break;
ea5697fe
DW		 1156 case CX23885_BOARD_MYGICA_X8558PRO:
1157 switch (port->nr) {
1158 /* port B */
1159 case 1:
1160 i2c_bus = &dev->i2c_bus[0];
1161 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1162 &mygica_x8558pro_atbm8830_cfg1,
1163 &i2c_bus->i2c_adap);
1164 if (fe0->dvb.frontend != NULL) {
1165 dvb_attach(max2165_attach,
1166 fe0->dvb.frontend,
1167 &i2c_bus->i2c_adap,
1168 &mygic_x8558pro_max2165_cfg1);
1169 }
1170 break;
1171 /* port C */
1172 case 2:
1173 i2c_bus = &dev->i2c_bus[1];
1174 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1175 &mygica_x8558pro_atbm8830_cfg2,
1176 &i2c_bus->i2c_adap);
1177 if (fe0->dvb.frontend != NULL) {
1178 dvb_attach(max2165_attach,
1179 fe0->dvb.frontend,
1180 &i2c_bus->i2c_adap,
1181 &mygic_x8558pro_max2165_cfg2);
1182 }
1183 break;
1184 }
1185 break;
78db8547
IL		 1186 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1187 i2c_bus = &dev->i2c_bus[0];
1188 mfe_shared = 1;/* MFE */
1189 port->frontends.gate = 0;/* not clear for me yet */
1190 /* ports B, C */
1191 /* MFE frontend 1 DVB-T */
1192 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1193 &netup_stv0367_config[port->nr - 1],
1194 &i2c_bus->i2c_adap);
4174ebf5 1195 if (fe0->dvb.frontend != NULL) {
78db8547
IL		 1196 if (NULL == dvb_attach(xc5000_attach,
1197 fe0->dvb.frontend,
1198 &i2c_bus->i2c_adap,
1199 &netup_xc5000_config[port->nr - 1]))
1200 goto frontend_detach;
4174ebf5
AO		 1201 /* load xc5000 firmware */
1202 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1203 }
78db8547
IL		 1204 /* MFE frontend 2 */
1205 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1206 if (fe1 == NULL)
1207 goto frontend_detach;
1208 /* DVB-C init */
1209 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1210 &netup_stv0367_config[port->nr - 1],
1211 &i2c_bus->i2c_adap);
1212 if (fe1->dvb.frontend != NULL) {
1213 fe1->dvb.frontend->id = 1;
1214 if (NULL == dvb_attach(xc5000_attach,
1215 fe1->dvb.frontend,
1216 &i2c_bus->i2c_adap,
1217 &netup_xc5000_config[port->nr - 1]))
1218 goto frontend_detach;
1219 }
1220 break;
722c90eb
SR		 1221 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1222 i2c_bus = &dev->i2c_bus[0];
1223 i2c_bus2 = &dev->i2c_bus[1];
1224
1225 switch (port->nr) {
1226 /* port b */
1227 case 1:
1228 fe0->dvb.frontend = dvb_attach(drxk_attach,
1229 &terratec_drxk_config[0],
1230 &i2c_bus->i2c_adap);
1231 if (fe0->dvb.frontend != NULL) {
1232 if (!dvb_attach(mt2063_attach,
1233 fe0->dvb.frontend,
1234 &terratec_mt2063_config[0],
1235 &i2c_bus2->i2c_adap))
1236 goto frontend_detach;
1237 }
1238 break;
1239 /* port c */
1240 case 2:
1241 fe0->dvb.frontend = dvb_attach(drxk_attach,
1242 &terratec_drxk_config[1],
1243 &i2c_bus->i2c_adap);
1244 if (fe0->dvb.frontend != NULL) {
1245 if (!dvb_attach(mt2063_attach,
1246 fe0->dvb.frontend,
1247 &terratec_mt2063_config[1],
1248 &i2c_bus2->i2c_adap))
1249 goto frontend_detach;
1250 }
1251 break;
1252 }
1253 break;
7b134e85
IL		 1254 case CX23885_BOARD_TEVII_S471:
1255 i2c_bus = &dev->i2c_bus[1];
1256
1257 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1258 &tevii_ds3000_config,
1259 &i2c_bus->i2c_adap);
b43ea806
JK		 1260 if (fe0->dvb.frontend != NULL) {
1261 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1262 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1263 }
7b134e85 1264 break;
f667190b
MB		 1265 case CX23885_BOARD_PROF_8000:
1266 i2c_bus = &dev->i2c_bus[0];
1267
1268 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1269 &prof_8000_stv090x_config,
1270 &i2c_bus->i2c_adap,
1271 STV090x_DEMODULATOR_0);
1272 if (fe0->dvb.frontend != NULL) {
1273 if (!dvb_attach(stb6100_attach,
1274 fe0->dvb.frontend,
1275 &prof_8000_stb6100_config,
1276 &i2c_bus->i2c_adap))
1277 goto frontend_detach;
1278
1279 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1280 }
1281 break;
7c62f5a1
MK		 1282 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1283 i2c_bus = &dev->i2c_bus[0];
1284 fe0->dvb.frontend = dvb_attach(tda10071_attach,
1285 &hauppauge_tda10071_config,
1286 &i2c_bus->i2c_adap);
1287 if (fe0->dvb.frontend != NULL) {
1288 dvb_attach(a8293_attach, fe0->dvb.frontend,
1289 &i2c_bus->i2c_adap,
1290 &hauppauge_a8293_config);
1291 }
1292 break;
d19770e5 1293 default:
9c8ced51
ST		 1294 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1295 " isn't supported yet\n",
d19770e5
ST		 1296 dev->name);
1297 break;
1298 }
78db8547
IL		 1299
1300 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1301 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL		 1302 dev->name);
1303 goto frontend_detach;
d19770e5 1304 }
78db8547 1305
d7cba043 1306 /* define general-purpose callback pointer */
363c35fc 1307 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL		 1308 if (fe1)
1309 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1310#if 0
1311 /* Ensure all frontends negotiate bus access */
1312 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1313 if (fe1)
1314 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1315#endif
d19770e5
ST		 1316
1317 /* Put the analog decoder in standby to keep it quiet */
622b828a 1318 call_all(dev, core, s_power, 0);
d19770e5 1319
363c35fc
ST		 1320 if (fe0->dvb.frontend->ops.analog_ops.standby)
1321 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1322
d19770e5 1323 /* register everything */
5a23b076 1324 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1325 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1326 if (ret)
78db8547 1327 goto frontend_detach;
363c35fc 1328
5a23b076
IL		 1329 /* init CI & MAC */
1330 switch (dev->board) {
1331 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1332 static struct netup_card_info cinfo;
1333
1334 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1335 memcpy(port->frontends.adapter.proposed_mac,
1336 cinfo.port[port->nr - 1].mac, 6);
be395157 1337 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1338 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL		 1339
1340 netup_ci_init(port);
1341 break;
1342 }
78db8547
IL		 1343 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1344 struct altera_ci_config netup_ci_cfg = {
1345 .dev = dev,/* magic number to identify*/
1346 .adapter = &port->frontends.adapter,/* for CI */
1347 .demux = &fe0->dvb.demux,/* for hw pid filter */
1348 .fpga_rw = netup_altera_fpga_rw,
1349 };
1350
1351 altera_ci_init(&netup_ci_cfg, port->nr);
1352 break;
1353 }
16bfdaa4
PG		 1354 case CX23885_BOARD_TEVII_S470: {
1355 u8 eeprom[256]; /* 24C02 i2c eeprom */
1356
1357 if (port->nr != 1)
1358 break;
1359
1360 /* Read entire EEPROM */
1361 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1362 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1363 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG		 1364 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1365 break;
1366 }
5a23b076
IL		 1367 }
1368
1369 return ret;
78db8547
IL		 1370
1371frontend_detach:
1372 port->gate_ctrl = NULL;
1373 videobuf_dvb_dealloc_frontends(&port->frontends);
1374 return -EINVAL;
d19770e5
ST		 1375}
1376
1377int cx23885_dvb_register(struct cx23885_tsport *port)
1378{
363c35fc
ST		 1379
1380 struct videobuf_dvb_frontend *fe0;
d19770e5 1381 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST		 1382 int err, i;
1383
1384 /* Here we need to allocate the correct number of frontends,
af901ca1 1385 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST		 1386 * no cx23885 boards support this - yet. But, if we don't modify this
1387 * code then the second frontend would never be allocated (later)
1388 * and fail with error before the attach in dvb_register().
1389 * Without these changes we risk an OOPS later. The changes here
1390 * are for safety, and should provide a good foundation for the
1391 * future addition of any multi-frontend cx23885 based boards.
1392 */
1393 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1394 port->num_frontends);
d19770e5 1395
eb0c58bb 1396 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1397 if (videobuf_dvb_alloc_frontend(
9c8ced51 1398 &port->frontends, i) == NULL) {
eb0c58bb
ST		 1399 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1400 return -ENOMEM;
1401 }
1402
1403 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1404 if (!fe0)
1405 err = -EINVAL;
363c35fc 1406
eb0c58bb 1407 dprintk(1, "%s\n", __func__);
9c8ced51 1408 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST		 1409 dev->board,
1410 dev->name,
1411 dev->pci_bus,
1412 dev->pci_slot);
d19770e5 1413
eb0c58bb 1414 err = -ENODEV;
d19770e5 1415
eb0c58bb
ST		 1416 /* dvb stuff */
1417 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST		 1418 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1419 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1420 &dev->pci->dev, &port->slock,
44a6481d 1421 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1422 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1423 }
d19770e5
ST		 1424 err = dvb_register(port);
1425 if (err != 0)
9c8ced51
ST		 1426 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1427 __func__, err);
d19770e5 1428
d19770e5
ST		 1429 return err;
1430}
1431
1432int cx23885_dvb_unregister(struct cx23885_tsport *port)
1433{
363c35fc
ST		 1434 struct videobuf_dvb_frontend *fe0;
1435
eb0c58bb
ST		 1436 /* FIXME: in an error condition where the we have
1437 * an expected number of frontends (attach problem)
1438 * then this might not clean up correctly, if 1
1439 * is invalid.
1440 * This comment only applies to future boards IF they
1441 * implement MFE support.
1442 */
92abe9ee 1443 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1444 if (fe0 && fe0->dvb.frontend)
363c35fc 1445 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1446
afd96668
HV		 1447 switch (port->dev->board) {
1448 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1449 netup_ci_exit(port);
1450 break;
78db8547
IL		 1451 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1452 altera_ci_release(port->dev, port->nr);
1453 break;
afd96668 1454 }
5a23b076 1455
78db8547
IL		 1456 port->gate_ctrl = NULL;
1457
d19770e5
ST		 1458 return 0;
1459}
44a6481d 1460
Linux kernel - Deliverables
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