[media] cx23885: add support for cx24117 with tbs6980 or tbs6981
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885-dvb.c
CommitLineData
d19770e5
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1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
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5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/fs.h>
26#include <linux/kthread.h>
27#include <linux/file.h>
28#include <linux/suspend.h>
29
30#include "cx23885.h"
d19770e5
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31#include <media/v4l2-common.h>
32
5a23b076 33#include "dvb_ca_en50221.h"
d19770e5 34#include "s5h1409.h"
52b50450 35#include "s5h1411.h"
d19770e5 36#include "mt2131.h"
3ba71d21 37#include "tda8290.h"
4041f1a5 38#include "tda18271.h"
9bc37caa 39#include "lgdt330x.h"
0cf8af57 40#include "xc4000.h"
d1987d55 41#include "xc5000.h"
ea5697fe 42#include "max2165.h"
b3ea0166 43#include "tda10048.h"
07b4a835 44#include "tuner-xc2028.h"
827855d3 45#include "tuner-simple.h"
66762373
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46#include "dib7000p.h"
47#include "dibx000_common.h"
aef2d186 48#include "zl10353.h"
5a23b076 49#include "stv0900.h"
f867c3f4 50#include "stv0900_reg.h"
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51#include "stv6110.h"
52#include "lnbh24.h"
96318d0c 53#include "cx24116.h"
e6001482 54#include "cx24117.h"
5a23b076 55#include "cimax2.h"
493b7127 56#include "lgs8gxx.h"
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57#include "netup-eeprom.h"
58#include "netup-init.h"
a5dbf457 59#include "lgdt3305.h"
ea5697fe 60#include "atbm8830.h"
73f0af44 61#include "ts2020.h"
09ea33e5
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62#include "ds3000.h"
63#include "cx23885-f300.h"
78db8547
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64#include "altera-ci.h"
65#include "stv0367.h"
722c90eb
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66#include "drxk.h"
67#include "mt2063.h"
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68#include "stv090x.h"
69#include "stb6100.h"
70#include "stb6100_cfg.h"
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71#include "tda10071.h"
72#include "a8293.h"
0d1b5265 73#include "mb86a20s.h"
d19770e5 74
4513fc69 75static unsigned int debug;
d19770e5 76
4513fc69
ST
77#define dprintk(level, fmt, arg...)\
78 do { if (debug >= level)\
79 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
80 } while (0)
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81
82/* ------------------------------------------------------------------ */
83
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84static unsigned int alt_tuner;
85module_param(alt_tuner, int, 0644);
86MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
87
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JG
88DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
89
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90/* ------------------------------------------------------------------ */
91
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92static int dvb_buf_setup(struct videobuf_queue *q,
93 unsigned int *count, unsigned int *size)
94{
95 struct cx23885_tsport *port = q->priv_data;
96
97 port->ts_packet_size = 188 * 4;
98 port->ts_packet_count = 32;
99
100 *size = port->ts_packet_size * port->ts_packet_count;
101 *count = 32;
102 return 0;
103}
104
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105static int dvb_buf_prepare(struct videobuf_queue *q,
106 struct videobuf_buffer *vb, enum v4l2_field field)
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107{
108 struct cx23885_tsport *port = q->priv_data;
9c8ced51 109 return cx23885_buf_prepare(q, port, (struct cx23885_buffer *)vb, field);
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110}
111
112static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
113{
114 struct cx23885_tsport *port = q->priv_data;
9c8ced51 115 cx23885_buf_queue(port, (struct cx23885_buffer *)vb);
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116}
117
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118static void dvb_buf_release(struct videobuf_queue *q,
119 struct videobuf_buffer *vb)
d19770e5 120{
9c8ced51 121 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
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122}
123
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124static void cx23885_dvb_gate_ctrl(struct cx23885_tsport *port, int open)
125{
126 struct videobuf_dvb_frontends *f;
127 struct videobuf_dvb_frontend *fe;
128
129 f = &port->frontends;
130
131 if (f->gate <= 1) /* undefined or fe0 */
132 fe = videobuf_dvb_get_frontend(f, 1);
133 else
134 fe = videobuf_dvb_get_frontend(f, f->gate);
135
136 if (fe && fe->dvb.frontend && fe->dvb.frontend->ops.i2c_gate_ctrl)
137 fe->dvb.frontend->ops.i2c_gate_ctrl(fe->dvb.frontend, open);
138}
139
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140static struct videobuf_queue_ops dvb_qops = {
141 .buf_setup = dvb_buf_setup,
142 .buf_prepare = dvb_buf_prepare,
143 .buf_queue = dvb_buf_queue,
144 .buf_release = dvb_buf_release,
145};
146
86184e06 147static struct s5h1409_config hauppauge_generic_config = {
fc959bef
ST
148 .demod_address = 0x32 >> 1,
149 .output_mode = S5H1409_SERIAL_OUTPUT,
150 .gpio = S5H1409_GPIO_ON,
2b03238a 151 .qam_if = 44000,
fc959bef 152 .inversion = S5H1409_INVERSION_OFF,
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153 .status_mode = S5H1409_DEMODLOCKING,
154 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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155};
156
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157static struct tda10048_config hauppauge_hvr1200_config = {
158 .demod_address = 0x10 >> 1,
159 .output_mode = TDA10048_SERIAL_OUTPUT,
160 .fwbulkwritelen = TDA10048_BULKWRITE_200,
484d9e05 161 .inversion = TDA10048_INVERSION_ON,
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162 .dtv6_if_freq_khz = TDA10048_IF_3300,
163 .dtv7_if_freq_khz = TDA10048_IF_3800,
164 .dtv8_if_freq_khz = TDA10048_IF_4300,
484d9e05 165 .clk_freq_khz = TDA10048_CLK_16000,
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166};
167
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168static struct tda10048_config hauppauge_hvr1210_config = {
169 .demod_address = 0x10 >> 1,
170 .output_mode = TDA10048_SERIAL_OUTPUT,
171 .fwbulkwritelen = TDA10048_BULKWRITE_200,
172 .inversion = TDA10048_INVERSION_ON,
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173 .dtv6_if_freq_khz = TDA10048_IF_3300,
174 .dtv7_if_freq_khz = TDA10048_IF_3500,
175 .dtv8_if_freq_khz = TDA10048_IF_4000,
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176 .clk_freq_khz = TDA10048_CLK_16000,
177};
178
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179static struct s5h1409_config hauppauge_ezqam_config = {
180 .demod_address = 0x32 >> 1,
181 .output_mode = S5H1409_SERIAL_OUTPUT,
182 .gpio = S5H1409_GPIO_OFF,
183 .qam_if = 4000,
184 .inversion = S5H1409_INVERSION_ON,
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185 .status_mode = S5H1409_DEMODLOCKING,
186 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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187};
188
fc959bef 189static struct s5h1409_config hauppauge_hvr1800lp_config = {
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190 .demod_address = 0x32 >> 1,
191 .output_mode = S5H1409_SERIAL_OUTPUT,
192 .gpio = S5H1409_GPIO_OFF,
2b03238a 193 .qam_if = 44000,
fe475163 194 .inversion = S5H1409_INVERSION_OFF,
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195 .status_mode = S5H1409_DEMODLOCKING,
196 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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197};
198
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199static struct s5h1409_config hauppauge_hvr1500_config = {
200 .demod_address = 0x32 >> 1,
201 .output_mode = S5H1409_SERIAL_OUTPUT,
202 .gpio = S5H1409_GPIO_OFF,
203 .inversion = S5H1409_INVERSION_OFF,
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204 .status_mode = S5H1409_DEMODLOCKING,
205 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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206};
207
86184e06 208static struct mt2131_config hauppauge_generic_tunerconfig = {
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209 0x61
210};
211
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212static struct lgdt330x_config fusionhdtv_5_express = {
213 .demod_address = 0x0e,
214 .demod_chip = LGDT3303,
215 .serial_mpeg = 0x40,
216};
217
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218static struct s5h1409_config hauppauge_hvr1500q_config = {
219 .demod_address = 0x32 >> 1,
220 .output_mode = S5H1409_SERIAL_OUTPUT,
221 .gpio = S5H1409_GPIO_ON,
222 .qam_if = 44000,
223 .inversion = S5H1409_INVERSION_OFF,
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224 .status_mode = S5H1409_DEMODLOCKING,
225 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
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226};
227
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228static struct s5h1409_config dvico_s5h1409_config = {
229 .demod_address = 0x32 >> 1,
230 .output_mode = S5H1409_SERIAL_OUTPUT,
231 .gpio = S5H1409_GPIO_ON,
232 .qam_if = 44000,
233 .inversion = S5H1409_INVERSION_OFF,
234 .status_mode = S5H1409_DEMODLOCKING,
235 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
236};
237
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238static struct s5h1411_config dvico_s5h1411_config = {
239 .output_mode = S5H1411_SERIAL_OUTPUT,
240 .gpio = S5H1411_GPIO_ON,
241 .qam_if = S5H1411_IF_44000,
242 .vsb_if = S5H1411_IF_44000,
243 .inversion = S5H1411_INVERSION_OFF,
244 .status_mode = S5H1411_DEMODLOCKING,
245 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
246};
247
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248static struct s5h1411_config hcw_s5h1411_config = {
249 .output_mode = S5H1411_SERIAL_OUTPUT,
250 .gpio = S5H1411_GPIO_OFF,
251 .vsb_if = S5H1411_IF_44000,
252 .qam_if = S5H1411_IF_4000,
253 .inversion = S5H1411_INVERSION_ON,
254 .status_mode = S5H1411_DEMODLOCKING,
255 .mpeg_timing = S5H1411_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
256};
257
d1987d55 258static struct xc5000_config hauppauge_hvr1500q_tunerconfig = {
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259 .i2c_address = 0x61,
260 .if_khz = 5380,
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261};
262
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263static struct xc5000_config dvico_xc5000_tunerconfig = {
264 .i2c_address = 0x64,
265 .if_khz = 5380,
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266};
267
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268static struct tda829x_config tda829x_no_probe = {
269 .probe_tuner = TDA829X_DONT_PROBE,
270};
271
f21e0d7f 272static struct tda18271_std_map hauppauge_tda18271_std_map = {
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273 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
274 .if_lvl = 6, .rfagc_top = 0x37 },
275 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
276 .if_lvl = 6, .rfagc_top = 0x37 },
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277};
278
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279static struct tda18271_std_map hauppauge_hvr1200_tda18271_std_map = {
280 .dvbt_6 = { .if_freq = 3300, .agc_mode = 3, .std = 4,
281 .if_lvl = 1, .rfagc_top = 0x37, },
282 .dvbt_7 = { .if_freq = 3800, .agc_mode = 3, .std = 5,
283 .if_lvl = 1, .rfagc_top = 0x37, },
284 .dvbt_8 = { .if_freq = 4300, .agc_mode = 3, .std = 6,
285 .if_lvl = 1, .rfagc_top = 0x37, },
286};
287
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288static struct tda18271_config hauppauge_tda18271_config = {
289 .std_map = &hauppauge_tda18271_std_map,
290 .gate = TDA18271_GATE_ANALOG,
04a68baa 291 .output_opt = TDA18271_OUTPUT_LT_OFF,
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292};
293
b3ea0166 294static struct tda18271_config hauppauge_hvr1200_tuner_config = {
b34cdc36 295 .std_map = &hauppauge_hvr1200_tda18271_std_map,
b3ea0166 296 .gate = TDA18271_GATE_ANALOG,
04a68baa 297 .output_opt = TDA18271_OUTPUT_LT_OFF,
b3ea0166
ST
298};
299
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300static struct tda18271_config hauppauge_hvr1210_tuner_config = {
301 .gate = TDA18271_GATE_DIGITAL,
04a68baa 302 .output_opt = TDA18271_OUTPUT_LT_OFF,
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303};
304
247bc540 305static struct tda18271_std_map hauppauge_hvr127x_std_map = {
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306 .atsc_6 = { .if_freq = 3250, .agc_mode = 3, .std = 4,
307 .if_lvl = 1, .rfagc_top = 0x58 },
308 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 5,
309 .if_lvl = 1, .rfagc_top = 0x58 },
310};
311
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312static struct tda18271_config hauppauge_hvr127x_config = {
313 .std_map = &hauppauge_hvr127x_std_map,
04a68baa 314 .output_opt = TDA18271_OUTPUT_LT_OFF,
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315};
316
247bc540 317static struct lgdt3305_config hauppauge_lgdt3305_config = {
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318 .i2c_addr = 0x0e,
319 .mpeg_mode = LGDT3305_MPEG_SERIAL,
320 .tpclk_edge = LGDT3305_TPCLK_FALLING_EDGE,
321 .tpvalid_polarity = LGDT3305_TP_VALID_HIGH,
322 .deny_i2c_rptr = 1,
323 .spectral_inversion = 1,
324 .qam_if_khz = 4000,
325 .vsb_if_khz = 3250,
326};
327
b1721d0d 328static struct dibx000_agc_config xc3028_agc_config = {
66762373
ST
329 BAND_VHF | BAND_UHF, /* band_caps */
330
331 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
332 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
333 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
334 * P_agc_nb_est=2, P_agc_write=0
335 */
336 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
337 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
338
339 712, /* inv_gain */
340 21, /* time_stabiliz */
341
342 0, /* alpha_level */
343 118, /* thlock */
344
345 0, /* wbd_inv */
346 2867, /* wbd_ref */
347 0, /* wbd_sel */
348 2, /* wbd_alpha */
349
350 0, /* agc1_max */
351 0, /* agc1_min */
352 39718, /* agc2_max */
353 9930, /* agc2_min */
354 0, /* agc1_pt1 */
355 0, /* agc1_pt2 */
356 0, /* agc1_pt3 */
357 0, /* agc1_slope1 */
358 0, /* agc1_slope2 */
359 0, /* agc2_pt1 */
360 128, /* agc2_pt2 */
361 29, /* agc2_slope1 */
362 29, /* agc2_slope2 */
363
364 17, /* alpha_mant */
365 27, /* alpha_exp */
366 23, /* beta_mant */
367 51, /* beta_exp */
368
369 1, /* perform_agc_softsplit */
370};
371
372/* PLL Configuration for COFDM BW_MHz = 8.000000
373 * With external clock = 30.000000 */
b1721d0d 374static struct dibx000_bandwidth_config xc3028_bw_config = {
66762373
ST
375 60000, /* internal */
376 30000, /* sampling */
377 1, /* pll_cfg: prediv */
378 8, /* pll_cfg: ratio */
379 3, /* pll_cfg: range */
380 1, /* pll_cfg: reset */
381 0, /* pll_cfg: bypass */
382 0, /* misc: refdiv */
383 0, /* misc: bypclk_div */
384 1, /* misc: IO_CLK_en_core */
385 1, /* misc: ADClkSrc */
386 0, /* misc: modulo */
387 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
388 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
389 20452225, /* timf */
390 30000000 /* xtal_hz */
391};
392
393static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
394 .output_mpeg2_in_188_bytes = 1,
395 .hostbus_diversity = 1,
396 .tuner_is_baseband = 0,
397 .update_lna = NULL,
398
399 .agc_config_count = 1,
400 .agc = &xc3028_agc_config,
401 .bw = &xc3028_bw_config,
402
403 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
404 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
405 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
406
407 .pwm_freq_div = 0,
408 .agc_control = NULL,
409 .spur_protect = 0,
410
411 .output_mode = OUTMODE_MPEG2_SERIAL,
412};
413
aef2d186
ST
414static struct zl10353_config dvico_fusionhdtv_xc3028 = {
415 .demod_address = 0x0f,
416 .if2 = 45600,
417 .no_tuner = 1,
d4dc673d 418 .disable_i2c_gate_ctrl = 1,
aef2d186
ST
419};
420
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IL
421static struct stv0900_reg stv0900_ts_regs[] = {
422 { R0900_TSGENERAL, 0x00 },
423 { R0900_P1_TSSPEED, 0x40 },
424 { R0900_P2_TSSPEED, 0x40 },
425 { R0900_P1_TSCFGM, 0xc0 },
426 { R0900_P2_TSCFGM, 0xc0 },
427 { R0900_P1_TSCFGH, 0xe0 },
428 { R0900_P2_TSCFGH, 0xe0 },
429 { R0900_P1_TSCFGL, 0x20 },
430 { R0900_P2_TSCFGL, 0x20 },
431 { 0xffff, 0xff }, /* terminate */
432};
433
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IL
434static struct stv0900_config netup_stv0900_config = {
435 .demod_address = 0x68,
29372a8d 436 .demod_mode = 1, /* dual */
644c7ef0 437 .xtal = 8000000,
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IL
438 .clkmode = 3,/* 0-CLKI, 2-XTALI, else AUTO */
439 .diseqc_mode = 2,/* 2/3 PWM */
f867c3f4 440 .ts_config_regs = stv0900_ts_regs,
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IL
441 .tun1_maddress = 0,/* 0x60 */
442 .tun2_maddress = 3,/* 0x63 */
443 .tun1_adc = 1,/* 1 Vpp */
444 .tun2_adc = 1,/* 1 Vpp */
445};
446
447static struct stv6110_config netup_stv6110_tunerconfig_a = {
448 .i2c_address = 0x60,
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AO
449 .mclk = 16000000,
450 .clk_div = 1,
873688cd 451 .gain = 8, /* +16 dB - maximum gain */
5a23b076
IL
452};
453
454static struct stv6110_config netup_stv6110_tunerconfig_b = {
455 .i2c_address = 0x63,
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AO
456 .mclk = 16000000,
457 .clk_div = 1,
873688cd 458 .gain = 8, /* +16 dB - maximum gain */
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IL
459};
460
96318d0c 461static struct cx24116_config tbs_cx24116_config = {
09ea33e5 462 .demod_address = 0x55,
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IL
463};
464
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465static struct cx24117_config tbs_cx24117_config = {
466 .demod_address = 0x55,
467};
468
09ea33e5
IL
469static struct ds3000_config tevii_ds3000_config = {
470 .demod_address = 0x68,
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IL
471};
472
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KD
473static struct ts2020_config tevii_ts2020_config = {
474 .tuner_address = 0x60,
b858c331 475 .clk_out_div = 1,
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KD
476};
477
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IL
478static struct cx24116_config dvbworld_cx24116_config = {
479 .demod_address = 0x05,
480};
481
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DW
482static struct lgs8gxx_config mygica_x8506_lgs8gl5_config = {
483 .prod = LGS8GXX_PROD_LGS8GL5,
484 .demod_address = 0x19,
485 .serial_ts = 0,
486 .ts_clk_pol = 1,
487 .ts_clk_gated = 1,
488 .if_clk_freq = 30400, /* 30.4 MHz */
489 .if_freq = 5380, /* 5.38 MHz */
490 .if_neg_center = 1,
491 .ext_adc = 0,
492 .adc_signed = 0,
493 .if_neg_edge = 0,
494};
495
496static struct xc5000_config mygica_x8506_xc5000_config = {
497 .i2c_address = 0x61,
498 .if_khz = 5380,
499};
500
0d1b5265
MCC
501static struct mb86a20s_config mygica_x8507_mb86a20s_config = {
502 .demod_address = 0x10,
503};
504
505static struct xc5000_config mygica_x8507_xc5000_config = {
506 .i2c_address = 0x61,
507 .if_khz = 4000,
508};
509
f667190b 510static struct stv090x_config prof_8000_stv090x_config = {
b858c331
IL
511 .device = STV0903,
512 .demod_mode = STV090x_SINGLE,
513 .clk_mode = STV090x_CLK_EXT,
514 .xtal = 27000000,
515 .address = 0x6A,
516 .ts1_mode = STV090x_TSMODE_PARALLEL_PUNCTURED,
517 .repeater_level = STV090x_RPTLEVEL_64,
518 .adc1_range = STV090x_ADC_2Vpp,
519 .diseqc_envelope_mode = false,
520
521 .tuner_get_frequency = stb6100_get_frequency,
522 .tuner_set_frequency = stb6100_set_frequency,
523 .tuner_set_bandwidth = stb6100_set_bandwidth,
524 .tuner_get_bandwidth = stb6100_get_bandwidth,
f667190b
MB
525};
526
527static struct stb6100_config prof_8000_stb6100_config = {
528 .tuner_address = 0x60,
529 .refclock = 27000000,
530};
531
532static int p8000_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
533{
534 struct cx23885_tsport *port = fe->dvb->priv;
535 struct cx23885_dev *dev = port->dev;
536
537 if (voltage == SEC_VOLTAGE_18)
538 cx_write(MC417_RWD, 0x00001e00);
539 else if (voltage == SEC_VOLTAGE_13)
540 cx_write(MC417_RWD, 0x00001a00);
541 else
542 cx_write(MC417_RWD, 0x00001800);
543 return 0;
544}
545
a7d44baa 546static int cx23885_dvb_set_frontend(struct dvb_frontend *fe)
f35b9e80 547{
a7d44baa 548 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
f35b9e80
MK
549 struct cx23885_tsport *port = fe->dvb->priv;
550 struct cx23885_dev *dev = port->dev;
551
552 switch (dev->board) {
553 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a7d44baa 554 switch (p->modulation) {
f35b9e80
MK
555 case VSB_8:
556 cx23885_gpio_clear(dev, GPIO_5);
557 break;
558 case QAM_64:
559 case QAM_256:
560 default:
561 cx23885_gpio_set(dev, GPIO_5);
562 break;
563 }
564 break;
6f0d8c02 565 case CX23885_BOARD_MYGICA_X8506:
0d1b5265 566 case CX23885_BOARD_MYGICA_X8507:
6f0d8c02
DW
567 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
568 /* Select Digital TV */
569 cx23885_gpio_set(dev, GPIO_0);
570 break;
f35b9e80 571 }
15472faf
MCC
572
573 /* Call the real set_frontend */
574 if (port->set_frontend)
575 return port->set_frontend(fe);
576
5bdd3962 577 return 0;
f35b9e80
MK
578}
579
15472faf
MCC
580static void cx23885_set_frontend_hook(struct cx23885_tsport *port,
581 struct dvb_frontend *fe)
582{
583 port->set_frontend = fe->ops.set_frontend;
584 fe->ops.set_frontend = cx23885_dvb_set_frontend;
585}
586
2365b2d3
DW
587static struct lgs8gxx_config magicpro_prohdtve2_lgs8g75_config = {
588 .prod = LGS8GXX_PROD_LGS8G75,
589 .demod_address = 0x19,
590 .serial_ts = 0,
591 .ts_clk_pol = 1,
592 .ts_clk_gated = 1,
593 .if_clk_freq = 30400, /* 30.4 MHz */
594 .if_freq = 6500, /* 6.50 MHz */
595 .if_neg_center = 1,
596 .ext_adc = 0,
597 .adc_signed = 1,
598 .adc_vpp = 2, /* 1.6 Vpp */
599 .if_neg_edge = 1,
600};
601
602static struct xc5000_config magicpro_prohdtve2_xc5000_config = {
603 .i2c_address = 0x61,
604 .if_khz = 6500,
605};
606
ea5697fe
DW
607static struct atbm8830_config mygica_x8558pro_atbm8830_cfg1 = {
608 .prod = ATBM8830_PROD_8830,
609 .demod_address = 0x44,
610 .serial_ts = 0,
611 .ts_sampling_edge = 1,
612 .ts_clk_gated = 0,
613 .osc_clk_freq = 30400, /* in kHz */
614 .if_freq = 0, /* zero IF */
615 .zif_swap_iq = 1,
c245c75c
DW
616 .agc_min = 0x2E,
617 .agc_max = 0xFF,
618 .agc_hold_loop = 0,
ea5697fe
DW
619};
620
621static struct max2165_config mygic_x8558pro_max2165_cfg1 = {
622 .i2c_address = 0x60,
623 .osc_clk = 20
624};
625
626static struct atbm8830_config mygica_x8558pro_atbm8830_cfg2 = {
627 .prod = ATBM8830_PROD_8830,
628 .demod_address = 0x44,
629 .serial_ts = 1,
630 .ts_sampling_edge = 1,
631 .ts_clk_gated = 0,
632 .osc_clk_freq = 30400, /* in kHz */
633 .if_freq = 0, /* zero IF */
634 .zif_swap_iq = 1,
c245c75c
DW
635 .agc_min = 0x2E,
636 .agc_max = 0xFF,
637 .agc_hold_loop = 0,
ea5697fe
DW
638};
639
640static struct max2165_config mygic_x8558pro_max2165_cfg2 = {
641 .i2c_address = 0x60,
642 .osc_clk = 20
643};
78db8547
IL
644static struct stv0367_config netup_stv0367_config[] = {
645 {
646 .demod_address = 0x1c,
647 .xtal = 27000000,
648 .if_khz = 4500,
649 .if_iq_mode = 0,
650 .ts_mode = 1,
651 .clk_pol = 0,
652 }, {
653 .demod_address = 0x1d,
654 .xtal = 27000000,
655 .if_khz = 4500,
656 .if_iq_mode = 0,
657 .ts_mode = 1,
658 .clk_pol = 0,
659 },
660};
661
662static struct xc5000_config netup_xc5000_config[] = {
663 {
664 .i2c_address = 0x61,
665 .if_khz = 4500,
666 }, {
667 .i2c_address = 0x64,
668 .if_khz = 4500,
669 },
670};
671
722c90eb
SR
672static struct drxk_config terratec_drxk_config[] = {
673 {
674 .adr = 0x29,
675 .no_i2c_bridge = 1,
676 }, {
677 .adr = 0x2a,
678 .no_i2c_bridge = 1,
679 },
680};
681
682static struct mt2063_config terratec_mt2063_config[] = {
683 {
684 .tuner_address = 0x60,
685 }, {
686 .tuner_address = 0x67,
687 },
688};
689
7c62f5a1 690static const struct tda10071_config hauppauge_tda10071_config = {
41f55d57 691 .demod_i2c_addr = 0x05,
7c62f5a1
MK
692 .tuner_i2c_addr = 0x54,
693 .i2c_wr_max = 64,
694 .ts_mode = TDA10071_TS_SERIAL,
695 .spec_inv = 0,
696 .xtal = 40444000, /* 40.444 MHz */
697 .pll_multiplier = 20,
698};
699
700static const struct a8293_config hauppauge_a8293_config = {
701 .i2c_addr = 0x0b,
702};
703
ada73eee 704static int netup_altera_fpga_rw(void *device, int flag, int data, int read)
78db8547
IL
705{
706 struct cx23885_dev *dev = (struct cx23885_dev *)device;
707 unsigned long timeout = jiffies + msecs_to_jiffies(1);
d164460f 708 uint32_t mem = 0;
78db8547 709
d164460f 710 mem = cx_read(MC417_RWD);
78db8547
IL
711 if (read)
712 cx_set(MC417_OEN, ALT_DATA);
713 else {
714 cx_clear(MC417_OEN, ALT_DATA);/* D0-D7 out */
78db8547
IL
715 mem &= ~ALT_DATA;
716 mem |= (data & ALT_DATA);
78db8547
IL
717 }
718
719 if (flag)
d164460f 720 mem |= ALT_AD_RG;
78db8547 721 else
d164460f 722 mem &= ~ALT_AD_RG;
78db8547 723
d164460f 724 mem &= ~ALT_CS;
78db8547 725 if (read)
d164460f 726 mem = (mem & ~ALT_RD) | ALT_WR;
78db8547 727 else
d164460f
AO
728 mem = (mem & ~ALT_WR) | ALT_RD;
729
730 cx_write(MC417_RWD, mem); /* start RW cycle */
78db8547
IL
731
732 for (;;) {
733 mem = cx_read(MC417_RWD);
734 if ((mem & ALT_RDY) == 0)
735 break;
736 if (time_after(jiffies, timeout))
737 break;
738 udelay(1);
739 }
740
741 cx_set(MC417_RWD, ALT_RD | ALT_WR | ALT_CS);
742 if (read)
743 return mem & ALT_DATA;
744
745 return 0;
746};
ea5697fe 747
d19770e5
ST
748static int dvb_register(struct cx23885_tsport *port)
749{
750 struct cx23885_dev *dev = port->dev;
493b7127 751 struct cx23885_i2c *i2c_bus = NULL, *i2c_bus2 = NULL;
78db8547
IL
752 struct videobuf_dvb_frontend *fe0, *fe1 = NULL;
753 int mfe_shared = 0; /* bus not shared by default */
5a23b076 754 int ret;
363c35fc 755
f972e0bd 756 /* Get the first frontend */
92abe9ee 757 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
363c35fc
ST
758 if (!fe0)
759 return -EINVAL;
d19770e5
ST
760
761 /* init struct videobuf_dvb */
363c35fc 762 fe0->dvb.name = dev->name;
d19770e5 763
78db8547
IL
764 /* multi-frontend gate control is undefined or defaults to fe0 */
765 port->frontends.gate = 0;
766
767 /* Sets the gate control callback to be used by i2c command calls */
768 port->gate_ctrl = cx23885_dvb_gate_ctrl;
769
d19770e5
ST
770 /* init frontend */
771 switch (dev->board) {
a77743bc 772 case CX23885_BOARD_HAUPPAUGE_HVR1250:
f139fa71 773 i2c_bus = &dev->i2c_bus[0];
363c35fc 774 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
86184e06 775 &hauppauge_generic_config,
f139fa71 776 &i2c_bus->i2c_adap);
363c35fc
ST
777 if (fe0->dvb.frontend != NULL) {
778 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 779 &i2c_bus->i2c_adap,
86184e06 780 &hauppauge_generic_tunerconfig, 0);
d19770e5
ST
781 }
782 break;
a5dbf457 783 case CX23885_BOARD_HAUPPAUGE_HVR1270:
d099becb 784 case CX23885_BOARD_HAUPPAUGE_HVR1275:
a5dbf457
MK
785 i2c_bus = &dev->i2c_bus[0];
786 fe0->dvb.frontend = dvb_attach(lgdt3305_attach,
247bc540 787 &hauppauge_lgdt3305_config,
a5dbf457
MK
788 &i2c_bus->i2c_adap);
789 if (fe0->dvb.frontend != NULL) {
790 dvb_attach(tda18271_attach, fe0->dvb.frontend,
791 0x60, &dev->i2c_bus[1].i2c_adap,
247bc540 792 &hauppauge_hvr127x_config);
a5dbf457 793 }
15472faf
MCC
794 if (dev->board == CX23885_BOARD_HAUPPAUGE_HVR1275)
795 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
a5dbf457 796 break;
19bc5796 797 case CX23885_BOARD_HAUPPAUGE_HVR1255:
0ac60acb 798 case CX23885_BOARD_HAUPPAUGE_HVR1255_22111:
19bc5796
MK
799 i2c_bus = &dev->i2c_bus[0];
800 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
801 &hcw_s5h1411_config,
802 &i2c_bus->i2c_adap);
803 if (fe0->dvb.frontend != NULL) {
804 dvb_attach(tda18271_attach, fe0->dvb.frontend,
805 0x60, &dev->i2c_bus[1].i2c_adap,
806 &hauppauge_tda18271_config);
807 }
0ac60acb
DH
808
809 tda18271_attach(&dev->ts1.analog_fe,
810 0x60, &dev->i2c_bus[1].i2c_adap,
811 &hauppauge_tda18271_config);
812
19bc5796 813 break;
3ba71d21
MK
814 case CX23885_BOARD_HAUPPAUGE_HVR1800:
815 i2c_bus = &dev->i2c_bus[0];
92abe9ee 816 switch (alt_tuner) {
3ba71d21 817 case 1:
363c35fc 818 fe0->dvb.frontend =
3ba71d21
MK
819 dvb_attach(s5h1409_attach,
820 &hauppauge_ezqam_config,
821 &i2c_bus->i2c_adap);
363c35fc
ST
822 if (fe0->dvb.frontend != NULL) {
823 dvb_attach(tda829x_attach, fe0->dvb.frontend,
3ba71d21 824 &dev->i2c_bus[1].i2c_adap, 0x42,
4041f1a5 825 &tda829x_no_probe);
363c35fc 826 dvb_attach(tda18271_attach, fe0->dvb.frontend,
4041f1a5 827 0x60, &dev->i2c_bus[1].i2c_adap,
f21e0d7f 828 &hauppauge_tda18271_config);
3ba71d21
MK
829 }
830 break;
831 case 0:
832 default:
363c35fc 833 fe0->dvb.frontend =
3ba71d21
MK
834 dvb_attach(s5h1409_attach,
835 &hauppauge_generic_config,
836 &i2c_bus->i2c_adap);
363c35fc
ST
837 if (fe0->dvb.frontend != NULL)
838 dvb_attach(mt2131_attach, fe0->dvb.frontend,
3ba71d21
MK
839 &i2c_bus->i2c_adap,
840 &hauppauge_generic_tunerconfig, 0);
841 break;
842 }
843 break;
fc959bef 844 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
f139fa71 845 i2c_bus = &dev->i2c_bus[0];
363c35fc 846 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
fc959bef 847 &hauppauge_hvr1800lp_config,
f139fa71 848 &i2c_bus->i2c_adap);
363c35fc
ST
849 if (fe0->dvb.frontend != NULL) {
850 dvb_attach(mt2131_attach, fe0->dvb.frontend,
f139fa71 851 &i2c_bus->i2c_adap,
fc959bef
ST
852 &hauppauge_generic_tunerconfig, 0);
853 }
854 break;
9bc37caa 855 case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
f139fa71 856 i2c_bus = &dev->i2c_bus[0];
363c35fc 857 fe0->dvb.frontend = dvb_attach(lgdt330x_attach,
9bc37caa 858 &fusionhdtv_5_express,
f139fa71 859 &i2c_bus->i2c_adap);
363c35fc
ST
860 if (fe0->dvb.frontend != NULL) {
861 dvb_attach(simple_tuner_attach, fe0->dvb.frontend,
827855d3
MK
862 &i2c_bus->i2c_adap, 0x61,
863 TUNER_LG_TDVS_H06XF);
9bc37caa
MK
864 }
865 break;
d1987d55
ST
866 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
867 i2c_bus = &dev->i2c_bus[1];
363c35fc 868 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
d1987d55
ST
869 &hauppauge_hvr1500q_config,
870 &dev->i2c_bus[0].i2c_adap);
363c35fc
ST
871 if (fe0->dvb.frontend != NULL)
872 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
873 &i2c_bus->i2c_adap,
874 &hauppauge_hvr1500q_tunerconfig);
d1987d55 875 break;
07b4a835
MK
876 case CX23885_BOARD_HAUPPAUGE_HVR1500:
877 i2c_bus = &dev->i2c_bus[1];
363c35fc 878 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
07b4a835
MK
879 &hauppauge_hvr1500_config,
880 &dev->i2c_bus[0].i2c_adap);
363c35fc 881 if (fe0->dvb.frontend != NULL) {
07b4a835
MK
882 struct dvb_frontend *fe;
883 struct xc2028_config cfg = {
884 .i2c_adap = &i2c_bus->i2c_adap,
885 .i2c_addr = 0x61,
07b4a835
MK
886 };
887 static struct xc2028_ctrl ctl = {
ef80bfeb 888 .fname = XC2028_DEFAULT_FIRMWARE,
07b4a835 889 .max_len = 64,
52c3d29c 890 .demod = XC3028_FE_OREN538,
07b4a835
MK
891 };
892
893 fe = dvb_attach(xc2028_attach,
363c35fc 894 fe0->dvb.frontend, &cfg);
07b4a835
MK
895 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
896 fe->ops.tuner_ops.set_config(fe, &ctl);
897 }
898 break;
b3ea0166 899 case CX23885_BOARD_HAUPPAUGE_HVR1200:
a780a31c 900 case CX23885_BOARD_HAUPPAUGE_HVR1700:
b3ea0166 901 i2c_bus = &dev->i2c_bus[0];
363c35fc 902 fe0->dvb.frontend = dvb_attach(tda10048_attach,
b3ea0166
ST
903 &hauppauge_hvr1200_config,
904 &i2c_bus->i2c_adap);
363c35fc
ST
905 if (fe0->dvb.frontend != NULL) {
906 dvb_attach(tda829x_attach, fe0->dvb.frontend,
b3ea0166
ST
907 &dev->i2c_bus[1].i2c_adap, 0x42,
908 &tda829x_no_probe);
363c35fc 909 dvb_attach(tda18271_attach, fe0->dvb.frontend,
b3ea0166
ST
910 0x60, &dev->i2c_bus[1].i2c_adap,
911 &hauppauge_hvr1200_tuner_config);
6b926eca
MK
912 }
913 break;
914 case CX23885_BOARD_HAUPPAUGE_HVR1210:
915 i2c_bus = &dev->i2c_bus[0];
916 fe0->dvb.frontend = dvb_attach(tda10048_attach,
917 &hauppauge_hvr1210_config,
918 &i2c_bus->i2c_adap);
919 if (fe0->dvb.frontend != NULL) {
920 dvb_attach(tda18271_attach, fe0->dvb.frontend,
921 0x60, &dev->i2c_bus[1].i2c_adap,
922 &hauppauge_hvr1210_tuner_config);
b3ea0166
ST
923 }
924 break;
66762373
ST
925 case CX23885_BOARD_HAUPPAUGE_HVR1400:
926 i2c_bus = &dev->i2c_bus[0];
363c35fc 927 fe0->dvb.frontend = dvb_attach(dib7000p_attach,
66762373
ST
928 &i2c_bus->i2c_adap,
929 0x12, &hauppauge_hvr1400_dib7000_config);
363c35fc 930 if (fe0->dvb.frontend != NULL) {
66762373
ST
931 struct dvb_frontend *fe;
932 struct xc2028_config cfg = {
933 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
934 .i2c_addr = 0x64,
66762373
ST
935 };
936 static struct xc2028_ctrl ctl = {
ef80bfeb 937 .fname = XC3028L_DEFAULT_FIRMWARE,
66762373 938 .max_len = 64,
9bed77ee 939 .demod = XC3028_FE_DIBCOM52,
9c8ced51
ST
940 /* This is true for all demods with
941 v36 firmware? */
0975fc68 942 .type = XC2028_D2633,
66762373
ST
943 };
944
945 fe = dvb_attach(xc2028_attach,
363c35fc 946 fe0->dvb.frontend, &cfg);
66762373
ST
947 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
948 fe->ops.tuner_ops.set_config(fe, &ctl);
949 }
950 break;
335377b7
MK
951 case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
952 i2c_bus = &dev->i2c_bus[port->nr - 1];
953
363c35fc 954 fe0->dvb.frontend = dvb_attach(s5h1409_attach,
335377b7
MK
955 &dvico_s5h1409_config,
956 &i2c_bus->i2c_adap);
363c35fc
ST
957 if (fe0->dvb.frontend == NULL)
958 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
52b50450
MK
959 &dvico_s5h1411_config,
960 &i2c_bus->i2c_adap);
363c35fc
ST
961 if (fe0->dvb.frontend != NULL)
962 dvb_attach(xc5000_attach, fe0->dvb.frontend,
30650961
MK
963 &i2c_bus->i2c_adap,
964 &dvico_xc5000_tunerconfig);
335377b7 965 break;
aef2d186
ST
966 case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP: {
967 i2c_bus = &dev->i2c_bus[port->nr - 1];
968
363c35fc 969 fe0->dvb.frontend = dvb_attach(zl10353_attach,
aef2d186
ST
970 &dvico_fusionhdtv_xc3028,
971 &i2c_bus->i2c_adap);
363c35fc 972 if (fe0->dvb.frontend != NULL) {
aef2d186
ST
973 struct dvb_frontend *fe;
974 struct xc2028_config cfg = {
975 .i2c_adap = &i2c_bus->i2c_adap,
976 .i2c_addr = 0x61,
aef2d186
ST
977 };
978 static struct xc2028_ctrl ctl = {
ef80bfeb 979 .fname = XC2028_DEFAULT_FIRMWARE,
aef2d186
ST
980 .max_len = 64,
981 .demod = XC3028_FE_ZARLINK456,
982 };
983
363c35fc 984 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
aef2d186
ST
985 &cfg);
986 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
987 fe->ops.tuner_ops.set_config(fe, &ctl);
988 }
989 break;
990 }
4c56b04a 991 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
9bb1b7e8 992 case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
34e383dd 993 case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
4c56b04a
ST
994 i2c_bus = &dev->i2c_bus[0];
995
363c35fc 996 fe0->dvb.frontend = dvb_attach(zl10353_attach,
4c56b04a
ST
997 &dvico_fusionhdtv_xc3028,
998 &i2c_bus->i2c_adap);
363c35fc 999 if (fe0->dvb.frontend != NULL) {
4c56b04a
ST
1000 struct dvb_frontend *fe;
1001 struct xc2028_config cfg = {
1002 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
1003 .i2c_addr = 0x61,
4c56b04a
ST
1004 };
1005 static struct xc2028_ctrl ctl = {
ef80bfeb 1006 .fname = XC2028_DEFAULT_FIRMWARE,
4c56b04a
ST
1007 .max_len = 64,
1008 .demod = XC3028_FE_ZARLINK456,
1009 };
1010
363c35fc 1011 fe = dvb_attach(xc2028_attach, fe0->dvb.frontend,
4c56b04a
ST
1012 &cfg);
1013 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
1014 fe->ops.tuner_ops.set_config(fe, &ctl);
1015 }
96318d0c 1016 break;
0cf8af57 1017 case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000:
1018 i2c_bus = &dev->i2c_bus[0];
1019
1020 fe0->dvb.frontend = dvb_attach(zl10353_attach,
1021 &dvico_fusionhdtv_xc3028,
1022 &i2c_bus->i2c_adap);
1023 if (fe0->dvb.frontend != NULL) {
1024 struct dvb_frontend *fe;
1025 struct xc4000_config cfg = {
1026 .i2c_address = 0x61,
1027 .default_pm = 0,
1028 .dvb_amplitude = 134,
1029 .set_smoothedcvbs = 1,
1030 .if_khz = 4560
1031 };
1032
1033 fe = dvb_attach(xc4000_attach, fe0->dvb.frontend,
1034 &dev->i2c_bus[1].i2c_adap, &cfg);
a7c8aada
MS
1035 if (!fe) {
1036 printk(KERN_ERR "%s/2: xc4000 attach failed\n",
1037 dev->name);
1038 goto frontend_detach;
1039 }
0cf8af57 1040 }
1041 break;
96318d0c 1042 case CX23885_BOARD_TBS_6920:
09ea33e5 1043 i2c_bus = &dev->i2c_bus[1];
96318d0c
IL
1044
1045 fe0->dvb.frontend = dvb_attach(cx24116_attach,
09ea33e5
IL
1046 &tbs_cx24116_config,
1047 &i2c_bus->i2c_adap);
96318d0c 1048 if (fe0->dvb.frontend != NULL)
09ea33e5 1049 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
96318d0c 1050
579943f5 1051 break;
e6001482
LA
1052 case CX23885_BOARD_TBS_6980:
1053 case CX23885_BOARD_TBS_6981:
1054 i2c_bus = &dev->i2c_bus[1];
1055
1056 switch (port->nr) {
1057 /* PORT B */
1058 case 1:
1059 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1060 &tbs_cx24117_config,
1061 &i2c_bus->i2c_adap, NULL);
1062 break;
1063 /* PORT C */
1064 case 2:
1065 /* use fe1 pointer as temporary holder */
1066 /* for the first frontend */
1067 fe1 = videobuf_dvb_get_frontend(
1068 &port->dev->ts1.frontends, 1);
1069
1070 fe0->dvb.frontend = dvb_attach(cx24117_attach,
1071 &tbs_cx24117_config,
1072 &i2c_bus->i2c_adap, fe1->dvb.frontend);
1073 /* we're done, so clear fe1 pointer */
1074 fe1 = NULL;
1075 break;
1076 }
1077 break;
579943f5
IL
1078 case CX23885_BOARD_TEVII_S470:
1079 i2c_bus = &dev->i2c_bus[1];
1080
09ea33e5
IL
1081 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1082 &tevii_ds3000_config,
1083 &i2c_bus->i2c_adap);
73f0af44
KD
1084 if (fe0->dvb.frontend != NULL) {
1085 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1086 &tevii_ts2020_config, &i2c_bus->i2c_adap);
09ea33e5 1087 fe0->dvb.frontend->ops.set_voltage = f300_set_voltage;
73f0af44 1088 }
579943f5 1089
4c56b04a 1090 break;
c9b8b04b
IL
1091 case CX23885_BOARD_DVBWORLD_2005:
1092 i2c_bus = &dev->i2c_bus[1];
1093
1094 fe0->dvb.frontend = dvb_attach(cx24116_attach,
1095 &dvbworld_cx24116_config,
1096 &i2c_bus->i2c_adap);
1097 break;
5a23b076
IL
1098 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1099 i2c_bus = &dev->i2c_bus[0];
1100 switch (port->nr) {
1101 /* port B */
1102 case 1:
1103 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1104 &netup_stv0900_config,
1105 &i2c_bus->i2c_adap, 0);
1106 if (fe0->dvb.frontend != NULL) {
1107 if (dvb_attach(stv6110_attach,
1108 fe0->dvb.frontend,
1109 &netup_stv6110_tunerconfig_a,
1110 &i2c_bus->i2c_adap)) {
1111 if (!dvb_attach(lnbh24_attach,
1112 fe0->dvb.frontend,
1113 &i2c_bus->i2c_adap,
9329fb5b
AO
1114 LNBH24_PCL | LNBH24_TTX,
1115 LNBH24_TEN, 0x09))
5a23b076
IL
1116 printk(KERN_ERR
1117 "No LNBH24 found!\n");
1118
1119 }
1120 }
1121 break;
1122 /* port C */
1123 case 2:
1124 fe0->dvb.frontend = dvb_attach(stv0900_attach,
1125 &netup_stv0900_config,
1126 &i2c_bus->i2c_adap, 1);
1127 if (fe0->dvb.frontend != NULL) {
1128 if (dvb_attach(stv6110_attach,
1129 fe0->dvb.frontend,
1130 &netup_stv6110_tunerconfig_b,
1131 &i2c_bus->i2c_adap)) {
1132 if (!dvb_attach(lnbh24_attach,
1133 fe0->dvb.frontend,
1134 &i2c_bus->i2c_adap,
9329fb5b
AO
1135 LNBH24_PCL | LNBH24_TTX,
1136 LNBH24_TEN, 0x0a))
5a23b076
IL
1137 printk(KERN_ERR
1138 "No LNBH24 found!\n");
1139
1140 }
1141 }
1142 break;
1143 }
1144 break;
493b7127
DW
1145 case CX23885_BOARD_MYGICA_X8506:
1146 i2c_bus = &dev->i2c_bus[0];
1147 i2c_bus2 = &dev->i2c_bus[1];
1148 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1149 &mygica_x8506_lgs8gl5_config,
1150 &i2c_bus->i2c_adap);
1151 if (fe0->dvb.frontend != NULL) {
1152 dvb_attach(xc5000_attach,
1153 fe0->dvb.frontend,
1154 &i2c_bus2->i2c_adap,
1155 &mygica_x8506_xc5000_config);
1156 }
15472faf 1157 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
493b7127 1158 break;
0d1b5265
MCC
1159 case CX23885_BOARD_MYGICA_X8507:
1160 i2c_bus = &dev->i2c_bus[0];
1161 i2c_bus2 = &dev->i2c_bus[1];
1162 fe0->dvb.frontend = dvb_attach(mb86a20s_attach,
1163 &mygica_x8507_mb86a20s_config,
1164 &i2c_bus->i2c_adap);
1165 if (fe0->dvb.frontend != NULL) {
1166 dvb_attach(xc5000_attach,
1167 fe0->dvb.frontend,
1168 &i2c_bus2->i2c_adap,
1169 &mygica_x8507_xc5000_config);
1170 }
1171 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
1172 break;
2365b2d3
DW
1173 case CX23885_BOARD_MAGICPRO_PROHDTVE2:
1174 i2c_bus = &dev->i2c_bus[0];
1175 i2c_bus2 = &dev->i2c_bus[1];
1176 fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
1177 &magicpro_prohdtve2_lgs8g75_config,
1178 &i2c_bus->i2c_adap);
1179 if (fe0->dvb.frontend != NULL) {
1180 dvb_attach(xc5000_attach,
1181 fe0->dvb.frontend,
1182 &i2c_bus2->i2c_adap,
1183 &magicpro_prohdtve2_xc5000_config);
1184 }
15472faf 1185 cx23885_set_frontend_hook(port, fe0->dvb.frontend);
2365b2d3 1186 break;
13697380 1187 case CX23885_BOARD_HAUPPAUGE_HVR1850:
35045137
ST
1188 i2c_bus = &dev->i2c_bus[0];
1189 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1190 &hcw_s5h1411_config,
1191 &i2c_bus->i2c_adap);
1192 if (fe0->dvb.frontend != NULL)
1193 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1194 0x60, &dev->i2c_bus[0].i2c_adap,
1195 &hauppauge_tda18271_config);
1196
1197 tda18271_attach(&dev->ts1.analog_fe,
1198 0x60, &dev->i2c_bus[1].i2c_adap,
1199 &hauppauge_tda18271_config);
1200
1201 break;
aee0b24c 1202 case CX23885_BOARD_HAUPPAUGE_HVR1290:
13697380
ST
1203 i2c_bus = &dev->i2c_bus[0];
1204 fe0->dvb.frontend = dvb_attach(s5h1411_attach,
1205 &hcw_s5h1411_config,
1206 &i2c_bus->i2c_adap);
1207 if (fe0->dvb.frontend != NULL)
1208 dvb_attach(tda18271_attach, fe0->dvb.frontend,
1209 0x60, &dev->i2c_bus[0].i2c_adap,
1210 &hauppauge_tda18271_config);
1211 break;
ea5697fe
DW
1212 case CX23885_BOARD_MYGICA_X8558PRO:
1213 switch (port->nr) {
1214 /* port B */
1215 case 1:
1216 i2c_bus = &dev->i2c_bus[0];
1217 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1218 &mygica_x8558pro_atbm8830_cfg1,
1219 &i2c_bus->i2c_adap);
1220 if (fe0->dvb.frontend != NULL) {
1221 dvb_attach(max2165_attach,
1222 fe0->dvb.frontend,
1223 &i2c_bus->i2c_adap,
1224 &mygic_x8558pro_max2165_cfg1);
1225 }
1226 break;
1227 /* port C */
1228 case 2:
1229 i2c_bus = &dev->i2c_bus[1];
1230 fe0->dvb.frontend = dvb_attach(atbm8830_attach,
1231 &mygica_x8558pro_atbm8830_cfg2,
1232 &i2c_bus->i2c_adap);
1233 if (fe0->dvb.frontend != NULL) {
1234 dvb_attach(max2165_attach,
1235 fe0->dvb.frontend,
1236 &i2c_bus->i2c_adap,
1237 &mygic_x8558pro_max2165_cfg2);
1238 }
1239 break;
1240 }
1241 break;
78db8547
IL
1242 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1243 i2c_bus = &dev->i2c_bus[0];
1244 mfe_shared = 1;/* MFE */
1245 port->frontends.gate = 0;/* not clear for me yet */
1246 /* ports B, C */
1247 /* MFE frontend 1 DVB-T */
1248 fe0->dvb.frontend = dvb_attach(stv0367ter_attach,
1249 &netup_stv0367_config[port->nr - 1],
1250 &i2c_bus->i2c_adap);
4174ebf5 1251 if (fe0->dvb.frontend != NULL) {
78db8547
IL
1252 if (NULL == dvb_attach(xc5000_attach,
1253 fe0->dvb.frontend,
1254 &i2c_bus->i2c_adap,
1255 &netup_xc5000_config[port->nr - 1]))
1256 goto frontend_detach;
4174ebf5
AO
1257 /* load xc5000 firmware */
1258 fe0->dvb.frontend->ops.tuner_ops.init(fe0->dvb.frontend);
1259 }
78db8547
IL
1260 /* MFE frontend 2 */
1261 fe1 = videobuf_dvb_get_frontend(&port->frontends, 2);
1262 if (fe1 == NULL)
1263 goto frontend_detach;
1264 /* DVB-C init */
1265 fe1->dvb.frontend = dvb_attach(stv0367cab_attach,
1266 &netup_stv0367_config[port->nr - 1],
1267 &i2c_bus->i2c_adap);
1268 if (fe1->dvb.frontend != NULL) {
1269 fe1->dvb.frontend->id = 1;
1270 if (NULL == dvb_attach(xc5000_attach,
1271 fe1->dvb.frontend,
1272 &i2c_bus->i2c_adap,
1273 &netup_xc5000_config[port->nr - 1]))
1274 goto frontend_detach;
1275 }
1276 break;
722c90eb
SR
1277 case CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL:
1278 i2c_bus = &dev->i2c_bus[0];
1279 i2c_bus2 = &dev->i2c_bus[1];
1280
1281 switch (port->nr) {
1282 /* port b */
1283 case 1:
1284 fe0->dvb.frontend = dvb_attach(drxk_attach,
1285 &terratec_drxk_config[0],
1286 &i2c_bus->i2c_adap);
1287 if (fe0->dvb.frontend != NULL) {
1288 if (!dvb_attach(mt2063_attach,
1289 fe0->dvb.frontend,
1290 &terratec_mt2063_config[0],
1291 &i2c_bus2->i2c_adap))
1292 goto frontend_detach;
1293 }
1294 break;
1295 /* port c */
1296 case 2:
1297 fe0->dvb.frontend = dvb_attach(drxk_attach,
1298 &terratec_drxk_config[1],
1299 &i2c_bus->i2c_adap);
1300 if (fe0->dvb.frontend != NULL) {
1301 if (!dvb_attach(mt2063_attach,
1302 fe0->dvb.frontend,
1303 &terratec_mt2063_config[1],
1304 &i2c_bus2->i2c_adap))
1305 goto frontend_detach;
1306 }
1307 break;
1308 }
1309 break;
7b134e85
IL
1310 case CX23885_BOARD_TEVII_S471:
1311 i2c_bus = &dev->i2c_bus[1];
1312
1313 fe0->dvb.frontend = dvb_attach(ds3000_attach,
1314 &tevii_ds3000_config,
1315 &i2c_bus->i2c_adap);
b43ea806
JK
1316 if (fe0->dvb.frontend != NULL) {
1317 dvb_attach(ts2020_attach, fe0->dvb.frontend,
1318 &tevii_ts2020_config, &i2c_bus->i2c_adap);
1319 }
7b134e85 1320 break;
f667190b
MB
1321 case CX23885_BOARD_PROF_8000:
1322 i2c_bus = &dev->i2c_bus[0];
1323
1324 fe0->dvb.frontend = dvb_attach(stv090x_attach,
1325 &prof_8000_stv090x_config,
1326 &i2c_bus->i2c_adap,
1327 STV090x_DEMODULATOR_0);
1328 if (fe0->dvb.frontend != NULL) {
1329 if (!dvb_attach(stb6100_attach,
1330 fe0->dvb.frontend,
1331 &prof_8000_stb6100_config,
1332 &i2c_bus->i2c_adap))
1333 goto frontend_detach;
1334
1335 fe0->dvb.frontend->ops.set_voltage = p8000_set_voltage;
1336 }
1337 break;
7c62f5a1
MK
1338 case CX23885_BOARD_HAUPPAUGE_HVR4400:
1339 i2c_bus = &dev->i2c_bus[0];
1340 fe0->dvb.frontend = dvb_attach(tda10071_attach,
1341 &hauppauge_tda10071_config,
1342 &i2c_bus->i2c_adap);
1343 if (fe0->dvb.frontend != NULL) {
1344 dvb_attach(a8293_attach, fe0->dvb.frontend,
1345 &i2c_bus->i2c_adap,
1346 &hauppauge_a8293_config);
1347 }
1348 break;
d19770e5 1349 default:
9c8ced51
ST
1350 printk(KERN_INFO "%s: The frontend of your DVB/ATSC card "
1351 " isn't supported yet\n",
d19770e5
ST
1352 dev->name);
1353 break;
1354 }
78db8547
IL
1355
1356 if ((NULL == fe0->dvb.frontend) || (fe1 && NULL == fe1->dvb.frontend)) {
9c8ced51 1357 printk(KERN_ERR "%s: frontend initialization failed\n",
78db8547
IL
1358 dev->name);
1359 goto frontend_detach;
d19770e5 1360 }
78db8547 1361
d7cba043 1362 /* define general-purpose callback pointer */
363c35fc 1363 fe0->dvb.frontend->callback = cx23885_tuner_callback;
78db8547
IL
1364 if (fe1)
1365 fe1->dvb.frontend->callback = cx23885_tuner_callback;
1366#if 0
1367 /* Ensure all frontends negotiate bus access */
1368 fe0->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1369 if (fe1)
1370 fe1->dvb.frontend->ops.ts_bus_ctrl = cx23885_dvb_bus_ctrl;
1371#endif
d19770e5
ST
1372
1373 /* Put the analog decoder in standby to keep it quiet */
622b828a 1374 call_all(dev, core, s_power, 0);
d19770e5 1375
363c35fc
ST
1376 if (fe0->dvb.frontend->ops.analog_ops.standby)
1377 fe0->dvb.frontend->ops.analog_ops.standby(fe0->dvb.frontend);
3ba71d21 1378
d19770e5 1379 /* register everything */
5a23b076 1380 ret = videobuf_dvb_register_bus(&port->frontends, THIS_MODULE, port,
9adf6132 1381 &dev->pci->dev, adapter_nr, mfe_shared);
bee30192 1382 if (ret)
78db8547 1383 goto frontend_detach;
363c35fc 1384
5a23b076
IL
1385 /* init CI & MAC */
1386 switch (dev->board) {
1387 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI: {
1388 static struct netup_card_info cinfo;
1389
1390 netup_get_card_info(&dev->i2c_bus[0].i2c_adap, &cinfo);
1391 memcpy(port->frontends.adapter.proposed_mac,
1392 cinfo.port[port->nr - 1].mac, 6);
be395157 1393 printk(KERN_INFO "NetUP Dual DVB-S2 CI card port%d MAC=%pM\n",
1394 port->nr, port->frontends.adapter.proposed_mac);
5a23b076
IL
1395
1396 netup_ci_init(port);
1397 break;
1398 }
78db8547
IL
1399 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF: {
1400 struct altera_ci_config netup_ci_cfg = {
1401 .dev = dev,/* magic number to identify*/
1402 .adapter = &port->frontends.adapter,/* for CI */
1403 .demux = &fe0->dvb.demux,/* for hw pid filter */
1404 .fpga_rw = netup_altera_fpga_rw,
1405 };
1406
1407 altera_ci_init(&netup_ci_cfg, port->nr);
1408 break;
1409 }
16bfdaa4
PG
1410 case CX23885_BOARD_TEVII_S470: {
1411 u8 eeprom[256]; /* 24C02 i2c eeprom */
1412
1413 if (port->nr != 1)
1414 break;
1415
1416 /* Read entire EEPROM */
1417 dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
1418 tveeprom_read(&dev->i2c_bus[0].i2c_client, eeprom, sizeof(eeprom));
5cac1f66 1419 printk(KERN_INFO "TeVii S470 MAC= %pM\n", eeprom + 0xa0);
16bfdaa4
PG
1420 memcpy(port->frontends.adapter.proposed_mac, eeprom + 0xa0, 6);
1421 break;
1422 }
5a23b076
IL
1423 }
1424
1425 return ret;
78db8547
IL
1426
1427frontend_detach:
1428 port->gate_ctrl = NULL;
1429 videobuf_dvb_dealloc_frontends(&port->frontends);
1430 return -EINVAL;
d19770e5
ST
1431}
1432
1433int cx23885_dvb_register(struct cx23885_tsport *port)
1434{
363c35fc
ST
1435
1436 struct videobuf_dvb_frontend *fe0;
d19770e5 1437 struct cx23885_dev *dev = port->dev;
eb0c58bb
ST
1438 int err, i;
1439
1440 /* Here we need to allocate the correct number of frontends,
af901ca1 1441 * as reflected in the cards struct. The reality is that currently
eb0c58bb
ST
1442 * no cx23885 boards support this - yet. But, if we don't modify this
1443 * code then the second frontend would never be allocated (later)
1444 * and fail with error before the attach in dvb_register().
1445 * Without these changes we risk an OOPS later. The changes here
1446 * are for safety, and should provide a good foundation for the
1447 * future addition of any multi-frontend cx23885 based boards.
1448 */
1449 printk(KERN_INFO "%s() allocating %d frontend(s)\n", __func__,
1450 port->num_frontends);
d19770e5 1451
eb0c58bb 1452 for (i = 1; i <= port->num_frontends; i++) {
96b7a1a8 1453 if (videobuf_dvb_alloc_frontend(
9c8ced51 1454 &port->frontends, i) == NULL) {
eb0c58bb
ST
1455 printk(KERN_ERR "%s() failed to alloc\n", __func__);
1456 return -ENOMEM;
1457 }
1458
1459 fe0 = videobuf_dvb_get_frontend(&port->frontends, i);
1460 if (!fe0)
1461 err = -EINVAL;
363c35fc 1462
eb0c58bb 1463 dprintk(1, "%s\n", __func__);
9c8ced51 1464 dprintk(1, " ->probed by Card=%d Name=%s, PCI %02x:%02x\n",
eb0c58bb
ST
1465 dev->board,
1466 dev->name,
1467 dev->pci_bus,
1468 dev->pci_slot);
d19770e5 1469
eb0c58bb 1470 err = -ENODEV;
d19770e5 1471
eb0c58bb
ST
1472 /* dvb stuff */
1473 /* We have to init the queue for each frontend on a port. */
9c8ced51
ST
1474 printk(KERN_INFO "%s: cx23885 based dvb card\n", dev->name);
1475 videobuf_queue_sg_init(&fe0->dvb.dvbq, &dvb_qops,
1476 &dev->pci->dev, &port->slock,
44a6481d 1477 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
08bff03e 1478 sizeof(struct cx23885_buffer), port, NULL);
eb0c58bb 1479 }
d19770e5
ST
1480 err = dvb_register(port);
1481 if (err != 0)
9c8ced51
ST
1482 printk(KERN_ERR "%s() dvb_register failed err = %d\n",
1483 __func__, err);
d19770e5 1484
d19770e5
ST
1485 return err;
1486}
1487
1488int cx23885_dvb_unregister(struct cx23885_tsport *port)
1489{
363c35fc
ST
1490 struct videobuf_dvb_frontend *fe0;
1491
eb0c58bb
ST
1492 /* FIXME: in an error condition where the we have
1493 * an expected number of frontends (attach problem)
1494 * then this might not clean up correctly, if 1
1495 * is invalid.
1496 * This comment only applies to future boards IF they
1497 * implement MFE support.
1498 */
92abe9ee 1499 fe0 = videobuf_dvb_get_frontend(&port->frontends, 1);
e66131ce 1500 if (fe0 && fe0->dvb.frontend)
363c35fc 1501 videobuf_dvb_unregister_bus(&port->frontends);
d19770e5 1502
afd96668
HV
1503 switch (port->dev->board) {
1504 case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
1505 netup_ci_exit(port);
1506 break;
78db8547
IL
1507 case CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF:
1508 altera_ci_release(port->dev, port->nr);
1509 break;
afd96668 1510 }
5a23b076 1511
78db8547
IL
1512 port->gate_ctrl = NULL;
1513
d19770e5
ST
1514 return 0;
1515}
44a6481d 1516
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