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[media] cx23885: convert to vb2
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
d19770e5
ST		 16 */
17
18#include <linux/pci.h>
19#include <linux/i2c.h>
d19770e5 20#include <linux/kdev_t.h>
5a0e3ad6 21#include <linux/slab.h>
d19770e5 22
c0714f6c 23#include <media/v4l2-device.h>
86dd9831 24#include <media/v4l2-fh.h>
da59a4de 25#include <media/v4l2-ctrls.h>
d19770e5
ST		 26#include <media/tuner.h>
27#include <media/tveeprom.h>
453afdd9
HV		 28#include <media/videobuf2-dma-sg.h>
29#include <media/videobuf2-dvb.h>
6bda9644 30#include <media/rc-core.h>
d19770e5
ST		 31
32#include "btcx-risc.h"
33#include "cx23885-reg.h"
b1b81f1d 34#include "media/cx2341x.h"
d19770e5 35
d19770e5
ST		 36#include <linux/mutex.h>
37
453afdd9 38#define CX23885_VERSION "0.0.4"
d19770e5
ST		 39
40#define UNSET (-1U)
41
42#define CX23885_MAXBOARDS 8
43
d19770e5
ST		 44/* Max number of inputs by card */
45#define MAX_CX23885_INPUT 8
7b888014 46#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
d19770e5 47
d19770e5
ST		 48#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
49
50#define CX23885_BOARD_NOAUTO UNSET
51#define CX23885_BOARD_UNKNOWN 0
52#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
53#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 54#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 55#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 56#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 57#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 58#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 59#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 60#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 61#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 62#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 63#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 64#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 65#define CX23885_BOARD_TBS_6920 14
579943f5 66#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 67#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 68#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 69#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 70#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 71#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 72#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 73#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 74#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 75#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 76#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 77#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 78#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 79#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 80#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 81#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
0cf8af57 82#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
2cb9ccd4 83#define CX23885_BOARD_MPX885 32
87988753 84#define CX23885_BOARD_MYGICA_X8507 33
722c90eb 85#define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
7b134e85 86#define CX23885_BOARD_TEVII_S471 35
0ac60acb 87#define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
f667190b 88#define CX23885_BOARD_PROF_8000 37
7c62f5a1 89#define CX23885_BOARD_HAUPPAUGE_HVR4400 38
e8d42373 90#define CX23885_BOARD_AVERMEDIA_HC81R 39
e6001482
LA		 91#define CX23885_BOARD_TBS_6981 40
92#define CX23885_BOARD_TBS_6980 41
642ca1a0 93#define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
cce11b09 94#define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
46b21bba 95#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44
d19770e5 96
6f8bee9b
ST		 97#define GPIO_0 0x00000001
98#define GPIO_1 0x00000002
99#define GPIO_2 0x00000004
100#define GPIO_3 0x00000008
101#define GPIO_4 0x00000010
102#define GPIO_5 0x00000020
103#define GPIO_6 0x00000040
104#define GPIO_7 0x00000080
105#define GPIO_8 0x00000100
106#define GPIO_9 0x00000200
f659c513
ST		 107#define GPIO_10 0x00000400
108#define GPIO_11 0x00000800
109#define GPIO_12 0x00001000
110#define GPIO_13 0x00002000
111#define GPIO_14 0x00004000
112#define GPIO_15 0x00008000
6f8bee9b 113
7b888014
ST		 114/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
115#define CX23885_NORMS (\
116 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
117 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
118 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
119 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
120
121struct cx23885_fmt {
122 char *name;
123 u32 fourcc; /* v4l2 format id */
124 int depth;
125 int flags;
126 u32 cxformat;
127};
128
7b888014
ST		 129struct cx23885_tvnorm {
130 char *name;
131 v4l2_std_id id;
132 u32 cxiformat;
133 u32 cxoformat;
134};
135
d19770e5
ST		 136enum cx23885_itype {
137 CX23885_VMUX_COMPOSITE1 = 1,
138 CX23885_VMUX_COMPOSITE2,
139 CX23885_VMUX_COMPOSITE3,
140 CX23885_VMUX_COMPOSITE4,
141 CX23885_VMUX_SVIDEO,
dac65fa1 142 CX23885_VMUX_COMPONENT,
d19770e5
ST		 143 CX23885_VMUX_TELEVISION,
144 CX23885_VMUX_CABLE,
145 CX23885_VMUX_DVB,
146 CX23885_VMUX_DEBUG,
147 CX23885_RADIO,
148};
149
579f1163
ST		 150enum cx23885_src_sel_type {
151 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
152 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
153};
154
d19770e5
ST		 155/* buffer for one video frame */
156struct cx23885_buffer {
157 /* common v4l buffer stuff -- must be first */
453afdd9
HV		 158 struct vb2_buffer vb;
159 struct list_head queue;
d19770e5
ST		 160
161 /* cx23885 specific */
162 unsigned int bpl;
163 struct btcx_riscmem risc;
164 struct cx23885_fmt *fmt;
165 u32 count;
166};
167
168struct cx23885_input {
169 enum cx23885_itype type;
170 unsigned int vmux;
8304be88 171 unsigned int amux;
d19770e5
ST		 172 u32 gpio0, gpio1, gpio2, gpio3;
173};
174
661c7e44
ST		 175typedef enum {
176 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 177 CX23885_MPEG_DVB,
178 CX23885_ANALOG_VIDEO,
b1b81f1d 179 CX23885_MPEG_ENCODER,
661c7e44
ST		 180} port_t;
181
d19770e5
ST		 182struct cx23885_board {
183 char *name;
7b888014 184 port_t porta, portb, portc;
10d0dcd7 185 int num_fds_portb, num_fds_portc;
7b888014
ST		 186 unsigned int tuner_type;
187 unsigned int radio_type;
188 unsigned char tuner_addr;
189 unsigned char radio_addr;
557f48d5 190 unsigned int tuner_bus;
c7712613
ST		 191
192 /* Vendors can and do run the PCIe bridge at different
193 * clock rates, driven physically by crystals on the PCBs.
25985edc 194 * The core has to accommodate this. This allows the user
c7712613
ST		 195 * to add new boards with new frequencys. The value is
196 * expressed in Hz.
197 *
198 * The core framework will default this value based on
199 * current designs, but it can vary.
200 */
201 u32 clk_freq;
d19770e5 202 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 203 int ci_type; /* for NetUP */
35045137
ST		 204 /* Force bottom field first during DMA (888 workaround) */
205 u32 force_bff;
d19770e5
ST		 206};
207
208struct cx23885_subid {
209 u16 subvendor;
210 u16 subdevice;
211 u32 card;
212};
213
214struct cx23885_i2c {
215 struct cx23885_dev *dev;
216
217 int nr;
218
219 /* i2c i/o */
220 struct i2c_adapter i2c_adap;
d19770e5
ST		 221 struct i2c_client i2c_client;
222 u32 i2c_rc;
223
224 /* 885 registers used for raw addess */
225 u32 i2c_period;
226 u32 reg_ctrl;
227 u32 reg_stat;
228 u32 reg_addr;
229 u32 reg_rdata;
230 u32 reg_wdata;
231};
232
233struct cx23885_dmaqueue {
234 struct list_head active;
d19770e5
ST		 235 u32 count;
236};
237
238struct cx23885_tsport {
239 struct cx23885_dev *dev;
240
241 int nr;
242 int sram_chno;
243
453afdd9 244 struct vb2_dvb_frontends frontends;
d19770e5
ST		 245
246 /* dma queues */
247 struct cx23885_dmaqueue mpegq;
248 u32 ts_packet_size;
249 u32 ts_packet_count;
250
251 int width;
252 int height;
253
254 spinlock_t slock;
255
256 /* registers */
257 u32 reg_gpcnt;
258 u32 reg_gpcnt_ctl;
259 u32 reg_dma_ctl;
260 u32 reg_lngth;
261 u32 reg_hw_sop_ctrl;
262 u32 reg_gen_ctrl;
263 u32 reg_bd_pkt_status;
264 u32 reg_sop_status;
265 u32 reg_fifo_ovfl_stat;
266 u32 reg_vld_misc;
267 u32 reg_ts_clk_en;
268 u32 reg_ts_int_msk;
a6a3f140 269 u32 reg_ts_int_stat;
579f1163 270 u32 reg_src_sel;
d19770e5
ST		 271
272 /* Default register vals */
273 int pci_irqmask;
274 u32 dma_ctl_val;
275 u32 ts_int_msk_val;
276 u32 gen_ctrl_val;
277 u32 ts_clk_en_val;
579f1163 278 u32 src_sel_val;
b1b81f1d
ST		 279 u32 vld_misc_val;
280 u32 hw_sop_ctrl_val;
a739a7e4
ST		 281
282 /* Allow a single tsport to have multiple frontends */
283 u32 num_frontends;
78db8547 284 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 285 void *port_priv;
35045137
ST		 286
287 /* Workaround for a temp dvb_frontend that the tuner can attached to */
288 struct dvb_frontend analog_fe;
15472faf
MCC		 289
290 int (*set_frontend)(struct dvb_frontend *fe);
d19770e5
ST		 291};
292
43c24078
AW		 293struct cx23885_kernel_ir {
294 struct cx23885_dev *cx;
eeefae53
AW		 295 char *name;
296 char *phys;
297
d8b4b582 298 struct rc_dev *rc;
eeefae53
AW		 299};
300
9e44d632
MM		 301struct cx23885_audio_buffer {
302 unsigned int bpl;
303 struct btcx_riscmem risc;
9529a4b0
HV		 304 void *vaddr;
305 struct scatterlist *sglist;
306 int sglen;
307 int nr_pages;
9e44d632
MM		 308};
309
310struct cx23885_audio_dev {
311 struct cx23885_dev *dev;
312
313 struct pci_dev *pci;
314
315 struct snd_card *card;
316
317 spinlock_t lock;
318
319 atomic_t count;
320
321 unsigned int dma_size;
322 unsigned int period_size;
323 unsigned int num_periods;
324
9e44d632
MM		 325 struct cx23885_audio_buffer *buf;
326
327 struct snd_pcm_substream *substream;
328};
329
d19770e5 330struct cx23885_dev {
d19770e5 331 atomic_t refcount;
c0714f6c 332 struct v4l2_device v4l2_dev;
da59a4de 333 struct v4l2_ctrl_handler ctrl_handler;
d19770e5
ST		 334
335 /* pci stuff */
336 struct pci_dev *pci;
337 unsigned char pci_rev, pci_lat;
338 int pci_bus, pci_slot;
339 u32 __iomem *lmmio;
340 u8 __iomem *bmmio;
d19770e5 341 int pci_irqmask;
dbe83a3b 342 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 343 int hwrevision;
d19770e5 344
c7712613
ST		 345 /* This valud is board specific and is used to configure the
346 * AV core so we see nice clean and stable video and audio. */
347 u32 clk_freq;
348
44a6481d 349 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 350 struct cx23885_i2c i2c_bus[3];
351
352 int nr;
353 struct mutex lock;
8386c27f 354 struct mutex gpio_lock;
d19770e5
ST		 355
356 /* board details */
357 unsigned int board;
358 char name[32];
359
a6a3f140 360 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 361
362 /* sram configuration */
363 struct sram_channel *sram_channels;
e133be0f
ST		 364
365 enum {
366 CX23885_BRIDGE_UNDEFINED = 0,
367 CX23885_BRIDGE_885 = 885,
368 CX23885_BRIDGE_887 = 887,
25ea66e2 369 CX23885_BRIDGE_888 = 888,
e133be0f 370 } bridge;
7b888014
ST		 371
372 /* Analog video */
7b888014 373 unsigned int input;
fc1a889d 374 unsigned int audinput; /* Selectable audio input */
7b888014
ST		 375 u32 tvaudio;
376 v4l2_std_id tvnorm;
377 unsigned int tuner_type;
378 unsigned char tuner_addr;
557f48d5 379 unsigned int tuner_bus;
7b888014
ST		 380 unsigned int radio_type;
381 unsigned char radio_addr;
0d5a19f1 382 struct v4l2_subdev *sd_cx25840;
e5514f10 383 struct work_struct cx25840_work;
f59ad611
AW		 384
385 /* Infrared */
386 struct v4l2_subdev *sd_ir;
387 struct work_struct ir_rx_work;
388 unsigned long ir_rx_notifications;
389 struct work_struct ir_tx_work;
390 unsigned long ir_tx_notifications;
7b888014 391
43c24078 392 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 393 atomic_t ir_input_stopping;
394
7b888014
ST		 395 /* V4l */
396 u32 freq;
397 struct video_device *video_dev;
398 struct video_device *vbi_dev;
7b888014 399
91d2d674
HV		 400 /* video capture */
401 struct cx23885_fmt *fmt;
402 unsigned int width, height;
453afdd9 403 unsigned field;
91d2d674 404
7b888014 405 struct cx23885_dmaqueue vidq;
453afdd9 406 struct vb2_queue vb2_vidq;
7b888014 407 struct cx23885_dmaqueue vbiq;
453afdd9
HV		 408 struct vb2_queue vb2_vbiq;
409
7b888014 410 spinlock_t slock;
b1b81f1d
ST		 411
412 /* MPEG Encoder ONLY settings */
413 u32 cx23417_mailbox;
5150392c 414 struct cx2341x_handler cxhdl;
b1b81f1d 415 struct video_device *v4l_device;
453afdd9 416 struct vb2_queue vb2_mpegq;
b1b81f1d
ST		 417 struct cx23885_tvnorm encodernorm;
418
9e44d632
MM		 419 /* Analog raw audio */
420 struct cx23885_audio_dev *audio_dev;
421
d19770e5
ST		 422};
423
c0714f6c
HV		 424static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
425{
426 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
427}
428
0d5a19f1
HV		 429#define call_all(dev, o, f, args...) \
430 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
431
d6b1850d
AW		 432#define CX23885_HW_888_IR (1 << 0)
433#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 434
435#define call_hw(dev, grpid, o, f, args...) \
436 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
437
438extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
439
d19770e5
ST		 440#define SRAM_CH01 0 /* Video A */
441#define SRAM_CH02 1 /* VBI A */
442#define SRAM_CH03 2 /* Video B */
443#define SRAM_CH04 3 /* Transport via B */
444#define SRAM_CH05 4 /* VBI B */
445#define SRAM_CH06 5 /* Video C */
446#define SRAM_CH07 6 /* Transport via C */
447#define SRAM_CH08 7 /* Audio Internal A */
448#define SRAM_CH09 8 /* Audio Internal B */
449#define SRAM_CH10 9 /* Audio External */
450#define SRAM_CH11 10 /* COMB_3D_N */
451#define SRAM_CH12 11 /* Comb 3D N1 */
452#define SRAM_CH13 12 /* Comb 3D N2 */
453#define SRAM_CH14 13 /* MOE Vid */
454#define SRAM_CH15 14 /* MOE RSLT */
455
456struct sram_channel {
457 char *name;
458 u32 cmds_start;
459 u32 ctrl_start;
460 u32 cdt;
1ebcad77 461 u32 fifo_start;
d19770e5
ST		 462 u32 fifo_size;
463 u32 ptr1_reg;
464 u32 ptr2_reg;
465 u32 cnt1_reg;
466 u32 cnt2_reg;
467 u32 jumponly;
468};
469
470/* ----------------------------------------------------------- */
471
472#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 473#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 474
9c8ced51 475#define cx_andor(reg, mask, value) \
d19770e5
ST		 476 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
477 ((value) & (mask)), dev->lmmio+((reg)>>2))
478
9c8ced51
ST		 479#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
480#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 481
d19770e5 482/* ----------------------------------------------------------- */
7b888014
ST		 483/* cx23885-core.c */
484
485extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
486 struct sram_channel *ch,
487 unsigned int bpl, u32 risc);
488
489extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
490 struct sram_channel *ch);
d19770e5 491
7b888014
ST		 492extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
493 struct scatterlist *sglist,
494 unsigned int top_offset, unsigned int bottom_offset,
495 unsigned int bpl, unsigned int padding, unsigned int lines);
496
5ab27e6d
ST		 497extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
498 struct btcx_riscmem *risc, struct scatterlist *sglist,
499 unsigned int top_offset, unsigned int bottom_offset,
500 unsigned int bpl, unsigned int padding, unsigned int lines);
501
453afdd9
HV		 502int cx23885_start_dma(struct cx23885_tsport *port,
503 struct cx23885_dmaqueue *q,
504 struct cx23885_buffer *buf);
7b888014
ST		 505void cx23885_cancel_buffers(struct cx23885_tsport *port);
506
7b888014 507
6f8bee9b
ST		 508extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
509extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 510extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 511extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
512 int asoutput);
513
dbe83a3b
AW		 514extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
515extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
516extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
517extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
7b888014
ST		 518
519/* ----------------------------------------------------------- */
520/* cx23885-cards.c */
d19770e5
ST		 521extern struct cx23885_board cx23885_boards[];
522extern const unsigned int cx23885_bcount;
523
524extern struct cx23885_subid cx23885_subids[];
525extern const unsigned int cx23885_idcount;
526
9c8ced51
ST		 527extern int cx23885_tuner_callback(void *priv, int component,
528 int command, int arg);
d19770e5 529extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 530extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 531extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
532extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 533extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5
ST		 534extern void cx23885_card_setup(struct cx23885_dev *dev);
535extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
536
537extern int cx23885_dvb_register(struct cx23885_tsport *port);
538extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
539
453afdd9
HV		 540extern int cx23885_buf_prepare(struct cx23885_buffer *buf,
541 struct cx23885_tsport *port);
44a6481d
MK		 542extern void cx23885_buf_queue(struct cx23885_tsport *port,
543 struct cx23885_buffer *buf);
453afdd9 544extern void cx23885_free_buffer(struct cx23885_dev *dev,
44a6481d 545 struct cx23885_buffer *buf);
d19770e5
ST		 546
547/* ----------------------------------------------------------- */
7b888014
ST		 548/* cx23885-video.c */
549/* Video */
550extern int cx23885_video_register(struct cx23885_dev *dev);
551extern void cx23885_video_unregister(struct cx23885_dev *dev);
552extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
b5f74050
ST		 553extern void cx23885_video_wakeup(struct cx23885_dev *dev,
554 struct cx23885_dmaqueue *q, u32 count);
35045137
ST		 555int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
556int cx23885_set_input(struct file *file, void *priv, unsigned int i);
557int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
b530a447 558int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
35045137 559int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
7b888014
ST		 560
561/* ----------------------------------------------------------- */
562/* cx23885-vbi.c */
563extern int cx23885_vbi_fmt(struct file *file, void *priv,
564 struct v4l2_format *f);
565extern void cx23885_vbi_timeout(unsigned long data);
453afdd9 566extern struct vb2_ops cx23885_vbi_qops;
b5f74050 567extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
7b888014 568
d19770e5
ST		 569/* cx23885-i2c.c */
570extern int cx23885_i2c_register(struct cx23885_i2c *bus);
571extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 572extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 573
b1b81f1d
ST		 574/* ----------------------------------------------------------- */
575/* cx23885-417.c */
576extern int cx23885_417_register(struct cx23885_dev *dev);
577extern void cx23885_417_unregister(struct cx23885_dev *dev);
578extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
579extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
580extern void cx23885_mc417_init(struct cx23885_dev *dev);
581extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
582extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244
AW		 583extern int mc417_register_read(struct cx23885_dev *dev,
584 u16 address, u32 *value);
585extern int mc417_register_write(struct cx23885_dev *dev,
586 u16 address, u32 value);
f659c513
ST		 587extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
588extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
589extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d 590
9e44d632
MM		 591/* ----------------------------------------------------------- */
592/* cx23885-alsa.c */
efa762f5
ST		 593extern struct cx23885_audio_dev *cx23885_audio_register(
594 struct cx23885_dev *dev);
595extern void cx23885_audio_unregister(struct cx23885_dev *dev);
9e44d632
MM		 596extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
597extern int cx23885_risc_databuffer(struct pci_dev *pci,
598 struct btcx_riscmem *risc,
599 struct scatterlist *sglist,
600 unsigned int bpl,
601 unsigned int lines,
602 unsigned int lpi);
b1b81f1d 603
7b888014
ST		 604/* ----------------------------------------------------------- */
605/* tv norms */
606
607static inline unsigned int norm_maxw(v4l2_std_id norm)
608{
609 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
610}
611
612static inline unsigned int norm_maxh(v4l2_std_id norm)
613{
614 return (norm & V4L2_STD_625_50) ? 576 : 480;
615}
616
617static inline unsigned int norm_swidth(v4l2_std_id norm)
618{
619 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
620}
Linux kernel - Deliverables
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