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[media] cx23885: add basic DVB-S2 support for Hauppauge HVR-4400
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include <linux/pci.h>
23#include <linux/i2c.h>
d19770e5 24#include <linux/kdev_t.h>
5a0e3ad6 25#include <linux/slab.h>
d19770e5 26
c0714f6c 27#include <media/v4l2-device.h>
d19770e5
ST		 28#include <media/tuner.h>
29#include <media/tveeprom.h>
409d84f8
TP		 30#include <media/videobuf-dma-sg.h>
31#include <media/videobuf-dvb.h>
6bda9644 32#include <media/rc-core.h>
d19770e5
ST		 33
34#include "btcx-risc.h"
35#include "cx23885-reg.h"
b1b81f1d 36#include "media/cx2341x.h"
d19770e5 37
d19770e5
ST		 38#include <linux/mutex.h>
39
1990d50b 40#define CX23885_VERSION "0.0.3"
d19770e5
ST		 41
42#define UNSET (-1U)
43
44#define CX23885_MAXBOARDS 8
45
d19770e5
ST		 46/* Max number of inputs by card */
47#define MAX_CX23885_INPUT 8
7b888014
ST		 48#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
49#define RESOURCE_OVERLAY 1
50#define RESOURCE_VIDEO 2
51#define RESOURCE_VBI 4
d19770e5 52
d19770e5
ST		 53#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
54
55#define CX23885_BOARD_NOAUTO UNSET
56#define CX23885_BOARD_UNKNOWN 0
57#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
58#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 59#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 60#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 61#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 62#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 63#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 64#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 65#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 66#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 67#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 68#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 69#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 70#define CX23885_BOARD_TBS_6920 14
579943f5 71#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 72#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 73#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 74#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 75#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 76#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 77#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 78#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 79#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 80#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 81#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 82#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 83#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 84#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 85#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 86#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
0cf8af57 87#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
2cb9ccd4 88#define CX23885_BOARD_MPX885 32
87988753 89#define CX23885_BOARD_MYGICA_X8507 33
722c90eb 90#define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
7b134e85 91#define CX23885_BOARD_TEVII_S471 35
0ac60acb 92#define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
f667190b 93#define CX23885_BOARD_PROF_8000 37
7c62f5a1 94#define CX23885_BOARD_HAUPPAUGE_HVR4400 38
d19770e5 95
6f8bee9b
ST		 96#define GPIO_0 0x00000001
97#define GPIO_1 0x00000002
98#define GPIO_2 0x00000004
99#define GPIO_3 0x00000008
100#define GPIO_4 0x00000010
101#define GPIO_5 0x00000020
102#define GPIO_6 0x00000040
103#define GPIO_7 0x00000080
104#define GPIO_8 0x00000100
105#define GPIO_9 0x00000200
f659c513
ST		 106#define GPIO_10 0x00000400
107#define GPIO_11 0x00000800
108#define GPIO_12 0x00001000
109#define GPIO_13 0x00002000
110#define GPIO_14 0x00004000
111#define GPIO_15 0x00008000
6f8bee9b 112
7b888014
ST		 113/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
114#define CX23885_NORMS (\
115 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
116 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
117 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
118 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
119
120struct cx23885_fmt {
121 char *name;
122 u32 fourcc; /* v4l2 format id */
123 int depth;
124 int flags;
125 u32 cxformat;
126};
127
128struct cx23885_ctrl {
129 struct v4l2_queryctrl v;
130 u32 off;
131 u32 reg;
132 u32 mask;
133 u32 shift;
134};
135
136struct cx23885_tvnorm {
137 char *name;
138 v4l2_std_id id;
139 u32 cxiformat;
140 u32 cxoformat;
141};
142
143struct cx23885_fh {
144 struct cx23885_dev *dev;
145 enum v4l2_buf_type type;
146 int radio;
147 u32 resources;
148
149 /* video overlay */
150 struct v4l2_window win;
151 struct v4l2_clip *clips;
152 unsigned int nclips;
153
154 /* video capture */
155 struct cx23885_fmt *fmt;
156 unsigned int width, height;
157
158 /* vbi capture */
159 struct videobuf_queue vidq;
160 struct videobuf_queue vbiq;
161
162 /* MPEG Encoder specifics ONLY */
163 struct videobuf_queue mpegq;
164 atomic_t v4l_reading;
165};
166
d19770e5
ST		 167enum cx23885_itype {
168 CX23885_VMUX_COMPOSITE1 = 1,
169 CX23885_VMUX_COMPOSITE2,
170 CX23885_VMUX_COMPOSITE3,
171 CX23885_VMUX_COMPOSITE4,
172 CX23885_VMUX_SVIDEO,
dac65fa1 173 CX23885_VMUX_COMPONENT,
d19770e5
ST		 174 CX23885_VMUX_TELEVISION,
175 CX23885_VMUX_CABLE,
176 CX23885_VMUX_DVB,
177 CX23885_VMUX_DEBUG,
178 CX23885_RADIO,
179};
180
579f1163
ST		 181enum cx23885_src_sel_type {
182 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
183 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
184};
185
d19770e5
ST		 186/* buffer for one video frame */
187struct cx23885_buffer {
188 /* common v4l buffer stuff -- must be first */
189 struct videobuf_buffer vb;
190
191 /* cx23885 specific */
192 unsigned int bpl;
193 struct btcx_riscmem risc;
194 struct cx23885_fmt *fmt;
195 u32 count;
196};
197
198struct cx23885_input {
199 enum cx23885_itype type;
200 unsigned int vmux;
8304be88 201 unsigned int amux;
d19770e5
ST		 202 u32 gpio0, gpio1, gpio2, gpio3;
203};
204
661c7e44
ST		 205typedef enum {
206 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 207 CX23885_MPEG_DVB,
208 CX23885_ANALOG_VIDEO,
b1b81f1d 209 CX23885_MPEG_ENCODER,
661c7e44
ST		 210} port_t;
211
d19770e5
ST		 212struct cx23885_board {
213 char *name;
7b888014 214 port_t porta, portb, portc;
10d0dcd7 215 int num_fds_portb, num_fds_portc;
7b888014
ST		 216 unsigned int tuner_type;
217 unsigned int radio_type;
218 unsigned char tuner_addr;
219 unsigned char radio_addr;
557f48d5 220 unsigned int tuner_bus;
c7712613
ST		 221
222 /* Vendors can and do run the PCIe bridge at different
223 * clock rates, driven physically by crystals on the PCBs.
25985edc 224 * The core has to accommodate this. This allows the user
c7712613
ST		 225 * to add new boards with new frequencys. The value is
226 * expressed in Hz.
227 *
228 * The core framework will default this value based on
229 * current designs, but it can vary.
230 */
231 u32 clk_freq;
d19770e5 232 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 233 int ci_type; /* for NetUP */
35045137
ST		 234 /* Force bottom field first during DMA (888 workaround) */
235 u32 force_bff;
d19770e5
ST		 236};
237
238struct cx23885_subid {
239 u16 subvendor;
240 u16 subdevice;
241 u32 card;
242};
243
244struct cx23885_i2c {
245 struct cx23885_dev *dev;
246
247 int nr;
248
249 /* i2c i/o */
250 struct i2c_adapter i2c_adap;
d19770e5
ST		 251 struct i2c_client i2c_client;
252 u32 i2c_rc;
253
254 /* 885 registers used for raw addess */
255 u32 i2c_period;
256 u32 reg_ctrl;
257 u32 reg_stat;
258 u32 reg_addr;
259 u32 reg_rdata;
260 u32 reg_wdata;
261};
262
263struct cx23885_dmaqueue {
264 struct list_head active;
265 struct list_head queued;
266 struct timer_list timeout;
267 struct btcx_riscmem stopper;
268 u32 count;
269};
270
271struct cx23885_tsport {
272 struct cx23885_dev *dev;
273
274 int nr;
275 int sram_chno;
276
363c35fc 277 struct videobuf_dvb_frontends frontends;
d19770e5
ST		 278
279 /* dma queues */
280 struct cx23885_dmaqueue mpegq;
281 u32 ts_packet_size;
282 u32 ts_packet_count;
283
284 int width;
285 int height;
286
287 spinlock_t slock;
288
289 /* registers */
290 u32 reg_gpcnt;
291 u32 reg_gpcnt_ctl;
292 u32 reg_dma_ctl;
293 u32 reg_lngth;
294 u32 reg_hw_sop_ctrl;
295 u32 reg_gen_ctrl;
296 u32 reg_bd_pkt_status;
297 u32 reg_sop_status;
298 u32 reg_fifo_ovfl_stat;
299 u32 reg_vld_misc;
300 u32 reg_ts_clk_en;
301 u32 reg_ts_int_msk;
a6a3f140 302 u32 reg_ts_int_stat;
579f1163 303 u32 reg_src_sel;
d19770e5
ST		 304
305 /* Default register vals */
306 int pci_irqmask;
307 u32 dma_ctl_val;
308 u32 ts_int_msk_val;
309 u32 gen_ctrl_val;
310 u32 ts_clk_en_val;
579f1163 311 u32 src_sel_val;
b1b81f1d
ST		 312 u32 vld_misc_val;
313 u32 hw_sop_ctrl_val;
a739a7e4
ST		 314
315 /* Allow a single tsport to have multiple frontends */
316 u32 num_frontends;
78db8547 317 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 318 void *port_priv;
35045137
ST		 319
320 /* Workaround for a temp dvb_frontend that the tuner can attached to */
321 struct dvb_frontend analog_fe;
d19770e5
ST		 322};
323
43c24078
AW		 324struct cx23885_kernel_ir {
325 struct cx23885_dev *cx;
eeefae53
AW		 326 char *name;
327 char *phys;
328
d8b4b582 329 struct rc_dev *rc;
eeefae53
AW		 330};
331
9e44d632
MM		 332struct cx23885_audio_buffer {
333 unsigned int bpl;
334 struct btcx_riscmem risc;
335 struct videobuf_dmabuf dma;
336};
337
338struct cx23885_audio_dev {
339 struct cx23885_dev *dev;
340
341 struct pci_dev *pci;
342
343 struct snd_card *card;
344
345 spinlock_t lock;
346
347 atomic_t count;
348
349 unsigned int dma_size;
350 unsigned int period_size;
351 unsigned int num_periods;
352
353 struct videobuf_dmabuf *dma_risc;
354
355 struct cx23885_audio_buffer *buf;
356
357 struct snd_pcm_substream *substream;
358};
359
d19770e5 360struct cx23885_dev {
d19770e5 361 atomic_t refcount;
c0714f6c 362 struct v4l2_device v4l2_dev;
d19770e5
ST		 363
364 /* pci stuff */
365 struct pci_dev *pci;
366 unsigned char pci_rev, pci_lat;
367 int pci_bus, pci_slot;
368 u32 __iomem *lmmio;
369 u8 __iomem *bmmio;
d19770e5 370 int pci_irqmask;
dbe83a3b 371 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 372 int hwrevision;
d19770e5 373
c7712613
ST		 374 /* This valud is board specific and is used to configure the
375 * AV core so we see nice clean and stable video and audio. */
376 u32 clk_freq;
377
44a6481d 378 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 379 struct cx23885_i2c i2c_bus[3];
380
381 int nr;
382 struct mutex lock;
8386c27f 383 struct mutex gpio_lock;
d19770e5
ST		 384
385 /* board details */
386 unsigned int board;
387 char name[32];
388
a6a3f140 389 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 390
391 /* sram configuration */
392 struct sram_channel *sram_channels;
e133be0f
ST		 393
394 enum {
395 CX23885_BRIDGE_UNDEFINED = 0,
396 CX23885_BRIDGE_885 = 885,
397 CX23885_BRIDGE_887 = 887,
25ea66e2 398 CX23885_BRIDGE_888 = 888,
e133be0f 399 } bridge;
7b888014
ST		 400
401 /* Analog video */
402 u32 resources;
403 unsigned int input;
fc1a889d 404 unsigned int audinput; /* Selectable audio input */
7b888014
ST		 405 u32 tvaudio;
406 v4l2_std_id tvnorm;
407 unsigned int tuner_type;
408 unsigned char tuner_addr;
557f48d5 409 unsigned int tuner_bus;
7b888014
ST		 410 unsigned int radio_type;
411 unsigned char radio_addr;
412 unsigned int has_radio;
0d5a19f1 413 struct v4l2_subdev *sd_cx25840;
e5514f10 414 struct work_struct cx25840_work;
f59ad611
AW		 415
416 /* Infrared */
417 struct v4l2_subdev *sd_ir;
418 struct work_struct ir_rx_work;
419 unsigned long ir_rx_notifications;
420 struct work_struct ir_tx_work;
421 unsigned long ir_tx_notifications;
7b888014 422
43c24078 423 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 424 atomic_t ir_input_stopping;
425
7b888014
ST		 426 /* V4l */
427 u32 freq;
428 struct video_device *video_dev;
429 struct video_device *vbi_dev;
430 struct video_device *radio_dev;
431
432 struct cx23885_dmaqueue vidq;
433 struct cx23885_dmaqueue vbiq;
434 spinlock_t slock;
b1b81f1d
ST		 435
436 /* MPEG Encoder ONLY settings */
437 u32 cx23417_mailbox;
438 struct cx2341x_mpeg_params mpeg_params;
439 struct video_device *v4l_device;
440 atomic_t v4l_reader_count;
441 struct cx23885_tvnorm encodernorm;
442
9e44d632
MM		 443 /* Analog raw audio */
444 struct cx23885_audio_dev *audio_dev;
445
d19770e5
ST		 446};
447
c0714f6c
HV		 448static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
449{
450 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
451}
452
0d5a19f1
HV		 453#define call_all(dev, o, f, args...) \
454 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
455
d6b1850d
AW		 456#define CX23885_HW_888_IR (1 << 0)
457#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 458
459#define call_hw(dev, grpid, o, f, args...) \
460 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
461
462extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
463
d19770e5
ST		 464#define SRAM_CH01 0 /* Video A */
465#define SRAM_CH02 1 /* VBI A */
466#define SRAM_CH03 2 /* Video B */
467#define SRAM_CH04 3 /* Transport via B */
468#define SRAM_CH05 4 /* VBI B */
469#define SRAM_CH06 5 /* Video C */
470#define SRAM_CH07 6 /* Transport via C */
471#define SRAM_CH08 7 /* Audio Internal A */
472#define SRAM_CH09 8 /* Audio Internal B */
473#define SRAM_CH10 9 /* Audio External */
474#define SRAM_CH11 10 /* COMB_3D_N */
475#define SRAM_CH12 11 /* Comb 3D N1 */
476#define SRAM_CH13 12 /* Comb 3D N2 */
477#define SRAM_CH14 13 /* MOE Vid */
478#define SRAM_CH15 14 /* MOE RSLT */
479
480struct sram_channel {
481 char *name;
482 u32 cmds_start;
483 u32 ctrl_start;
484 u32 cdt;
1ebcad77 485 u32 fifo_start;
d19770e5
ST		 486 u32 fifo_size;
487 u32 ptr1_reg;
488 u32 ptr2_reg;
489 u32 cnt1_reg;
490 u32 cnt2_reg;
491 u32 jumponly;
492};
493
494/* ----------------------------------------------------------- */
495
496#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 497#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 498
9c8ced51 499#define cx_andor(reg, mask, value) \
d19770e5
ST		 500 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
501 ((value) & (mask)), dev->lmmio+((reg)>>2))
502
9c8ced51
ST		 503#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
504#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 505
d19770e5 506/* ----------------------------------------------------------- */
7b888014
ST		 507/* cx23885-core.c */
508
509extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
510 struct sram_channel *ch,
511 unsigned int bpl, u32 risc);
512
513extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
514 struct sram_channel *ch);
d19770e5 515
7b888014
ST		 516extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
517 u32 reg, u32 mask, u32 value);
518
519extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
520 struct scatterlist *sglist,
521 unsigned int top_offset, unsigned int bottom_offset,
522 unsigned int bpl, unsigned int padding, unsigned int lines);
523
5ab27e6d
ST		 524extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
525 struct btcx_riscmem *risc, struct scatterlist *sglist,
526 unsigned int top_offset, unsigned int bottom_offset,
527 unsigned int bpl, unsigned int padding, unsigned int lines);
528
7b888014
ST		 529void cx23885_cancel_buffers(struct cx23885_tsport *port);
530
531extern int cx23885_restart_queue(struct cx23885_tsport *port,
532 struct cx23885_dmaqueue *q);
533
534extern void cx23885_wakeup(struct cx23885_tsport *port,
535 struct cx23885_dmaqueue *q, u32 count);
536
6f8bee9b
ST		 537extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
538extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 539extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 540extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
541 int asoutput);
542
dbe83a3b
AW		 543extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
544extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
545extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
546extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
7b888014
ST		 547
548/* ----------------------------------------------------------- */
549/* cx23885-cards.c */
d19770e5
ST		 550extern struct cx23885_board cx23885_boards[];
551extern const unsigned int cx23885_bcount;
552
553extern struct cx23885_subid cx23885_subids[];
554extern const unsigned int cx23885_idcount;
555
9c8ced51
ST		 556extern int cx23885_tuner_callback(void *priv, int component,
557 int command, int arg);
d19770e5 558extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 559extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 560extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
561extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 562extern void cx23885_gpio_setup(struct cx23885_dev *dev);
d19770e5
ST		 563extern void cx23885_card_setup(struct cx23885_dev *dev);
564extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
565
566extern int cx23885_dvb_register(struct cx23885_tsport *port);
567extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
568
44a6481d
MK		 569extern int cx23885_buf_prepare(struct videobuf_queue *q,
570 struct cx23885_tsport *port,
571 struct cx23885_buffer *buf,
572 enum v4l2_field field);
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MK		 573extern void cx23885_buf_queue(struct cx23885_tsport *port,
574 struct cx23885_buffer *buf);
575extern void cx23885_free_buffer(struct videobuf_queue *q,
576 struct cx23885_buffer *buf);
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ST		 577
578/* ----------------------------------------------------------- */
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ST		 579/* cx23885-video.c */
580/* Video */
581extern int cx23885_video_register(struct cx23885_dev *dev);
582extern void cx23885_video_unregister(struct cx23885_dev *dev);
583extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
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ST		 584extern void cx23885_video_wakeup(struct cx23885_dev *dev,
585 struct cx23885_dmaqueue *q, u32 count);
35045137
ST		 586int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
587int cx23885_set_input(struct file *file, void *priv, unsigned int i);
588int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
589int cx23885_set_frequency(struct file *file, void *priv, struct v4l2_frequency *f);
590int cx23885_set_control(struct cx23885_dev *dev, struct v4l2_control *ctl);
591int cx23885_get_control(struct cx23885_dev *dev, struct v4l2_control *ctl);
592int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
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ST		 593
594/* ----------------------------------------------------------- */
595/* cx23885-vbi.c */
596extern int cx23885_vbi_fmt(struct file *file, void *priv,
597 struct v4l2_format *f);
598extern void cx23885_vbi_timeout(unsigned long data);
599extern struct videobuf_queue_ops cx23885_vbi_qops;
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ST		 600extern int cx23885_restart_vbi_queue(struct cx23885_dev *dev,
601 struct cx23885_dmaqueue *q);
602extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
7b888014 603
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ST		 604/* cx23885-i2c.c */
605extern int cx23885_i2c_register(struct cx23885_i2c *bus);
606extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 607extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 608
b1b81f1d
ST		 609/* ----------------------------------------------------------- */
610/* cx23885-417.c */
611extern int cx23885_417_register(struct cx23885_dev *dev);
612extern void cx23885_417_unregister(struct cx23885_dev *dev);
613extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
614extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
615extern void cx23885_mc417_init(struct cx23885_dev *dev);
616extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
617extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244
AW		 618extern int mc417_register_read(struct cx23885_dev *dev,
619 u16 address, u32 *value);
620extern int mc417_register_write(struct cx23885_dev *dev,
621 u16 address, u32 value);
f659c513
ST		 622extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
623extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
624extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d 625
9e44d632
MM		 626/* ----------------------------------------------------------- */
627/* cx23885-alsa.c */
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ST		 628extern struct cx23885_audio_dev *cx23885_audio_register(
629 struct cx23885_dev *dev);
630extern void cx23885_audio_unregister(struct cx23885_dev *dev);
9e44d632
MM		 631extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
632extern int cx23885_risc_databuffer(struct pci_dev *pci,
633 struct btcx_riscmem *risc,
634 struct scatterlist *sglist,
635 unsigned int bpl,
636 unsigned int lines,
637 unsigned int lpi);
b1b81f1d 638
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ST		 639/* ----------------------------------------------------------- */
640/* tv norms */
641
642static inline unsigned int norm_maxw(v4l2_std_id norm)
643{
644 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768;
645}
646
647static inline unsigned int norm_maxh(v4l2_std_id norm)
648{
649 return (norm & V4L2_STD_625_50) ? 576 : 480;
650}
651
652static inline unsigned int norm_swidth(v4l2_std_id norm)
653{
654 return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922;
655}
Linux kernel - Deliverables
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