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[media] include/media: move driver interface headers to a separate dir
[deliverable/linux.git] / drivers / media / pci / cx23885 / cx23885.h
CommitLineData
d19770e5
ST		 1/*
2 * Driver for the Conexant CX23885 PCIe bridge
3 *
6d897616 4 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
d19770e5
ST		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 *
15 * GNU General Public License for more details.
d19770e5
ST		 16 */
17
18#include <linux/pci.h>
19#include <linux/i2c.h>
d19770e5 20#include <linux/kdev_t.h>
5a0e3ad6 21#include <linux/slab.h>
d19770e5 22
c0714f6c 23#include <media/v4l2-device.h>
86dd9831 24#include <media/v4l2-fh.h>
da59a4de 25#include <media/v4l2-ctrls.h>
d19770e5
ST		 26#include <media/tuner.h>
27#include <media/tveeprom.h>
453afdd9
HV		 28#include <media/videobuf2-dma-sg.h>
29#include <media/videobuf2-dvb.h>
6bda9644 30#include <media/rc-core.h>
d19770e5 31
d19770e5 32#include "cx23885-reg.h"
d647f0b7 33#include "media/drv-intf/cx2341x.h"
d19770e5 34
d19770e5
ST		 35#include <linux/mutex.h>
36
453afdd9 37#define CX23885_VERSION "0.0.4"
d19770e5
ST		 38
39#define UNSET (-1U)
40
41#define CX23885_MAXBOARDS 8
42
d19770e5
ST		 43/* Max number of inputs by card */
44#define MAX_CX23885_INPUT 8
7b888014 45#define INPUT(nr) (&cx23885_boards[dev->board].input[nr])
d19770e5 46
d19770e5
ST		 47#define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */
48
49#define CX23885_BOARD_NOAUTO UNSET
50#define CX23885_BOARD_UNKNOWN 0
51#define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1
52#define CX23885_BOARD_HAUPPAUGE_HVR1800 2
a77743bc 53#define CX23885_BOARD_HAUPPAUGE_HVR1250 3
9bc37caa 54#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
d1987d55 55#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
07b4a835 56#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
b3ea0166 57#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
a780a31c 58#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
66762373 59#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
335377b7 60#define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10
aef2d186 61#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11
4c56b04a 62#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12
9bb1b7e8 63#define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13
96318d0c 64#define CX23885_BOARD_TBS_6920 14
579943f5 65#define CX23885_BOARD_TEVII_S470 15
c9b8b04b 66#define CX23885_BOARD_DVBWORLD_2005 16
5a23b076 67#define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17
2074dffa 68#define CX23885_BOARD_HAUPPAUGE_HVR1270 18
d099becb 69#define CX23885_BOARD_HAUPPAUGE_HVR1275 19
19bc5796 70#define CX23885_BOARD_HAUPPAUGE_HVR1255 20
6b926eca 71#define CX23885_BOARD_HAUPPAUGE_HVR1210 21
493b7127 72#define CX23885_BOARD_MYGICA_X8506 22
2365b2d3 73#define CX23885_BOARD_MAGICPRO_PROHDTVE2 23
13697380 74#define CX23885_BOARD_HAUPPAUGE_HVR1850 24
34e383dd 75#define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25
aee0b24c 76#define CX23885_BOARD_HAUPPAUGE_HVR1290 26
ea5697fe 77#define CX23885_BOARD_MYGICA_X8558PRO 27
0b32d65c 78#define CX23885_BOARD_LEADTEK_WINFAST_PXTV1200 28
9028f58f 79#define CX23885_BOARD_GOTVIEW_X5_3D_HYBRID 29
78db8547 80#define CX23885_BOARD_NETUP_DUAL_DVB_T_C_CI_RF 30
0cf8af57 81#define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H_XC4000 31
2cb9ccd4 82#define CX23885_BOARD_MPX885 32
87988753 83#define CX23885_BOARD_MYGICA_X8507 33
722c90eb 84#define CX23885_BOARD_TERRATEC_CINERGY_T_PCIE_DUAL 34
7b134e85 85#define CX23885_BOARD_TEVII_S471 35
0ac60acb 86#define CX23885_BOARD_HAUPPAUGE_HVR1255_22111 36
f667190b 87#define CX23885_BOARD_PROF_8000 37
7c62f5a1 88#define CX23885_BOARD_HAUPPAUGE_HVR4400 38
e8d42373 89#define CX23885_BOARD_AVERMEDIA_HC81R 39
e6001482
LA		 90#define CX23885_BOARD_TBS_6981 40
91#define CX23885_BOARD_TBS_6980 41
642ca1a0 92#define CX23885_BOARD_LEADTEK_WINFAST_PXPVR2200 42
cce11b09 93#define CX23885_BOARD_HAUPPAUGE_IMPACTVCBE 43
46b21bba 94#define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP2 44
29442266 95#define CX23885_BOARD_DVBSKY_T9580 45
82c10276 96#define CX23885_BOARD_DVBSKY_T980C 46
0e6c7b01 97#define CX23885_BOARD_DVBSKY_S950C 47
61b103e8 98#define CX23885_BOARD_TT_CT2_4500_CI 48
cba5480c 99#define CX23885_BOARD_DVBSKY_S950 49
c29d6a83 100#define CX23885_BOARD_DVBSKY_S952 50
c02ef64a 101#define CX23885_BOARD_DVBSKY_T982 51
1fc77d01 102#define CX23885_BOARD_HAUPPAUGE_HVR5525 52
4a8ba331 103#define CX23885_BOARD_HAUPPAUGE_STARBURST 53
d19770e5 104
6f8bee9b
ST		 105#define GPIO_0 0x00000001
106#define GPIO_1 0x00000002
107#define GPIO_2 0x00000004
108#define GPIO_3 0x00000008
109#define GPIO_4 0x00000010
110#define GPIO_5 0x00000020
111#define GPIO_6 0x00000040
112#define GPIO_7 0x00000080
113#define GPIO_8 0x00000100
114#define GPIO_9 0x00000200
f659c513
ST		 115#define GPIO_10 0x00000400
116#define GPIO_11 0x00000800
117#define GPIO_12 0x00001000
118#define GPIO_13 0x00002000
119#define GPIO_14 0x00004000
120#define GPIO_15 0x00008000
6f8bee9b 121
7b888014
ST		 122/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
123#define CX23885_NORMS (\
124 V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \
125 V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \
126 V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \
127 V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK)
128
129struct cx23885_fmt {
130 char *name;
131 u32 fourcc; /* v4l2 format id */
132 int depth;
133 int flags;
134 u32 cxformat;
135};
136
7b888014
ST		 137struct cx23885_tvnorm {
138 char *name;
139 v4l2_std_id id;
140 u32 cxiformat;
141 u32 cxoformat;
142};
143
d19770e5
ST		 144enum cx23885_itype {
145 CX23885_VMUX_COMPOSITE1 = 1,
146 CX23885_VMUX_COMPOSITE2,
147 CX23885_VMUX_COMPOSITE3,
148 CX23885_VMUX_COMPOSITE4,
149 CX23885_VMUX_SVIDEO,
dac65fa1 150 CX23885_VMUX_COMPONENT,
d19770e5
ST		 151 CX23885_VMUX_TELEVISION,
152 CX23885_VMUX_CABLE,
153 CX23885_VMUX_DVB,
154 CX23885_VMUX_DEBUG,
155 CX23885_RADIO,
156};
157
579f1163
ST		 158enum cx23885_src_sel_type {
159 CX23885_SRC_SEL_EXT_656_VIDEO = 0,
160 CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
161};
162
4d63a25c
HV		 163struct cx23885_riscmem {
164 unsigned int size;
165 __le32 *cpu;
166 __le32 *jmp;
167 dma_addr_t dma;
168};
169
d19770e5
ST		 170/* buffer for one video frame */
171struct cx23885_buffer {
172 /* common v4l buffer stuff -- must be first */
2d700715 173 struct vb2_v4l2_buffer vb;
453afdd9 174 struct list_head queue;
d19770e5
ST		 175
176 /* cx23885 specific */
177 unsigned int bpl;
4d63a25c 178 struct cx23885_riscmem risc;
d19770e5
ST		 179 struct cx23885_fmt *fmt;
180 u32 count;
181};
182
183struct cx23885_input {
184 enum cx23885_itype type;
185 unsigned int vmux;
8304be88 186 unsigned int amux;
d19770e5
ST		 187 u32 gpio0, gpio1, gpio2, gpio3;
188};
189
661c7e44
ST		 190typedef enum {
191 CX23885_MPEG_UNDEFINED = 0,
7b888014
ST		 192 CX23885_MPEG_DVB,
193 CX23885_ANALOG_VIDEO,
b1b81f1d 194 CX23885_MPEG_ENCODER,
661c7e44
ST		 195} port_t;
196
d19770e5
ST		 197struct cx23885_board {
198 char *name;
7b888014 199 port_t porta, portb, portc;
10d0dcd7 200 int num_fds_portb, num_fds_portc;
7b888014
ST		 201 unsigned int tuner_type;
202 unsigned int radio_type;
203 unsigned char tuner_addr;
204 unsigned char radio_addr;
557f48d5 205 unsigned int tuner_bus;
c7712613
ST		 206
207 /* Vendors can and do run the PCIe bridge at different
208 * clock rates, driven physically by crystals on the PCBs.
25985edc 209 * The core has to accommodate this. This allows the user
c7712613
ST		 210 * to add new boards with new frequencys. The value is
211 * expressed in Hz.
212 *
213 * The core framework will default this value based on
214 * current designs, but it can vary.
215 */
216 u32 clk_freq;
d19770e5 217 struct cx23885_input input[MAX_CX23885_INPUT];
78db8547 218 int ci_type; /* for NetUP */
35045137
ST		 219 /* Force bottom field first during DMA (888 workaround) */
220 u32 force_bff;
d19770e5
ST		 221};
222
223struct cx23885_subid {
224 u16 subvendor;
225 u16 subdevice;
226 u32 card;
227};
228
229struct cx23885_i2c {
230 struct cx23885_dev *dev;
231
232 int nr;
233
234 /* i2c i/o */
235 struct i2c_adapter i2c_adap;
d19770e5
ST		 236 struct i2c_client i2c_client;
237 u32 i2c_rc;
238
239 /* 885 registers used for raw addess */
240 u32 i2c_period;
241 u32 reg_ctrl;
242 u32 reg_stat;
243 u32 reg_addr;
244 u32 reg_rdata;
245 u32 reg_wdata;
246};
247
248struct cx23885_dmaqueue {
249 struct list_head active;
d19770e5
ST		 250 u32 count;
251};
252
253struct cx23885_tsport {
254 struct cx23885_dev *dev;
255
256 int nr;
257 int sram_chno;
258
453afdd9 259 struct vb2_dvb_frontends frontends;
d19770e5
ST		 260
261 /* dma queues */
262 struct cx23885_dmaqueue mpegq;
263 u32 ts_packet_size;
264 u32 ts_packet_count;
265
266 int width;
267 int height;
268
269 spinlock_t slock;
270
271 /* registers */
272 u32 reg_gpcnt;
273 u32 reg_gpcnt_ctl;
274 u32 reg_dma_ctl;
275 u32 reg_lngth;
276 u32 reg_hw_sop_ctrl;
277 u32 reg_gen_ctrl;
278 u32 reg_bd_pkt_status;
279 u32 reg_sop_status;
280 u32 reg_fifo_ovfl_stat;
281 u32 reg_vld_misc;
282 u32 reg_ts_clk_en;
283 u32 reg_ts_int_msk;
a6a3f140 284 u32 reg_ts_int_stat;
579f1163 285 u32 reg_src_sel;
d19770e5
ST		 286
287 /* Default register vals */
288 int pci_irqmask;
289 u32 dma_ctl_val;
290 u32 ts_int_msk_val;
291 u32 gen_ctrl_val;
292 u32 ts_clk_en_val;
579f1163 293 u32 src_sel_val;
b1b81f1d
ST		 294 u32 vld_misc_val;
295 u32 hw_sop_ctrl_val;
a739a7e4
ST		 296
297 /* Allow a single tsport to have multiple frontends */
298 u32 num_frontends;
78db8547 299 void (*gate_ctrl)(struct cx23885_tsport *port, int open);
5a23b076 300 void *port_priv;
35045137
ST		 301
302 /* Workaround for a temp dvb_frontend that the tuner can attached to */
303 struct dvb_frontend analog_fe;
15472faf 304
b0b12e63
OS		 305 struct i2c_client *i2c_client_demod;
306 struct i2c_client *i2c_client_tuner;
bf5e3ef0 307 struct i2c_client *i2c_client_sec;
e450de45 308 struct i2c_client *i2c_client_ci;
b0b12e63 309
15472faf 310 int (*set_frontend)(struct dvb_frontend *fe);
5cd3b6b4 311 int (*fe_set_voltage)(struct dvb_frontend *fe,
0df289a2 312 enum fe_sec_voltage voltage);
d19770e5
ST		 313};
314
43c24078
AW		 315struct cx23885_kernel_ir {
316 struct cx23885_dev *cx;
eeefae53
AW		 317 char *name;
318 char *phys;
319
d8b4b582 320 struct rc_dev *rc;
eeefae53
AW		 321};
322
9e44d632
MM		 323struct cx23885_audio_buffer {
324 unsigned int bpl;
4d63a25c 325 struct cx23885_riscmem risc;
9529a4b0
HV		 326 void *vaddr;
327 struct scatterlist *sglist;
328 int sglen;
329 int nr_pages;
9e44d632
MM		 330};
331
332struct cx23885_audio_dev {
333 struct cx23885_dev *dev;
334
335 struct pci_dev *pci;
336
337 struct snd_card *card;
338
339 spinlock_t lock;
340
341 atomic_t count;
342
343 unsigned int dma_size;
344 unsigned int period_size;
345 unsigned int num_periods;
346
9e44d632
MM		 347 struct cx23885_audio_buffer *buf;
348
349 struct snd_pcm_substream *substream;
350};
351
d19770e5 352struct cx23885_dev {
d19770e5 353 atomic_t refcount;
c0714f6c 354 struct v4l2_device v4l2_dev;
da59a4de 355 struct v4l2_ctrl_handler ctrl_handler;
d19770e5
ST		 356
357 /* pci stuff */
358 struct pci_dev *pci;
359 unsigned char pci_rev, pci_lat;
360 int pci_bus, pci_slot;
361 u32 __iomem *lmmio;
362 u8 __iomem *bmmio;
d19770e5 363 int pci_irqmask;
dbe83a3b 364 spinlock_t pci_irqmask_lock; /* protects mask reg too */
0ac5881a 365 int hwrevision;
d19770e5 366
c7712613
ST		 367 /* This valud is board specific and is used to configure the
368 * AV core so we see nice clean and stable video and audio. */
369 u32 clk_freq;
370
44a6481d 371 /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */
d19770e5
ST		 372 struct cx23885_i2c i2c_bus[3];
373
374 int nr;
375 struct mutex lock;
8386c27f 376 struct mutex gpio_lock;
d19770e5
ST		 377
378 /* board details */
379 unsigned int board;
380 char name[32];
381
a6a3f140 382 struct cx23885_tsport ts1, ts2;
d19770e5
ST		 383
384 /* sram configuration */
385 struct sram_channel *sram_channels;
e133be0f
ST		 386
387 enum {
388 CX23885_BRIDGE_UNDEFINED = 0,
389 CX23885_BRIDGE_885 = 885,
390 CX23885_BRIDGE_887 = 887,
25ea66e2 391 CX23885_BRIDGE_888 = 888,
e133be0f 392 } bridge;
7b888014
ST		 393
394 /* Analog video */
7b888014 395 unsigned int input;
fc1a889d 396 unsigned int audinput; /* Selectable audio input */
7b888014
ST		 397 u32 tvaudio;
398 v4l2_std_id tvnorm;
399 unsigned int tuner_type;
400 unsigned char tuner_addr;
557f48d5 401 unsigned int tuner_bus;
7b888014
ST		 402 unsigned int radio_type;
403 unsigned char radio_addr;
0d5a19f1 404 struct v4l2_subdev *sd_cx25840;
e5514f10 405 struct work_struct cx25840_work;
f59ad611
AW		 406
407 /* Infrared */
408 struct v4l2_subdev *sd_ir;
409 struct work_struct ir_rx_work;
410 unsigned long ir_rx_notifications;
411 struct work_struct ir_tx_work;
412 unsigned long ir_tx_notifications;
7b888014 413
43c24078 414 struct cx23885_kernel_ir *kernel_ir;
dbda8f70
AW		 415 atomic_t ir_input_stopping;
416
7b888014
ST		 417 /* V4l */
418 u32 freq;
419 struct video_device *video_dev;
420 struct video_device *vbi_dev;
7b888014 421
91d2d674
HV		 422 /* video capture */
423 struct cx23885_fmt *fmt;
424 unsigned int width, height;
453afdd9 425 unsigned field;
91d2d674 426
7b888014 427 struct cx23885_dmaqueue vidq;
453afdd9 428 struct vb2_queue vb2_vidq;
7b888014 429 struct cx23885_dmaqueue vbiq;
453afdd9 430 struct vb2_queue vb2_vbiq;
0c3a14c1 431 void *alloc_ctx;
453afdd9 432
7b888014 433 spinlock_t slock;
b1b81f1d
ST		 434
435 /* MPEG Encoder ONLY settings */
436 u32 cx23417_mailbox;
5150392c 437 struct cx2341x_handler cxhdl;
b1b81f1d 438 struct video_device *v4l_device;
453afdd9 439 struct vb2_queue vb2_mpegq;
b1b81f1d
ST		 440 struct cx23885_tvnorm encodernorm;
441
9e44d632
MM		 442 /* Analog raw audio */
443 struct cx23885_audio_dev *audio_dev;
444
d19770e5
ST		 445};
446
c0714f6c
HV		 447static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev)
448{
449 return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev);
450}
451
0d5a19f1
HV		 452#define call_all(dev, o, f, args...) \
453 v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args)
454
d6b1850d
AW		 455#define CX23885_HW_888_IR (1 << 0)
456#define CX23885_HW_AV_CORE (1 << 1)
29f8a0a5
AW		 457
458#define call_hw(dev, grpid, o, f, args...) \
459 v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args)
460
461extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw);
462
d19770e5
ST		 463#define SRAM_CH01 0 /* Video A */
464#define SRAM_CH02 1 /* VBI A */
465#define SRAM_CH03 2 /* Video B */
466#define SRAM_CH04 3 /* Transport via B */
467#define SRAM_CH05 4 /* VBI B */
468#define SRAM_CH06 5 /* Video C */
469#define SRAM_CH07 6 /* Transport via C */
470#define SRAM_CH08 7 /* Audio Internal A */
471#define SRAM_CH09 8 /* Audio Internal B */
472#define SRAM_CH10 9 /* Audio External */
473#define SRAM_CH11 10 /* COMB_3D_N */
474#define SRAM_CH12 11 /* Comb 3D N1 */
475#define SRAM_CH13 12 /* Comb 3D N2 */
476#define SRAM_CH14 13 /* MOE Vid */
477#define SRAM_CH15 14 /* MOE RSLT */
478
479struct sram_channel {
480 char *name;
481 u32 cmds_start;
482 u32 ctrl_start;
483 u32 cdt;
1ebcad77 484 u32 fifo_start;
d19770e5
ST		 485 u32 fifo_size;
486 u32 ptr1_reg;
487 u32 ptr2_reg;
488 u32 cnt1_reg;
489 u32 cnt2_reg;
490 u32 jumponly;
491};
492
493/* ----------------------------------------------------------- */
494
495#define cx_read(reg) readl(dev->lmmio + ((reg)>>2))
9c8ced51 496#define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))
d19770e5 497
9c8ced51 498#define cx_andor(reg, mask, value) \
d19770e5
ST		 499 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\
500 ((value) & (mask)), dev->lmmio+((reg)>>2))
501
9c8ced51
ST		 502#define cx_set(reg, bit) cx_andor((reg), (bit), (bit))
503#define cx_clear(reg, bit) cx_andor((reg), (bit), 0)
d19770e5 504
d19770e5 505/* ----------------------------------------------------------- */
7b888014
ST		 506/* cx23885-core.c */
507
508extern int cx23885_sram_channel_setup(struct cx23885_dev *dev,
509 struct sram_channel *ch,
510 unsigned int bpl, u32 risc);
511
512extern void cx23885_sram_channel_dump(struct cx23885_dev *dev,
513 struct sram_channel *ch);
d19770e5 514
4d63a25c 515extern int cx23885_risc_buffer(struct pci_dev *pci, struct cx23885_riscmem *risc,
7b888014
ST		 516 struct scatterlist *sglist,
517 unsigned int top_offset, unsigned int bottom_offset,
518 unsigned int bpl, unsigned int padding, unsigned int lines);
519
5ab27e6d 520extern int cx23885_risc_vbibuffer(struct pci_dev *pci,
4d63a25c 521 struct cx23885_riscmem *risc, struct scatterlist *sglist,
5ab27e6d
ST		 522 unsigned int top_offset, unsigned int bottom_offset,
523 unsigned int bpl, unsigned int padding, unsigned int lines);
524
453afdd9
HV		 525int cx23885_start_dma(struct cx23885_tsport *port,
526 struct cx23885_dmaqueue *q,
527 struct cx23885_buffer *buf);
7b888014
ST		 528void cx23885_cancel_buffers(struct cx23885_tsport *port);
529
7b888014 530
6f8bee9b
ST		 531extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask);
532extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask);
09ea33e5 533extern u32 cx23885_gpio_get(struct cx23885_dev *dev, u32 mask);
6f8bee9b
ST		 534extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask,
535 int asoutput);
536
dbe83a3b
AW		 537extern void cx23885_irq_add_enable(struct cx23885_dev *dev, u32 mask);
538extern void cx23885_irq_enable(struct cx23885_dev *dev, u32 mask);
539extern void cx23885_irq_disable(struct cx23885_dev *dev, u32 mask);
540extern void cx23885_irq_remove(struct cx23885_dev *dev, u32 mask);
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ST		 541
542/* ----------------------------------------------------------- */
543/* cx23885-cards.c */
d19770e5
ST		 544extern struct cx23885_board cx23885_boards[];
545extern const unsigned int cx23885_bcount;
546
547extern struct cx23885_subid cx23885_subids[];
548extern const unsigned int cx23885_idcount;
549
9c8ced51
ST		 550extern int cx23885_tuner_callback(void *priv, int component,
551 int command, int arg);
d19770e5 552extern void cx23885_card_list(struct cx23885_dev *dev);
a6a3f140 553extern int cx23885_ir_init(struct cx23885_dev *dev);
f59ad611
AW		 554extern void cx23885_ir_pci_int_enable(struct cx23885_dev *dev);
555extern void cx23885_ir_fini(struct cx23885_dev *dev);
a6a3f140 556extern void cx23885_gpio_setup(struct cx23885_dev *dev);
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ST		 557extern void cx23885_card_setup(struct cx23885_dev *dev);
558extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev);
559
560extern int cx23885_dvb_register(struct cx23885_tsport *port);
561extern int cx23885_dvb_unregister(struct cx23885_tsport *port);
562
453afdd9
HV		 563extern int cx23885_buf_prepare(struct cx23885_buffer *buf,
564 struct cx23885_tsport *port);
44a6481d
MK		 565extern void cx23885_buf_queue(struct cx23885_tsport *port,
566 struct cx23885_buffer *buf);
453afdd9 567extern void cx23885_free_buffer(struct cx23885_dev *dev,
44a6481d 568 struct cx23885_buffer *buf);
d19770e5
ST		 569
570/* ----------------------------------------------------------- */
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ST		 571/* cx23885-video.c */
572/* Video */
573extern int cx23885_video_register(struct cx23885_dev *dev);
574extern void cx23885_video_unregister(struct cx23885_dev *dev);
575extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status);
b5f74050
ST		 576extern void cx23885_video_wakeup(struct cx23885_dev *dev,
577 struct cx23885_dmaqueue *q, u32 count);
35045137
ST		 578int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i);
579int cx23885_set_input(struct file *file, void *priv, unsigned int i);
580int cx23885_get_input(struct file *file, void *priv, unsigned int *i);
b530a447 581int cx23885_set_frequency(struct file *file, void *priv, const struct v4l2_frequency *f);
35045137 582int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm);
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ST		 583
584/* ----------------------------------------------------------- */
585/* cx23885-vbi.c */
586extern int cx23885_vbi_fmt(struct file *file, void *priv,
587 struct v4l2_format *f);
588extern void cx23885_vbi_timeout(unsigned long data);
453afdd9 589extern struct vb2_ops cx23885_vbi_qops;
b5f74050 590extern int cx23885_vbi_irq(struct cx23885_dev *dev, u32 status);
7b888014 591
d19770e5
ST		 592/* cx23885-i2c.c */
593extern int cx23885_i2c_register(struct cx23885_i2c *bus);
594extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
a589b665 595extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
d19770e5 596
b1b81f1d
ST		 597/* ----------------------------------------------------------- */
598/* cx23885-417.c */
599extern int cx23885_417_register(struct cx23885_dev *dev);
600extern void cx23885_417_unregister(struct cx23885_dev *dev);
601extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
602extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
603extern void cx23885_mc417_init(struct cx23885_dev *dev);
604extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
605extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
74618244
AW		 606extern int mc417_register_read(struct cx23885_dev *dev,
607 u16 address, u32 *value);
608extern int mc417_register_write(struct cx23885_dev *dev,
609 u16 address, u32 value);
f659c513
ST		 610extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask);
611extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask);
612extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput);
b1b81f1d 613
9e44d632
MM		 614/* ----------------------------------------------------------- */
615/* cx23885-alsa.c */
efa762f5
ST		 616extern struct cx23885_audio_dev *cx23885_audio_register(
617 struct cx23885_dev *dev);
618extern void cx23885_audio_unregister(struct cx23885_dev *dev);
9e44d632
MM		 619extern int cx23885_audio_irq(struct cx23885_dev *dev, u32 status, u32 mask);
620extern int cx23885_risc_databuffer(struct pci_dev *pci,
4d63a25c 621 struct cx23885_riscmem *risc,
9e44d632
MM		 622 struct scatterlist *sglist,
623 unsigned int bpl,
624 unsigned int lines,
625 unsigned int lpi);
b1b81f1d 626
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ST		 627/* ----------------------------------------------------------- */
628/* tv norms */
629
630static inline unsigned int norm_maxw(v4l2_std_id norm)
631{
1c5eaa23 632 return (norm & V4L2_STD_525_60) ? 720 : 768;
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ST		 633}
634
635static inline unsigned int norm_maxh(v4l2_std_id norm)
636{
1c5eaa23 637 return (norm & V4L2_STD_525_60) ? 480 : 576;
7b888014 638}
Linux kernel - Deliverables
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