Commit | Line | Data |
---|---|---|
02b20b0b MCC |
1 | /* |
2 | * Driver for the Conexant CX25821 PCIe bridge | |
3 | * | |
bb4c9a74 | 4 | * Copyright (C) 2009 Conexant Systems Inc. |
02b20b0b | 5 | * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com> |
b671ae6b | 6 | * Based on Steven Toth <stoth@linuxtv.org> cx25821 driver |
6d8c2ba1 PB |
7 | * Parts adapted/taken from Eduardo Moscoso Rubino |
8 | * Copyright (C) 2009 Eduardo Moscoso Rubino <moscoso@TopoLogica.com> | |
9 | * | |
02b20b0b MCC |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
26 | ||
36d89f7d JP |
27 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
28 | ||
02b20b0b MCC |
29 | #include "cx25821-video.h" |
30 | ||
31 | MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards"); | |
6d8c2ba1 | 32 | MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>"); |
02b20b0b MCC |
33 | MODULE_LICENSE("GPL"); |
34 | ||
53e712d0 | 35 | static unsigned int video_nr[] = {[0 ... (CX25821_MAXBOARDS - 1)] = UNSET }; |
02b20b0b MCC |
36 | |
37 | module_param_array(video_nr, int, NULL, 0444); | |
02b20b0b MCC |
38 | |
39 | MODULE_PARM_DESC(video_nr, "video device numbers"); | |
02b20b0b | 40 | |
1a9fc855 | 41 | static unsigned int video_debug = VIDEO_DEBUG; |
02b20b0b MCC |
42 | module_param(video_debug, int, 0644); |
43 | MODULE_PARM_DESC(video_debug, "enable debug messages [video]"); | |
44 | ||
45 | static unsigned int irq_debug; | |
46 | module_param(irq_debug, int, 0644); | |
47 | MODULE_PARM_DESC(irq_debug, "enable debug messages [IRQ handler]"); | |
48 | ||
02b20b0b MCC |
49 | #define FORMAT_FLAGS_PACKED 0x01 |
50 | ||
95c232a2 | 51 | static const struct cx25821_fmt formats[] = { |
1a9fc855 | 52 | { |
d7d93387 MCC |
53 | .name = "4:1:1, packed, Y41P", |
54 | .fourcc = V4L2_PIX_FMT_Y41P, | |
55 | .depth = 12, | |
56 | .flags = FORMAT_FLAGS_PACKED, | |
57 | }, { | |
58 | .name = "4:2:2, packed, YUYV", | |
59 | .fourcc = V4L2_PIX_FMT_YUYV, | |
60 | .depth = 16, | |
61 | .flags = FORMAT_FLAGS_PACKED, | |
d7d93387 | 62 | }, |
02b20b0b MCC |
63 | }; |
64 | ||
95c232a2 | 65 | static const struct cx25821_fmt *cx25821_format_by_fourcc(unsigned int fourcc) |
02b20b0b | 66 | { |
1a9fc855 | 67 | unsigned int i; |
02b20b0b | 68 | |
1a9fc855 MCC |
69 | for (i = 0; i < ARRAY_SIZE(formats); i++) |
70 | if (formats[i].fourcc == fourcc) | |
71 | return formats + i; | |
1a9fc855 | 72 | return NULL; |
02b20b0b MCC |
73 | } |
74 | ||
02b20b0b | 75 | int cx25821_start_video_dma(struct cx25821_dev *dev, |
1a9fc855 MCC |
76 | struct cx25821_dmaqueue *q, |
77 | struct cx25821_buffer *buf, | |
bfef0d35 | 78 | const struct sram_channel *channel) |
02b20b0b | 79 | { |
1a9fc855 | 80 | int tmp = 0; |
02b20b0b | 81 | |
1a9fc855 MCC |
82 | /* setup fifo + format */ |
83 | cx25821_sram_channel_setup(dev, channel, buf->bpl, buf->risc.dma); | |
02b20b0b | 84 | |
1a9fc855 MCC |
85 | /* reset counter */ |
86 | cx_write(channel->gpcnt_ctl, 3); | |
02b20b0b | 87 | |
1a9fc855 MCC |
88 | /* enable irq */ |
89 | cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << channel->i)); | |
90 | cx_set(channel->int_msk, 0x11); | |
02b20b0b | 91 | |
1a9fc855 MCC |
92 | /* start dma */ |
93 | cx_write(channel->dma_ctl, 0x11); /* FIFO and RISC enable */ | |
02b20b0b | 94 | |
1a9fc855 MCC |
95 | /* make sure upstream setting if any is reversed */ |
96 | tmp = cx_read(VID_CH_MODE_SEL); | |
97 | cx_write(VID_CH_MODE_SEL, tmp & 0xFFFFFE00); | |
02b20b0b | 98 | |
1a9fc855 | 99 | return 0; |
02b20b0b MCC |
100 | } |
101 | ||
02b20b0b MCC |
102 | int cx25821_video_irq(struct cx25821_dev *dev, int chan_num, u32 status) |
103 | { | |
1a9fc855 MCC |
104 | int handled = 0; |
105 | u32 mask; | |
bfef0d35 | 106 | const struct sram_channel *channel = dev->channels[chan_num].sram_channels; |
1a9fc855 MCC |
107 | |
108 | mask = cx_read(channel->int_msk); | |
109 | if (0 == (status & mask)) | |
110 | return handled; | |
111 | ||
112 | cx_write(channel->int_stat, status); | |
113 | ||
114 | /* risc op code error */ | |
115 | if (status & (1 << 16)) { | |
36d89f7d JP |
116 | pr_warn("%s, %s: video risc op code error\n", |
117 | dev->name, channel->name); | |
1a9fc855 MCC |
118 | cx_clear(channel->dma_ctl, 0x11); |
119 | cx25821_sram_channel_dump(dev, channel); | |
120 | } | |
02b20b0b | 121 | |
1a9fc855 MCC |
122 | /* risc1 y */ |
123 | if (status & FLD_VID_DST_RISC1) { | |
b671ae6b HV |
124 | struct cx25821_dmaqueue *dmaq = |
125 | &dev->channels[channel->i].dma_vidq; | |
126 | struct cx25821_buffer *buf; | |
02b20b0b | 127 | |
1a9fc855 | 128 | spin_lock(&dev->slock); |
b671ae6b HV |
129 | if (!list_empty(&dmaq->active)) { |
130 | buf = list_entry(dmaq->active.next, | |
131 | struct cx25821_buffer, queue); | |
132 | ||
133 | v4l2_get_timestamp(&buf->vb.v4l2_buf.timestamp); | |
134 | buf->vb.v4l2_buf.sequence = dmaq->count++; | |
135 | list_del(&buf->queue); | |
136 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_DONE); | |
137 | } | |
1a9fc855 MCC |
138 | spin_unlock(&dev->slock); |
139 | handled++; | |
140 | } | |
141 | return handled; | |
02b20b0b MCC |
142 | } |
143 | ||
b671ae6b HV |
144 | static int cx25821_queue_setup(struct vb2_queue *q, const struct v4l2_format *fmt, |
145 | unsigned int *num_buffers, unsigned int *num_planes, | |
146 | unsigned int sizes[], void *alloc_ctxs[]) | |
02b20b0b | 147 | { |
b671ae6b | 148 | struct cx25821_channel *chan = q->drv_priv; |
11c8a2df HV |
149 | unsigned size = (chan->fmt->depth * chan->width * chan->height) >> 3; |
150 | ||
151 | if (fmt && fmt->fmt.pix.sizeimage < size) | |
152 | return -EINVAL; | |
02b20b0b | 153 | |
b671ae6b | 154 | *num_planes = 1; |
11c8a2df | 155 | sizes[0] = fmt ? fmt->fmt.pix.sizeimage : size; |
b671ae6b | 156 | alloc_ctxs[0] = chan->dev->alloc_ctx; |
1a9fc855 | 157 | return 0; |
02b20b0b MCC |
158 | } |
159 | ||
b671ae6b | 160 | static int cx25821_buffer_prepare(struct vb2_buffer *vb) |
02b20b0b | 161 | { |
b671ae6b | 162 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
2efe2cc4 | 163 | struct cx25821_dev *dev = chan->dev; |
1a9fc855 | 164 | struct cx25821_buffer *buf = |
f2539814 | 165 | container_of(vb, struct cx25821_buffer, vb); |
b671ae6b | 166 | struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0); |
30fdf035 | 167 | u32 line0_offset; |
1a9fc855 | 168 | int bpl_local = LINE_SIZE_D1; |
b671ae6b | 169 | int ret; |
1a9fc855 | 170 | |
b671ae6b HV |
171 | if (chan->pixel_formats == PIXEL_FRMT_411) |
172 | buf->bpl = (chan->fmt->depth * chan->width) >> 3; | |
173 | else | |
174 | buf->bpl = (chan->fmt->depth >> 3) * chan->width; | |
bb4c9a74 | 175 | |
b671ae6b | 176 | if (vb2_plane_size(vb, 0) < chan->height * buf->bpl) |
1a9fc855 | 177 | return -EINVAL; |
b671ae6b HV |
178 | vb2_set_plane_payload(vb, 0, chan->height * buf->bpl); |
179 | buf->vb.v4l2_buf.field = chan->field; | |
bb4c9a74 | 180 | |
b671ae6b HV |
181 | if (chan->pixel_formats == PIXEL_FRMT_411) { |
182 | bpl_local = buf->bpl; | |
183 | } else { | |
184 | bpl_local = buf->bpl; /* Default */ | |
1a9fc855 | 185 | |
b671ae6b HV |
186 | if (chan->use_cif_resolution) { |
187 | if (dev->tvnorm & V4L2_STD_625_50) | |
188 | bpl_local = 352 << 1; | |
189 | else | |
190 | bpl_local = chan->cif_width << 1; | |
bb4c9a74 | 191 | } |
bb4c9a74 MCC |
192 | } |
193 | ||
b671ae6b HV |
194 | switch (chan->field) { |
195 | case V4L2_FIELD_TOP: | |
196 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
197 | sgt->sgl, 0, UNSET, | |
198 | buf->bpl, 0, chan->height); | |
199 | break; | |
200 | case V4L2_FIELD_BOTTOM: | |
201 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
202 | sgt->sgl, UNSET, 0, | |
203 | buf->bpl, 0, chan->height); | |
204 | break; | |
205 | case V4L2_FIELD_INTERLACED: | |
206 | /* All other formats are top field first */ | |
207 | line0_offset = 0; | |
208 | dprintk(1, "top field first\n"); | |
209 | ||
210 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
211 | sgt->sgl, line0_offset, | |
212 | bpl_local, bpl_local, bpl_local, | |
213 | chan->height >> 1); | |
214 | break; | |
215 | case V4L2_FIELD_SEQ_TB: | |
216 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
217 | sgt->sgl, | |
218 | 0, buf->bpl * (chan->height >> 1), | |
219 | buf->bpl, 0, chan->height >> 1); | |
220 | break; | |
221 | case V4L2_FIELD_SEQ_BT: | |
222 | ret = cx25821_risc_buffer(dev->pci, &buf->risc, | |
223 | sgt->sgl, | |
224 | buf->bpl * (chan->height >> 1), 0, | |
225 | buf->bpl, 0, chan->height >> 1); | |
226 | break; | |
227 | default: | |
228 | WARN_ON(1); | |
229 | ret = -EINVAL; | |
230 | break; | |
bb4c9a74 | 231 | } |
02b20b0b | 232 | |
1a9fc855 | 233 | dprintk(2, "[%p/%d] buffer_prep - %dx%d %dbpp \"%s\" - dma=0x%08lx\n", |
b671ae6b HV |
234 | buf, buf->vb.v4l2_buf.index, chan->width, chan->height, |
235 | chan->fmt->depth, chan->fmt->name, | |
236 | (unsigned long)buf->risc.dma); | |
02b20b0b | 237 | |
b671ae6b | 238 | return ret; |
02b20b0b MCC |
239 | } |
240 | ||
b671ae6b | 241 | static void cx25821_buffer_finish(struct vb2_buffer *vb) |
02b20b0b | 242 | { |
1a9fc855 | 243 | struct cx25821_buffer *buf = |
f2539814 | 244 | container_of(vb, struct cx25821_buffer, vb); |
b671ae6b HV |
245 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
246 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 247 | |
b671ae6b | 248 | cx25821_free_buffer(dev, buf); |
02b20b0b MCC |
249 | } |
250 | ||
b671ae6b | 251 | static void cx25821_buffer_queue(struct vb2_buffer *vb) |
6d8c2ba1 | 252 | { |
8e4ac074 | 253 | struct cx25821_buffer *buf = |
f2539814 | 254 | container_of(vb, struct cx25821_buffer, vb); |
b671ae6b | 255 | struct cx25821_channel *chan = vb->vb2_queue->drv_priv; |
2efe2cc4 | 256 | struct cx25821_dev *dev = chan->dev; |
b671ae6b | 257 | struct cx25821_buffer *prev; |
2efe2cc4 | 258 | struct cx25821_dmaqueue *q = &dev->channels[chan->id].dma_vidq; |
e6cf66c1 | 259 | |
b671ae6b HV |
260 | buf->risc.cpu[1] = cpu_to_le32(buf->risc.dma + 12); |
261 | buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_CNT_INC); | |
262 | buf->risc.jmp[1] = cpu_to_le32(buf->risc.dma + 12); | |
263 | buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */ | |
264 | ||
265 | if (list_empty(&q->active)) { | |
266 | list_add_tail(&buf->queue, &q->active); | |
e6cf66c1 | 267 | } else { |
b671ae6b | 268 | buf->risc.cpu[0] |= cpu_to_le32(RISC_IRQ1); |
e6cf66c1 | 269 | prev = list_entry(q->active.prev, struct cx25821_buffer, |
b671ae6b HV |
270 | queue); |
271 | list_add_tail(&buf->queue, &q->active); | |
272 | prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); | |
8ebbda49 | 273 | } |
6d8c2ba1 PB |
274 | } |
275 | ||
b671ae6b | 276 | static int cx25821_start_streaming(struct vb2_queue *q, unsigned int count) |
6d8c2ba1 | 277 | { |
b671ae6b | 278 | struct cx25821_channel *chan = q->drv_priv; |
8d125c50 | 279 | struct cx25821_dev *dev = chan->dev; |
b671ae6b HV |
280 | struct cx25821_dmaqueue *dmaq = &dev->channels[chan->id].dma_vidq; |
281 | struct cx25821_buffer *buf = list_entry(dmaq->active.next, | |
282 | struct cx25821_buffer, queue); | |
84293f08 | 283 | |
b671ae6b HV |
284 | dmaq->count = 0; |
285 | cx25821_start_video_dma(dev, dmaq, buf, chan->sram_channels); | |
286 | return 0; | |
6d8c2ba1 PB |
287 | } |
288 | ||
b671ae6b | 289 | static void cx25821_stop_streaming(struct vb2_queue *q) |
6d8c2ba1 | 290 | { |
b671ae6b | 291 | struct cx25821_channel *chan = q->drv_priv; |
2efe2cc4 | 292 | struct cx25821_dev *dev = chan->dev; |
b671ae6b HV |
293 | struct cx25821_dmaqueue *dmaq = &dev->channels[chan->id].dma_vidq; |
294 | unsigned long flags; | |
6d8c2ba1 | 295 | |
b671ae6b HV |
296 | cx_write(chan->sram_channels->dma_ctl, 0); /* FIFO and RISC disable */ |
297 | spin_lock_irqsave(&dev->slock, flags); | |
298 | while (!list_empty(&dmaq->active)) { | |
299 | struct cx25821_buffer *buf = list_entry(dmaq->active.next, | |
300 | struct cx25821_buffer, queue); | |
6d8c2ba1 | 301 | |
b671ae6b HV |
302 | list_del(&buf->queue); |
303 | vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR); | |
21377cdd | 304 | } |
b671ae6b | 305 | spin_unlock_irqrestore(&dev->slock, flags); |
6d8c2ba1 PB |
306 | } |
307 | ||
b671ae6b HV |
308 | static struct vb2_ops cx25821_video_qops = { |
309 | .queue_setup = cx25821_queue_setup, | |
310 | .buf_prepare = cx25821_buffer_prepare, | |
311 | .buf_finish = cx25821_buffer_finish, | |
312 | .buf_queue = cx25821_buffer_queue, | |
313 | .wait_prepare = vb2_ops_wait_prepare, | |
314 | .wait_finish = vb2_ops_wait_finish, | |
315 | .start_streaming = cx25821_start_streaming, | |
316 | .stop_streaming = cx25821_stop_streaming, | |
317 | }; | |
318 | ||
95c232a2 | 319 | /* VIDEO IOCTLS */ |
4c1d0f73 HV |
320 | |
321 | static int cx25821_vidioc_enum_fmt_vid_cap(struct file *file, void *priv, | |
322 | struct v4l2_fmtdesc *f) | |
323 | { | |
324 | if (unlikely(f->index >= ARRAY_SIZE(formats))) | |
325 | return -EINVAL; | |
326 | ||
327 | strlcpy(f->description, formats[f->index].name, sizeof(f->description)); | |
328 | f->pixelformat = formats[f->index].fourcc; | |
329 | ||
330 | return 0; | |
331 | } | |
332 | ||
95c232a2 HV |
333 | static int cx25821_vidioc_g_fmt_vid_cap(struct file *file, void *priv, |
334 | struct v4l2_format *f) | |
335 | { | |
2efe2cc4 | 336 | struct cx25821_channel *chan = video_drvdata(file); |
95c232a2 | 337 | |
2efe2cc4 HV |
338 | f->fmt.pix.width = chan->width; |
339 | f->fmt.pix.height = chan->height; | |
b671ae6b | 340 | f->fmt.pix.field = chan->field; |
2efe2cc4 | 341 | f->fmt.pix.pixelformat = chan->fmt->fourcc; |
988f7b80 HV |
342 | f->fmt.pix.bytesperline = (chan->width * chan->fmt->depth) >> 3; |
343 | f->fmt.pix.sizeimage = chan->height * f->fmt.pix.bytesperline; | |
344 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
95c232a2 HV |
345 | |
346 | return 0; | |
347 | } | |
348 | ||
349 | static int cx25821_vidioc_try_fmt_vid_cap(struct file *file, void *priv, | |
350 | struct v4l2_format *f) | |
351 | { | |
988f7b80 HV |
352 | struct cx25821_channel *chan = video_drvdata(file); |
353 | struct cx25821_dev *dev = chan->dev; | |
95c232a2 | 354 | const struct cx25821_fmt *fmt; |
988f7b80 | 355 | enum v4l2_field field = f->fmt.pix.field; |
66f93178 | 356 | unsigned int maxh; |
988f7b80 | 357 | unsigned w; |
95c232a2 HV |
358 | |
359 | fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
360 | if (NULL == fmt) | |
361 | return -EINVAL; | |
988f7b80 HV |
362 | maxh = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; |
363 | ||
364 | w = f->fmt.pix.width; | |
365 | if (field != V4L2_FIELD_BOTTOM) | |
366 | field = V4L2_FIELD_TOP; | |
367 | if (w < 352) { | |
368 | w = 176; | |
369 | f->fmt.pix.height = maxh / 4; | |
370 | } else if (w < 720) { | |
371 | w = 352; | |
372 | f->fmt.pix.height = maxh / 2; | |
373 | } else { | |
374 | w = 720; | |
375 | f->fmt.pix.height = maxh; | |
376 | field = V4L2_FIELD_INTERLACED; | |
95c232a2 | 377 | } |
95c232a2 | 378 | f->fmt.pix.field = field; |
988f7b80 | 379 | f->fmt.pix.width = w; |
95c232a2 HV |
380 | f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; |
381 | f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; | |
988f7b80 | 382 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; |
95c232a2 HV |
383 | |
384 | return 0; | |
385 | } | |
6d8c2ba1 PB |
386 | |
387 | static int vidioc_s_fmt_vid_cap(struct file *file, void *priv, | |
c1e6e241 | 388 | struct v4l2_format *f) |
6d8c2ba1 | 389 | { |
2efe2cc4 | 390 | struct cx25821_channel *chan = video_drvdata(file); |
8d125c50 | 391 | struct cx25821_dev *dev = chan->dev; |
a39bea3a | 392 | int pix_format = PIXEL_FRMT_422; |
a6aa0dc4 | 393 | int err; |
a39bea3a | 394 | |
255c040a | 395 | err = cx25821_vidioc_try_fmt_vid_cap(file, priv, f); |
6d8c2ba1 | 396 | |
255c040a LF |
397 | if (0 != err) |
398 | return err; | |
6d8c2ba1 | 399 | |
2efe2cc4 | 400 | chan->fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); |
b671ae6b | 401 | chan->field = f->fmt.pix.field; |
988f7b80 HV |
402 | chan->width = f->fmt.pix.width; |
403 | chan->height = f->fmt.pix.height; | |
6d8c2ba1 | 404 | |
6678762a LF |
405 | if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) |
406 | pix_format = PIXEL_FRMT_411; | |
6678762a | 407 | else |
988f7b80 | 408 | pix_format = PIXEL_FRMT_422; |
6d8c2ba1 | 409 | |
6678762a | 410 | cx25821_set_pixel_format(dev, SRAM_CH00, pix_format); |
6d8c2ba1 | 411 | |
6678762a | 412 | /* check if cif resolution */ |
2efe2cc4 HV |
413 | if (chan->width == 320 || chan->width == 352) |
414 | chan->use_cif_resolution = 1; | |
6678762a | 415 | else |
2efe2cc4 | 416 | chan->use_cif_resolution = 0; |
6d8c2ba1 | 417 | |
2efe2cc4 HV |
418 | chan->cif_width = chan->width; |
419 | medusa_set_resolution(dev, chan->width, SRAM_CH00); | |
6678762a | 420 | return 0; |
6d8c2ba1 PB |
421 | } |
422 | ||
6d8c2ba1 PB |
423 | static int vidioc_log_status(struct file *file, void *priv) |
424 | { | |
8d125c50 HV |
425 | struct cx25821_channel *chan = video_drvdata(file); |
426 | struct cx25821_dev *dev = chan->dev; | |
427 | const struct sram_channel *sram_ch = chan->sram_channels; | |
02859b61 | 428 | u32 tmp = 0; |
6d8c2ba1 | 429 | |
02859b61 | 430 | tmp = cx_read(sram_ch->dma_ctl); |
36d89f7d JP |
431 | pr_info("Video input 0 is %s\n", |
432 | (tmp & 0x11) ? "streaming" : "stopped"); | |
02859b61 | 433 | return 0; |
6d8c2ba1 PB |
434 | } |
435 | ||
02b20b0b | 436 | |
95c232a2 | 437 | static int cx25821_vidioc_querycap(struct file *file, void *priv, |
c1e6e241 | 438 | struct v4l2_capability *cap) |
02b20b0b | 439 | { |
8d125c50 HV |
440 | struct cx25821_channel *chan = video_drvdata(file); |
441 | struct cx25821_dev *dev = chan->dev; | |
3dd473ca HV |
442 | const u32 cap_input = V4L2_CAP_VIDEO_CAPTURE | |
443 | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; | |
0df13d99 | 444 | const u32 cap_output = V4L2_CAP_VIDEO_OUTPUT | V4L2_CAP_READWRITE; |
1a9fc855 MCC |
445 | |
446 | strcpy(cap->driver, "cx25821"); | |
447 | strlcpy(cap->card, cx25821_boards[dev->board].name, sizeof(cap->card)); | |
448 | sprintf(cap->bus_info, "PCIe:%s", pci_name(dev->pci)); | |
8d125c50 | 449 | if (chan->id >= VID_CHANNEL_NUM) |
3dd473ca HV |
450 | cap->device_caps = cap_output; |
451 | else | |
452 | cap->device_caps = cap_input; | |
0df13d99 | 453 | cap->capabilities = cap_input | cap_output | V4L2_CAP_DEVICE_CAPS; |
1a9fc855 | 454 | return 0; |
02b20b0b MCC |
455 | } |
456 | ||
95c232a2 | 457 | static int cx25821_vidioc_g_std(struct file *file, void *priv, v4l2_std_id *tvnorms) |
18c73af6 | 458 | { |
8d125c50 | 459 | struct cx25821_channel *chan = video_drvdata(file); |
18c73af6 | 460 | |
8d125c50 | 461 | *tvnorms = chan->dev->tvnorm; |
18c73af6 HV |
462 | return 0; |
463 | } | |
464 | ||
a3f17af2 MCC |
465 | static int cx25821_vidioc_s_std(struct file *file, void *priv, |
466 | v4l2_std_id tvnorms) | |
02b20b0b | 467 | { |
8d125c50 HV |
468 | struct cx25821_channel *chan = video_drvdata(file); |
469 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 470 | |
314527ac | 471 | if (dev->tvnorm == tvnorms) |
1a9fc855 | 472 | return 0; |
02b20b0b | 473 | |
a6aa0dc4 | 474 | dev->tvnorm = tvnorms; |
988f7b80 HV |
475 | chan->width = 720; |
476 | chan->height = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; | |
02b20b0b | 477 | |
1a9fc855 | 478 | medusa_set_videostandard(dev); |
02b20b0b | 479 | |
1a9fc855 | 480 | return 0; |
02b20b0b | 481 | } |
02b20b0b | 482 | |
95c232a2 HV |
483 | static int cx25821_vidioc_enum_input(struct file *file, void *priv, |
484 | struct v4l2_input *i) | |
02b20b0b | 485 | { |
a6aa0dc4 | 486 | if (i->index) |
1a9fc855 | 487 | return -EINVAL; |
02b20b0b | 488 | |
1a9fc855 | 489 | i->type = V4L2_INPUT_TYPE_CAMERA; |
1a9fc855 | 490 | i->std = CX25821_NORMS; |
a6aa0dc4 | 491 | strcpy(i->name, "Composite"); |
1a9fc855 | 492 | return 0; |
02b20b0b MCC |
493 | } |
494 | ||
95c232a2 | 495 | static int cx25821_vidioc_g_input(struct file *file, void *priv, unsigned int *i) |
bb4c9a74 | 496 | { |
a6aa0dc4 | 497 | *i = 0; |
1a9fc855 | 498 | return 0; |
02b20b0b MCC |
499 | } |
500 | ||
95c232a2 | 501 | static int cx25821_vidioc_s_input(struct file *file, void *priv, unsigned int i) |
02b20b0b | 502 | { |
a6aa0dc4 | 503 | return i ? -EINVAL : 0; |
02b20b0b MCC |
504 | } |
505 | ||
f8d7ee70 | 506 | static int cx25821_s_ctrl(struct v4l2_ctrl *ctrl) |
02b20b0b | 507 | { |
f8d7ee70 HV |
508 | struct cx25821_channel *chan = |
509 | container_of(ctrl->handler, struct cx25821_channel, hdl); | |
510 | struct cx25821_dev *dev = chan->dev; | |
02b20b0b | 511 | |
f8d7ee70 | 512 | switch (ctrl->id) { |
1a9fc855 | 513 | case V4L2_CID_BRIGHTNESS: |
f8d7ee70 | 514 | medusa_set_brightness(dev, ctrl->val, chan->id); |
02b20b0b | 515 | break; |
1a9fc855 | 516 | case V4L2_CID_HUE: |
f8d7ee70 | 517 | medusa_set_hue(dev, ctrl->val, chan->id); |
02b20b0b | 518 | break; |
1a9fc855 | 519 | case V4L2_CID_CONTRAST: |
f8d7ee70 | 520 | medusa_set_contrast(dev, ctrl->val, chan->id); |
02b20b0b | 521 | break; |
1a9fc855 | 522 | case V4L2_CID_SATURATION: |
f8d7ee70 | 523 | medusa_set_saturation(dev, ctrl->val, chan->id); |
02b20b0b | 524 | break; |
1a9fc855 | 525 | default: |
f8d7ee70 | 526 | return -EINVAL; |
02b20b0b | 527 | } |
f8d7ee70 | 528 | return 0; |
02b20b0b MCC |
529 | } |
530 | ||
1f198870 HV |
531 | static int cx25821_vidioc_enum_output(struct file *file, void *priv, |
532 | struct v4l2_output *o) | |
6d8c2ba1 | 533 | { |
1f198870 HV |
534 | if (o->index) |
535 | return -EINVAL; | |
6d8c2ba1 | 536 | |
1f198870 HV |
537 | o->type = V4L2_INPUT_TYPE_CAMERA; |
538 | o->std = CX25821_NORMS; | |
539 | strcpy(o->name, "Composite"); | |
6f87cc6c | 540 | return 0; |
6d8c2ba1 PB |
541 | } |
542 | ||
1f198870 | 543 | static int cx25821_vidioc_g_output(struct file *file, void *priv, unsigned int *o) |
6d8c2ba1 | 544 | { |
1f198870 | 545 | *o = 0; |
f9ef6be3 | 546 | return 0; |
6d8c2ba1 PB |
547 | } |
548 | ||
1f198870 | 549 | static int cx25821_vidioc_s_output(struct file *file, void *priv, unsigned int o) |
6d8c2ba1 | 550 | { |
1f198870 | 551 | return o ? -EINVAL : 0; |
6d8c2ba1 PB |
552 | } |
553 | ||
e90878ab HV |
554 | static int cx25821_vidioc_try_fmt_vid_out(struct file *file, void *priv, |
555 | struct v4l2_format *f) | |
556 | { | |
557 | struct cx25821_channel *chan = video_drvdata(file); | |
558 | struct cx25821_dev *dev = chan->dev; | |
559 | const struct cx25821_fmt *fmt; | |
560 | ||
561 | fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
562 | if (NULL == fmt) | |
563 | return -EINVAL; | |
564 | f->fmt.pix.width = 720; | |
565 | f->fmt.pix.height = (dev->tvnorm & V4L2_STD_625_50) ? 576 : 480; | |
566 | f->fmt.pix.field = V4L2_FIELD_INTERLACED; | |
567 | f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3; | |
568 | f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline; | |
569 | f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M; | |
e90878ab HV |
570 | return 0; |
571 | } | |
572 | ||
573 | static int vidioc_s_fmt_vid_out(struct file *file, void *priv, | |
574 | struct v4l2_format *f) | |
575 | { | |
576 | struct cx25821_channel *chan = video_drvdata(file); | |
577 | int err; | |
578 | ||
579 | err = cx25821_vidioc_try_fmt_vid_out(file, priv, f); | |
580 | ||
581 | if (0 != err) | |
582 | return err; | |
583 | ||
584 | chan->fmt = cx25821_format_by_fourcc(f->fmt.pix.pixelformat); | |
b671ae6b | 585 | chan->field = f->fmt.pix.field; |
e90878ab HV |
586 | chan->width = f->fmt.pix.width; |
587 | chan->height = f->fmt.pix.height; | |
588 | if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_Y41P) | |
589 | chan->pixel_formats = PIXEL_FRMT_411; | |
590 | else | |
591 | chan->pixel_formats = PIXEL_FRMT_422; | |
592 | return 0; | |
593 | } | |
594 | ||
f8d7ee70 HV |
595 | static const struct v4l2_ctrl_ops cx25821_ctrl_ops = { |
596 | .s_ctrl = cx25821_s_ctrl, | |
597 | }; | |
598 | ||
6d8c2ba1 | 599 | static const struct v4l2_file_operations video_fops = { |
fa7ce1f4 | 600 | .owner = THIS_MODULE, |
8d125c50 | 601 | .open = v4l2_fh_open, |
b671ae6b HV |
602 | .release = vb2_fop_release, |
603 | .read = vb2_fop_read, | |
604 | .poll = vb2_fop_poll, | |
1f198870 | 605 | .unlocked_ioctl = video_ioctl2, |
b671ae6b | 606 | .mmap = vb2_fop_mmap, |
6d8c2ba1 PB |
607 | }; |
608 | ||
609 | static const struct v4l2_ioctl_ops video_ioctl_ops = { | |
fa7ce1f4 LF |
610 | .vidioc_querycap = cx25821_vidioc_querycap, |
611 | .vidioc_enum_fmt_vid_cap = cx25821_vidioc_enum_fmt_vid_cap, | |
612 | .vidioc_g_fmt_vid_cap = cx25821_vidioc_g_fmt_vid_cap, | |
613 | .vidioc_try_fmt_vid_cap = cx25821_vidioc_try_fmt_vid_cap, | |
614 | .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap, | |
b671ae6b HV |
615 | .vidioc_reqbufs = vb2_ioctl_reqbufs, |
616 | .vidioc_prepare_buf = vb2_ioctl_prepare_buf, | |
11c8a2df | 617 | .vidioc_create_bufs = vb2_ioctl_create_bufs, |
b671ae6b HV |
618 | .vidioc_querybuf = vb2_ioctl_querybuf, |
619 | .vidioc_qbuf = vb2_ioctl_qbuf, | |
620 | .vidioc_dqbuf = vb2_ioctl_dqbuf, | |
621 | .vidioc_streamon = vb2_ioctl_streamon, | |
622 | .vidioc_streamoff = vb2_ioctl_streamoff, | |
18c73af6 | 623 | .vidioc_g_std = cx25821_vidioc_g_std, |
fa7ce1f4 | 624 | .vidioc_s_std = cx25821_vidioc_s_std, |
fa7ce1f4 LF |
625 | .vidioc_enum_input = cx25821_vidioc_enum_input, |
626 | .vidioc_g_input = cx25821_vidioc_g_input, | |
627 | .vidioc_s_input = cx25821_vidioc_s_input, | |
fa7ce1f4 | 628 | .vidioc_log_status = vidioc_log_status, |
8d125c50 HV |
629 | .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, |
630 | .vidioc_unsubscribe_event = v4l2_event_unsubscribe, | |
6d8c2ba1 PB |
631 | }; |
632 | ||
ffd3c233 HV |
633 | static const struct video_device cx25821_video_device = { |
634 | .name = "cx25821-video", | |
527db49d | 635 | .fops = &video_fops, |
467870ca | 636 | .release = video_device_release_empty, |
ffd3c233 | 637 | .minor = -1, |
527db49d LF |
638 | .ioctl_ops = &video_ioctl_ops, |
639 | .tvnorms = CX25821_NORMS, | |
6d8c2ba1 | 640 | }; |
ffd3c233 | 641 | |
1f198870 HV |
642 | static const struct v4l2_file_operations video_out_fops = { |
643 | .owner = THIS_MODULE, | |
644 | .open = v4l2_fh_open, | |
b671ae6b HV |
645 | .release = vb2_fop_release, |
646 | .write = vb2_fop_write, | |
647 | .poll = vb2_fop_poll, | |
1f198870 | 648 | .unlocked_ioctl = video_ioctl2, |
b671ae6b | 649 | .mmap = vb2_fop_mmap, |
1f198870 HV |
650 | }; |
651 | ||
652 | static const struct v4l2_ioctl_ops video_out_ioctl_ops = { | |
653 | .vidioc_querycap = cx25821_vidioc_querycap, | |
e90878ab HV |
654 | .vidioc_enum_fmt_vid_out = cx25821_vidioc_enum_fmt_vid_cap, |
655 | .vidioc_g_fmt_vid_out = cx25821_vidioc_g_fmt_vid_cap, | |
656 | .vidioc_try_fmt_vid_out = cx25821_vidioc_try_fmt_vid_out, | |
657 | .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out, | |
1f198870 HV |
658 | .vidioc_g_std = cx25821_vidioc_g_std, |
659 | .vidioc_s_std = cx25821_vidioc_s_std, | |
660 | .vidioc_enum_output = cx25821_vidioc_enum_output, | |
661 | .vidioc_g_output = cx25821_vidioc_g_output, | |
662 | .vidioc_s_output = cx25821_vidioc_s_output, | |
663 | .vidioc_log_status = vidioc_log_status, | |
664 | }; | |
665 | ||
666 | static const struct video_device cx25821_video_out_device = { | |
667 | .name = "cx25821-video", | |
668 | .fops = &video_out_fops, | |
669 | .release = video_device_release_empty, | |
670 | .minor = -1, | |
671 | .ioctl_ops = &video_out_ioctl_ops, | |
672 | .tvnorms = CX25821_NORMS, | |
673 | }; | |
674 | ||
ffd3c233 HV |
675 | void cx25821_video_unregister(struct cx25821_dev *dev, int chan_num) |
676 | { | |
677 | cx_clear(PCI_INT_MSK, 1); | |
678 | ||
467870ca HV |
679 | if (video_is_registered(&dev->channels[chan_num].vdev)) { |
680 | video_unregister_device(&dev->channels[chan_num].vdev); | |
f8d7ee70 | 681 | v4l2_ctrl_handler_free(&dev->channels[chan_num].hdl); |
ffd3c233 | 682 | } |
ffd3c233 HV |
683 | } |
684 | ||
685 | int cx25821_video_register(struct cx25821_dev *dev) | |
686 | { | |
687 | int err; | |
688 | int i; | |
689 | ||
be178cb4 | 690 | /* initial device configuration */ |
a6aa0dc4 | 691 | dev->tvnorm = V4L2_STD_NTSC_M; |
be178cb4 | 692 | |
ffd3c233 HV |
693 | spin_lock_init(&dev->slock); |
694 | ||
1f198870 | 695 | for (i = 0; i < MAX_VID_CHANNEL_NUM - 1; ++i) { |
2efe2cc4 HV |
696 | struct cx25821_channel *chan = &dev->channels[i]; |
697 | struct video_device *vdev = &chan->vdev; | |
698 | struct v4l2_ctrl_handler *hdl = &chan->hdl; | |
b671ae6b | 699 | struct vb2_queue *q; |
1f198870 | 700 | bool is_output = i > SRAM_CH08; |
467870ca | 701 | |
ffd3c233 HV |
702 | if (i == SRAM_CH08) /* audio channel */ |
703 | continue; | |
704 | ||
1f198870 HV |
705 | if (!is_output) { |
706 | v4l2_ctrl_handler_init(hdl, 4); | |
707 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
708 | V4L2_CID_BRIGHTNESS, 0, 10000, 1, 6200); | |
709 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
710 | V4L2_CID_CONTRAST, 0, 10000, 1, 5000); | |
711 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
712 | V4L2_CID_SATURATION, 0, 10000, 1, 5000); | |
713 | v4l2_ctrl_new_std(hdl, &cx25821_ctrl_ops, | |
714 | V4L2_CID_HUE, 0, 10000, 1, 5000); | |
715 | if (hdl->error) { | |
716 | err = hdl->error; | |
717 | goto fail_unreg; | |
718 | } | |
719 | err = v4l2_ctrl_handler_setup(hdl); | |
720 | if (err) | |
721 | goto fail_unreg; | |
7087d31b HV |
722 | } else { |
723 | chan->out = &dev->vid_out_data[i - SRAM_CH09]; | |
724 | chan->out->chan = chan; | |
f8d7ee70 | 725 | } |
ffd3c233 | 726 | |
2efe2cc4 | 727 | chan->sram_channels = &cx25821_sram_channels[i]; |
2efe2cc4 | 728 | chan->width = 720; |
b671ae6b | 729 | chan->field = V4L2_FIELD_INTERLACED; |
2efe2cc4 HV |
730 | if (dev->tvnorm & V4L2_STD_625_50) |
731 | chan->height = 576; | |
732 | else | |
733 | chan->height = 480; | |
ffd3c233 | 734 | |
2efe2cc4 HV |
735 | if (chan->pixel_formats == PIXEL_FRMT_411) |
736 | chan->fmt = cx25821_format_by_fourcc(V4L2_PIX_FMT_Y41P); | |
737 | else | |
738 | chan->fmt = cx25821_format_by_fourcc(V4L2_PIX_FMT_YUYV); | |
ffd3c233 | 739 | |
2efe2cc4 | 740 | cx_write(chan->sram_channels->int_stat, 0xffffffff); |
ffd3c233 | 741 | |
2efe2cc4 | 742 | INIT_LIST_HEAD(&chan->dma_vidq.active); |
2efe2cc4 | 743 | |
b671ae6b HV |
744 | q = &chan->vidq; |
745 | ||
746 | q->type = is_output ? V4L2_BUF_TYPE_VIDEO_OUTPUT : | |
747 | V4L2_BUF_TYPE_VIDEO_CAPTURE; | |
748 | q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; | |
749 | q->io_modes |= is_output ? VB2_WRITE : VB2_READ; | |
750 | q->gfp_flags = GFP_DMA32; | |
751 | q->min_buffers_needed = 2; | |
752 | q->drv_priv = chan; | |
753 | q->buf_struct_size = sizeof(struct cx25821_buffer); | |
754 | q->ops = &cx25821_video_qops; | |
755 | q->mem_ops = &vb2_dma_sg_memops; | |
756 | q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC; | |
757 | q->lock = &dev->lock; | |
2efe2cc4 | 758 | |
b671ae6b HV |
759 | if (!is_output) { |
760 | err = vb2_queue_init(q); | |
761 | if (err < 0) | |
762 | goto fail_unreg; | |
763 | } | |
ffd3c233 HV |
764 | |
765 | /* register v4l devices */ | |
1f198870 | 766 | *vdev = is_output ? cx25821_video_out_device : cx25821_video_device; |
467870ca | 767 | vdev->v4l2_dev = &dev->v4l2_dev; |
1f198870 HV |
768 | if (!is_output) |
769 | vdev->ctrl_handler = hdl; | |
770 | else | |
771 | vdev->vfl_dir = VFL_DIR_TX; | |
be178cb4 | 772 | vdev->lock = &dev->lock; |
b671ae6b | 773 | vdev->queue = q; |
467870ca | 774 | snprintf(vdev->name, sizeof(vdev->name), "%s #%d", dev->name, i); |
2efe2cc4 | 775 | video_set_drvdata(vdev, chan); |
ffd3c233 | 776 | |
467870ca HV |
777 | err = video_register_device(vdev, VFL_TYPE_GRABBER, |
778 | video_nr[dev->nr]); | |
ffd3c233 HV |
779 | |
780 | if (err < 0) | |
781 | goto fail_unreg; | |
ffd3c233 HV |
782 | } |
783 | ||
784 | /* set PCI interrupt */ | |
785 | cx_set(PCI_INT_MSK, 0xff); | |
786 | ||
ffd3c233 HV |
787 | return 0; |
788 | ||
789 | fail_unreg: | |
467870ca HV |
790 | while (i >= 0) |
791 | cx25821_video_unregister(dev, i--); | |
ffd3c233 HV |
792 | return err; |
793 | } |