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dae52d00 MB |
1 | /* |
2 | * ngene.h: nGene PCIe bridge driver | |
3 | * | |
4 | * Copyright (C) 2005-2007 Micronas | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * version 2 only, as published by the Free Software Foundation. | |
9 | * | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA | |
20 | * 02110-1301, USA | |
21 | * Or, point your browser to http://www.gnu.org/copyleft/gpl.html | |
22 | */ | |
23 | ||
24 | #ifndef _NGENE_H_ | |
25 | #define _NGENE_H_ | |
26 | ||
dae52d00 MB |
27 | #include <linux/types.h> |
28 | #include <linux/sched.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/i2c.h> | |
31 | #include <asm/dma.h> | |
684688d8 | 32 | #include <linux/scatterlist.h> |
dae52d00 MB |
33 | |
34 | #include <linux/dvb/frontend.h> | |
dae52d00 MB |
35 | |
36 | #include "dmxdev.h" | |
37 | #include "dvbdev.h" | |
38 | #include "dvb_demux.h" | |
0f0b270f | 39 | #include "dvb_ca_en50221.h" |
dae52d00 MB |
40 | #include "dvb_frontend.h" |
41 | #include "dvb_ringbuffer.h" | |
cce33c34 | 42 | #include "dvb_net.h" |
0f0b270f | 43 | #include "cxd2099.h" |
dae52d00 | 44 | |
cbddcba6 DH |
45 | #define DEVICE_NAME "ngene" |
46 | ||
dae52d00 MB |
47 | #define NGENE_VID 0x18c3 |
48 | #define NGENE_PID 0x0720 | |
49 | ||
50 | #ifndef VIDEO_CAP_VC1 | |
51 | #define VIDEO_CAP_AVC 128 | |
52 | #define VIDEO_CAP_H264 128 | |
53 | #define VIDEO_CAP_VC1 256 | |
54 | #define VIDEO_CAP_WMV9 256 | |
55 | #define VIDEO_CAP_MPEG4 512 | |
56 | #endif | |
57 | ||
58 | enum STREAM { | |
59 | STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */ | |
60 | STREAM_VIDEOIN2, | |
61 | STREAM_AUDIOIN1, /* I2S or SPI Input */ | |
62 | STREAM_AUDIOIN2, | |
63 | STREAM_AUDIOOUT, | |
64 | MAX_STREAM | |
65 | }; | |
66 | ||
67 | enum SMODE_BITS { | |
68 | SMODE_AUDIO_SPDIF = 0x20, | |
69 | SMODE_AVSYNC = 0x10, | |
70 | SMODE_TRANSPORT_STREAM = 0x08, | |
71 | SMODE_AUDIO_CAPTURE = 0x04, | |
72 | SMODE_VBI_CAPTURE = 0x02, | |
73 | SMODE_VIDEO_CAPTURE = 0x01 | |
74 | }; | |
75 | ||
76 | enum STREAM_FLAG_BITS { | |
77 | SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */ | |
78 | SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */ | |
79 | SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */ | |
80 | SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */ | |
81 | SFLAG_COLORBAR = 0x04, /* Select colorbar */ | |
82 | }; | |
83 | ||
84 | #define PROGRAM_ROM 0x0000 | |
85 | #define PROGRAM_SRAM 0x1000 | |
86 | #define PERIPHERALS0 0x8000 | |
87 | #define PERIPHERALS1 0x9000 | |
88 | #define SHARED_BUFFER 0xC000 | |
89 | ||
90 | #define HOST_TO_NGENE (SHARED_BUFFER+0x0000) | |
91 | #define NGENE_TO_HOST (SHARED_BUFFER+0x0100) | |
92 | #define NGENE_COMMAND (SHARED_BUFFER+0x0200) | |
93 | #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204) | |
94 | #define NGENE_STATUS (SHARED_BUFFER+0x0208) | |
95 | #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C) | |
96 | #define NGENE_EVENT (SHARED_BUFFER+0x0210) | |
97 | #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214) | |
98 | #define VARIABLES (SHARED_BUFFER+0x0210) | |
99 | ||
100 | #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260) | |
101 | #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264) | |
102 | #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268) | |
103 | ||
104 | #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800) | |
105 | #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900) | |
106 | #define EEPROM_AREA (SHARED_BUFFER+0x0A00) | |
107 | ||
108 | #define SG_V_IN_1 (SHARED_BUFFER+0x0A80) | |
109 | #define SG_VBI_1 (SHARED_BUFFER+0x0B00) | |
110 | #define SG_A_IN_1 (SHARED_BUFFER+0x0B80) | |
111 | #define SG_V_IN_2 (SHARED_BUFFER+0x0C00) | |
112 | #define SG_VBI_2 (SHARED_BUFFER+0x0C80) | |
113 | #define SG_A_IN_2 (SHARED_BUFFER+0x0D00) | |
114 | #define SG_V_OUT (SHARED_BUFFER+0x0D80) | |
115 | #define SG_A_OUT2 (SHARED_BUFFER+0x0E00) | |
116 | ||
117 | #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80) | |
118 | #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00) | |
119 | #define DATA_A_OUT (SHARED_BUFFER+0x0F80) | |
120 | #define DATA_V_IN_1 (SHARED_BUFFER+0x1000) | |
121 | #define DATA_V_IN_2 (SHARED_BUFFER+0x2000) | |
122 | #define DATA_V_OUT (SHARED_BUFFER+0x3000) | |
123 | ||
124 | #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000) | |
125 | ||
126 | #define TIMESTAMPS 0xA000 | |
127 | #define SCRATCHPAD 0xA080 | |
128 | #define FORCE_INT 0xA088 | |
129 | #define FORCE_NMI 0xA090 | |
130 | #define INT_STATUS 0xA0A0 | |
131 | ||
132 | #define DEV_VER 0x9004 | |
133 | ||
134 | #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF) | |
135 | ||
136 | struct SG_ADDR { | |
137 | u64 start; | |
138 | u64 curr; | |
139 | u16 curr_ptr; | |
140 | u16 elements; | |
141 | u32 pad[3]; | |
142 | } __attribute__ ((__packed__)); | |
143 | ||
144 | struct SHARED_MEMORY { | |
145 | /* C000 */ | |
146 | u32 HostToNgene[64]; | |
147 | ||
148 | /* C100 */ | |
149 | u32 NgeneToHost[64]; | |
150 | ||
151 | /* C200 */ | |
152 | u64 NgeneCommand; | |
153 | u64 NgeneStatus; | |
154 | u64 NgeneEvent; | |
155 | ||
156 | /* C210 */ | |
157 | u8 pad1[0xc260 - 0xc218]; | |
158 | ||
159 | /* C260 */ | |
160 | u32 IntCounts; | |
161 | u32 IntEnable; | |
162 | ||
163 | /* C268 */ | |
164 | u8 pad2[0xd000 - 0xc268]; | |
165 | ||
166 | } __attribute__ ((__packed__)); | |
167 | ||
168 | struct BUFFER_STREAM_RESULTS { | |
169 | u32 Clock; /* Stream time in 100ns units */ | |
170 | u16 RemainingLines; /* Remaining lines in this field. | |
171 | 0 for complete field */ | |
172 | u8 FieldCount; /* Video field number */ | |
173 | u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow, | |
174 | Bit 0 = FieldID */ | |
175 | u16 BlockCount; /* Audio block count (unused) */ | |
176 | u8 Reserved[2]; | |
177 | u32 DTOUpdate; | |
178 | } __attribute__ ((__packed__)); | |
179 | ||
180 | struct HW_SCATTER_GATHER_ELEMENT { | |
181 | u64 Address; | |
182 | u32 Length; | |
183 | u32 Reserved; | |
184 | } __attribute__ ((__packed__)); | |
185 | ||
186 | struct BUFFER_HEADER { | |
187 | u64 Next; | |
188 | struct BUFFER_STREAM_RESULTS SR; | |
189 | ||
190 | u32 Number_of_entries_1; | |
191 | u32 Reserved5; | |
192 | u64 Address_of_first_entry_1; | |
193 | ||
194 | u32 Number_of_entries_2; | |
195 | u32 Reserved7; | |
196 | u64 Address_of_first_entry_2; | |
197 | } __attribute__ ((__packed__)); | |
198 | ||
199 | struct EVENT_BUFFER { | |
200 | u32 TimeStamp; | |
201 | u8 GPIOStatus; | |
202 | u8 UARTStatus; | |
203 | u8 RXCharacter; | |
204 | u8 EventStatus; | |
205 | u32 Reserved[2]; | |
206 | } __attribute__ ((__packed__)); | |
207 | ||
dae52d00 MB |
208 | /* Firmware commands. */ |
209 | ||
210 | enum OPCODES { | |
211 | CMD_NOP = 0, | |
212 | CMD_FWLOAD_PREPARE = 0x01, | |
213 | CMD_FWLOAD_FINISH = 0x02, | |
214 | CMD_I2C_READ = 0x03, | |
215 | CMD_I2C_WRITE = 0x04, | |
216 | ||
217 | CMD_I2C_WRITE_NOSTOP = 0x05, | |
218 | CMD_I2C_CONTINUE_WRITE = 0x06, | |
219 | CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07, | |
220 | ||
221 | CMD_DEBUG_OUTPUT = 0x09, | |
222 | ||
223 | CMD_CONTROL = 0x10, | |
224 | CMD_CONFIGURE_BUFFER = 0x11, | |
225 | CMD_CONFIGURE_FREE_BUFFER = 0x12, | |
226 | ||
227 | CMD_SPI_READ = 0x13, | |
228 | CMD_SPI_WRITE = 0x14, | |
229 | ||
230 | CMD_MEM_READ = 0x20, | |
231 | CMD_MEM_WRITE = 0x21, | |
232 | CMD_SFR_READ = 0x22, | |
233 | CMD_SFR_WRITE = 0x23, | |
234 | CMD_IRAM_READ = 0x24, | |
235 | CMD_IRAM_WRITE = 0x25, | |
236 | CMD_SET_GPIO_PIN = 0x26, | |
237 | CMD_SET_GPIO_INT = 0x27, | |
238 | CMD_CONFIGURE_UART = 0x28, | |
239 | CMD_WRITE_UART = 0x29, | |
240 | MAX_CMD | |
241 | }; | |
242 | ||
243 | enum RESPONSES { | |
244 | OK = 0, | |
245 | ERROR = 1 | |
246 | }; | |
247 | ||
248 | struct FW_HEADER { | |
249 | u8 Opcode; | |
250 | u8 Length; | |
251 | } __attribute__ ((__packed__)); | |
252 | ||
253 | struct FW_I2C_WRITE { | |
254 | struct FW_HEADER hdr; | |
255 | u8 Device; | |
256 | u8 Data[250]; | |
257 | } __attribute__ ((__packed__)); | |
258 | ||
259 | struct FW_I2C_CONTINUE_WRITE { | |
260 | struct FW_HEADER hdr; | |
261 | u8 Data[250]; | |
262 | } __attribute__ ((__packed__)); | |
263 | ||
264 | struct FW_I2C_READ { | |
265 | struct FW_HEADER hdr; | |
266 | u8 Device; | |
267 | u8 Data[252]; /* followed by two bytes of read data count */ | |
268 | } __attribute__ ((__packed__)); | |
269 | ||
270 | struct FW_SPI_WRITE { | |
271 | struct FW_HEADER hdr; | |
272 | u8 ModeSelect; | |
273 | u8 Data[250]; | |
274 | } __attribute__ ((__packed__)); | |
275 | ||
276 | struct FW_SPI_READ { | |
277 | struct FW_HEADER hdr; | |
278 | u8 ModeSelect; | |
279 | u8 Data[252]; /* followed by two bytes of read data count */ | |
280 | } __attribute__ ((__packed__)); | |
281 | ||
282 | struct FW_FWLOAD_PREPARE { | |
283 | struct FW_HEADER hdr; | |
284 | } __attribute__ ((__packed__)); | |
285 | ||
286 | struct FW_FWLOAD_FINISH { | |
287 | struct FW_HEADER hdr; | |
288 | u16 Address; /* address of final block */ | |
289 | u16 Length; | |
290 | } __attribute__ ((__packed__)); | |
291 | ||
292 | /* | |
293 | * Meaning of FW_STREAM_CONTROL::Mode bits: | |
294 | * Bit 7: Loopback PEXin to PEXout using TVOut channel | |
295 | * Bit 6: AVLOOP | |
296 | * Bit 5: Audio select; 0=I2S, 1=SPDIF | |
297 | * Bit 4: AVSYNC | |
298 | * Bit 3: Enable transport stream | |
299 | * Bit 2: Enable audio capture | |
300 | * Bit 1: Enable ITU-Video VBI capture | |
301 | * Bit 0: Enable ITU-Video capture | |
302 | * | |
303 | * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL) | |
304 | * Bit 7: continuous capture | |
305 | * Bit 6: capture one field | |
306 | * Bit 5: capture one frame | |
307 | * Bit 4: unused | |
308 | * Bit 3: starting field; 0=odd, 1=even | |
309 | * Bit 2: sample size; 0=8-bit, 1=10-bit | |
310 | * Bit 1: data format; 0=UYVY, 1=YUY2 | |
311 | * Bit 0: resets buffer pointers | |
312 | */ | |
313 | ||
314 | enum FSC_MODE_BITS { | |
315 | SMODE_LOOPBACK = 0x80, | |
316 | SMODE_AVLOOP = 0x40, | |
317 | _SMODE_AUDIO_SPDIF = 0x20, | |
318 | _SMODE_AVSYNC = 0x10, | |
319 | _SMODE_TRANSPORT_STREAM = 0x08, | |
320 | _SMODE_AUDIO_CAPTURE = 0x04, | |
321 | _SMODE_VBI_CAPTURE = 0x02, | |
322 | _SMODE_VIDEO_CAPTURE = 0x01 | |
323 | }; | |
324 | ||
325 | ||
326 | /* Meaning of FW_STREAM_CONTROL::Stream bits: | |
327 | * Bit 3: Audio sample count: 0 = relative, 1 = absolute | |
328 | * Bit 2: color bar select; 1=color bars, 0=CV3 decoder | |
329 | * Bits 1-0: stream select, UVI1, UVI2, TVOUT | |
330 | */ | |
331 | ||
332 | struct FW_STREAM_CONTROL { | |
333 | struct FW_HEADER hdr; | |
334 | u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */ | |
335 | u8 Control; /* Value written to UVI1_CTL */ | |
336 | u8 Mode; /* Controls clock source */ | |
337 | u8 SetupDataLen; /* Length of setup data, MSB=1 write | |
338 | backwards */ | |
339 | u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer | |
340 | for TS and Audio */ | |
341 | u64 Buffer_Address; /* Address of first buffer header */ | |
342 | u16 BytesPerVideoLine; | |
343 | u16 MaxLinesPerField; | |
344 | u16 MinLinesPerField; | |
345 | u16 Reserved_1; | |
346 | u16 BytesPerVBILine; | |
347 | u16 MaxVBILinesPerField; | |
348 | u16 MinVBILinesPerField; | |
349 | u16 SetupDataAddr; /* ngene relative address of setup data */ | |
350 | u8 SetupData[32]; /* setup data */ | |
351 | } __attribute__((__packed__)); | |
352 | ||
353 | #define AUDIO_BLOCK_SIZE 256 | |
354 | #define TS_BLOCK_SIZE 256 | |
355 | ||
356 | struct FW_MEM_READ { | |
357 | struct FW_HEADER hdr; | |
358 | u16 address; | |
359 | } __attribute__ ((__packed__)); | |
360 | ||
361 | struct FW_MEM_WRITE { | |
362 | struct FW_HEADER hdr; | |
363 | u16 address; | |
364 | u8 data; | |
365 | } __attribute__ ((__packed__)); | |
366 | ||
367 | struct FW_SFR_IRAM_READ { | |
368 | struct FW_HEADER hdr; | |
369 | u8 address; | |
370 | } __attribute__ ((__packed__)); | |
371 | ||
372 | struct FW_SFR_IRAM_WRITE { | |
373 | struct FW_HEADER hdr; | |
374 | u8 address; | |
375 | u8 data; | |
376 | } __attribute__ ((__packed__)); | |
377 | ||
378 | struct FW_SET_GPIO_PIN { | |
379 | struct FW_HEADER hdr; | |
380 | u8 select; | |
381 | } __attribute__ ((__packed__)); | |
382 | ||
383 | struct FW_SET_GPIO_INT { | |
384 | struct FW_HEADER hdr; | |
385 | u8 select; | |
386 | } __attribute__ ((__packed__)); | |
387 | ||
388 | struct FW_SET_DEBUGMODE { | |
389 | struct FW_HEADER hdr; | |
390 | u8 debug_flags; | |
391 | } __attribute__ ((__packed__)); | |
392 | ||
393 | struct FW_CONFIGURE_BUFFERS { | |
394 | struct FW_HEADER hdr; | |
395 | u8 config; | |
396 | } __attribute__ ((__packed__)); | |
397 | ||
398 | enum _BUFFER_CONFIGS { | |
399 | /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */ | |
400 | BUFFER_CONFIG_4422 = 0, | |
401 | /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */ | |
402 | BUFFER_CONFIG_3333 = 1, | |
403 | /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */ | |
404 | BUFFER_CONFIG_8022 = 2, | |
405 | BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */ | |
406 | }; | |
407 | ||
408 | struct FW_CONFIGURE_FREE_BUFFERS { | |
409 | struct FW_HEADER hdr; | |
410 | u8 UVI1_BufferLength; | |
411 | u8 UVI2_BufferLength; | |
412 | u8 TVO_BufferLength; | |
413 | u8 AUD1_BufferLength; | |
414 | u8 AUD2_BufferLength; | |
415 | u8 TVA_BufferLength; | |
416 | } __attribute__ ((__packed__)); | |
417 | ||
418 | struct FW_CONFIGURE_UART { | |
419 | struct FW_HEADER hdr; | |
420 | u8 UartControl; | |
421 | } __attribute__ ((__packed__)); | |
422 | ||
423 | enum _UART_CONFIG { | |
424 | _UART_BAUDRATE_19200 = 0, | |
425 | _UART_BAUDRATE_9600 = 1, | |
426 | _UART_BAUDRATE_4800 = 2, | |
427 | _UART_BAUDRATE_2400 = 3, | |
428 | _UART_RX_ENABLE = 0x40, | |
429 | _UART_TX_ENABLE = 0x80, | |
430 | }; | |
431 | ||
432 | struct FW_WRITE_UART { | |
433 | struct FW_HEADER hdr; | |
434 | u8 Data[252]; | |
435 | } __attribute__ ((__packed__)); | |
436 | ||
437 | ||
438 | struct ngene_command { | |
439 | u32 in_len; | |
440 | u32 out_len; | |
441 | union { | |
442 | u32 raw[64]; | |
443 | u8 raw8[256]; | |
444 | struct FW_HEADER hdr; | |
445 | struct FW_I2C_WRITE I2CWrite; | |
446 | struct FW_I2C_CONTINUE_WRITE I2CContinueWrite; | |
447 | struct FW_I2C_READ I2CRead; | |
448 | struct FW_STREAM_CONTROL StreamControl; | |
449 | struct FW_FWLOAD_PREPARE FWLoadPrepare; | |
450 | struct FW_FWLOAD_FINISH FWLoadFinish; | |
451 | struct FW_MEM_READ MemoryRead; | |
452 | struct FW_MEM_WRITE MemoryWrite; | |
453 | struct FW_SFR_IRAM_READ SfrIramRead; | |
454 | struct FW_SFR_IRAM_WRITE SfrIramWrite; | |
455 | struct FW_SPI_WRITE SPIWrite; | |
456 | struct FW_SPI_READ SPIRead; | |
457 | struct FW_SET_GPIO_PIN SetGpioPin; | |
458 | struct FW_SET_GPIO_INT SetGpioInt; | |
459 | struct FW_SET_DEBUGMODE SetDebugMode; | |
460 | struct FW_CONFIGURE_BUFFERS ConfigureBuffers; | |
461 | struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers; | |
462 | struct FW_CONFIGURE_UART ConfigureUart; | |
463 | struct FW_WRITE_UART WriteUart; | |
464 | } cmd; | |
465 | } __attribute__ ((__packed__)); | |
466 | ||
467 | #define NGENE_INTERFACE_VERSION 0x103 | |
468 | #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */ | |
469 | #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */ | |
470 | #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */ | |
471 | #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */ | |
472 | #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page | |
473 | Max: (1920x1080i60) */ | |
474 | ||
475 | #define OVERFLOW_BUFFER_SIZE (8192) | |
476 | ||
477 | #define RING_SIZE_VIDEO 4 | |
478 | #define RING_SIZE_AUDIO 8 | |
479 | #define RING_SIZE_TS 8 | |
480 | ||
481 | #define NUM_SCATTER_GATHER_ENTRIES 8 | |
482 | ||
483 | #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \ | |
484 | RING_SIZE_VIDEO * 2) + \ | |
485 | (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \ | |
486 | (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \ | |
487 | (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \ | |
488 | (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \ | |
489 | (RING_SIZE_TS * PAGE_SIZE * 4) + \ | |
490 | 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE) | |
491 | ||
492 | #define EVENT_QUEUE_SIZE 16 | |
493 | ||
dae52d00 MB |
494 | /* Gathers the current state of a single channel. */ |
495 | ||
496 | struct SBufferHeader { | |
497 | struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */ | |
498 | struct SBufferHeader *Next; | |
499 | void *Buffer1; | |
684688d8 | 500 | struct HW_SCATTER_GATHER_ELEMENT *scList1; |
dae52d00 | 501 | void *Buffer2; |
684688d8 | 502 | struct HW_SCATTER_GATHER_ELEMENT *scList2; |
dae52d00 MB |
503 | }; |
504 | ||
505 | /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */ | |
506 | #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63) | |
507 | ||
508 | enum HWSTATE { | |
509 | HWSTATE_STOP, | |
510 | HWSTATE_STARTUP, | |
511 | HWSTATE_RUN, | |
512 | HWSTATE_PAUSE, | |
513 | }; | |
514 | ||
515 | enum KSSTATE { | |
516 | KSSTATE_STOP, | |
517 | KSSTATE_ACQUIRE, | |
518 | KSSTATE_PAUSE, | |
519 | KSSTATE_RUN, | |
520 | }; | |
521 | ||
522 | struct SRingBufferDescriptor { | |
523 | struct SBufferHeader *Head; /* Points to first buffer in ring buffer | |
524 | structure*/ | |
525 | u64 PAHead; /* Physical address of first buffer */ | |
526 | u32 MemSize; /* Memory size of allocated ring buffers | |
527 | (needed for freeing) */ | |
528 | u32 NumBuffers; /* Number of buffers in the ring */ | |
529 | u32 Buffer1Length; /* Allocated length of Buffer 1 */ | |
530 | u32 Buffer2Length; /* Allocated length of Buffer 2 */ | |
531 | void *SCListMem; /* Memory to hold scatter gather lists for this | |
532 | ring */ | |
533 | u64 PASCListMem; /* Physical address .. */ | |
534 | u32 SCListMemSize; /* Size of this memory */ | |
535 | }; | |
536 | ||
537 | enum STREAMMODEFLAGS { | |
538 | StreamMode_NONE = 0, /* Stream not used */ | |
539 | StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */ | |
540 | StreamMode_TSIN = 2, /* Transport stream input (all) */ | |
541 | StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60 | |
542 | (only stream 0) */ | |
543 | StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */ | |
544 | }; | |
545 | ||
546 | ||
547 | enum BufferExchangeFlags { | |
548 | BEF_EVEN_FIELD = 0x00000001, | |
549 | BEF_CONTINUATION = 0x00000002, | |
550 | BEF_MORE_DATA = 0x00000004, | |
551 | BEF_OVERFLOW = 0x00000008, | |
552 | DF_SWAP32 = 0x00010000, | |
553 | }; | |
554 | ||
555 | typedef void *(IBufferExchange)(void *, void *, u32, u32, u32); | |
556 | ||
684688d8 | 557 | struct MICI_STREAMINFO { |
dae52d00 MB |
558 | IBufferExchange *pExchange; |
559 | IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */ | |
560 | u8 Stream; | |
561 | u8 Flags; | |
562 | u8 Mode; | |
563 | u8 Reserved; | |
564 | u16 nLinesVideo; | |
565 | u16 nBytesPerLineVideo; | |
566 | u16 nLinesVBI; | |
567 | u16 nBytesPerLineVBI; | |
568 | u32 CaptureLength; /* Used for audio and transport stream */ | |
684688d8 | 569 | }; |
dae52d00 MB |
570 | |
571 | /****************************************************************************/ | |
572 | /* STRUCTS ******************************************************************/ | |
573 | /****************************************************************************/ | |
574 | ||
575 | /* sound hardware definition */ | |
576 | #define MIXER_ADDR_TVTUNER 0 | |
577 | #define MIXER_ADDR_LAST 0 | |
578 | ||
579 | struct ngene_channel; | |
580 | ||
581 | /*struct sound chip*/ | |
582 | ||
583 | struct mychip { | |
584 | struct ngene_channel *chan; | |
585 | struct snd_card *card; | |
586 | struct pci_dev *pci; | |
587 | struct snd_pcm_substream *substream; | |
588 | struct snd_pcm *pcm; | |
589 | unsigned long port; | |
590 | int irq; | |
591 | spinlock_t mixer_lock; | |
592 | spinlock_t lock; | |
593 | int mixer_volume[MIXER_ADDR_LAST + 1][2]; | |
594 | int capture_source[MIXER_ADDR_LAST + 1][2]; | |
595 | }; | |
596 | ||
597 | #ifdef NGENE_V4L | |
598 | struct ngene_overlay { | |
599 | int tvnorm; | |
600 | struct v4l2_rect w; | |
601 | enum v4l2_field field; | |
602 | struct v4l2_clip *clips; | |
603 | int nclips; | |
604 | int setup_ok; | |
605 | }; | |
606 | ||
607 | struct ngene_tvnorm { | |
608 | int v4l2_id; | |
609 | char *name; | |
610 | u16 swidth, sheight; /* scaled standard width, height */ | |
611 | int tuner_norm; | |
612 | int soundstd; | |
613 | }; | |
614 | ||
615 | struct ngene_vopen { | |
616 | struct ngene_channel *ch; | |
617 | enum v4l2_priority prio; | |
618 | int width; | |
619 | int height; | |
620 | int depth; | |
621 | struct videobuf_queue vbuf_q; | |
622 | struct videobuf_queue vbi; | |
623 | int fourcc; | |
624 | int picxcount; | |
625 | int resources; | |
626 | enum v4l2_buf_type type; | |
627 | const struct ngene_format *fmt; | |
628 | ||
629 | const struct ngene_format *ovfmt; | |
630 | struct ngene_overlay ov; | |
631 | }; | |
632 | #endif | |
633 | ||
634 | struct ngene_channel { | |
635 | struct device device; | |
636 | struct i2c_adapter i2c_adapter; | |
637 | ||
638 | struct ngene *dev; | |
639 | int number; | |
640 | int type; | |
641 | int mode; | |
3d0cef2c OE |
642 | bool has_adapter; |
643 | bool has_demux; | |
9ca9efb0 RM |
644 | int demod_type; |
645 | int (*gate_ctrl)(struct dvb_frontend *, int); | |
dae52d00 MB |
646 | |
647 | struct dvb_frontend *fe; | |
9ca9efb0 | 648 | struct dvb_frontend *fe2; |
dae52d00 MB |
649 | struct dmxdev dmxdev; |
650 | struct dvb_demux demux; | |
cce33c34 | 651 | struct dvb_net dvbnet; |
dae52d00 MB |
652 | struct dmx_frontend hw_frontend; |
653 | struct dmx_frontend mem_frontend; | |
654 | int users; | |
655 | struct video_device *v4l_dev; | |
0f0b270f | 656 | struct dvb_device *ci_dev; |
dae52d00 MB |
657 | struct tasklet_struct demux_tasklet; |
658 | ||
659 | struct SBufferHeader *nextBuffer; | |
660 | enum KSSTATE State; | |
661 | enum HWSTATE HWState; | |
662 | u8 Stream; | |
663 | u8 Flags; | |
664 | u8 Mode; | |
665 | IBufferExchange *pBufferExchange; | |
666 | IBufferExchange *pBufferExchange2; | |
667 | ||
668 | spinlock_t state_lock; | |
669 | u16 nLines; | |
670 | u16 nBytesPerLine; | |
671 | u16 nVBILines; | |
672 | u16 nBytesPerVBILine; | |
673 | u16 itumode; | |
674 | u32 Capture1Length; | |
675 | u32 Capture2Length; | |
676 | struct SRingBufferDescriptor RingBuffer; | |
677 | struct SRingBufferDescriptor TSRingBuffer; | |
678 | struct SRingBufferDescriptor TSIdleBuffer; | |
679 | ||
680 | u32 DataFormatFlags; | |
681 | ||
682 | int AudioDTOUpdated; | |
683 | u32 AudioDTOValue; | |
684 | ||
685 | int (*set_tone)(struct dvb_frontend *, fe_sec_tone_mode_t); | |
686 | u8 lnbh; | |
687 | ||
688 | /* stuff from analog driver */ | |
689 | ||
690 | int minor; | |
691 | struct mychip *mychip; | |
692 | struct snd_card *soundcard; | |
693 | u8 *evenbuffer; | |
dae52d00 MB |
694 | u8 dma_on; |
695 | int soundstreamon; | |
696 | int audiomute; | |
697 | int soundbuffisallocated; | |
698 | int sndbuffflag; | |
699 | int tun_rdy; | |
700 | int dec_rdy; | |
701 | int tun_dec_rdy; | |
702 | int lastbufferflag; | |
703 | ||
704 | struct ngene_tvnorm *tvnorms; | |
705 | int tvnorm_num; | |
706 | int tvnorm; | |
707 | ||
708 | #ifdef NGENE_V4L | |
709 | int videousers; | |
710 | struct v4l2_prio_state prio; | |
711 | struct ngene_vopen init; | |
712 | int resources; | |
713 | struct v4l2_framebuffer fbuf; | |
714 | struct ngene_buffer *screen; /* overlay */ | |
715 | struct list_head capture; /* video capture queue */ | |
716 | spinlock_t s_lock; | |
717 | struct semaphore reslock; | |
718 | #endif | |
719 | ||
720 | int running; | |
721 | }; | |
722 | ||
0f0b270f RM |
723 | |
724 | struct ngene_ci { | |
725 | struct device device; | |
726 | struct i2c_adapter i2c_adapter; | |
727 | ||
728 | struct ngene *dev; | |
729 | struct dvb_ca_en50221 *en; | |
730 | }; | |
731 | ||
dae52d00 MB |
732 | struct ngene; |
733 | ||
734 | typedef void (rx_cb_t)(struct ngene *, u32, u8); | |
735 | typedef void (tx_cb_t)(struct ngene *, u32); | |
736 | ||
737 | struct ngene { | |
738 | int nr; | |
739 | struct pci_dev *pci_dev; | |
740 | unsigned char *iomem; | |
741 | ||
dae52d00 MB |
742 | /*struct i2c_adapter i2c_adapter;*/ |
743 | ||
744 | u32 device_version; | |
745 | u32 fw_interface_version; | |
746 | u32 icounts; | |
43874181 | 747 | bool msi_enabled; |
5a2a1848 | 748 | bool cmd_timeout_workaround; |
dae52d00 MB |
749 | |
750 | u8 *CmdDoneByte; | |
751 | int BootFirmware; | |
752 | void *OverflowBuffer; | |
753 | dma_addr_t PAOverflowBuffer; | |
754 | void *FWInterfaceBuffer; | |
755 | dma_addr_t PAFWInterfaceBuffer; | |
756 | u8 *ngenetohost; | |
757 | u8 *hosttongene; | |
758 | ||
759 | struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE]; | |
760 | int EventQueueOverflowCount; | |
761 | int EventQueueOverflowFlag; | |
762 | struct tasklet_struct event_tasklet; | |
763 | struct EVENT_BUFFER *EventBuffer; | |
764 | int EventQueueWriteIndex; | |
765 | int EventQueueReadIndex; | |
766 | ||
767 | wait_queue_head_t cmd_wq; | |
768 | int cmd_done; | |
769 | struct semaphore cmd_mutex; | |
770 | struct semaphore stream_mutex; | |
771 | struct semaphore pll_mutex; | |
772 | struct semaphore i2c_switch_mutex; | |
773 | int i2c_current_channel; | |
774 | int i2c_current_bus; | |
775 | spinlock_t cmd_lock; | |
776 | ||
cf1b12f2 | 777 | struct dvb_adapter adapter[MAX_STREAM]; |
fdafc96c | 778 | struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */ |
dae52d00 MB |
779 | struct ngene_channel channel[MAX_STREAM]; |
780 | ||
781 | struct ngene_info *card_info; | |
782 | ||
783 | tx_cb_t *TxEventNotify; | |
784 | rx_cb_t *RxEventNotify; | |
785 | int tx_busy; | |
786 | wait_queue_head_t tx_wq; | |
787 | wait_queue_head_t rx_wq; | |
788 | #define UART_RBUF_LEN 4096 | |
789 | u8 uart_rbuf[UART_RBUF_LEN]; | |
790 | int uart_rp, uart_wp; | |
791 | ||
36e3fc89 OE |
792 | #define TS_FILLER 0x6f |
793 | ||
dae52d00 MB |
794 | u8 *tsout_buf; |
795 | #define TSOUT_BUF_SIZE (512*188*8) | |
796 | struct dvb_ringbuffer tsout_rbuf; | |
797 | ||
0f0b270f RM |
798 | u8 *tsin_buf; |
799 | #define TSIN_BUF_SIZE (512*188*8) | |
800 | struct dvb_ringbuffer tsin_rbuf; | |
801 | ||
dae52d00 MB |
802 | u8 *ain_buf; |
803 | #define AIN_BUF_SIZE (128*1024) | |
804 | struct dvb_ringbuffer ain_rbuf; | |
805 | ||
806 | ||
807 | u8 *vin_buf; | |
808 | #define VIN_BUF_SIZE (4*1920*1080) | |
809 | struct dvb_ringbuffer vin_rbuf; | |
810 | ||
811 | unsigned long exp_val; | |
812 | int prev_cmd; | |
0f0b270f RM |
813 | |
814 | struct ngene_ci ci; | |
dae52d00 MB |
815 | }; |
816 | ||
dae52d00 MB |
817 | struct ngene_info { |
818 | int type; | |
819 | #define NGENE_APP 0 | |
820 | #define NGENE_TERRATEC 1 | |
821 | #define NGENE_SIDEWINDER 2 | |
822 | #define NGENE_RACER 3 | |
823 | #define NGENE_VIPER 4 | |
824 | #define NGENE_PYTHON 5 | |
825 | #define NGENE_VBOX_V1 6 | |
826 | #define NGENE_VBOX_V2 7 | |
827 | ||
828 | int fw_version; | |
43874181 | 829 | bool msi_supported; |
dae52d00 MB |
830 | char *name; |
831 | ||
832 | int io_type[MAX_STREAM]; | |
833 | #define NGENE_IO_NONE 0 | |
834 | #define NGENE_IO_TV 1 | |
835 | #define NGENE_IO_HDTV 2 | |
836 | #define NGENE_IO_TSIN 4 | |
837 | #define NGENE_IO_TSOUT 8 | |
838 | #define NGENE_IO_AIN 16 | |
839 | ||
840 | void *fe_config[4]; | |
841 | void *tuner_config[4]; | |
842 | ||
843 | int (*demod_attach[4])(struct ngene_channel *); | |
844 | int (*tuner_attach[4])(struct ngene_channel *); | |
845 | ||
846 | u8 avf[4]; | |
847 | u8 msp[4]; | |
848 | u8 demoda[4]; | |
849 | u8 lnb[4]; | |
850 | int i2c_access; | |
851 | u8 ntsc; | |
dae52d00 MB |
852 | u8 tsf[4]; |
853 | u8 i2s[4]; | |
854 | ||
855 | int (*gate_ctrl)(struct dvb_frontend *, int); | |
856 | int (*switch_ctrl)(struct ngene_channel *, int, int); | |
857 | }; | |
858 | ||
859 | #ifdef NGENE_V4L | |
9143a437 | 860 | struct ngene_format { |
dae52d00 MB |
861 | char *name; |
862 | int fourcc; /* video4linux 2 */ | |
863 | int btformat; /* BT848_COLOR_FMT_* */ | |
864 | int format; | |
865 | int btswap; /* BT848_COLOR_CTL_* */ | |
866 | int depth; /* bit/pixel */ | |
867 | int flags; | |
868 | int hshift, vshift; /* for planar modes */ | |
869 | int palette; | |
870 | }; | |
871 | ||
872 | #define RESOURCE_OVERLAY 1 | |
873 | #define RESOURCE_VIDEO 2 | |
874 | #define RESOURCE_VBI 4 | |
875 | ||
876 | struct ngene_buffer { | |
877 | /* common v4l buffer stuff -- must be first */ | |
878 | struct videobuf_buffer vb; | |
879 | ||
880 | /* ngene specific */ | |
881 | const struct ngene_format *fmt; | |
882 | int tvnorm; | |
883 | int btformat; | |
884 | int btswap; | |
885 | }; | |
886 | #endif | |
887 | ||
dae52d00 | 888 | |
cb1c0f8e | 889 | /* Provided by ngene-core.c */ |
4c62e976 GKH |
890 | int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id); |
891 | void ngene_remove(struct pci_dev *pdev); | |
1b7c41ef | 892 | void ngene_shutdown(struct pci_dev *pdev); |
cb1c0f8e DH |
893 | int ngene_command(struct ngene *dev, struct ngene_command *com); |
894 | int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level); | |
1899e97c DH |
895 | void set_transfer(struct ngene_channel *chan, int state); |
896 | void FillTSBuffer(void *Buffer, int Length, u32 Flags); | |
cb1c0f8e DH |
897 | |
898 | /* Provided by ngene-i2c.c */ | |
899 | int ngene_i2c_init(struct ngene *dev, int dev_nr); | |
900 | ||
1899e97c | 901 | /* Provided by ngene-dvb.c */ |
0f0b270f | 902 | extern struct dvb_device ngene_dvbdev_ci; |
1899e97c DH |
903 | void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); |
904 | void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); | |
905 | int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed); | |
906 | int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed); | |
907 | int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, | |
908 | int (*start_feed)(struct dvb_demux_feed *), | |
909 | int (*stop_feed)(struct dvb_demux_feed *), | |
910 | void *priv); | |
911 | int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, | |
912 | struct dvb_demux *dvbdemux, | |
913 | struct dmx_frontend *hw_frontend, | |
914 | struct dmx_frontend *mem_frontend, | |
915 | struct dvb_adapter *dvb_adapter); | |
916 | ||
dae52d00 MB |
917 | #endif |
918 | ||
919 | /* LocalWords: Endif | |
920 | */ |