projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 417d2e50 BP |
1 | /* |
| 2 | * TI AM437x Image Sensor Interface Registers | |
| 3 | * | |
| 4 | * Copyright (C) 2013 - 2014 Texas Instruments, Inc. | |
| 5 | * | |
| 6 | * Benoit Parrot <bparrot@ti.com> | |
| 7 | * Lad, Prabhakar <prabhakar.csengg@gmail.com> | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | * | |
| 13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
| 14 | * kind, whether express or implied; without even the implied warranty | |
| 15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | */ | |
| 18 | ||
| 19 | #ifndef AM437X_VPFE_REGS_H | |
| 20 | #define AM437X_VPFE_REGS_H | |
| 21 | ||
| 22 | /* VPFE module register offset */ | |
| 23 | #define VPFE_REVISION 0x0 | |
| 24 | #define VPFE_PCR 0x4 | |
| 25 | #define VPFE_SYNMODE 0x8 | |
| 26 | #define VPFE_HD_VD_WID 0xc | |
| 27 | #define VPFE_PIX_LINES 0x10 | |
| 28 | #define VPFE_HORZ_INFO 0x14 | |
| 29 | #define VPFE_VERT_START 0x18 | |
| 30 | #define VPFE_VERT_LINES 0x1c | |
| 31 | #define VPFE_CULLING 0x20 | |
| 32 | #define VPFE_HSIZE_OFF 0x24 | |
| 33 | #define VPFE_SDOFST 0x28 | |
| 34 | #define VPFE_SDR_ADDR 0x2c | |
| 35 | #define VPFE_CLAMP 0x30 | |
| 36 | #define VPFE_DCSUB 0x34 | |
| 37 | #define VPFE_COLPTN 0x38 | |
| 38 | #define VPFE_BLKCMP 0x3c | |
| 39 | #define VPFE_VDINT 0x48 | |
| 40 | #define VPFE_ALAW 0x4c | |
| 41 | #define VPFE_REC656IF 0x50 | |
| 42 | #define VPFE_CCDCFG 0x54 | |
| 43 | #define VPFE_DMA_CNTL 0x98 | |
| 44 | #define VPFE_SYSCONFIG 0x104 | |
| 45 | #define VPFE_CONFIG 0x108 | |
| 46 | #define VPFE_IRQ_EOI 0x110 | |
| 47 | #define VPFE_IRQ_STS_RAW 0x114 | |
| 48 | #define VPFE_IRQ_STS 0x118 | |
| 49 | #define VPFE_IRQ_EN_SET 0x11c | |
| 50 | #define VPFE_IRQ_EN_CLR 0x120 | |
| 51 | #define VPFE_REG_END 0x124 | |
| 52 | ||
| 53 | /* Define bit fields within selected registers */ | |
| 54 | #define VPFE_FID_POL_MASK 1 | |
| 55 | #define VPFE_FID_POL_SHIFT 4 | |
| 56 | #define VPFE_HD_POL_MASK 1 | |
| 57 | #define VPFE_HD_POL_SHIFT 3 | |
| 58 | #define VPFE_VD_POL_MASK 1 | |
| 59 | #define VPFE_VD_POL_SHIFT 2 | |
| 60 | #define VPFE_HSIZE_OFF_MASK 0xffffffe0 | |
| 61 | #define VPFE_32BYTE_ALIGN_VAL 31 | |
| 62 | #define VPFE_FRM_FMT_MASK 0x1 | |
| 63 | #define VPFE_FRM_FMT_SHIFT 7 | |
| 64 | #define VPFE_DATA_SZ_MASK 7 | |
| 65 | #define VPFE_DATA_SZ_SHIFT 8 | |
| 66 | #define VPFE_PIX_FMT_MASK 3 | |
| 67 | #define VPFE_PIX_FMT_SHIFT 12 | |
| 68 | #define VPFE_VP2SDR_DISABLE 0xfffbffff | |
| 69 | #define VPFE_WEN_ENABLE (1 << 17) | |
| 70 | #define VPFE_SDR2RSZ_DISABLE 0xfff7ffff | |
| 71 | #define VPFE_VDHDEN_ENABLE (1 << 16) | |
| 72 | #define VPFE_LPF_ENABLE (1 << 14) | |
| 73 | #define VPFE_ALAW_ENABLE (1 << 3) | |
| 74 | #define VPFE_ALAW_GAMMA_WD_MASK 7 | |
| 75 | #define VPFE_BLK_CLAMP_ENABLE (1 << 31) | |
| 76 | #define VPFE_BLK_SGAIN_MASK 0x1f | |
| 77 | #define VPFE_BLK_ST_PXL_MASK 0x7fff | |
| 78 | #define VPFE_BLK_ST_PXL_SHIFT 10 | |
| 79 | #define VPFE_BLK_SAMPLE_LN_MASK 7 | |
| 80 | #define VPFE_BLK_SAMPLE_LN_SHIFT 28 | |
| 81 | #define VPFE_BLK_SAMPLE_LINE_MASK 7 | |
| 82 | #define VPFE_BLK_SAMPLE_LINE_SHIFT 25 | |
| 83 | #define VPFE_BLK_DC_SUB_MASK 0x03fff | |
| 84 | #define VPFE_BLK_COMP_MASK 0xff | |
| 85 | #define VPFE_BLK_COMP_GB_COMP_SHIFT 8 | |
| 86 | #define VPFE_BLK_COMP_GR_COMP_SHIFT 16 | |
| 87 | #define VPFE_BLK_COMP_R_COMP_SHIFT 24 | |
| 88 | #define VPFE_LATCH_ON_VSYNC_DISABLE (1 << 15) | |
| 89 | #define VPFE_DATA_PACK_ENABLE (1 << 11) | |
| 90 | #define VPFE_HORZ_INFO_SPH_SHIFT 16 | |
| 91 | #define VPFE_VERT_START_SLV0_SHIFT 16 | |
| 92 | #define VPFE_VDINT_VDINT0_SHIFT 16 | |
| 93 | #define VPFE_VDINT_VDINT1_MASK 0xffff | |
| 94 | #define VPFE_PPC_RAW 1 | |
| 95 | #define VPFE_DCSUB_DEFAULT_VAL 0 | |
| 96 | #define VPFE_CLAMP_DEFAULT_VAL 0 | |
| 97 | #define VPFE_COLPTN_VAL 0xbb11bb11 | |
| 98 | #define VPFE_TWO_BYTES_PER_PIXEL 2 | |
| 99 | #define VPFE_INTERLACED_IMAGE_INVERT 0x4b6d | |
| 100 | #define VPFE_INTERLACED_NO_IMAGE_INVERT 0x0249 | |
| 101 | #define VPFE_PROGRESSIVE_IMAGE_INVERT 0x4000 | |
| 102 | #define VPFE_PROGRESSIVE_NO_IMAGE_INVERT 0 | |
| 103 | #define VPFE_INTERLACED_HEIGHT_SHIFT 1 | |
| 104 | #define VPFE_SYN_MODE_INPMOD_SHIFT 12 | |
| 105 | #define VPFE_SYN_MODE_INPMOD_MASK 3 | |
| 106 | #define VPFE_SYN_MODE_8BITS (7 << 8) | |
| 107 | #define VPFE_SYN_MODE_10BITS (6 << 8) | |
| 108 | #define VPFE_SYN_MODE_11BITS (5 << 8) | |
| 109 | #define VPFE_SYN_MODE_12BITS (4 << 8) | |
| 110 | #define VPFE_SYN_MODE_13BITS (3 << 8) | |
| 111 | #define VPFE_SYN_MODE_14BITS (2 << 8) | |
| 112 | #define VPFE_SYN_MODE_15BITS (1 << 8) | |
| 113 | #define VPFE_SYN_MODE_16BITS (0 << 8) | |
| 114 | #define VPFE_SYN_FLDMODE_MASK 1 | |
| 115 | #define VPFE_SYN_FLDMODE_SHIFT 7 | |
| 116 | #define VPFE_REC656IF_BT656_EN 3 | |
| 117 | #define VPFE_SYN_MODE_VD_POL_NEGATIVE (1 << 2) | |
| 118 | #define VPFE_CCDCFG_Y8POS_SHIFT 11 | |
| 119 | #define VPFE_CCDCFG_BW656_10BIT (1 << 5) | |
| 120 | #define VPFE_SDOFST_FIELD_INTERLEAVED 0x249 | |
| 121 | #define VPFE_NO_CULLING 0xffff00ff | |
| 122 | #define VPFE_VDINT0 (1 << 0) | |
| 123 | #define VPFE_VDINT1 (1 << 1) | |
| 124 | #define VPFE_VDINT2 (1 << 2) | |
| 125 | #define VPFE_DMA_CNTL_OVERFLOW (1 << 31) | |
| 126 | ||
| 127 | #define VPFE_CONFIG_PCLK_INV_SHIFT 0 | |
| 128 | #define VPFE_CONFIG_PCLK_INV_MASK 1 | |
| 129 | #define VPFE_CONFIG_PCLK_INV_NOT_INV 0 | |
| 130 | #define VPFE_CONFIG_PCLK_INV_INV 1 | |
| 131 | #define VPFE_CONFIG_EN_SHIFT 1 | |
| 132 | #define VPFE_CONFIG_EN_MASK 2 | |
| 133 | #define VPFE_CONFIG_EN_DISABLE 0 | |
| 134 | #define VPFE_CONFIG_EN_ENABLE 1 | |
| 135 | #define VPFE_CONFIG_ST_SHIFT 2 | |
| 136 | #define VPFE_CONFIG_ST_MASK 4 | |
| 137 | #define VPFE_CONFIG_ST_OCP_ACTIVE 0 | |
| 138 | #define VPFE_CONFIG_ST_OCP_STANDBY 1 | |
| 139 | ||
| 140 | #endif /* AM437X_VPFE_REGS_H */ |