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[media] media: coda: fix IRAM/AXI handling for i.MX53
[deliverable/linux.git] / drivers / media / platform / coda.c
CommitLineData
186b250a
JM		 1/*
2 * Coda multi-standard codec IP
3 *
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/firmware.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/videodev2.h>
25#include <linux/of.h>
26
1043667b 27#include <mach/iram.h>
186b250a
JM		 28#include <media/v4l2-ctrls.h>
29#include <media/v4l2-device.h>
30#include <media/v4l2-ioctl.h>
31#include <media/v4l2-mem2mem.h>
32#include <media/videobuf2-core.h>
33#include <media/videobuf2-dma-contig.h>
34
35#include "coda.h"
36
37#define CODA_NAME "coda"
38
39#define CODA_MAX_INSTANCES 4
40
41#define CODA_FMO_BUF_SIZE 32
42#define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
43#define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
44#define CODA_PARA_BUF_SIZE (10 * 1024)
45#define CODA_ISRAM_SIZE (2048 * 2)
1043667b 46#define CODA7_IRAM_SIZE 0x14000 /* 81920 bytes */
186b250a
JM		 47
48#define CODA_OUTPUT_BUFS 4
49#define CODA_CAPTURE_BUFS 2
50
51#define MAX_W 720
52#define MAX_H 576
53#define CODA_MAX_FRAME_SIZE 0x90000
54#define FMO_SLICE_SAVE_BUF_SIZE (32)
55#define CODA_DEFAULT_GAMMA 4096
56
57#define MIN_W 176
58#define MIN_H 144
59#define MAX_W 720
60#define MAX_H 576
61
62#define S_ALIGN 1 /* multiple of 2 */
63#define W_ALIGN 1 /* multiple of 2 */
64#define H_ALIGN 1 /* multiple of 2 */
65
66#define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
67
68static int coda_debug;
69module_param(coda_debug, int, 0);
70MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
71
72enum {
73 V4L2_M2M_SRC = 0,
74 V4L2_M2M_DST = 1,
75};
76
77enum coda_fmt_type {
78 CODA_FMT_ENC,
79 CODA_FMT_RAW,
80};
81
82enum coda_inst_type {
83 CODA_INST_ENCODER,
84 CODA_INST_DECODER,
85};
86
87enum coda_product {
88 CODA_DX6 = 0xf001,
df1e74cc 89 CODA_7541 = 0xf012,
186b250a
JM		 90};
91
92struct coda_fmt {
93 char *name;
94 u32 fourcc;
95 enum coda_fmt_type type;
96};
97
98struct coda_devtype {
99 char *firmware;
100 enum coda_product product;
101 struct coda_fmt *formats;
102 unsigned int num_formats;
103 size_t workbuf_size;
104};
105
106/* Per-queue, driver-specific private data */
107struct coda_q_data {
108 unsigned int width;
109 unsigned int height;
110 unsigned int sizeimage;
111 struct coda_fmt *fmt;
112};
113
114struct coda_aux_buf {
115 void *vaddr;
116 dma_addr_t paddr;
117 u32 size;
118};
119
120struct coda_dev {
121 struct v4l2_device v4l2_dev;
122 struct video_device vfd;
123 struct platform_device *plat_dev;
c06d8752 124 const struct coda_devtype *devtype;
186b250a
JM		 125
126 void __iomem *regs_base;
127 struct clk *clk_per;
128 struct clk *clk_ahb;
129
130 struct coda_aux_buf codebuf;
131 struct coda_aux_buf workbuf;
1043667b 132 long unsigned int iram_paddr;
186b250a
JM		 133
134 spinlock_t irqlock;
135 struct mutex dev_mutex;
136 struct v4l2_m2m_dev *m2m_dev;
137 struct vb2_alloc_ctx *alloc_ctx;
138 int instances;
139};
140
141struct coda_params {
142 u8 h264_intra_qp;
143 u8 h264_inter_qp;
144 u8 mpeg4_intra_qp;
145 u8 mpeg4_inter_qp;
146 u8 gop_size;
147 int codec_mode;
148 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
149 u32 framerate;
150 u16 bitrate;
151 u32 slice_max_mb;
152};
153
154struct coda_ctx {
155 struct coda_dev *dev;
156 int aborting;
157 int rawstreamon;
158 int compstreamon;
159 u32 isequence;
160 struct coda_q_data q_data[2];
161 enum coda_inst_type inst_type;
162 enum v4l2_colorspace colorspace;
163 struct coda_params params;
164 struct v4l2_m2m_ctx *m2m_ctx;
165 struct v4l2_ctrl_handler ctrls;
166 struct v4l2_fh fh;
167 struct vb2_buffer *reference;
168 int gopcounter;
169 char vpu_header[3][64];
170 int vpu_header_size[3];
171 struct coda_aux_buf parabuf;
172 int idx;
173};
174
175static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
176{
177 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
178 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
179 writel(data, dev->regs_base + reg);
180}
181
182static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
183{
184 u32 data;
185 data = readl(dev->regs_base + reg);
186 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
187 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
188 return data;
189}
190
191static inline unsigned long coda_isbusy(struct coda_dev *dev)
192{
193 return coda_read(dev, CODA_REG_BIT_BUSY);
194}
195
196static inline int coda_is_initialized(struct coda_dev *dev)
197{
198 return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
199}
200
201static int coda_wait_timeout(struct coda_dev *dev)
202{
203 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
204
205 while (coda_isbusy(dev)) {
206 if (time_after(jiffies, timeout))
207 return -ETIMEDOUT;
208 }
209 return 0;
210}
211
212static void coda_command_async(struct coda_ctx *ctx, int cmd)
213{
214 struct coda_dev *dev = ctx->dev;
215 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
216
217 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
218 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
219 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
220}
221
222static int coda_command_sync(struct coda_ctx *ctx, int cmd)
223{
224 struct coda_dev *dev = ctx->dev;
225
226 coda_command_async(ctx, cmd);
227 return coda_wait_timeout(dev);
228}
229
230static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
231 enum v4l2_buf_type type)
232{
233 switch (type) {
234 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
235 return &(ctx->q_data[V4L2_M2M_SRC]);
236 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
237 return &(ctx->q_data[V4L2_M2M_DST]);
238 default:
239 BUG();
240 }
241 return NULL;
242}
243
244/*
245 * Add one array of supported formats for each version of Coda:
246 * i.MX27 -> codadx6
247 * i.MX51 -> coda7
248 * i.MX6 -> coda960
249 */
250static struct coda_fmt codadx6_formats[] = {
251 {
252 .name = "YUV 4:2:0 Planar",
253 .fourcc = V4L2_PIX_FMT_YUV420,
254 .type = CODA_FMT_RAW,
255 },
256 {
257 .name = "H264 Encoded Stream",
258 .fourcc = V4L2_PIX_FMT_H264,
259 .type = CODA_FMT_ENC,
260 },
261 {
262 .name = "MPEG4 Encoded Stream",
263 .fourcc = V4L2_PIX_FMT_MPEG4,
264 .type = CODA_FMT_ENC,
265 },
266};
267
df1e74cc
PZ		 268static struct coda_fmt coda7_formats[] = {
269 {
270 .name = "YUV 4:2:0 Planar",
271 .fourcc = V4L2_PIX_FMT_YUV420,
272 .type = CODA_FMT_RAW,
273 },
274 {
275 .name = "H264 Encoded Stream",
276 .fourcc = V4L2_PIX_FMT_H264,
277 .type = CODA_FMT_ENC,
278 },
279 {
280 .name = "MPEG4 Encoded Stream",
281 .fourcc = V4L2_PIX_FMT_MPEG4,
282 .type = CODA_FMT_ENC,
283 },
284};
285
186b250a
JM		 286static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
287{
288 struct coda_fmt *formats = dev->devtype->formats;
289 int num_formats = dev->devtype->num_formats;
290 unsigned int k;
291
292 for (k = 0; k < num_formats; k++) {
293 if (formats[k].fourcc == f->fmt.pix.pixelformat)
294 break;
295 }
296
297 if (k == num_formats)
298 return NULL;
299
300 return &formats[k];
301}
302
303/*
304 * V4L2 ioctl() operations.
305 */
306static int vidioc_querycap(struct file *file, void *priv,
307 struct v4l2_capability *cap)
308{
309 strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
310 strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
311 strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
c3aac8be
SN		 312 /*
313 * This is only a mem-to-mem video device. The capture and output
314 * device capability flags are left only for backward compatibility
315 * and are scheduled for removal.
316 */
317 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
318 V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
186b250a
JM		 319 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
320
321 return 0;
322}
323
324static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
325 enum coda_fmt_type type)
326{
327 struct coda_ctx *ctx = fh_to_ctx(priv);
328 struct coda_dev *dev = ctx->dev;
329 struct coda_fmt *formats = dev->devtype->formats;
330 struct coda_fmt *fmt;
331 int num_formats = dev->devtype->num_formats;
332 int i, num = 0;
333
334 for (i = 0; i < num_formats; i++) {
335 if (formats[i].type == type) {
336 if (num == f->index)
337 break;
338 ++num;
339 }
340 }
341
342 if (i < num_formats) {
343 fmt = &formats[i];
344 strlcpy(f->description, fmt->name, sizeof(f->description));
345 f->pixelformat = fmt->fourcc;
346 return 0;
347 }
348
349 /* Format not found */
350 return -EINVAL;
351}
352
353static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
354 struct v4l2_fmtdesc *f)
355{
356 return enum_fmt(priv, f, CODA_FMT_ENC);
357}
358
359static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
360 struct v4l2_fmtdesc *f)
361{
362 return enum_fmt(priv, f, CODA_FMT_RAW);
363}
364
365static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
366{
367 struct vb2_queue *vq;
368 struct coda_q_data *q_data;
369 struct coda_ctx *ctx = fh_to_ctx(priv);
370
371 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
372 if (!vq)
373 return -EINVAL;
374
375 q_data = get_q_data(ctx, f->type);
376
377 f->fmt.pix.field = V4L2_FIELD_NONE;
378 f->fmt.pix.pixelformat = q_data->fmt->fourcc;
379 f->fmt.pix.width = q_data->width;
380 f->fmt.pix.height = q_data->height;
381 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
382 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
383 else /* encoded formats h.264/mpeg4 */
384 f->fmt.pix.bytesperline = 0;
385
386 f->fmt.pix.sizeimage = q_data->sizeimage;
387 f->fmt.pix.colorspace = ctx->colorspace;
388
389 return 0;
390}
391
392static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
393{
394 enum v4l2_field field;
395
396 field = f->fmt.pix.field;
397 if (field == V4L2_FIELD_ANY)
398 field = V4L2_FIELD_NONE;
399 else if (V4L2_FIELD_NONE != field)
400 return -EINVAL;
401
402 /* V4L2 specification suggests the driver corrects the format struct
403 * if any of the dimensions is unsupported */
404 f->fmt.pix.field = field;
405
406 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
407 v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
408 W_ALIGN, &f->fmt.pix.height,
409 MIN_H, MAX_H, H_ALIGN, S_ALIGN);
410 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
411 f->fmt.pix.sizeimage = f->fmt.pix.height *
412 f->fmt.pix.bytesperline;
413 } else { /*encoded formats h.264/mpeg4 */
414 f->fmt.pix.bytesperline = 0;
415 f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
416 }
417
418 return 0;
419}
420
421static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
422 struct v4l2_format *f)
423{
424 int ret;
425 struct coda_fmt *fmt;
426 struct coda_ctx *ctx = fh_to_ctx(priv);
427
428 fmt = find_format(ctx->dev, f);
429 /*
430 * Since decoding support is not implemented yet do not allow
431 * CODA_FMT_RAW formats in the capture interface.
432 */
433 if (!fmt || !(fmt->type == CODA_FMT_ENC))
434 f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
435
436 f->fmt.pix.colorspace = ctx->colorspace;
437
438 ret = vidioc_try_fmt(ctx->dev, f);
439 if (ret < 0)
440 return ret;
441
442 return 0;
443}
444
445static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
446 struct v4l2_format *f)
447{
448 struct coda_ctx *ctx = fh_to_ctx(priv);
449 struct coda_fmt *fmt;
450 int ret;
451
452 fmt = find_format(ctx->dev, f);
453 /*
454 * Since decoding support is not implemented yet do not allow
455 * CODA_FMT formats in the capture interface.
456 */
457 if (!fmt || !(fmt->type == CODA_FMT_RAW))
458 f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
459
460 if (!f->fmt.pix.colorspace)
461 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
462
463 ret = vidioc_try_fmt(ctx->dev, f);
464 if (ret < 0)
465 return ret;
466
467 return 0;
468}
469
470static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
471{
472 struct coda_q_data *q_data;
473 struct vb2_queue *vq;
474 int ret;
475
476 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
477 if (!vq)
478 return -EINVAL;
479
480 q_data = get_q_data(ctx, f->type);
481 if (!q_data)
482 return -EINVAL;
483
484 if (vb2_is_busy(vq)) {
485 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
486 return -EBUSY;
487 }
488
489 ret = vidioc_try_fmt(ctx->dev, f);
490 if (ret)
491 return ret;
492
493 q_data->fmt = find_format(ctx->dev, f);
494 q_data->width = f->fmt.pix.width;
495 q_data->height = f->fmt.pix.height;
496 if (q_data->fmt->fourcc == V4L2_PIX_FMT_YUV420) {
497 q_data->sizeimage = q_data->width * q_data->height * 3 / 2;
498 } else { /* encoded format h.264/mpeg-4 */
499 q_data->sizeimage = CODA_MAX_FRAME_SIZE;
500 }
501
502 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
503 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
504 f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
505
506 return 0;
507}
508
509static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
510 struct v4l2_format *f)
511{
512 int ret;
513
514 ret = vidioc_try_fmt_vid_cap(file, priv, f);
515 if (ret)
516 return ret;
517
518 return vidioc_s_fmt(fh_to_ctx(priv), f);
519}
520
521static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
522 struct v4l2_format *f)
523{
524 struct coda_ctx *ctx = fh_to_ctx(priv);
525 int ret;
526
527 ret = vidioc_try_fmt_vid_out(file, priv, f);
528 if (ret)
529 return ret;
530
8d621472 531 ret = vidioc_s_fmt(ctx, f);
186b250a
JM		 532 if (ret)
533 ctx->colorspace = f->fmt.pix.colorspace;
534
535 return ret;
536}
537
538static int vidioc_reqbufs(struct file *file, void *priv,
539 struct v4l2_requestbuffers *reqbufs)
540{
541 struct coda_ctx *ctx = fh_to_ctx(priv);
542
543 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
544}
545
546static int vidioc_querybuf(struct file *file, void *priv,
547 struct v4l2_buffer *buf)
548{
549 struct coda_ctx *ctx = fh_to_ctx(priv);
550
551 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
552}
553
554static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
555{
556 struct coda_ctx *ctx = fh_to_ctx(priv);
557
558 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
559}
560
561static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
562{
563 struct coda_ctx *ctx = fh_to_ctx(priv);
564
565 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
566}
567
568static int vidioc_streamon(struct file *file, void *priv,
569 enum v4l2_buf_type type)
570{
571 struct coda_ctx *ctx = fh_to_ctx(priv);
572
573 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
574}
575
576static int vidioc_streamoff(struct file *file, void *priv,
577 enum v4l2_buf_type type)
578{
579 struct coda_ctx *ctx = fh_to_ctx(priv);
580
581 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
582}
583
584static const struct v4l2_ioctl_ops coda_ioctl_ops = {
585 .vidioc_querycap = vidioc_querycap,
586
587 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
588 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
589 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
590 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
591
592 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
593 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
594 .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
595 .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
596
597 .vidioc_reqbufs = vidioc_reqbufs,
598 .vidioc_querybuf = vidioc_querybuf,
599
600 .vidioc_qbuf = vidioc_qbuf,
601 .vidioc_dqbuf = vidioc_dqbuf,
602
603 .vidioc_streamon = vidioc_streamon,
604 .vidioc_streamoff = vidioc_streamoff,
605};
606
607/*
608 * Mem-to-mem operations.
609 */
610static void coda_device_run(void *m2m_priv)
611{
612 struct coda_ctx *ctx = m2m_priv;
613 struct coda_q_data *q_data_src, *q_data_dst;
614 struct vb2_buffer *src_buf, *dst_buf;
615 struct coda_dev *dev = ctx->dev;
616 int force_ipicture;
617 int quant_param = 0;
618 u32 picture_y, picture_cb, picture_cr;
619 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
620 u32 dst_fourcc;
621
622 src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
623 dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
624 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
625 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
626 dst_fourcc = q_data_dst->fmt->fourcc;
627
628 src_buf->v4l2_buf.sequence = ctx->isequence;
629 dst_buf->v4l2_buf.sequence = ctx->isequence;
630 ctx->isequence++;
631
632 /*
633 * Workaround coda firmware BUG that only marks the first
634 * frame as IDR. This is a problem for some decoders that can't
635 * recover when a frame is lost.
636 */
637 if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
638 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
639 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
640 } else {
641 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
642 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
643 }
644
645 /*
646 * Copy headers at the beginning of the first frame for H.264 only.
647 * In MPEG4 they are already copied by the coda.
648 */
649 if (src_buf->v4l2_buf.sequence == 0) {
650 pic_stream_buffer_addr =
651 vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
652 ctx->vpu_header_size[0] +
653 ctx->vpu_header_size[1] +
654 ctx->vpu_header_size[2];
655 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
656 ctx->vpu_header_size[0] -
657 ctx->vpu_header_size[1] -
658 ctx->vpu_header_size[2];
659 memcpy(vb2_plane_vaddr(dst_buf, 0),
660 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
661 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
662 &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
663 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
664 ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
665 ctx->vpu_header_size[2]);
666 } else {
667 pic_stream_buffer_addr =
668 vb2_dma_contig_plane_dma_addr(dst_buf, 0);
669 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
670 }
671
672 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
673 force_ipicture = 1;
674 switch (dst_fourcc) {
675 case V4L2_PIX_FMT_H264:
676 quant_param = ctx->params.h264_intra_qp;
677 break;
678 case V4L2_PIX_FMT_MPEG4:
679 quant_param = ctx->params.mpeg4_intra_qp;
680 break;
681 default:
682 v4l2_warn(&ctx->dev->v4l2_dev,
683 "cannot set intra qp, fmt not supported\n");
684 break;
685 }
686 } else {
687 force_ipicture = 0;
688 switch (dst_fourcc) {
689 case V4L2_PIX_FMT_H264:
690 quant_param = ctx->params.h264_inter_qp;
691 break;
692 case V4L2_PIX_FMT_MPEG4:
693 quant_param = ctx->params.mpeg4_inter_qp;
694 break;
695 default:
696 v4l2_warn(&ctx->dev->v4l2_dev,
697 "cannot set inter qp, fmt not supported\n");
698 break;
699 }
700 }
701
702 /* submit */
703 coda_write(dev, 0, CODA_CMD_ENC_PIC_ROT_MODE);
704 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
705
706
707 picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
708 picture_cb = picture_y + q_data_src->width * q_data_src->height;
709 picture_cr = picture_cb + q_data_src->width / 2 *
710 q_data_src->height / 2;
711
712 coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
713 coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
714 coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
715 coda_write(dev, force_ipicture << 1 & 0x2,
716 CODA_CMD_ENC_PIC_OPTION);
717
718 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
719 coda_write(dev, pic_stream_buffer_size / 1024,
720 CODA_CMD_ENC_PIC_BB_SIZE);
1043667b
PZ		 721
722 if (dev->devtype->product == CODA_7541) {
723 coda_write(dev, CODA7_USE_BIT_ENABLE | CODA7_USE_HOST_BIT_ENABLE |
724 CODA7_USE_ME_ENABLE | CODA7_USE_HOST_ME_ENABLE,
725 CODA7_REG_BIT_AXI_SRAM_USE);
726 }
727
186b250a
JM		 728 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
729}
730
731static int coda_job_ready(void *m2m_priv)
732{
733 struct coda_ctx *ctx = m2m_priv;
734
735 /*
736 * For both 'P' and 'key' frame cases 1 picture
737 * and 1 frame are needed.
738 */
739 if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
740 !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
741 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
742 "not ready: not enough video buffers.\n");
743 return 0;
744 }
745
746 /* For P frames a reference picture is needed too */
747 if ((ctx->gopcounter != (ctx->params.gop_size - 1)) &&
748 !ctx->reference) {
749 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
750 "not ready: reference picture not available.\n");
751 return 0;
752 }
753
754 if (coda_isbusy(ctx->dev)) {
755 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
756 "not ready: coda is still busy.\n");
757 return 0;
758 }
759
760 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
761 "job ready\n");
762 return 1;
763}
764
765static void coda_job_abort(void *priv)
766{
767 struct coda_ctx *ctx = priv;
768 struct coda_dev *dev = ctx->dev;
769
770 ctx->aborting = 1;
771
772 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
773 "Aborting task\n");
774
775 v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
776}
777
778static void coda_lock(void *m2m_priv)
779{
780 struct coda_ctx *ctx = m2m_priv;
781 struct coda_dev *pcdev = ctx->dev;
782 mutex_lock(&pcdev->dev_mutex);
783}
784
785static void coda_unlock(void *m2m_priv)
786{
787 struct coda_ctx *ctx = m2m_priv;
788 struct coda_dev *pcdev = ctx->dev;
789 mutex_unlock(&pcdev->dev_mutex);
790}
791
792static struct v4l2_m2m_ops coda_m2m_ops = {
793 .device_run = coda_device_run,
794 .job_ready = coda_job_ready,
795 .job_abort = coda_job_abort,
796 .lock = coda_lock,
797 .unlock = coda_unlock,
798};
799
800static void set_default_params(struct coda_ctx *ctx)
801{
802 struct coda_dev *dev = ctx->dev;
803
804 ctx->params.codec_mode = CODA_MODE_INVALID;
805 ctx->colorspace = V4L2_COLORSPACE_REC709;
806 ctx->params.framerate = 30;
807 ctx->reference = NULL;
808 ctx->aborting = 0;
809
810 /* Default formats for output and input queues */
811 ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
812 ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
813 ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
814 ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
815 ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
816 ctx->q_data[V4L2_M2M_DST].width = MAX_W;
817 ctx->q_data[V4L2_M2M_DST].height = MAX_H;
818 ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
819}
820
821/*
822 * Queue operations
823 */
824static int coda_queue_setup(struct vb2_queue *vq,
825 const struct v4l2_format *fmt,
826 unsigned int *nbuffers, unsigned int *nplanes,
827 unsigned int sizes[], void *alloc_ctxs[])
828{
829 struct coda_ctx *ctx = vb2_get_drv_priv(vq);
830 unsigned int size;
831
832 if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
833 *nbuffers = CODA_OUTPUT_BUFS;
834 if (fmt)
835 size = fmt->fmt.pix.width *
836 fmt->fmt.pix.height * 3 / 2;
837 else
838 size = MAX_W *
839 MAX_H * 3 / 2;
840 } else {
841 *nbuffers = CODA_CAPTURE_BUFS;
842 size = CODA_MAX_FRAME_SIZE;
843 }
844
845 *nplanes = 1;
846 sizes[0] = size;
847
848 alloc_ctxs[0] = ctx->dev->alloc_ctx;
849
850 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
851 "get %d buffer(s) of size %d each.\n", *nbuffers, size);
852
853 return 0;
854}
855
856static int coda_buf_prepare(struct vb2_buffer *vb)
857{
858 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
859 struct coda_q_data *q_data;
860
861 q_data = get_q_data(ctx, vb->vb2_queue->type);
862
863 if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
864 v4l2_warn(&ctx->dev->v4l2_dev,
865 "%s data will not fit into plane (%lu < %lu)\n",
866 __func__, vb2_plane_size(vb, 0),
867 (long)q_data->sizeimage);
868 return -EINVAL;
869 }
870
871 vb2_set_plane_payload(vb, 0, q_data->sizeimage);
872
873 return 0;
874}
875
876static void coda_buf_queue(struct vb2_buffer *vb)
877{
878 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
879 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
880}
881
882static void coda_wait_prepare(struct vb2_queue *q)
883{
884 struct coda_ctx *ctx = vb2_get_drv_priv(q);
885 coda_unlock(ctx);
886}
887
888static void coda_wait_finish(struct vb2_queue *q)
889{
890 struct coda_ctx *ctx = vb2_get_drv_priv(q);
891 coda_lock(ctx);
892}
893
894static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
895{
896 struct coda_ctx *ctx = vb2_get_drv_priv(q);
897 struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
898 u32 bitstream_buf, bitstream_size;
899 struct coda_dev *dev = ctx->dev;
900 struct coda_q_data *q_data_src, *q_data_dst;
901 u32 dst_fourcc;
902 struct vb2_buffer *buf;
903 struct vb2_queue *src_vq;
904 u32 value;
905 int i = 0;
906
907 if (count < 1)
908 return -EINVAL;
909
910 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
911 ctx->rawstreamon = 1;
912 else
913 ctx->compstreamon = 1;
914
915 /* Don't start the coda unless both queues are on */
916 if (!(ctx->rawstreamon & ctx->compstreamon))
917 return 0;
918
919 ctx->gopcounter = ctx->params.gop_size - 1;
920
921 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
922 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
923 bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
924 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
925 bitstream_size = q_data_dst->sizeimage;
926 dst_fourcc = q_data_dst->fmt->fourcc;
927
928 /* Find out whether coda must encode or decode */
929 if (q_data_src->fmt->type == CODA_FMT_RAW &&
930 q_data_dst->fmt->type == CODA_FMT_ENC) {
931 ctx->inst_type = CODA_INST_ENCODER;
932 } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
933 q_data_dst->fmt->type == CODA_FMT_RAW) {
934 ctx->inst_type = CODA_INST_DECODER;
935 v4l2_err(v4l2_dev, "decoding not supported.\n");
936 return -EINVAL;
937 } else {
938 v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
939 return -EINVAL;
940 }
941
942 if (!coda_is_initialized(dev)) {
943 v4l2_err(v4l2_dev, "coda is not initialized.\n");
944 return -EFAULT;
945 }
946 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
947 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
948 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
949 switch (dev->devtype->product) {
950 case CODA_DX6:
951 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
952 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
953 break;
954 default:
955 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
956 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
957 }
958
1043667b
PZ		 959 if (dev->devtype->product == CODA_DX6) {
960 /* Configure the coda */
961 coda_write(dev, dev->iram_paddr, CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
962 }
186b250a
JM		 963
964 /* Could set rotation here if needed */
965 switch (dev->devtype->product) {
966 case CODA_DX6:
967 value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
968 break;
969 default:
970 value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
971 }
972 value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
973 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
974 coda_write(dev, ctx->params.framerate,
975 CODA_CMD_ENC_SEQ_SRC_F_RATE);
976
977 switch (dst_fourcc) {
978 case V4L2_PIX_FMT_MPEG4:
979 if (dev->devtype->product == CODA_DX6)
980 ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
981 else
982 ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
983
984 coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
985 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
986 break;
987 case V4L2_PIX_FMT_H264:
988 if (dev->devtype->product == CODA_DX6)
989 ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
990 else
991 ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
992
993 coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
994 coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
995 break;
996 default:
997 v4l2_err(v4l2_dev,
998 "dst format (0x%08x) invalid.\n", dst_fourcc);
999 return -EINVAL;
1000 }
1001
1002 value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
1003 value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
1004 if (ctx->params.slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB)
1005 value |= 1 & CODA_SLICING_MODE_MASK;
1006 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
1007 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
1008 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
1009
1010 if (ctx->params.bitrate) {
1011 /* Rate control enabled */
1012 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
1013 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
1014 } else {
1015 value = 0;
1016 }
1017 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
1018
1019 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
1020 coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
1021
1022 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
1023 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
1024
1025 /* set default gamma */
1026 value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
1027 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
1028
1029 value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
1030 value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
1031 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
1032
1033 if (dst_fourcc == V4L2_PIX_FMT_H264) {
1034 value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
1035 value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
1036 value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
1043667b
PZ		 1037 if (dev->devtype->product == CODA_DX6) {
1038 coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
1039 } else {
1040 coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
1041 coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
1042 }
186b250a
JM		 1043 }
1044
1045 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1046 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1047 return -ETIMEDOUT;
1048 }
1049
1050 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
1051 return -EFAULT;
1052
1053 /*
1054 * Walk the src buffer list and let the codec know the
1055 * addresses of the pictures.
1056 */
1057 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1058 for (i = 0; i < src_vq->num_buffers; i++) {
1059 u32 *p;
1060
1061 buf = src_vq->bufs[i];
1062 p = ctx->parabuf.vaddr;
1063
1064 p[i * 3] = vb2_dma_contig_plane_dma_addr(buf, 0);
1065 p[i * 3 + 1] = p[i * 3] + q_data_src->width *
1066 q_data_src->height;
1067 p[i * 3 + 2] = p[i * 3 + 1] + q_data_src->width / 2 *
1068 q_data_src->height / 2;
1069 }
1070
1071 coda_write(dev, src_vq->num_buffers, CODA_CMD_SET_FRAME_BUF_NUM);
1043667b
PZ		 1072 coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
1073 if (dev->devtype->product != CODA_DX6) {
1074 coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
1075 coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
1076 coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
1077 coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
1078 coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
1079 coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
1080 }
186b250a
JM		 1081 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1082 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1083 return -ETIMEDOUT;
1084 }
1085
1086 /* Save stream headers */
1087 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
1088 switch (dst_fourcc) {
1089 case V4L2_PIX_FMT_H264:
1090 /*
1091 * Get SPS in the first frame and copy it to an
1092 * intermediate buffer.
1093 */
1094 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1095 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1096 coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
1097 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1098 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1099 return -ETIMEDOUT;
1100 }
1101 ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1102 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1103 memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
1104 ctx->vpu_header_size[0]);
1105
1106 /*
1107 * Get PPS in the first frame and copy it to an
1108 * intermediate buffer.
1109 */
1110 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1111 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1112 coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
1113 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1114 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1115 return -ETIMEDOUT;
1116 }
1117 ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1118 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1119 memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
1120 ctx->vpu_header_size[1]);
1121 ctx->vpu_header_size[2] = 0;
1122 break;
1123 case V4L2_PIX_FMT_MPEG4:
1124 /*
1125 * Get VOS in the first frame and copy it to an
1126 * intermediate buffer
1127 */
1128 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1129 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1130 coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
1131 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1132 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1133 return -ETIMEDOUT;
1134 }
1135 ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1136 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1137 memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
1138 ctx->vpu_header_size[0]);
1139
1140 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1141 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1142 coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
1143 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1144 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
1145 return -ETIMEDOUT;
1146 }
1147 ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1148 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1149 memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
1150 ctx->vpu_header_size[1]);
1151
1152 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1153 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1154 coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
1155 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1156 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
1157 return -ETIMEDOUT;
1158 }
1159 ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1160 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1161 memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
1162 ctx->vpu_header_size[2]);
1163 break;
1164 default:
1165 /* No more formats need to save headers at the moment */
1166 break;
1167 }
1168
1169 return 0;
1170}
1171
1172static int coda_stop_streaming(struct vb2_queue *q)
1173{
1174 struct coda_ctx *ctx = vb2_get_drv_priv(q);
1175
1176 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1177 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1178 "%s: output\n", __func__);
1179 ctx->rawstreamon = 0;
1180 } else {
1181 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1182 "%s: capture\n", __func__);
1183 ctx->compstreamon = 0;
1184 }
1185
1186 if (!ctx->rawstreamon && !ctx->compstreamon) {
1187 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1188 "%s: sent command 'SEQ_END' to coda\n", __func__);
1189 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1190 v4l2_err(&ctx->dev->v4l2_dev,
1191 "CODA_COMMAND_SEQ_END failed\n");
1192 return -ETIMEDOUT;
1193 }
1194 }
1195
1196 return 0;
1197}
1198
1199static struct vb2_ops coda_qops = {
1200 .queue_setup = coda_queue_setup,
1201 .buf_prepare = coda_buf_prepare,
1202 .buf_queue = coda_buf_queue,
1203 .wait_prepare = coda_wait_prepare,
1204 .wait_finish = coda_wait_finish,
1205 .start_streaming = coda_start_streaming,
1206 .stop_streaming = coda_stop_streaming,
1207};
1208
1209static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
1210{
1211 struct coda_ctx *ctx =
1212 container_of(ctrl->handler, struct coda_ctx, ctrls);
1213
1214 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1215 "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
1216
1217 switch (ctrl->id) {
1218 case V4L2_CID_MPEG_VIDEO_BITRATE:
1219 ctx->params.bitrate = ctrl->val / 1000;
1220 break;
1221 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
1222 ctx->params.gop_size = ctrl->val;
1223 break;
1224 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
1225 ctx->params.h264_intra_qp = ctrl->val;
1226 break;
1227 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
1228 ctx->params.h264_inter_qp = ctrl->val;
1229 break;
1230 case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
1231 ctx->params.mpeg4_intra_qp = ctrl->val;
1232 break;
1233 case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
1234 ctx->params.mpeg4_inter_qp = ctrl->val;
1235 break;
1236 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
1237 ctx->params.slice_mode = ctrl->val;
1238 break;
1239 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
1240 ctx->params.slice_max_mb = ctrl->val;
1241 break;
1242 case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
1243 break;
1244 default:
1245 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1246 "Invalid control, id=%d, val=%d\n",
1247 ctrl->id, ctrl->val);
1248 return -EINVAL;
1249 }
1250
1251 return 0;
1252}
1253
1254static struct v4l2_ctrl_ops coda_ctrl_ops = {
1255 .s_ctrl = coda_s_ctrl,
1256};
1257
1258static int coda_ctrls_setup(struct coda_ctx *ctx)
1259{
1260 v4l2_ctrl_handler_init(&ctx->ctrls, 9);
1261
1262 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1263 V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
1264 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1265 V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
1266 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1267 V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
1268 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1269 V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
1270 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1271 V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
1272 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1273 V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
1274 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1275 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
1276 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB, 0,
1277 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB);
1278 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1279 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
1280 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1281 V4L2_CID_MPEG_VIDEO_HEADER_MODE,
1282 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
1283 (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
1284 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
1285
1286 if (ctx->ctrls.error) {
1287 v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
1288 ctx->ctrls.error);
1289 return -EINVAL;
1290 }
1291
1292 return v4l2_ctrl_handler_setup(&ctx->ctrls);
1293}
1294
1295static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
1296 struct vb2_queue *dst_vq)
1297{
1298 struct coda_ctx *ctx = priv;
1299 int ret;
1300
186b250a
JM		 1301 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1302 src_vq->io_modes = VB2_MMAP;
1303 src_vq->drv_priv = ctx;
1304 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1305 src_vq->ops = &coda_qops;
1306 src_vq->mem_ops = &vb2_dma_contig_memops;
1307
1308 ret = vb2_queue_init(src_vq);
1309 if (ret)
1310 return ret;
1311
186b250a
JM		 1312 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1313 dst_vq->io_modes = VB2_MMAP;
1314 dst_vq->drv_priv = ctx;
1315 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1316 dst_vq->ops = &coda_qops;
1317 dst_vq->mem_ops = &vb2_dma_contig_memops;
1318
1319 return vb2_queue_init(dst_vq);
1320}
1321
1322static int coda_open(struct file *file)
1323{
1324 struct coda_dev *dev = video_drvdata(file);
1325 struct coda_ctx *ctx = NULL;
1326 int ret = 0;
1327
1328 if (dev->instances >= CODA_MAX_INSTANCES)
1329 return -EBUSY;
1330
1331 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1332 if (!ctx)
1333 return -ENOMEM;
1334
1335 v4l2_fh_init(&ctx->fh, video_devdata(file));
1336 file->private_data = &ctx->fh;
1337 v4l2_fh_add(&ctx->fh);
1338 ctx->dev = dev;
1339
1340 set_default_params(ctx);
1341 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
1342 &coda_queue_init);
1343 if (IS_ERR(ctx->m2m_ctx)) {
1344 int ret = PTR_ERR(ctx->m2m_ctx);
1345
1346 v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
1347 __func__, ret);
1348 goto err;
1349 }
1350 ret = coda_ctrls_setup(ctx);
1351 if (ret) {
1352 v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
1353 goto err;
1354 }
1355
1356 ctx->fh.ctrl_handler = &ctx->ctrls;
1357
1358 ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
1359 CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
1360 if (!ctx->parabuf.vaddr) {
1361 v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
1362 ret = -ENOMEM;
1363 goto err;
1364 }
1365
1366 coda_lock(ctx);
1367 ctx->idx = dev->instances++;
1368 coda_unlock(ctx);
1369
1370 clk_prepare_enable(dev->clk_per);
1371 clk_prepare_enable(dev->clk_ahb);
1372
1373 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
1374 ctx->idx, ctx);
1375
1376 return 0;
1377
1378err:
1379 v4l2_fh_del(&ctx->fh);
1380 v4l2_fh_exit(&ctx->fh);
1381 kfree(ctx);
1382 return ret;
1383}
1384
1385static int coda_release(struct file *file)
1386{
1387 struct coda_dev *dev = video_drvdata(file);
1388 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1389
1390 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
1391 ctx);
1392
1393 coda_lock(ctx);
1394 dev->instances--;
1395 coda_unlock(ctx);
1396
1397 dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
1398 ctx->parabuf.vaddr, ctx->parabuf.paddr);
1399 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1400 v4l2_ctrl_handler_free(&ctx->ctrls);
1401 clk_disable_unprepare(dev->clk_per);
1402 clk_disable_unprepare(dev->clk_ahb);
1403 v4l2_fh_del(&ctx->fh);
1404 v4l2_fh_exit(&ctx->fh);
1405 kfree(ctx);
1406
1407 return 0;
1408}
1409
1410static unsigned int coda_poll(struct file *file,
1411 struct poll_table_struct *wait)
1412{
1413 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1414 int ret;
1415
1416 coda_lock(ctx);
1417 ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1418 coda_unlock(ctx);
1419 return ret;
1420}
1421
1422static int coda_mmap(struct file *file, struct vm_area_struct *vma)
1423{
1424 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1425
1426 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1427}
1428
1429static const struct v4l2_file_operations coda_fops = {
1430 .owner = THIS_MODULE,
1431 .open = coda_open,
1432 .release = coda_release,
1433 .poll = coda_poll,
1434 .unlocked_ioctl = video_ioctl2,
1435 .mmap = coda_mmap,
1436};
1437
1438static irqreturn_t coda_irq_handler(int irq, void *data)
1439{
1440 struct vb2_buffer *src_buf, *dst_buf, *tmp_buf;
1441 struct coda_dev *dev = data;
1442 u32 wr_ptr, start_ptr;
1443 struct coda_ctx *ctx;
1444
1445 /* read status register to attend the IRQ */
1446 coda_read(dev, CODA_REG_BIT_INT_STATUS);
1447 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
1448 CODA_REG_BIT_INT_CLEAR);
1449
1450 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1451 if (ctx == NULL) {
1452 v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
1453 return IRQ_HANDLED;
1454 }
1455
1456 if (ctx->aborting) {
1457 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1458 "task has been aborted\n");
1459 return IRQ_HANDLED;
1460 }
1461
1462 if (coda_isbusy(ctx->dev)) {
1463 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1464 "coda is still busy!!!!\n");
1465 return IRQ_NONE;
1466 }
1467
1468 src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
1469 dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
1470
1471 /* Get results from the coda */
1472 coda_read(dev, CODA_RET_ENC_PIC_TYPE);
1473 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1474 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
1475 /* Calculate bytesused field */
1476 if (dst_buf->v4l2_buf.sequence == 0) {
1477 dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
1478 ctx->vpu_header_size[0] +
1479 ctx->vpu_header_size[1] +
1480 ctx->vpu_header_size[2];
1481 } else {
1482 dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
1483 }
1484
1485 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1486 wr_ptr - start_ptr);
1487
1488 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1489 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1490
1491 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1492 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1493 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1494 } else {
1495 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1496 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1497 }
1498
1499 /* Free previous reference picture if available */
1500 if (ctx->reference) {
1501 v4l2_m2m_buf_done(ctx->reference, VB2_BUF_STATE_DONE);
1502 ctx->reference = NULL;
1503 }
1504
1505 /*
1506 * For the last frame of the gop we don't need to save
1507 * a reference picture.
1508 */
1509 v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
1510 tmp_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1511 if (ctx->gopcounter == 0)
1512 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1513 else
1514 ctx->reference = tmp_buf;
1515
1516 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1517
1518 ctx->gopcounter--;
1519 if (ctx->gopcounter < 0)
1520 ctx->gopcounter = ctx->params.gop_size - 1;
1521
1522 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1523 "job finished: encoding frame (%d) (%s)\n",
1524 dst_buf->v4l2_buf.sequence,
1525 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1526 "KEYFRAME" : "PFRAME");
1527
1528 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
1529
1530 return IRQ_HANDLED;
1531}
1532
1533static u32 coda_supported_firmwares[] = {
1534 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
df1e74cc 1535 CODA_FIRMWARE_VERNUM(CODA_7541, 13, 4, 29),
186b250a
JM		 1536};
1537
1538static bool coda_firmware_supported(u32 vernum)
1539{
1540 int i;
1541
1542 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
1543 if (vernum == coda_supported_firmwares[i])
1544 return true;
1545 return false;
1546}
1547
1548static char *coda_product_name(int product)
1549{
1550 static char buf[9];
1551
1552 switch (product) {
1553 case CODA_DX6:
1554 return "CodaDx6";
df1e74cc
PZ		 1555 case CODA_7541:
1556 return "CODA7541";
186b250a
JM		 1557 default:
1558 snprintf(buf, sizeof(buf), "(0x%04x)", product);
1559 return buf;
1560 }
1561}
1562
87048bb4 1563static int coda_hw_init(struct coda_dev *dev)
186b250a
JM		 1564{
1565 u16 product, major, minor, release;
1566 u32 data;
1567 u16 *p;
1568 int i;
1569
1570 clk_prepare_enable(dev->clk_per);
1571 clk_prepare_enable(dev->clk_ahb);
1572
186b250a
JM		 1573 /*
1574 * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
87048bb4
PZ		 1575 * The 16-bit chars in the code buffer are in memory access
1576 * order, re-sort them to CODA order for register download.
186b250a
JM		 1577 * Data in this SRAM survives a reboot.
1578 */
87048bb4
PZ		 1579 p = (u16 *)dev->codebuf.vaddr;
1580 if (dev->devtype->product == CODA_DX6) {
1581 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
1582 data = CODA_DOWN_ADDRESS_SET(i) |
1583 CODA_DOWN_DATA_SET(p[i ^ 1]);
1584 coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
1585 }
1586 } else {
1587 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
1588 data = CODA_DOWN_ADDRESS_SET(i) |
1589 CODA_DOWN_DATA_SET(p[round_down(i, 4) +
1590 3 - (i % 4)]);
1591 coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
1592 }
186b250a 1593 }
186b250a
JM		 1594
1595 /* Tell the BIT where to find everything it needs */
1596 coda_write(dev, dev->workbuf.paddr,
1597 CODA_REG_BIT_WORK_BUF_ADDR);
1598 coda_write(dev, dev->codebuf.paddr,
1599 CODA_REG_BIT_CODE_BUF_ADDR);
1600 coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
1601
1602 /* Set default values */
1603 switch (dev->devtype->product) {
1604 case CODA_DX6:
1605 coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
1606 break;
1607 default:
1608 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
1609 }
1610 coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
1043667b
PZ		 1611
1612 if (dev->devtype->product != CODA_DX6)
1613 coda_write(dev, 0, CODA7_REG_BIT_AXI_SRAM_USE);
1614
186b250a
JM		 1615 coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
1616 CODA_REG_BIT_INT_ENABLE);
1617
1618 /* Reset VPU and start processor */
1619 data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
1620 data |= CODA_REG_RESET_ENABLE;
1621 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
1622 udelay(10);
1623 data &= ~CODA_REG_RESET_ENABLE;
1624 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
1625 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
1626
1627 /* Load firmware */
1628 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
1629 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
1630 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
1631 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
1632 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
1633 if (coda_wait_timeout(dev)) {
1634 clk_disable_unprepare(dev->clk_per);
1635 clk_disable_unprepare(dev->clk_ahb);
1636 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
1637 return -EIO;
1638 }
1639
1640 /* Check we are compatible with the loaded firmware */
1641 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
1642 product = CODA_FIRMWARE_PRODUCT(data);
1643 major = CODA_FIRMWARE_MAJOR(data);
1644 minor = CODA_FIRMWARE_MINOR(data);
1645 release = CODA_FIRMWARE_RELEASE(data);
1646
1647 clk_disable_unprepare(dev->clk_per);
1648 clk_disable_unprepare(dev->clk_ahb);
1649
1650 if (product != dev->devtype->product) {
1651 v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
1652 " Version: %u.%u.%u\n",
1653 coda_product_name(dev->devtype->product),
1654 coda_product_name(product), major, minor, release);
1655 return -EINVAL;
1656 }
1657
1658 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
1659 coda_product_name(product));
1660
1661 if (coda_firmware_supported(data)) {
1662 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
1663 major, minor, release);
1664 } else {
1665 v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
1666 "%u.%u.%u\n", major, minor, release);
1667 }
1668
1669 return 0;
1670}
1671
1672static void coda_fw_callback(const struct firmware *fw, void *context)
1673{
1674 struct coda_dev *dev = context;
1675 struct platform_device *pdev = dev->plat_dev;
1676 int ret;
1677
1678 if (!fw) {
1679 v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
1680 return;
1681 }
1682
1683 /* allocate auxiliary per-device code buffer for the BIT processor */
1684 dev->codebuf.size = fw->size;
1685 dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
1686 &dev->codebuf.paddr,
1687 GFP_KERNEL);
1688 if (!dev->codebuf.vaddr) {
1689 dev_err(&pdev->dev, "failed to allocate code buffer\n");
1690 return;
1691 }
1692
87048bb4
PZ		 1693 /* Copy the whole firmware image to the code buffer */
1694 memcpy(dev->codebuf.vaddr, fw->data, fw->size);
1695 release_firmware(fw);
1696
1697 ret = coda_hw_init(dev);
186b250a
JM		 1698 if (ret) {
1699 v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
1700 return;
1701 }
1702
1703 dev->vfd.fops = &coda_fops,
1704 dev->vfd.ioctl_ops = &coda_ioctl_ops;
1705 dev->vfd.release = video_device_release_empty,
1706 dev->vfd.lock = &dev->dev_mutex;
1707 dev->vfd.v4l2_dev = &dev->v4l2_dev;
954f340f 1708 dev->vfd.vfl_dir = VFL_DIR_M2M;
186b250a
JM		 1709 snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
1710 video_set_drvdata(&dev->vfd, dev);
1711
1712 dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1713 if (IS_ERR(dev->alloc_ctx)) {
1714 v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
1715 return;
1716 }
1717
1718 dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
1719 if (IS_ERR(dev->m2m_dev)) {
1720 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
1721 goto rel_ctx;
1722 }
1723
1724 ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
1725 if (ret) {
1726 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1727 goto rel_m2m;
1728 }
1729 v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
1730 dev->vfd.num);
1731
1732 return;
1733
1734rel_m2m:
1735 v4l2_m2m_release(dev->m2m_dev);
1736rel_ctx:
1737 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
1738}
1739
1740static int coda_firmware_request(struct coda_dev *dev)
1741{
1742 char *fw = dev->devtype->firmware;
1743
1744 dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
1745 coda_product_name(dev->devtype->product));
1746
1747 return request_firmware_nowait(THIS_MODULE, true,
1748 fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
1749}
1750
1751enum coda_platform {
1752 CODA_IMX27,
df1e74cc 1753 CODA_IMX53,
186b250a
JM		 1754};
1755
c06d8752 1756static const struct coda_devtype coda_devdata[] = {
186b250a
JM		 1757 [CODA_IMX27] = {
1758 .firmware = "v4l-codadx6-imx27.bin",
1759 .product = CODA_DX6,
1760 .formats = codadx6_formats,
1761 .num_formats = ARRAY_SIZE(codadx6_formats),
1762 },
df1e74cc
PZ		 1763 [CODA_IMX53] = {
1764 .firmware = "v4l-coda7541-imx53.bin",
1765 .product = CODA_7541,
1766 .formats = coda7_formats,
1767 .num_formats = ARRAY_SIZE(coda7_formats),
1768 },
186b250a
JM		 1769};
1770
1771static struct platform_device_id coda_platform_ids[] = {
1772 { .name = "coda-imx27", .driver_data = CODA_IMX27 },
df1e74cc 1773 { .name = "coda-imx53", .driver_data = CODA_7541 },
186b250a
JM		 1774 { /* sentinel */ }
1775};
1776MODULE_DEVICE_TABLE(platform, coda_platform_ids);
1777
1778#ifdef CONFIG_OF
1779static const struct of_device_id coda_dt_ids[] = {
1780 { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
df1e74cc 1781 { .compatible = "fsl,imx53-vpu", .data = &coda_devdata[CODA_IMX53] },
186b250a
JM		 1782 { /* sentinel */ }
1783};
1784MODULE_DEVICE_TABLE(of, coda_dt_ids);
1785#endif
1786
1787static int __devinit coda_probe(struct platform_device *pdev)
1788{
1789 const struct of_device_id *of_id =
1790 of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
1791 const struct platform_device_id *pdev_id;
1792 struct coda_dev *dev;
1793 struct resource *res;
1794 int ret, irq;
1795
1796 dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
1797 if (!dev) {
1798 dev_err(&pdev->dev, "Not enough memory for %s\n",
1799 CODA_NAME);
1800 return -ENOMEM;
1801 }
1802
1803 spin_lock_init(&dev->irqlock);
1804
1805 dev->plat_dev = pdev;
1806 dev->clk_per = devm_clk_get(&pdev->dev, "per");
1807 if (IS_ERR(dev->clk_per)) {
1808 dev_err(&pdev->dev, "Could not get per clock\n");
1809 return PTR_ERR(dev->clk_per);
1810 }
1811
1812 dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1813 if (IS_ERR(dev->clk_ahb)) {
1814 dev_err(&pdev->dev, "Could not get ahb clock\n");
1815 return PTR_ERR(dev->clk_ahb);
1816 }
1817
1818 /* Get memory for physical registers */
1819 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1820 if (res == NULL) {
1821 dev_err(&pdev->dev, "failed to get memory region resource\n");
1822 return -ENOENT;
1823 }
1824
1825 if (devm_request_mem_region(&pdev->dev, res->start,
1826 resource_size(res), CODA_NAME) == NULL) {
1827 dev_err(&pdev->dev, "failed to request memory region\n");
1828 return -ENOENT;
1829 }
1830 dev->regs_base = devm_ioremap(&pdev->dev, res->start,
1831 resource_size(res));
1832 if (!dev->regs_base) {
1833 dev_err(&pdev->dev, "failed to ioremap address region\n");
1834 return -ENOENT;
1835 }
1836
1837 /* IRQ */
1838 irq = platform_get_irq(pdev, 0);
1839 if (irq < 0) {
1840 dev_err(&pdev->dev, "failed to get irq resource\n");
1841 return -ENOENT;
1842 }
1843
1844 if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
1845 0, CODA_NAME, dev) < 0) {
1846 dev_err(&pdev->dev, "failed to request irq\n");
1847 return -ENOENT;
1848 }
1849
1850 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1851 if (ret)
1852 return ret;
1853
1854 mutex_init(&dev->dev_mutex);
1855
1856 pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
1857
1858 if (of_id) {
1859 dev->devtype = of_id->data;
1860 } else if (pdev_id) {
1861 dev->devtype = &coda_devdata[pdev_id->driver_data];
1862 } else {
1863 v4l2_device_unregister(&dev->v4l2_dev);
1864 return -EINVAL;
1865 }
1866
1867 /* allocate auxiliary per-device buffers for the BIT processor */
1868 switch (dev->devtype->product) {
1869 case CODA_DX6:
1870 dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
1871 break;
1872 default:
1873 dev->workbuf.size = CODA7_WORK_BUF_SIZE;
1874 }
1875 dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
1876 &dev->workbuf.paddr,
1877 GFP_KERNEL);
1878 if (!dev->workbuf.vaddr) {
1879 dev_err(&pdev->dev, "failed to allocate work buffer\n");
1880 v4l2_device_unregister(&dev->v4l2_dev);
1881 return -ENOMEM;
1882 }
1883
1043667b
PZ		 1884 if (dev->devtype->product == CODA_DX6) {
1885 dev->iram_paddr = 0xffff4c00;
1886 } else {
1887 void __iomem *iram_vaddr;
1888
1889 iram_vaddr = iram_alloc(CODA7_IRAM_SIZE,
1890 &dev->iram_paddr);
1891 if (!iram_vaddr) {
1892 dev_err(&pdev->dev, "unable to alloc iram\n");
1893 return -ENOMEM;
1894 }
1895 }
1896
186b250a
JM		 1897 platform_set_drvdata(pdev, dev);
1898
1899 return coda_firmware_request(dev);
1900}
1901
1902static int coda_remove(struct platform_device *pdev)
1903{
1904 struct coda_dev *dev = platform_get_drvdata(pdev);
1905
1906 video_unregister_device(&dev->vfd);
1907 if (dev->m2m_dev)
1908 v4l2_m2m_release(dev->m2m_dev);
1909 if (dev->alloc_ctx)
1910 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
1911 v4l2_device_unregister(&dev->v4l2_dev);
1043667b
PZ		 1912 if (dev->iram_paddr)
1913 iram_free(dev->iram_paddr, CODA7_IRAM_SIZE);
186b250a
JM		 1914 if (dev->codebuf.vaddr)
1915 dma_free_coherent(&pdev->dev, dev->codebuf.size,
1916 &dev->codebuf.vaddr, dev->codebuf.paddr);
1917 if (dev->workbuf.vaddr)
1918 dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
1919 dev->workbuf.paddr);
1920 return 0;
1921}
1922
1923static struct platform_driver coda_driver = {
1924 .probe = coda_probe,
1925 .remove = __devexit_p(coda_remove),
1926 .driver = {
1927 .name = CODA_NAME,
1928 .owner = THIS_MODULE,
1929 .of_match_table = of_match_ptr(coda_dt_ids),
1930 },
1931 .id_table = coda_platform_ids,
1932};
1933
1934module_platform_driver(coda_driver);
1935
1936MODULE_LICENSE("GPL");
1937MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1938MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");
Linux kernel - Deliverables
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