[deliverable/linux.git] / drivers / media / platform / davinci / vpif.c

/*
 * vpif - Video Port Interface driver
 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
 * that receiveing video byte stream and two channels(2, 3) for video output.
 * The hardware supports SDTV, HDTV formats, raw data capture.
 * Currently, the driver supports NTSC and PAL standards.
 *
 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/err.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/spinlock.h>
#include <linux/v4l2-dv-timings.h>

#include "vpif.h"

MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
MODULE_LICENSE("GPL");

#define VPIF_CH0_MAX_MODES	22
#define VPIF_CH1_MAX_MODES	2
#define VPIF_CH2_MAX_MODES	15
#define VPIF_CH3_MAX_MODES	2

spinlock_t vpif_lock;
EXPORT_SYMBOL_GPL(vpif_lock);

void __iomem *vpif_base;
EXPORT_SYMBOL_GPL(vpif_base);

/**
 * vpif_ch_params: video standard configuration parameters for vpif
 * The table must include all presets from supported subdevices.
 */
const struct vpif_channel_config_params vpif_ch_params[] = {
	/* HDTV formats */
	{
		.name = "480p59_94",
		.width = 720,
		.height = 480,
		.frm_fmt = 1,
		.ycmux_mode = 0,
		.eav2sav = 138-8,
		.sav2eav = 720,
		.l1 = 1,
		.l3 = 43,
		.l5 = 523,
		.vsize = 525,
		.capture_format = 0,
		.vbi_supported = 0,
		.hd_sd = 1,
		.dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
	},
	{
		.name = "576p50",
		.width = 720,
		.height = 576,
		.frm_fmt = 1,
		.ycmux_mode = 0,
		.eav2sav = 144-8,
		.sav2eav = 720,
		.l1 = 1,
		.l3 = 45,
		.l5 = 621,
		.vsize = 625,
		.capture_format = 0,
		.vbi_supported = 0,
		.hd_sd = 1,
		.dv_timings = V4L2_DV_BT_CEA_720X576P50,
	},
	{
		.name = "720p50",
		.width = 1280,
		.height = 720,
		.frm_fmt = 1,
		.ycmux_mode = 0,
		.eav2sav = 700-8,
		.sav2eav = 1280,
		.l1 = 1,
		.l3 = 26,
		.l5 = 746,
		.vsize = 750,
		.capture_format = 0,
		.vbi_supported = 0,
		.hd_sd = 1,
		.dv_timings = V4L2_DV_BT_CEA_1280X720P50,
	},
	{
		.name = "720p60",
		.width = 1280,
		.height = 720,
		.frm_fmt = 1,
		.ycmux_mode = 0,
		.eav2sav = 370 - 8,
		.sav2eav = 1280,
		.l1 = 1,
		.l3 = 26,
		.l5 = 746,
		.vsize = 750,
		.capture_format = 0,
		.vbi_supported = 0,
		.hd_sd = 1,
		.dv_timings = V4L2_DV_BT_CEA_1280X720P60,
	},
	{
		.name = "1080I50",
		.width = 1920,
		.height = 1080,
		.frm_fmt = 0,
		.ycmux_mode = 0,
		.eav2sav = 720 - 8,
		.sav2eav = 1920,
		.l1 = 1,
		.l3 = 21,
		.l5 = 561,
		.l7 = 563,
		.l9 = 584,
		.l11 = 1124,
		.vsize = 1125,
		.capture_format = 0,
		.vbi_supported = 0,
		.hd_sd = 1,
		.dv_timings = V4L2_DV_BT_CEA_1920X1080I50,
	},
	{
		.name = "1080I60",
		.width = 1920,
		.height = 1080,
		.frm_fmt = 0,
		.ycmux_mode = 0,
		.eav2sav = 280 - 8,
		.sav2eav = 1920,
		.l1 = 1,
		.l3 = 21,
		.l5 = 561,
		.l7 = 563,
		.l9 = 584,
		.l11 = 1124,
		.vsize = 1125,
		.capture_format = 0,
		.vbi_supported = 0,
		.hd_sd = 1,
		.dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
	},
	{
		.name = "1080p60",
		.width = 1920,
		.height = 1080,
		.frm_fmt = 1,
		.ycmux_mode = 0,
		.eav2sav = 280 - 8,
		.sav2eav = 1920,
		.l1 = 1,
		.l3 = 42,
		.l5 = 1122,
		.vsize = 1125,
		.capture_format = 0,
		.vbi_supported = 0,
		.hd_sd = 1,
		.dv_timings = V4L2_DV_BT_CEA_1920X1080P60,
	},

	/* SDTV formats */
	{
		.name = "NTSC_M",
		.width = 720,
		.height = 480,
		.frm_fmt = 0,
		.ycmux_mode = 1,
		.eav2sav = 268,
		.sav2eav = 1440,
		.l1 = 1,
		.l3 = 23,
		.l5 = 263,
		.l7 = 266,
		.l9 = 286,
		.l11 = 525,
		.vsize = 525,
		.capture_format = 0,
		.vbi_supported = 1,
		.hd_sd = 0,
		.stdid = V4L2_STD_525_60,
	},
	{
		.name = "PAL_BDGHIK",
		.width = 720,
		.height = 576,
		.frm_fmt = 0,
		.ycmux_mode = 1,
		.eav2sav = 280,
		.sav2eav = 1440,
		.l1 = 1,
		.l3 = 23,
		.l5 = 311,
		.l7 = 313,
		.l9 = 336,
		.l11 = 624,
		.vsize = 625,
		.capture_format = 0,
		.vbi_supported = 1,
		.hd_sd = 0,
		.stdid = V4L2_STD_625_50,
	},
};
EXPORT_SYMBOL_GPL(vpif_ch_params);

const unsigned int vpif_ch_params_count = ARRAY_SIZE(vpif_ch_params);
EXPORT_SYMBOL_GPL(vpif_ch_params_count);

static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
{
	if (val)
		vpif_set_bit(reg, bit);
	else
		vpif_clr_bit(reg, bit);
}

/* This structure is used to keep track of VPIF size register's offsets */
struct vpif_registers {
	u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
	u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
	u32 vanc1_size, width_mask, len_mask;
	u8 max_modes;
};

static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
	/* Channel0 */
	{
		VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
		VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
		VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
		VPIF_CH0_MAX_MODES,
	},
	/* Channel1 */
	{
		VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
		VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
		VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
		VPIF_CH1_MAX_MODES,
	},
	/* Channel2 */
	{
		VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
		VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
		VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
		VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
		VPIF_CH2_MAX_MODES
	},
	/* Channel3 */
	{
		VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
		VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
		VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
		VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
		VPIF_CH3_MAX_MODES
	},
};

/* vpif_set_mode_info:
 * This function is used to set horizontal and vertical config parameters
 * As per the standard in the channel, configure the values of L1, L3,
 * L5, L7  L9, L11 in VPIF Register , also write width and height
 */
static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
				u8 channel_id, u8 config_channel_id)
{
	u32 value;

	value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
	value <<= VPIF_CH_LEN_SHIFT;
	value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
	regw(value, vpifregs[channel_id].h_cfg);

	value = (config->l1 & vpifregs[config_channel_id].len_mask);
	value <<= VPIF_CH_LEN_SHIFT;
	value |= (config->l3 & vpifregs[config_channel_id].len_mask);
	regw(value, vpifregs[channel_id].v_cfg_00);

	value = (config->l5 & vpifregs[config_channel_id].len_mask);
	value <<= VPIF_CH_LEN_SHIFT;
	value |= (config->l7 & vpifregs[config_channel_id].len_mask);
	regw(value, vpifregs[channel_id].v_cfg_01);

	value = (config->l9 & vpifregs[config_channel_id].len_mask);
	value <<= VPIF_CH_LEN_SHIFT;
	value |= (config->l11 & vpifregs[config_channel_id].len_mask);
	regw(value, vpifregs[channel_id].v_cfg_02);

	value = (config->vsize & vpifregs[config_channel_id].len_mask);
	regw(value, vpifregs[channel_id].v_cfg);
}

/* config_vpif_params
 * Function to set the parameters of a channel
 * Mainly modifies the channel ciontrol register
 * It sets frame format, yc mux mode
 */
static void config_vpif_params(struct vpif_params *vpifparams,
				u8 channel_id, u8 found)
{
	const struct vpif_channel_config_params *config = &vpifparams->std_info;
	u32 value, ch_nip, reg;
	u8 start, end;
	int i;

	start = channel_id;
	end = channel_id + found;

	for (i = start; i < end; i++) {
		reg = vpifregs[i].ch_ctrl;
		if (channel_id < 2)
			ch_nip = VPIF_CAPTURE_CH_NIP;
		else
			ch_nip = VPIF_DISPLAY_CH_NIP;

		vpif_wr_bit(reg, ch_nip, config->frm_fmt);
		vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
		vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
					vpifparams->video_params.storage_mode);

		/* Set raster scanning SDR Format */
		vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
		vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);

		if (channel_id > 1)	/* Set the Pixel enable bit */
			vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
		else if (config->capture_format) {
			/* Set the polarity of various pins */
			vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
					vpifparams->iface.fid_pol);
			vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
					vpifparams->iface.vd_pol);
			vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
					vpifparams->iface.hd_pol);

			value = regr(reg);
			/* Set data width */
			value &= ~(0x3u <<
					VPIF_CH_DATA_WIDTH_BIT);
			value |= ((vpifparams->params.data_sz) <<
						     VPIF_CH_DATA_WIDTH_BIT);
			regw(value, reg);
		}

		/* Write the pitch in the driver */
		regw((vpifparams->video_params.hpitch),
						vpifregs[i].line_offset);
	}
}

/* vpif_set_video_params
 * This function is used to set video parameters in VPIF register
 */
int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
{
	const struct vpif_channel_config_params *config = &vpifparams->std_info;
	int found = 1;

	vpif_set_mode_info(config, channel_id, channel_id);
	if (!config->ycmux_mode) {
		/* YC are on separate channels (HDTV formats) */
		vpif_set_mode_info(config, channel_id + 1, channel_id);
		found = 2;
	}

	config_vpif_params(vpifparams, channel_id, found);

	regw(0x80, VPIF_REQ_SIZE);
	regw(0x01, VPIF_EMULATION_CTRL);

	return found;
}
EXPORT_SYMBOL(vpif_set_video_params);

void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
				u8 channel_id)
{
	u32 value;

	value = 0x3F8 & (vbiparams->hstart0);
	value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
	regw(value, vpifregs[channel_id].vanc0_strt);

	value = 0x3F8 & (vbiparams->hstart1);
	value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
	regw(value, vpifregs[channel_id].vanc1_strt);

	value = 0x3F8 & (vbiparams->hsize0);
	value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
	regw(value, vpifregs[channel_id].vanc0_size);

	value = 0x3F8 & (vbiparams->hsize1);
	value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
	regw(value, vpifregs[channel_id].vanc1_size);

}
EXPORT_SYMBOL(vpif_set_vbi_display_params);

int vpif_channel_getfid(u8 channel_id)
{
	return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
					>> VPIF_CH_FID_SHIFT;
}
EXPORT_SYMBOL(vpif_channel_getfid);

static int vpif_probe(struct platform_device *pdev)
{
	static struct resource	*res;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	vpif_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(vpif_base))
		return PTR_ERR(vpif_base);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get(&pdev->dev);

	spin_lock_init(&vpif_lock);
	dev_info(&pdev->dev, "vpif probe success\n");
	return 0;
}

static int vpif_remove(struct platform_device *pdev)
{
	pm_runtime_disable(&pdev->dev);
	return 0;
}

#ifdef CONFIG_PM
static int vpif_suspend(struct device *dev)
{
	pm_runtime_put(dev);
	return 0;
}

static int vpif_resume(struct device *dev)
{
	pm_runtime_get(dev);
	return 0;
}

static const struct dev_pm_ops vpif_pm = {
	.suspend        = vpif_suspend,
	.resume         = vpif_resume,
};

#define vpif_pm_ops (&vpif_pm)
#else
#define vpif_pm_ops NULL
#endif

static struct platform_driver vpif_driver = {
	.driver = {
		.name	= "vpif",
		.pm	= vpif_pm_ops,
	},
	.remove = vpif_remove,
	.probe = vpif_probe,
};

static void vpif_exit(void)
{
	platform_driver_unregister(&vpif_driver);
}

static int __init vpif_init(void)
{
	return platform_driver_register(&vpif_driver);
}
subsys_initcall(vpif_init);
module_exit(vpif_exit);
Commit	Line	Data
63a8e71c	1	/*
0a63172a	2	* vpif - Video Port Interface driver
63a8e71c C	3	* VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
	4	* that receiveing video byte stream and two channels(2, 3) for video output.
	5	* The hardware supports SDTV, HDTV formats, raw data capture.
	6	* Currently, the driver supports NTSC and PAL standards.
	7	*
	8	* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation version 2.
	13	*
	14	* This program is distributed .as is. WITHOUT ANY WARRANTY of any
	15	* kind, whether express or implied; without even the implied warranty
	16	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*/
	19
01105690	20	#include <linux/err.h>
63a8e71c	21	#include <linux/init.h>
01105690 LP	22	#include <linux/io.h>
01105690 LP	23	#include <linux/kernel.h>
63a8e71c	24	#include <linux/module.h>
d28a6df6	25	#include <linux/platform_device.h>
407ccc65	26	#include <linux/pm_runtime.h>
01105690	27	#include <linux/spinlock.h>
0598c17b HV	28	#include <linux/v4l2-dv-timings.h>
0598c17b HV	29
63a8e71c C	30	#include "vpif.h"
	31
	32	MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
	33	MODULE_LICENSE("GPL");
	34
079b3852 LP	35	#define VPIF_CH0_MAX_MODES 22
	36	#define VPIF_CH1_MAX_MODES 2
	37	#define VPIF_CH2_MAX_MODES 15
	38	#define VPIF_CH3_MAX_MODES 2
63a8e71c	39
d28a6df6	40	spinlock_t vpif_lock;
f5281fc8	41	EXPORT_SYMBOL_GPL(vpif_lock);
d28a6df6 MK	42
d28a6df6 MK	43	void __iomem *vpif_base;
ced9b21f LP	44	EXPORT_SYMBOL_GPL(vpif_base);
ced9b21f LP	45
aa444406	46	/**
ced9b21f	47	* vpif_ch_params: video standard configuration parameters for vpif
aa444406 MR	48	* The table must include all presets from supported subdevices.
aa444406 MR	49	*/
ced9b21f	50	const struct vpif_channel_config_params vpif_ch_params[] = {
40c8bcea MR	51	/* HDTV formats */
	52	{
	53	.name = "480p59_94",
	54	.width = 720,
	55	.height = 480,
	56	.frm_fmt = 1,
	57	.ycmux_mode = 0,
	58	.eav2sav = 138-8,
	59	.sav2eav = 720,
	60	.l1 = 1,
	61	.l3 = 43,
	62	.l5 = 523,
	63	.vsize = 525,
	64	.capture_format = 0,
	65	.vbi_supported = 0,
	66	.hd_sd = 1,
0598c17b	67	.dv_timings = V4L2_DV_BT_CEA_720X480P59_94,
40c8bcea MR	68	},
	69	{
	70	.name = "576p50",
	71	.width = 720,
	72	.height = 576,
	73	.frm_fmt = 1,
	74	.ycmux_mode = 0,
	75	.eav2sav = 144-8,
	76	.sav2eav = 720,
	77	.l1 = 1,
	78	.l3 = 45,
	79	.l5 = 621,
	80	.vsize = 625,
	81	.capture_format = 0,
	82	.vbi_supported = 0,
	83	.hd_sd = 1,
0598c17b	84	.dv_timings = V4L2_DV_BT_CEA_720X576P50,
40c8bcea MR	85	},
	86	{
	87	.name = "720p50",
	88	.width = 1280,
	89	.height = 720,
	90	.frm_fmt = 1,
	91	.ycmux_mode = 0,
	92	.eav2sav = 700-8,
	93	.sav2eav = 1280,
	94	.l1 = 1,
	95	.l3 = 26,
	96	.l5 = 746,
	97	.vsize = 750,
	98	.capture_format = 0,
	99	.vbi_supported = 0,
	100	.hd_sd = 1,
0598c17b	101	.dv_timings = V4L2_DV_BT_CEA_1280X720P50,
40c8bcea MR	102	},
	103	{
	104	.name = "720p60",
	105	.width = 1280,
	106	.height = 720,
	107	.frm_fmt = 1,
	108	.ycmux_mode = 0,
	109	.eav2sav = 370 - 8,
	110	.sav2eav = 1280,
	111	.l1 = 1,
	112	.l3 = 26,
	113	.l5 = 746,
	114	.vsize = 750,
	115	.capture_format = 0,
	116	.vbi_supported = 0,
	117	.hd_sd = 1,
0598c17b	118	.dv_timings = V4L2_DV_BT_CEA_1280X720P60,
40c8bcea MR	119	},
	120	{
	121	.name = "1080I50",
	122	.width = 1920,
	123	.height = 1080,
	124	.frm_fmt = 0,
	125	.ycmux_mode = 0,
	126	.eav2sav = 720 - 8,
	127	.sav2eav = 1920,
	128	.l1 = 1,
	129	.l3 = 21,
	130	.l5 = 561,
	131	.l7 = 563,
	132	.l9 = 584,
	133	.l11 = 1124,
	134	.vsize = 1125,
	135	.capture_format = 0,
	136	.vbi_supported = 0,
	137	.hd_sd = 1,
0598c17b	138	.dv_timings = V4L2_DV_BT_CEA_1920X1080I50,
40c8bcea MR	139	},
	140	{
	141	.name = "1080I60",
	142	.width = 1920,
	143	.height = 1080,
	144	.frm_fmt = 0,
	145	.ycmux_mode = 0,
	146	.eav2sav = 280 - 8,
	147	.sav2eav = 1920,
	148	.l1 = 1,
	149	.l3 = 21,
	150	.l5 = 561,
	151	.l7 = 563,
	152	.l9 = 584,
	153	.l11 = 1124,
	154	.vsize = 1125,
	155	.capture_format = 0,
	156	.vbi_supported = 0,
	157	.hd_sd = 1,
0598c17b	158	.dv_timings = V4L2_DV_BT_CEA_1920X1080I60,
40c8bcea MR	159	},
	160	{
	161	.name = "1080p60",
	162	.width = 1920,
	163	.height = 1080,
	164	.frm_fmt = 1,
	165	.ycmux_mode = 0,
	166	.eav2sav = 280 - 8,
	167	.sav2eav = 1920,
	168	.l1 = 1,
	169	.l3 = 42,
	170	.l5 = 1122,
	171	.vsize = 1125,
	172	.capture_format = 0,
	173	.vbi_supported = 0,
	174	.hd_sd = 1,
0598c17b	175	.dv_timings = V4L2_DV_BT_CEA_1920X1080P60,
40c8bcea MR	176	},
40c8bcea MR	177
aa444406 MR	178	/* SDTV formats */
	179	{
	180	.name = "NTSC_M",
	181	.width = 720,
	182	.height = 480,
	183	.frm_fmt = 0,
	184	.ycmux_mode = 1,
	185	.eav2sav = 268,
	186	.sav2eav = 1440,
	187	.l1 = 1,
	188	.l3 = 23,
	189	.l5 = 263,
	190	.l7 = 266,
	191	.l9 = 286,
	192	.l11 = 525,
	193	.vsize = 525,
	194	.capture_format = 0,
	195	.vbi_supported = 1,
	196	.hd_sd = 0,
	197	.stdid = V4L2_STD_525_60,
	198	},
	199	{
	200	.name = "PAL_BDGHIK",
	201	.width = 720,
	202	.height = 576,
	203	.frm_fmt = 0,
	204	.ycmux_mode = 1,
	205	.eav2sav = 280,
	206	.sav2eav = 1440,
	207	.l1 = 1,
	208	.l3 = 23,
	209	.l5 = 311,
	210	.l7 = 313,
	211	.l9 = 336,
	212	.l11 = 624,
	213	.vsize = 625,
	214	.capture_format = 0,
	215	.vbi_supported = 1,
	216	.hd_sd = 0,
	217	.stdid = V4L2_STD_625_50,
	218	},
	219	};
ced9b21f	220	EXPORT_SYMBOL_GPL(vpif_ch_params);
aa444406	221
ced9b21f LP	222	const unsigned int vpif_ch_params_count = ARRAY_SIZE(vpif_ch_params);
ced9b21f LP	223	EXPORT_SYMBOL_GPL(vpif_ch_params_count);
aa444406	224
63a8e71c C	225	static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
	226	{
	227	if (val)
	228	vpif_set_bit(reg, bit);
	229	else
	230	vpif_clr_bit(reg, bit);
	231	}
	232
	233	/* This structure is used to keep track of VPIF size register's offsets */
	234	struct vpif_registers {
	235	u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
	236	u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
	237	u32 vanc1_size, width_mask, len_mask;
	238	u8 max_modes;
	239	};
	240
	241	static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
	242	/* Channel0 */
	243	{
	244	VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
	245	VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
	246	VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
	247	VPIF_CH0_MAX_MODES,
	248	},
	249	/* Channel1 */
	250	{
	251	VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
	252	VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
	253	VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
	254	VPIF_CH1_MAX_MODES,
	255	},
	256	/* Channel2 */
	257	{
	258	VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
	259	VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
	260	VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
	261	VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
	262	VPIF_CH2_MAX_MODES
	263	},
	264	/* Channel3 */
	265	{
	266	VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
	267	VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
	268	VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
	269	VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
	270	VPIF_CH3_MAX_MODES
	271	},
	272	};
	273
	274	/* vpif_set_mode_info:
	275	* This function is used to set horizontal and vertical config parameters
	276	* As per the standard in the channel, configure the values of L1, L3,
	277	* L5, L7 L9, L11 in VPIF Register , also write width and height
	278	*/
	279	static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
	280	u8 channel_id, u8 config_channel_id)
	281	{
	282	u32 value;
	283
	284	value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
	285	value <<= VPIF_CH_LEN_SHIFT;
	286	value \|= (config->sav2eav & vpifregs[config_channel_id].width_mask);
	287	regw(value, vpifregs[channel_id].h_cfg);
	288
289	value = (config->l1 & vpifregs[config_channel_id].len_mask);
290	value <<= VPIF_CH_LEN_SHIFT;
291	value \|= (config->l3 & vpifregs[config_channel_id].len_mask);
292	regw(value, vpifregs[channel_id].v_cfg_00);
293
294	value = (config->l5 & vpifregs[config_channel_id].len_mask);
295	value <<= VPIF_CH_LEN_SHIFT;
296	value \|= (config->l7 & vpifregs[config_channel_id].len_mask);
297	regw(value, vpifregs[channel_id].v_cfg_01);
298
299	value = (config->l9 & vpifregs[config_channel_id].len_mask);
300	value <<= VPIF_CH_LEN_SHIFT;
301	value \|= (config->l11 & vpifregs[config_channel_id].len_mask);
302	regw(value, vpifregs[channel_id].v_cfg_02);
303
304	value = (config->vsize & vpifregs[config_channel_id].len_mask);
305	regw(value, vpifregs[channel_id].v_cfg);
306	}
307
308	/* config_vpif_params
309	* Function to set the parameters of a channel
310	* Mainly modifies the channel ciontrol register
311	* It sets frame format, yc mux mode
312	*/
313	static void config_vpif_params(struct vpif_params *vpifparams,
314	u8 channel_id, u8 found)
315	{
316	const struct vpif_channel_config_params *config = &vpifparams->std_info;
317	u32 value, ch_nip, reg;
318	u8 start, end;
319	int i;
320
321	start = channel_id;
322	end = channel_id + found;
323
324	for (i = start; i < end; i++) {
325	reg = vpifregs[i].ch_ctrl;
326	if (channel_id < 2)
327	ch_nip = VPIF_CAPTURE_CH_NIP;
328	else
329	ch_nip = VPIF_DISPLAY_CH_NIP;
330
331	vpif_wr_bit(reg, ch_nip, config->frm_fmt);
332	vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
333	vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
334	vpifparams->video_params.storage_mode);
335
336	/* Set raster scanning SDR Format */
337	vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
338	vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
339
340	if (channel_id > 1) /* Set the Pixel enable bit */
341	vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
342	else if (config->capture_format) {
343	/* Set the polarity of various pins */
344	vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
d28a6df6	345	vpifparams->iface.fid_pol);
63a8e71c	346	vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
d28a6df6	347	vpifparams->iface.vd_pol);
63a8e71c	348	vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
d28a6df6	349	vpifparams->iface.hd_pol);
63a8e71c C	350
	351	value = regr(reg);
	352	/* Set data width */
3bc1953b	353	value &= ~(0x3u <<
63a8e71c	354	VPIF_CH_DATA_WIDTH_BIT);
d28a6df6	355	value \|= ((vpifparams->params.data_sz) <<
63a8e71c C	356	VPIF_CH_DATA_WIDTH_BIT);
	357	regw(value, reg);
	358	}
	359
	360	/* Write the pitch in the driver */
	361	regw((vpifparams->video_params.hpitch),
	362	vpifregs[i].line_offset);
	363	}
	364	}
	365
	366	/* vpif_set_video_params
	367	* This function is used to set video parameters in VPIF register
	368	*/
	369	int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
	370	{
	371	const struct vpif_channel_config_params *config = &vpifparams->std_info;
	372	int found = 1;
	373
	374	vpif_set_mode_info(config, channel_id, channel_id);
	375	if (!config->ycmux_mode) {
	376	/* YC are on separate channels (HDTV formats) */
	377	vpif_set_mode_info(config, channel_id + 1, channel_id);
	378	found = 2;
	379	}
	380
	381	config_vpif_params(vpifparams, channel_id, found);
	382
	383	regw(0x80, VPIF_REQ_SIZE);
	384	regw(0x01, VPIF_EMULATION_CTRL);
	385
	386	return found;
	387	}
	388	EXPORT_SYMBOL(vpif_set_video_params);
	389
	390	void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
	391	u8 channel_id)
	392	{
	393	u32 value;
	394
	395	value = 0x3F8 & (vbiparams->hstart0);
	396	value \|= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
	397	regw(value, vpifregs[channel_id].vanc0_strt);
	398
	399	value = 0x3F8 & (vbiparams->hstart1);
	400	value \|= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
	401	regw(value, vpifregs[channel_id].vanc1_strt);
	402
	403	value = 0x3F8 & (vbiparams->hsize0);
	404	value \|= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
	405	regw(value, vpifregs[channel_id].vanc0_size);
	406
	407	value = 0x3F8 & (vbiparams->hsize1);
	408	value \|= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
	409	regw(value, vpifregs[channel_id].vanc1_size);
	410
	411	}
	412	EXPORT_SYMBOL(vpif_set_vbi_display_params);
	413
	414	int vpif_channel_getfid(u8 channel_id)
	415	{
	416	return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
	417	>> VPIF_CH_FID_SHIFT;
	418	}
	419	EXPORT_SYMBOL(vpif_channel_getfid);
420
4c62e976	421	static int vpif_probe(struct platform_device *pdev)
d28a6df6	422	{
c7f808d1	423	static struct resource *res;
d28a6df6 MK	424
d28a6df6 MK	425	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
c7f808d1 LP	426	vpif_base = devm_ioremap_resource(&pdev->dev, res);
	427	if (IS_ERR(vpif_base))
	428	return PTR_ERR(vpif_base);
d28a6df6	429
407ccc65 LP	430	pm_runtime_enable(&pdev->dev);
407ccc65 LP	431	pm_runtime_get(&pdev->dev);
31415d0e	432
d28a6df6 MK	433	spin_lock_init(&vpif_lock);
	434	dev_info(&pdev->dev, "vpif probe success\n");
	435	return 0;
d28a6df6 MK	436	}
d28a6df6 MK	437
4c62e976	438	static int vpif_remove(struct platform_device *pdev)
63a8e71c	439	{
407ccc65	440	pm_runtime_disable(&pdev->dev);
d28a6df6	441	return 0;
63a8e71c	442	}
d28a6df6	443
31415d0e MH	444	#ifdef CONFIG_PM
	445	static int vpif_suspend(struct device *dev)
	446	{
407ccc65	447	pm_runtime_put(dev);
31415d0e MH	448	return 0;
	449	}
	450
	451	static int vpif_resume(struct device *dev)
	452	{
407ccc65	453	pm_runtime_get(dev);
31415d0e MH	454	return 0;
	455	}
	456
	457	static const struct dev_pm_ops vpif_pm = {
	458	.suspend = vpif_suspend,
	459	.resume = vpif_resume,
	460	};
	461
	462	#define vpif_pm_ops (&vpif_pm)
	463	#else
	464	#define vpif_pm_ops NULL
	465	#endif
	466
a1b3a6ce	467	static struct platform_driver vpif_driver = {
d28a6df6 MK	468	.driver = {
d28a6df6 MK	469	.name = "vpif",
31415d0e	470	.pm = vpif_pm_ops,
d28a6df6	471	},
4c62e976	472	.remove = vpif_remove,
d28a6df6 MK	473	.probe = vpif_probe,
	474	};
	475
	476	static void vpif_exit(void)
	477	{
	478	platform_driver_unregister(&vpif_driver);
	479	}
	480
	481	static int __init vpif_init(void)
	482	{
	483	return platform_driver_register(&vpif_driver);
	484	}
	485	subsys_initcall(vpif_init);
	486	module_exit(vpif_exit);
	487