Commit | Line | Data |
---|---|---|
63a8e71c | 1 | /* |
0a63172a | 2 | * vpif - Video Port Interface driver |
63a8e71c C |
3 | * VPIF is a receiver and transmitter for video data. It has two channels(0, 1) |
4 | * that receiveing video byte stream and two channels(2, 3) for video output. | |
5 | * The hardware supports SDTV, HDTV formats, raw data capture. | |
6 | * Currently, the driver supports NTSC and PAL standards. | |
7 | * | |
8 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation version 2. | |
13 | * | |
14 | * This program is distributed .as is. WITHOUT ANY WARRANTY of any | |
15 | * kind, whether express or implied; without even the implied warranty | |
16 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/module.h> | |
d28a6df6 MK |
22 | #include <linux/platform_device.h> |
23 | #include <linux/spinlock.h> | |
63a8e71c | 24 | #include <linux/kernel.h> |
d28a6df6 | 25 | #include <linux/io.h> |
31415d0e MH |
26 | #include <linux/clk.h> |
27 | #include <linux/err.h> | |
0598c17b HV |
28 | #include <linux/v4l2-dv-timings.h> |
29 | ||
d28a6df6 | 30 | #include <mach/hardware.h> |
63a8e71c C |
31 | |
32 | #include "vpif.h" | |
33 | ||
34 | MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver"); | |
35 | MODULE_LICENSE("GPL"); | |
36 | ||
37 | #define VPIF_CH0_MAX_MODES (22) | |
38 | #define VPIF_CH1_MAX_MODES (02) | |
39 | #define VPIF_CH2_MAX_MODES (15) | |
40 | #define VPIF_CH3_MAX_MODES (02) | |
41 | ||
d28a6df6 MK |
42 | static resource_size_t res_len; |
43 | static struct resource *res; | |
44 | spinlock_t vpif_lock; | |
45 | ||
46 | void __iomem *vpif_base; | |
31415d0e | 47 | struct clk *vpif_clk; |
d28a6df6 | 48 | |
aa444406 MR |
49 | /** |
50 | * ch_params: video standard configuration parameters for vpif | |
51 | * The table must include all presets from supported subdevices. | |
52 | */ | |
53 | const struct vpif_channel_config_params ch_params[] = { | |
40c8bcea MR |
54 | /* HDTV formats */ |
55 | { | |
56 | .name = "480p59_94", | |
57 | .width = 720, | |
58 | .height = 480, | |
59 | .frm_fmt = 1, | |
60 | .ycmux_mode = 0, | |
61 | .eav2sav = 138-8, | |
62 | .sav2eav = 720, | |
63 | .l1 = 1, | |
64 | .l3 = 43, | |
65 | .l5 = 523, | |
66 | .vsize = 525, | |
67 | .capture_format = 0, | |
68 | .vbi_supported = 0, | |
69 | .hd_sd = 1, | |
0598c17b | 70 | .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, |
40c8bcea MR |
71 | }, |
72 | { | |
73 | .name = "576p50", | |
74 | .width = 720, | |
75 | .height = 576, | |
76 | .frm_fmt = 1, | |
77 | .ycmux_mode = 0, | |
78 | .eav2sav = 144-8, | |
79 | .sav2eav = 720, | |
80 | .l1 = 1, | |
81 | .l3 = 45, | |
82 | .l5 = 621, | |
83 | .vsize = 625, | |
84 | .capture_format = 0, | |
85 | .vbi_supported = 0, | |
86 | .hd_sd = 1, | |
0598c17b | 87 | .dv_timings = V4L2_DV_BT_CEA_720X576P50, |
40c8bcea MR |
88 | }, |
89 | { | |
90 | .name = "720p50", | |
91 | .width = 1280, | |
92 | .height = 720, | |
93 | .frm_fmt = 1, | |
94 | .ycmux_mode = 0, | |
95 | .eav2sav = 700-8, | |
96 | .sav2eav = 1280, | |
97 | .l1 = 1, | |
98 | .l3 = 26, | |
99 | .l5 = 746, | |
100 | .vsize = 750, | |
101 | .capture_format = 0, | |
102 | .vbi_supported = 0, | |
103 | .hd_sd = 1, | |
0598c17b | 104 | .dv_timings = V4L2_DV_BT_CEA_1280X720P50, |
40c8bcea MR |
105 | }, |
106 | { | |
107 | .name = "720p60", | |
108 | .width = 1280, | |
109 | .height = 720, | |
110 | .frm_fmt = 1, | |
111 | .ycmux_mode = 0, | |
112 | .eav2sav = 370 - 8, | |
113 | .sav2eav = 1280, | |
114 | .l1 = 1, | |
115 | .l3 = 26, | |
116 | .l5 = 746, | |
117 | .vsize = 750, | |
118 | .capture_format = 0, | |
119 | .vbi_supported = 0, | |
120 | .hd_sd = 1, | |
0598c17b | 121 | .dv_timings = V4L2_DV_BT_CEA_1280X720P60, |
40c8bcea MR |
122 | }, |
123 | { | |
124 | .name = "1080I50", | |
125 | .width = 1920, | |
126 | .height = 1080, | |
127 | .frm_fmt = 0, | |
128 | .ycmux_mode = 0, | |
129 | .eav2sav = 720 - 8, | |
130 | .sav2eav = 1920, | |
131 | .l1 = 1, | |
132 | .l3 = 21, | |
133 | .l5 = 561, | |
134 | .l7 = 563, | |
135 | .l9 = 584, | |
136 | .l11 = 1124, | |
137 | .vsize = 1125, | |
138 | .capture_format = 0, | |
139 | .vbi_supported = 0, | |
140 | .hd_sd = 1, | |
0598c17b | 141 | .dv_timings = V4L2_DV_BT_CEA_1920X1080I50, |
40c8bcea MR |
142 | }, |
143 | { | |
144 | .name = "1080I60", | |
145 | .width = 1920, | |
146 | .height = 1080, | |
147 | .frm_fmt = 0, | |
148 | .ycmux_mode = 0, | |
149 | .eav2sav = 280 - 8, | |
150 | .sav2eav = 1920, | |
151 | .l1 = 1, | |
152 | .l3 = 21, | |
153 | .l5 = 561, | |
154 | .l7 = 563, | |
155 | .l9 = 584, | |
156 | .l11 = 1124, | |
157 | .vsize = 1125, | |
158 | .capture_format = 0, | |
159 | .vbi_supported = 0, | |
160 | .hd_sd = 1, | |
0598c17b | 161 | .dv_timings = V4L2_DV_BT_CEA_1920X1080I60, |
40c8bcea MR |
162 | }, |
163 | { | |
164 | .name = "1080p60", | |
165 | .width = 1920, | |
166 | .height = 1080, | |
167 | .frm_fmt = 1, | |
168 | .ycmux_mode = 0, | |
169 | .eav2sav = 280 - 8, | |
170 | .sav2eav = 1920, | |
171 | .l1 = 1, | |
172 | .l3 = 42, | |
173 | .l5 = 1122, | |
174 | .vsize = 1125, | |
175 | .capture_format = 0, | |
176 | .vbi_supported = 0, | |
177 | .hd_sd = 1, | |
0598c17b | 178 | .dv_timings = V4L2_DV_BT_CEA_1920X1080P60, |
40c8bcea MR |
179 | }, |
180 | ||
aa444406 MR |
181 | /* SDTV formats */ |
182 | { | |
183 | .name = "NTSC_M", | |
184 | .width = 720, | |
185 | .height = 480, | |
186 | .frm_fmt = 0, | |
187 | .ycmux_mode = 1, | |
188 | .eav2sav = 268, | |
189 | .sav2eav = 1440, | |
190 | .l1 = 1, | |
191 | .l3 = 23, | |
192 | .l5 = 263, | |
193 | .l7 = 266, | |
194 | .l9 = 286, | |
195 | .l11 = 525, | |
196 | .vsize = 525, | |
197 | .capture_format = 0, | |
198 | .vbi_supported = 1, | |
199 | .hd_sd = 0, | |
200 | .stdid = V4L2_STD_525_60, | |
201 | }, | |
202 | { | |
203 | .name = "PAL_BDGHIK", | |
204 | .width = 720, | |
205 | .height = 576, | |
206 | .frm_fmt = 0, | |
207 | .ycmux_mode = 1, | |
208 | .eav2sav = 280, | |
209 | .sav2eav = 1440, | |
210 | .l1 = 1, | |
211 | .l3 = 23, | |
212 | .l5 = 311, | |
213 | .l7 = 313, | |
214 | .l9 = 336, | |
215 | .l11 = 624, | |
216 | .vsize = 625, | |
217 | .capture_format = 0, | |
218 | .vbi_supported = 1, | |
219 | .hd_sd = 0, | |
220 | .stdid = V4L2_STD_625_50, | |
221 | }, | |
222 | }; | |
223 | ||
224 | const unsigned int vpif_ch_params_count = ARRAY_SIZE(ch_params); | |
225 | ||
63a8e71c C |
226 | static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val) |
227 | { | |
228 | if (val) | |
229 | vpif_set_bit(reg, bit); | |
230 | else | |
231 | vpif_clr_bit(reg, bit); | |
232 | } | |
233 | ||
234 | /* This structure is used to keep track of VPIF size register's offsets */ | |
235 | struct vpif_registers { | |
236 | u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl; | |
237 | u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt; | |
238 | u32 vanc1_size, width_mask, len_mask; | |
239 | u8 max_modes; | |
240 | }; | |
241 | ||
242 | static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = { | |
243 | /* Channel0 */ | |
244 | { | |
245 | VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01, | |
246 | VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL, | |
247 | VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF, | |
248 | VPIF_CH0_MAX_MODES, | |
249 | }, | |
250 | /* Channel1 */ | |
251 | { | |
252 | VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01, | |
253 | VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL, | |
254 | VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF, | |
255 | VPIF_CH1_MAX_MODES, | |
256 | }, | |
257 | /* Channel2 */ | |
258 | { | |
259 | VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01, | |
260 | VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL, | |
261 | VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE, | |
262 | VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF, | |
263 | VPIF_CH2_MAX_MODES | |
264 | }, | |
265 | /* Channel3 */ | |
266 | { | |
267 | VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01, | |
268 | VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL, | |
269 | VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE, | |
270 | VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF, | |
271 | VPIF_CH3_MAX_MODES | |
272 | }, | |
273 | }; | |
274 | ||
275 | /* vpif_set_mode_info: | |
276 | * This function is used to set horizontal and vertical config parameters | |
277 | * As per the standard in the channel, configure the values of L1, L3, | |
278 | * L5, L7 L9, L11 in VPIF Register , also write width and height | |
279 | */ | |
280 | static void vpif_set_mode_info(const struct vpif_channel_config_params *config, | |
281 | u8 channel_id, u8 config_channel_id) | |
282 | { | |
283 | u32 value; | |
284 | ||
285 | value = (config->eav2sav & vpifregs[config_channel_id].width_mask); | |
286 | value <<= VPIF_CH_LEN_SHIFT; | |
287 | value |= (config->sav2eav & vpifregs[config_channel_id].width_mask); | |
288 | regw(value, vpifregs[channel_id].h_cfg); | |
289 | ||
290 | value = (config->l1 & vpifregs[config_channel_id].len_mask); | |
291 | value <<= VPIF_CH_LEN_SHIFT; | |
292 | value |= (config->l3 & vpifregs[config_channel_id].len_mask); | |
293 | regw(value, vpifregs[channel_id].v_cfg_00); | |
294 | ||
295 | value = (config->l5 & vpifregs[config_channel_id].len_mask); | |
296 | value <<= VPIF_CH_LEN_SHIFT; | |
297 | value |= (config->l7 & vpifregs[config_channel_id].len_mask); | |
298 | regw(value, vpifregs[channel_id].v_cfg_01); | |
299 | ||
300 | value = (config->l9 & vpifregs[config_channel_id].len_mask); | |
301 | value <<= VPIF_CH_LEN_SHIFT; | |
302 | value |= (config->l11 & vpifregs[config_channel_id].len_mask); | |
303 | regw(value, vpifregs[channel_id].v_cfg_02); | |
304 | ||
305 | value = (config->vsize & vpifregs[config_channel_id].len_mask); | |
306 | regw(value, vpifregs[channel_id].v_cfg); | |
307 | } | |
308 | ||
309 | /* config_vpif_params | |
310 | * Function to set the parameters of a channel | |
311 | * Mainly modifies the channel ciontrol register | |
312 | * It sets frame format, yc mux mode | |
313 | */ | |
314 | static void config_vpif_params(struct vpif_params *vpifparams, | |
315 | u8 channel_id, u8 found) | |
316 | { | |
317 | const struct vpif_channel_config_params *config = &vpifparams->std_info; | |
318 | u32 value, ch_nip, reg; | |
319 | u8 start, end; | |
320 | int i; | |
321 | ||
322 | start = channel_id; | |
323 | end = channel_id + found; | |
324 | ||
325 | for (i = start; i < end; i++) { | |
326 | reg = vpifregs[i].ch_ctrl; | |
327 | if (channel_id < 2) | |
328 | ch_nip = VPIF_CAPTURE_CH_NIP; | |
329 | else | |
330 | ch_nip = VPIF_DISPLAY_CH_NIP; | |
331 | ||
332 | vpif_wr_bit(reg, ch_nip, config->frm_fmt); | |
333 | vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode); | |
334 | vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT, | |
335 | vpifparams->video_params.storage_mode); | |
336 | ||
337 | /* Set raster scanning SDR Format */ | |
338 | vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT); | |
339 | vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format); | |
340 | ||
341 | if (channel_id > 1) /* Set the Pixel enable bit */ | |
342 | vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT); | |
343 | else if (config->capture_format) { | |
344 | /* Set the polarity of various pins */ | |
345 | vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT, | |
d28a6df6 | 346 | vpifparams->iface.fid_pol); |
63a8e71c | 347 | vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT, |
d28a6df6 | 348 | vpifparams->iface.vd_pol); |
63a8e71c | 349 | vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT, |
d28a6df6 | 350 | vpifparams->iface.hd_pol); |
63a8e71c C |
351 | |
352 | value = regr(reg); | |
353 | /* Set data width */ | |
3bc1953b | 354 | value &= ~(0x3u << |
63a8e71c | 355 | VPIF_CH_DATA_WIDTH_BIT); |
d28a6df6 | 356 | value |= ((vpifparams->params.data_sz) << |
63a8e71c C |
357 | VPIF_CH_DATA_WIDTH_BIT); |
358 | regw(value, reg); | |
359 | } | |
360 | ||
361 | /* Write the pitch in the driver */ | |
362 | regw((vpifparams->video_params.hpitch), | |
363 | vpifregs[i].line_offset); | |
364 | } | |
365 | } | |
366 | ||
367 | /* vpif_set_video_params | |
368 | * This function is used to set video parameters in VPIF register | |
369 | */ | |
370 | int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id) | |
371 | { | |
372 | const struct vpif_channel_config_params *config = &vpifparams->std_info; | |
373 | int found = 1; | |
374 | ||
375 | vpif_set_mode_info(config, channel_id, channel_id); | |
376 | if (!config->ycmux_mode) { | |
377 | /* YC are on separate channels (HDTV formats) */ | |
378 | vpif_set_mode_info(config, channel_id + 1, channel_id); | |
379 | found = 2; | |
380 | } | |
381 | ||
382 | config_vpif_params(vpifparams, channel_id, found); | |
383 | ||
384 | regw(0x80, VPIF_REQ_SIZE); | |
385 | regw(0x01, VPIF_EMULATION_CTRL); | |
386 | ||
387 | return found; | |
388 | } | |
389 | EXPORT_SYMBOL(vpif_set_video_params); | |
390 | ||
391 | void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams, | |
392 | u8 channel_id) | |
393 | { | |
394 | u32 value; | |
395 | ||
396 | value = 0x3F8 & (vbiparams->hstart0); | |
397 | value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16); | |
398 | regw(value, vpifregs[channel_id].vanc0_strt); | |
399 | ||
400 | value = 0x3F8 & (vbiparams->hstart1); | |
401 | value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16); | |
402 | regw(value, vpifregs[channel_id].vanc1_strt); | |
403 | ||
404 | value = 0x3F8 & (vbiparams->hsize0); | |
405 | value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16); | |
406 | regw(value, vpifregs[channel_id].vanc0_size); | |
407 | ||
408 | value = 0x3F8 & (vbiparams->hsize1); | |
409 | value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16); | |
410 | regw(value, vpifregs[channel_id].vanc1_size); | |
411 | ||
412 | } | |
413 | EXPORT_SYMBOL(vpif_set_vbi_display_params); | |
414 | ||
415 | int vpif_channel_getfid(u8 channel_id) | |
416 | { | |
417 | return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK) | |
418 | >> VPIF_CH_FID_SHIFT; | |
419 | } | |
420 | EXPORT_SYMBOL(vpif_channel_getfid); | |
421 | ||
4c62e976 | 422 | static int vpif_probe(struct platform_device *pdev) |
d28a6df6 MK |
423 | { |
424 | int status = 0; | |
425 | ||
426 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
427 | if (!res) | |
428 | return -ENOENT; | |
429 | ||
28f65c11 | 430 | res_len = resource_size(res); |
d28a6df6 MK |
431 | |
432 | res = request_mem_region(res->start, res_len, res->name); | |
433 | if (!res) | |
434 | return -EBUSY; | |
435 | ||
436 | vpif_base = ioremap(res->start, res_len); | |
437 | if (!vpif_base) { | |
438 | status = -EBUSY; | |
439 | goto fail; | |
440 | } | |
441 | ||
31415d0e MH |
442 | vpif_clk = clk_get(&pdev->dev, "vpif"); |
443 | if (IS_ERR(vpif_clk)) { | |
444 | status = PTR_ERR(vpif_clk); | |
445 | goto clk_fail; | |
446 | } | |
1f5a5e62 | 447 | clk_prepare_enable(vpif_clk); |
31415d0e | 448 | |
d28a6df6 MK |
449 | spin_lock_init(&vpif_lock); |
450 | dev_info(&pdev->dev, "vpif probe success\n"); | |
451 | return 0; | |
452 | ||
31415d0e MH |
453 | clk_fail: |
454 | iounmap(vpif_base); | |
d28a6df6 MK |
455 | fail: |
456 | release_mem_region(res->start, res_len); | |
457 | return status; | |
458 | } | |
459 | ||
4c62e976 | 460 | static int vpif_remove(struct platform_device *pdev) |
63a8e71c | 461 | { |
31415d0e | 462 | if (vpif_clk) { |
1f5a5e62 | 463 | clk_disable_unprepare(vpif_clk); |
31415d0e MH |
464 | clk_put(vpif_clk); |
465 | } | |
466 | ||
d28a6df6 MK |
467 | iounmap(vpif_base); |
468 | release_mem_region(res->start, res_len); | |
469 | return 0; | |
63a8e71c | 470 | } |
d28a6df6 | 471 | |
31415d0e MH |
472 | #ifdef CONFIG_PM |
473 | static int vpif_suspend(struct device *dev) | |
474 | { | |
1f5a5e62 | 475 | clk_disable_unprepare(vpif_clk); |
31415d0e MH |
476 | return 0; |
477 | } | |
478 | ||
479 | static int vpif_resume(struct device *dev) | |
480 | { | |
1f5a5e62 | 481 | clk_prepare_enable(vpif_clk); |
31415d0e MH |
482 | return 0; |
483 | } | |
484 | ||
485 | static const struct dev_pm_ops vpif_pm = { | |
486 | .suspend = vpif_suspend, | |
487 | .resume = vpif_resume, | |
488 | }; | |
489 | ||
490 | #define vpif_pm_ops (&vpif_pm) | |
491 | #else | |
492 | #define vpif_pm_ops NULL | |
493 | #endif | |
494 | ||
a1b3a6ce | 495 | static struct platform_driver vpif_driver = { |
d28a6df6 MK |
496 | .driver = { |
497 | .name = "vpif", | |
498 | .owner = THIS_MODULE, | |
31415d0e | 499 | .pm = vpif_pm_ops, |
d28a6df6 | 500 | }, |
4c62e976 | 501 | .remove = vpif_remove, |
d28a6df6 MK |
502 | .probe = vpif_probe, |
503 | }; | |
504 | ||
505 | static void vpif_exit(void) | |
506 | { | |
507 | platform_driver_unregister(&vpif_driver); | |
508 | } | |
509 | ||
510 | static int __init vpif_init(void) | |
511 | { | |
512 | return platform_driver_register(&vpif_driver); | |
513 | } | |
514 | subsys_initcall(vpif_init); | |
515 | module_exit(vpif_exit); | |
516 |