Commit | Line | Data |
---|---|---|
5fd8f738 | 1 | /* |
97d97422 | 2 | * Samsung S5P/EXYNOS4 SoC series FIMC (CAMIF) driver |
5fd8f738 | 3 | * |
0c9204d3 SN |
4 | * Copyright (C) 2010-2012 Samsung Electronics Co., Ltd. |
5 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
5fd8f738 SN |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published | |
9 | * by the Free Software Foundation, either version 2 of the License, | |
10 | * or (at your option) any later version. | |
11 | */ | |
12 | ||
13 | #include <linux/module.h> | |
14 | #include <linux/kernel.h> | |
5fd8f738 SN |
15 | #include <linux/types.h> |
16 | #include <linux/errno.h> | |
17 | #include <linux/bug.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/platform_device.h> | |
e9e21083 | 21 | #include <linux/pm_runtime.h> |
5fd8f738 | 22 | #include <linux/list.h> |
88fa8311 | 23 | #include <linux/mfd/syscon.h> |
5fd8f738 | 24 | #include <linux/io.h> |
e80cb1fa SN |
25 | #include <linux/of.h> |
26 | #include <linux/of_device.h> | |
5fd8f738 SN |
27 | #include <linux/slab.h> |
28 | #include <linux/clk.h> | |
29 | #include <media/v4l2-ioctl.h> | |
2dab38e2 SN |
30 | #include <media/videobuf2-core.h> |
31 | #include <media/videobuf2-dma-contig.h> | |
5fd8f738 SN |
32 | |
33 | #include "fimc-core.h" | |
c83a1ff0 | 34 | #include "fimc-reg.h" |
56fa1a6a | 35 | #include "media-dev.h" |
5fd8f738 | 36 | |
a25be18d | 37 | static char *fimc_clocks[MAX_FIMC_CLOCKS] = { |
ebdfea81 | 38 | "sclk_fimc", "fimc" |
a25be18d | 39 | }; |
5fd8f738 SN |
40 | |
41 | static struct fimc_fmt fimc_formats[] = { | |
42 | { | |
ef7af59b | 43 | .name = "RGB565", |
f83f71fd | 44 | .fourcc = V4L2_PIX_FMT_RGB565, |
ef7af59b | 45 | .depth = { 16 }, |
3d112d9a | 46 | .color = FIMC_FMT_RGB565, |
ef7af59b SN |
47 | .memplanes = 1, |
48 | .colplanes = 1, | |
ef7af59b | 49 | .flags = FMT_FLAGS_M2M, |
5fd8f738 | 50 | }, { |
ef7af59b SN |
51 | .name = "BGR666", |
52 | .fourcc = V4L2_PIX_FMT_BGR666, | |
53 | .depth = { 32 }, | |
3d112d9a | 54 | .color = FIMC_FMT_RGB666, |
ef7af59b SN |
55 | .memplanes = 1, |
56 | .colplanes = 1, | |
57 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 58 | }, { |
dafb9c70 | 59 | .name = "ARGB8888, 32 bpp", |
ef7af59b SN |
60 | .fourcc = V4L2_PIX_FMT_RGB32, |
61 | .depth = { 32 }, | |
3d112d9a | 62 | .color = FIMC_FMT_RGB888, |
ef7af59b SN |
63 | .memplanes = 1, |
64 | .colplanes = 1, | |
dafb9c70 SN |
65 | .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA, |
66 | }, { | |
67 | .name = "ARGB1555", | |
68 | .fourcc = V4L2_PIX_FMT_RGB555, | |
69 | .depth = { 16 }, | |
3d112d9a | 70 | .color = FIMC_FMT_RGB555, |
dafb9c70 SN |
71 | .memplanes = 1, |
72 | .colplanes = 1, | |
73 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
74 | }, { | |
75 | .name = "ARGB4444", | |
76 | .fourcc = V4L2_PIX_FMT_RGB444, | |
77 | .depth = { 16 }, | |
3d112d9a | 78 | .color = FIMC_FMT_RGB444, |
dafb9c70 SN |
79 | .memplanes = 1, |
80 | .colplanes = 1, | |
81 | .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, | |
88fa8311 SN |
82 | }, { |
83 | .name = "YUV 4:4:4", | |
84 | .mbus_code = V4L2_MBUS_FMT_YUV10_1X30, | |
85 | .flags = FMT_FLAGS_WRITEBACK, | |
5fd8f738 | 86 | }, { |
ef7af59b SN |
87 | .name = "YUV 4:2:2 packed, YCbYCr", |
88 | .fourcc = V4L2_PIX_FMT_YUYV, | |
89 | .depth = { 16 }, | |
3d112d9a | 90 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
91 | .memplanes = 1, |
92 | .colplanes = 1, | |
93 | .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, | |
94 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5f3cc447 | 95 | }, { |
ef7af59b SN |
96 | .name = "YUV 4:2:2 packed, CbYCrY", |
97 | .fourcc = V4L2_PIX_FMT_UYVY, | |
98 | .depth = { 16 }, | |
3d112d9a | 99 | .color = FIMC_FMT_CBYCRY422, |
ef7af59b SN |
100 | .memplanes = 1, |
101 | .colplanes = 1, | |
102 | .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8, | |
103 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 104 | }, { |
ef7af59b SN |
105 | .name = "YUV 4:2:2 packed, CrYCbY", |
106 | .fourcc = V4L2_PIX_FMT_VYUY, | |
107 | .depth = { 16 }, | |
3d112d9a | 108 | .color = FIMC_FMT_CRYCBY422, |
ef7af59b SN |
109 | .memplanes = 1, |
110 | .colplanes = 1, | |
111 | .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8, | |
112 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 113 | }, { |
ef7af59b SN |
114 | .name = "YUV 4:2:2 packed, YCrYCb", |
115 | .fourcc = V4L2_PIX_FMT_YVYU, | |
116 | .depth = { 16 }, | |
3d112d9a | 117 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
118 | .memplanes = 1, |
119 | .colplanes = 1, | |
120 | .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8, | |
121 | .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM, | |
5fd8f738 | 122 | }, { |
ef7af59b SN |
123 | .name = "YUV 4:2:2 planar, Y/Cb/Cr", |
124 | .fourcc = V4L2_PIX_FMT_YUV422P, | |
125 | .depth = { 12 }, | |
3d112d9a | 126 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
127 | .memplanes = 1, |
128 | .colplanes = 3, | |
129 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 130 | }, { |
ef7af59b SN |
131 | .name = "YUV 4:2:2 planar, Y/CbCr", |
132 | .fourcc = V4L2_PIX_FMT_NV16, | |
133 | .depth = { 16 }, | |
3d112d9a | 134 | .color = FIMC_FMT_YCBYCR422, |
ef7af59b SN |
135 | .memplanes = 1, |
136 | .colplanes = 2, | |
137 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 138 | }, { |
ef7af59b SN |
139 | .name = "YUV 4:2:2 planar, Y/CrCb", |
140 | .fourcc = V4L2_PIX_FMT_NV61, | |
141 | .depth = { 16 }, | |
3d112d9a | 142 | .color = FIMC_FMT_YCRYCB422, |
ef7af59b SN |
143 | .memplanes = 1, |
144 | .colplanes = 2, | |
145 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 146 | }, { |
ef7af59b SN |
147 | .name = "YUV 4:2:0 planar, YCbCr", |
148 | .fourcc = V4L2_PIX_FMT_YUV420, | |
149 | .depth = { 12 }, | |
3d112d9a | 150 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
151 | .memplanes = 1, |
152 | .colplanes = 3, | |
153 | .flags = FMT_FLAGS_M2M, | |
5fd8f738 | 154 | }, { |
ef7af59b SN |
155 | .name = "YUV 4:2:0 planar, Y/CbCr", |
156 | .fourcc = V4L2_PIX_FMT_NV12, | |
157 | .depth = { 12 }, | |
3d112d9a | 158 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
159 | .memplanes = 1, |
160 | .colplanes = 2, | |
161 | .flags = FMT_FLAGS_M2M, | |
162 | }, { | |
0a198bcd | 163 | .name = "YUV 4:2:0 non-contig. 2p, Y/CbCr", |
ef7af59b | 164 | .fourcc = V4L2_PIX_FMT_NV12M, |
3d112d9a | 165 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
166 | .depth = { 8, 4 }, |
167 | .memplanes = 2, | |
168 | .colplanes = 2, | |
169 | .flags = FMT_FLAGS_M2M, | |
170 | }, { | |
0a198bcd | 171 | .name = "YUV 4:2:0 non-contig. 3p, Y/Cb/Cr", |
ef7af59b | 172 | .fourcc = V4L2_PIX_FMT_YUV420M, |
3d112d9a | 173 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
174 | .depth = { 8, 2, 2 }, |
175 | .memplanes = 3, | |
176 | .colplanes = 3, | |
177 | .flags = FMT_FLAGS_M2M, | |
178 | }, { | |
0a198bcd | 179 | .name = "YUV 4:2:0 non-contig. 2p, tiled", |
ef7af59b | 180 | .fourcc = V4L2_PIX_FMT_NV12MT, |
3d112d9a | 181 | .color = FIMC_FMT_YCBCR420, |
ef7af59b SN |
182 | .depth = { 8, 4 }, |
183 | .memplanes = 2, | |
184 | .colplanes = 2, | |
185 | .flags = FMT_FLAGS_M2M, | |
ee7160e5 SN |
186 | }, { |
187 | .name = "JPEG encoded data", | |
188 | .fourcc = V4L2_PIX_FMT_JPEG, | |
3d112d9a | 189 | .color = FIMC_FMT_JPEG, |
ee7160e5 SN |
190 | .depth = { 8 }, |
191 | .memplanes = 1, | |
192 | .colplanes = 1, | |
193 | .mbus_code = V4L2_MBUS_FMT_JPEG_1X8, | |
14783d25 SN |
194 | .flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED, |
195 | }, { | |
196 | .name = "S5C73MX interleaved UYVY/JPEG", | |
197 | .fourcc = V4L2_PIX_FMT_S5C_UYVY_JPG, | |
198 | .color = FIMC_FMT_YUYV_JPEG, | |
199 | .depth = { 8 }, | |
200 | .memplanes = 2, | |
201 | .colplanes = 1, | |
202 | .mdataplanes = 0x2, /* plane 1 holds frame meta data */ | |
203 | .mbus_code = V4L2_MBUS_FMT_S5C_UYVY_JPEG_1X8, | |
204 | .flags = FMT_FLAGS_CAM | FMT_FLAGS_COMPRESSED, | |
5f3cc447 | 205 | }, |
548aafcd | 206 | }; |
5fd8f738 | 207 | |
bb7c276e | 208 | struct fimc_fmt *fimc_get_format(unsigned int index) |
dafb9c70 | 209 | { |
97d97422 SN |
210 | if (index >= ARRAY_SIZE(fimc_formats)) |
211 | return NULL; | |
212 | ||
213 | return &fimc_formats[index]; | |
dafb9c70 SN |
214 | } |
215 | ||
ee7160e5 SN |
216 | int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh, |
217 | int dw, int dh, int rotation) | |
5fd8f738 | 218 | { |
ee7160e5 SN |
219 | if (rotation == 90 || rotation == 270) |
220 | swap(dw, dh); | |
5fd8f738 | 221 | |
ee7160e5 SN |
222 | if (!ctx->scaler.enabled) |
223 | return (sw == dw && sh == dh) ? 0 : -EINVAL; | |
5fd8f738 | 224 | |
ee7160e5 | 225 | if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh)) |
1b09f292 HK |
226 | return -EINVAL; |
227 | ||
5fd8f738 SN |
228 | return 0; |
229 | } | |
230 | ||
231 | static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift) | |
232 | { | |
548aafcd SN |
233 | u32 sh = 6; |
234 | ||
235 | if (src >= 64 * tar) | |
5fd8f738 | 236 | return -EINVAL; |
548aafcd SN |
237 | |
238 | while (sh--) { | |
239 | u32 tmp = 1 << sh; | |
240 | if (src >= tar * tmp) { | |
241 | *shift = sh, *ratio = tmp; | |
242 | return 0; | |
243 | } | |
5fd8f738 | 244 | } |
548aafcd | 245 | *shift = 0, *ratio = 1; |
5fd8f738 SN |
246 | return 0; |
247 | } | |
248 | ||
5f3cc447 | 249 | int fimc_set_scaler_info(struct fimc_ctx *ctx) |
5fd8f738 | 250 | { |
405f230c | 251 | const struct fimc_variant *variant = ctx->fimc_dev->variant; |
30c9939d | 252 | struct device *dev = &ctx->fimc_dev->pdev->dev; |
5fd8f738 SN |
253 | struct fimc_scaler *sc = &ctx->scaler; |
254 | struct fimc_frame *s_frame = &ctx->s_frame; | |
255 | struct fimc_frame *d_frame = &ctx->d_frame; | |
256 | int tx, ty, sx, sy; | |
257 | int ret; | |
258 | ||
47654df8 SN |
259 | if (ctx->rotation == 90 || ctx->rotation == 270) { |
260 | ty = d_frame->width; | |
261 | tx = d_frame->height; | |
262 | } else { | |
263 | tx = d_frame->width; | |
264 | ty = d_frame->height; | |
265 | } | |
5fd8f738 | 266 | if (tx <= 0 || ty <= 0) { |
969e877c | 267 | dev_err(dev, "Invalid target size: %dx%d\n", tx, ty); |
5fd8f738 SN |
268 | return -EINVAL; |
269 | } | |
270 | ||
271 | sx = s_frame->width; | |
272 | sy = s_frame->height; | |
273 | if (sx <= 0 || sy <= 0) { | |
969e877c | 274 | dev_err(dev, "Invalid source size: %dx%d\n", sx, sy); |
5fd8f738 SN |
275 | return -EINVAL; |
276 | } | |
5fd8f738 SN |
277 | sc->real_width = sx; |
278 | sc->real_height = sy; | |
5fd8f738 SN |
279 | |
280 | ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor); | |
281 | if (ret) | |
282 | return ret; | |
283 | ||
284 | ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor); | |
285 | if (ret) | |
286 | return ret; | |
287 | ||
288 | sc->pre_dst_width = sx / sc->pre_hratio; | |
289 | sc->pre_dst_height = sy / sc->pre_vratio; | |
290 | ||
b241c6d6 HK |
291 | if (variant->has_mainscaler_ext) { |
292 | sc->main_hratio = (sx << 14) / (tx << sc->hfactor); | |
293 | sc->main_vratio = (sy << 14) / (ty << sc->vfactor); | |
294 | } else { | |
295 | sc->main_hratio = (sx << 8) / (tx << sc->hfactor); | |
296 | sc->main_vratio = (sy << 8) / (ty << sc->vfactor); | |
297 | ||
298 | } | |
5fd8f738 SN |
299 | |
300 | sc->scaleup_h = (tx >= sx) ? 1 : 0; | |
301 | sc->scaleup_v = (ty >= sy) ? 1 : 0; | |
302 | ||
303 | /* check to see if input and output size/format differ */ | |
304 | if (s_frame->fmt->color == d_frame->fmt->color | |
305 | && s_frame->width == d_frame->width | |
306 | && s_frame->height == d_frame->height) | |
307 | sc->copy_mode = 1; | |
308 | else | |
309 | sc->copy_mode = 0; | |
310 | ||
311 | return 0; | |
312 | } | |
313 | ||
e9e21083 | 314 | static irqreturn_t fimc_irq_handler(int irq, void *priv) |
5fd8f738 | 315 | { |
548aafcd | 316 | struct fimc_dev *fimc = priv; |
4ecbf5d1 | 317 | struct fimc_ctx *ctx; |
5fd8f738 | 318 | |
5fd8f738 SN |
319 | fimc_hw_clear_irq(fimc); |
320 | ||
e9e21083 SN |
321 | spin_lock(&fimc->slock); |
322 | ||
4ecbf5d1 | 323 | if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) { |
e9e21083 SN |
324 | if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) { |
325 | set_bit(ST_M2M_SUSPENDED, &fimc->state); | |
326 | wake_up(&fimc->irq_queue); | |
327 | goto out; | |
328 | } | |
4ecbf5d1 SN |
329 | ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev); |
330 | if (ctx != NULL) { | |
e9e21083 | 331 | spin_unlock(&fimc->slock); |
4ecbf5d1 | 332 | fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE); |
5fd8f738 | 333 | |
4ecbf5d1 SN |
334 | if (ctx->state & FIMC_CTX_SHUT) { |
335 | ctx->state &= ~FIMC_CTX_SHUT; | |
336 | wake_up(&fimc->irq_queue); | |
337 | } | |
efb13c3d | 338 | return IRQ_HANDLED; |
5fd8f738 | 339 | } |
ee7160e5 | 340 | } else if (test_bit(ST_CAPT_PEND, &fimc->state)) { |
97d97422 SN |
341 | int last_buf = test_bit(ST_CAPT_JPEG, &fimc->state) && |
342 | fimc->vid_cap.reqbufs_count == 1; | |
343 | fimc_capture_irq_handler(fimc, !last_buf); | |
5fd8f738 | 344 | } |
e9e21083 | 345 | out: |
5fd8f738 SN |
346 | spin_unlock(&fimc->slock); |
347 | return IRQ_HANDLED; | |
348 | } | |
349 | ||
ef7af59b | 350 | /* The color format (colplanes, memplanes) must be already configured. */ |
2dab38e2 | 351 | int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb, |
548aafcd | 352 | struct fimc_frame *frame, struct fimc_addr *paddr) |
5fd8f738 | 353 | { |
5fd8f738 | 354 | int ret = 0; |
548aafcd | 355 | u32 pix_size; |
5fd8f738 | 356 | |
2dab38e2 | 357 | if (vb == NULL || frame == NULL) |
5fd8f738 SN |
358 | return -EINVAL; |
359 | ||
360 | pix_size = frame->width * frame->height; | |
361 | ||
ef7af59b SN |
362 | dbg("memplanes= %d, colplanes= %d, pix_size= %d", |
363 | frame->fmt->memplanes, frame->fmt->colplanes, pix_size); | |
364 | ||
ba7fcb0c | 365 | paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0); |
5fd8f738 | 366 | |
ef7af59b SN |
367 | if (frame->fmt->memplanes == 1) { |
368 | switch (frame->fmt->colplanes) { | |
5fd8f738 SN |
369 | case 1: |
370 | paddr->cb = 0; | |
371 | paddr->cr = 0; | |
372 | break; | |
373 | case 2: | |
374 | /* decompose Y into Y/Cb */ | |
375 | paddr->cb = (u32)(paddr->y + pix_size); | |
376 | paddr->cr = 0; | |
377 | break; | |
378 | case 3: | |
379 | paddr->cb = (u32)(paddr->y + pix_size); | |
380 | /* decompose Y into Y/Cb/Cr */ | |
3d112d9a | 381 | if (FIMC_FMT_YCBCR420 == frame->fmt->color) |
5fd8f738 SN |
382 | paddr->cr = (u32)(paddr->cb |
383 | + (pix_size >> 2)); | |
384 | else /* 422 */ | |
385 | paddr->cr = (u32)(paddr->cb | |
386 | + (pix_size >> 1)); | |
387 | break; | |
388 | default: | |
389 | return -EINVAL; | |
390 | } | |
14783d25 | 391 | } else if (!frame->fmt->mdataplanes) { |
ef7af59b | 392 | if (frame->fmt->memplanes >= 2) |
ba7fcb0c | 393 | paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1); |
ef7af59b SN |
394 | |
395 | if (frame->fmt->memplanes == 3) | |
ba7fcb0c | 396 | paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2); |
5fd8f738 SN |
397 | } |
398 | ||
548aafcd SN |
399 | dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d", |
400 | paddr->y, paddr->cb, paddr->cr, ret); | |
5fd8f738 SN |
401 | |
402 | return ret; | |
403 | } | |
404 | ||
405 | /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */ | |
9e803a04 | 406 | void fimc_set_yuv_order(struct fimc_ctx *ctx) |
5fd8f738 SN |
407 | { |
408 | /* The one only mode supported in SoC. */ | |
c83a1ff0 SN |
409 | ctx->in_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; |
410 | ctx->out_order_2p = FIMC_REG_CIOCTRL_ORDER422_2P_LSB_CRCB; | |
5fd8f738 SN |
411 | |
412 | /* Set order for 1 plane input formats. */ | |
413 | switch (ctx->s_frame.fmt->color) { | |
3d112d9a | 414 | case FIMC_FMT_YCRYCB422: |
43979798 | 415 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB; |
5fd8f738 | 416 | break; |
3d112d9a | 417 | case FIMC_FMT_CBYCRY422: |
43979798 | 418 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY; |
5fd8f738 | 419 | break; |
3d112d9a | 420 | case FIMC_FMT_CRYCBY422: |
43979798 | 421 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY; |
5fd8f738 | 422 | break; |
3d112d9a | 423 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 424 | default: |
43979798 | 425 | ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR; |
5fd8f738 SN |
426 | break; |
427 | } | |
428 | dbg("ctx->in_order_1p= %d", ctx->in_order_1p); | |
429 | ||
430 | switch (ctx->d_frame.fmt->color) { | |
3d112d9a | 431 | case FIMC_FMT_YCRYCB422: |
43979798 | 432 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB; |
5fd8f738 | 433 | break; |
3d112d9a | 434 | case FIMC_FMT_CBYCRY422: |
43979798 | 435 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY; |
5fd8f738 | 436 | break; |
3d112d9a | 437 | case FIMC_FMT_CRYCBY422: |
43979798 | 438 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY; |
5fd8f738 | 439 | break; |
3d112d9a | 440 | case FIMC_FMT_YCBYCR422: |
5fd8f738 | 441 | default: |
43979798 | 442 | ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR; |
5fd8f738 SN |
443 | break; |
444 | } | |
445 | dbg("ctx->out_order_1p= %d", ctx->out_order_1p); | |
446 | } | |
447 | ||
9e803a04 | 448 | void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f) |
ddc79e0f | 449 | { |
e80cb1fa | 450 | bool pix_hoff = ctx->fimc_dev->drv_data->dma_pix_hoff; |
ef7af59b SN |
451 | u32 i, depth = 0; |
452 | ||
453 | for (i = 0; i < f->fmt->colplanes; i++) | |
454 | depth += f->fmt->depth[i]; | |
ddc79e0f SN |
455 | |
456 | f->dma_offset.y_h = f->offs_h; | |
e80cb1fa | 457 | if (!pix_hoff) |
ef7af59b | 458 | f->dma_offset.y_h *= (depth >> 3); |
ddc79e0f SN |
459 | |
460 | f->dma_offset.y_v = f->offs_v; | |
461 | ||
462 | f->dma_offset.cb_h = f->offs_h; | |
463 | f->dma_offset.cb_v = f->offs_v; | |
464 | ||
465 | f->dma_offset.cr_h = f->offs_h; | |
466 | f->dma_offset.cr_v = f->offs_v; | |
467 | ||
e80cb1fa | 468 | if (!pix_hoff) { |
ef7af59b | 469 | if (f->fmt->colplanes == 3) { |
ddc79e0f SN |
470 | f->dma_offset.cb_h >>= 1; |
471 | f->dma_offset.cr_h >>= 1; | |
472 | } | |
3d112d9a | 473 | if (f->fmt->color == FIMC_FMT_YCBCR420) { |
ddc79e0f SN |
474 | f->dma_offset.cb_v >>= 1; |
475 | f->dma_offset.cr_v >>= 1; | |
476 | } | |
477 | } | |
478 | ||
479 | dbg("in_offset: color= %d, y_h= %d, y_v= %d", | |
480 | f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v); | |
481 | } | |
482 | ||
7e566be2 | 483 | static int fimc_set_color_effect(struct fimc_ctx *ctx, enum v4l2_colorfx colorfx) |
9448ab7d SN |
484 | { |
485 | struct fimc_effect *effect = &ctx->effect; | |
486 | ||
487 | switch (colorfx) { | |
488 | case V4L2_COLORFX_NONE: | |
489 | effect->type = FIMC_REG_CIIMGEFF_FIN_BYPASS; | |
490 | break; | |
491 | case V4L2_COLORFX_BW: | |
492 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
493 | effect->pat_cb = 128; | |
494 | effect->pat_cr = 128; | |
495 | break; | |
496 | case V4L2_COLORFX_SEPIA: | |
497 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
498 | effect->pat_cb = 115; | |
499 | effect->pat_cr = 145; | |
500 | break; | |
501 | case V4L2_COLORFX_NEGATIVE: | |
502 | effect->type = FIMC_REG_CIIMGEFF_FIN_NEGATIVE; | |
503 | break; | |
504 | case V4L2_COLORFX_EMBOSS: | |
505 | effect->type = FIMC_REG_CIIMGEFF_FIN_EMBOSSING; | |
506 | break; | |
507 | case V4L2_COLORFX_ART_FREEZE: | |
508 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARTFREEZE; | |
509 | break; | |
510 | case V4L2_COLORFX_SILHOUETTE: | |
511 | effect->type = FIMC_REG_CIIMGEFF_FIN_SILHOUETTE; | |
512 | break; | |
513 | case V4L2_COLORFX_SET_CBCR: | |
514 | effect->type = FIMC_REG_CIIMGEFF_FIN_ARBITRARY; | |
515 | effect->pat_cb = ctx->ctrls.colorfx_cbcr->val >> 8; | |
516 | effect->pat_cr = ctx->ctrls.colorfx_cbcr->val & 0xff; | |
517 | break; | |
518 | default: | |
519 | return -EINVAL; | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
131b6c61 SN |
525 | /* |
526 | * V4L2 controls handling | |
527 | */ | |
528 | #define ctrl_to_ctx(__ctrl) \ | |
9448ab7d | 529 | container_of((__ctrl)->handler, struct fimc_ctx, ctrls.handler) |
131b6c61 | 530 | |
dafb9c70 | 531 | static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl) |
131b6c61 | 532 | { |
131b6c61 | 533 | struct fimc_dev *fimc = ctx->fimc_dev; |
405f230c | 534 | const struct fimc_variant *variant = fimc->variant; |
131b6c61 SN |
535 | int ret = 0; |
536 | ||
537 | if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE) | |
538 | return 0; | |
539 | ||
540 | switch (ctrl->id) { | |
541 | case V4L2_CID_HFLIP: | |
131b6c61 SN |
542 | ctx->hflip = ctrl->val; |
543 | break; | |
544 | ||
545 | case V4L2_CID_VFLIP: | |
131b6c61 SN |
546 | ctx->vflip = ctrl->val; |
547 | break; | |
548 | ||
549 | case V4L2_CID_ROTATE: | |
81619ce1 | 550 | if (fimc_capture_pending(fimc)) { |
ee7160e5 | 551 | ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width, |
131b6c61 SN |
552 | ctx->s_frame.height, ctx->d_frame.width, |
553 | ctx->d_frame.height, ctrl->val); | |
dafb9c70 SN |
554 | if (ret) |
555 | return -EINVAL; | |
131b6c61 SN |
556 | } |
557 | if ((ctrl->val == 90 || ctrl->val == 270) && | |
558 | !variant->has_out_rot) | |
559 | return -EINVAL; | |
dafb9c70 | 560 | |
131b6c61 SN |
561 | ctx->rotation = ctrl->val; |
562 | break; | |
563 | ||
dafb9c70 SN |
564 | case V4L2_CID_ALPHA_COMPONENT: |
565 | ctx->d_frame.alpha = ctrl->val; | |
566 | break; | |
9448ab7d SN |
567 | |
568 | case V4L2_CID_COLORFX: | |
569 | ret = fimc_set_color_effect(ctx, ctrl->val); | |
570 | if (ret) | |
571 | return ret; | |
572 | break; | |
131b6c61 | 573 | } |
9448ab7d | 574 | |
131b6c61 SN |
575 | ctx->state |= FIMC_PARAMS; |
576 | set_bit(ST_CAPT_APPLY_CFG, &fimc->state); | |
131b6c61 SN |
577 | return 0; |
578 | } | |
579 | ||
dafb9c70 SN |
580 | static int fimc_s_ctrl(struct v4l2_ctrl *ctrl) |
581 | { | |
582 | struct fimc_ctx *ctx = ctrl_to_ctx(ctrl); | |
583 | unsigned long flags; | |
584 | int ret; | |
585 | ||
efb13c3d | 586 | spin_lock_irqsave(&ctx->fimc_dev->slock, flags); |
dafb9c70 | 587 | ret = __fimc_s_ctrl(ctx, ctrl); |
efb13c3d | 588 | spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags); |
dafb9c70 SN |
589 | |
590 | return ret; | |
591 | } | |
592 | ||
131b6c61 SN |
593 | static const struct v4l2_ctrl_ops fimc_ctrl_ops = { |
594 | .s_ctrl = fimc_s_ctrl, | |
595 | }; | |
596 | ||
597 | int fimc_ctrls_create(struct fimc_ctx *ctx) | |
598 | { | |
dafb9c70 | 599 | unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt); |
9448ab7d SN |
600 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
601 | struct v4l2_ctrl_handler *handler = &ctrls->handler; | |
dafb9c70 | 602 | |
9448ab7d | 603 | if (ctx->ctrls.ready) |
131b6c61 | 604 | return 0; |
131b6c61 | 605 | |
9448ab7d SN |
606 | v4l2_ctrl_handler_init(handler, 6); |
607 | ||
608 | ctrls->rotate = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
53e5ab94 | 609 | V4L2_CID_ROTATE, 0, 270, 90, 0); |
9448ab7d | 610 | ctrls->hflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 611 | V4L2_CID_HFLIP, 0, 1, 1, 0); |
9448ab7d | 612 | ctrls->vflip = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
53e5ab94 | 613 | V4L2_CID_VFLIP, 0, 1, 1, 0); |
9448ab7d | 614 | |
e80cb1fa | 615 | if (ctx->fimc_dev->drv_data->alpha_color) |
9448ab7d SN |
616 | ctrls->alpha = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, |
617 | V4L2_CID_ALPHA_COMPONENT, | |
618 | 0, max_alpha, 1, 0); | |
dafb9c70 | 619 | else |
9448ab7d SN |
620 | ctrls->alpha = NULL; |
621 | ||
622 | ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, &fimc_ctrl_ops, | |
623 | V4L2_CID_COLORFX, V4L2_COLORFX_SET_CBCR, | |
624 | ~0x983f, V4L2_COLORFX_NONE); | |
625 | ||
626 | ctrls->colorfx_cbcr = v4l2_ctrl_new_std(handler, &fimc_ctrl_ops, | |
627 | V4L2_CID_COLORFX_CBCR, 0, 0xffff, 1, 0); | |
dafb9c70 | 628 | |
9448ab7d | 629 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 | 630 | |
9448ab7d | 631 | if (!handler->error) { |
4c4ed226 | 632 | v4l2_ctrl_cluster(2, &ctrls->colorfx); |
9448ab7d SN |
633 | ctrls->ready = true; |
634 | } | |
635 | ||
636 | return handler->error; | |
131b6c61 SN |
637 | } |
638 | ||
639 | void fimc_ctrls_delete(struct fimc_ctx *ctx) | |
640 | { | |
9448ab7d SN |
641 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
642 | ||
643 | if (ctrls->ready) { | |
644 | v4l2_ctrl_handler_free(&ctrls->handler); | |
645 | ctrls->ready = false; | |
646 | ctrls->alpha = NULL; | |
131b6c61 SN |
647 | } |
648 | } | |
649 | ||
650 | void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active) | |
651 | { | |
dafb9c70 | 652 | unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA; |
9448ab7d | 653 | struct fimc_ctrls *ctrls = &ctx->ctrls; |
dafb9c70 | 654 | |
9448ab7d | 655 | if (!ctrls->ready) |
131b6c61 SN |
656 | return; |
657 | ||
8183e7a7 | 658 | mutex_lock(ctrls->handler.lock); |
9448ab7d SN |
659 | v4l2_ctrl_activate(ctrls->rotate, active); |
660 | v4l2_ctrl_activate(ctrls->hflip, active); | |
661 | v4l2_ctrl_activate(ctrls->vflip, active); | |
662 | v4l2_ctrl_activate(ctrls->colorfx, active); | |
663 | if (ctrls->alpha) | |
664 | v4l2_ctrl_activate(ctrls->alpha, active && has_alpha); | |
131b6c61 SN |
665 | |
666 | if (active) { | |
9448ab7d SN |
667 | fimc_set_color_effect(ctx, ctrls->colorfx->cur.val); |
668 | ctx->rotation = ctrls->rotate->val; | |
669 | ctx->hflip = ctrls->hflip->val; | |
670 | ctx->vflip = ctrls->vflip->val; | |
131b6c61 | 671 | } else { |
9448ab7d | 672 | ctx->effect.type = FIMC_REG_CIIMGEFF_FIN_BYPASS; |
131b6c61 SN |
673 | ctx->rotation = 0; |
674 | ctx->hflip = 0; | |
675 | ctx->vflip = 0; | |
676 | } | |
8183e7a7 | 677 | mutex_unlock(ctrls->handler.lock); |
131b6c61 SN |
678 | } |
679 | ||
dafb9c70 SN |
680 | /* Update maximum value of the alpha color control */ |
681 | void fimc_alpha_ctrl_update(struct fimc_ctx *ctx) | |
682 | { | |
683 | struct fimc_dev *fimc = ctx->fimc_dev; | |
9448ab7d | 684 | struct v4l2_ctrl *ctrl = ctx->ctrls.alpha; |
dafb9c70 | 685 | |
e80cb1fa | 686 | if (ctrl == NULL || !fimc->drv_data->alpha_color) |
dafb9c70 SN |
687 | return; |
688 | ||
689 | v4l2_ctrl_lock(ctrl); | |
690 | ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt); | |
691 | ||
692 | if (ctrl->cur.val > ctrl->maximum) | |
693 | ctrl->cur.val = ctrl->maximum; | |
694 | ||
695 | v4l2_ctrl_unlock(ctrl); | |
696 | } | |
697 | ||
fa8880be | 698 | void __fimc_get_format(struct fimc_frame *frame, struct v4l2_format *f) |
5fd8f738 | 699 | { |
e578588e | 700 | struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp; |
91707b8b | 701 | int i; |
5fd8f738 | 702 | |
e578588e SN |
703 | pixm->width = frame->o_width; |
704 | pixm->height = frame->o_height; | |
705 | pixm->field = V4L2_FIELD_NONE; | |
706 | pixm->pixelformat = frame->fmt->fourcc; | |
707 | pixm->colorspace = V4L2_COLORSPACE_JPEG; | |
708 | pixm->num_planes = frame->fmt->memplanes; | |
91707b8b SN |
709 | |
710 | for (i = 0; i < pixm->num_planes; ++i) { | |
fa8880be SN |
711 | pixm->plane_fmt[i].bytesperline = frame->bytesperline[i]; |
712 | pixm->plane_fmt[i].sizeimage = frame->payload[i]; | |
91707b8b | 713 | } |
5fd8f738 SN |
714 | } |
715 | ||
4db5e27e SN |
716 | /** |
717 | * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane | |
718 | * @fmt: fimc pixel format description (input) | |
719 | * @width: requested pixel width | |
720 | * @height: requested pixel height | |
721 | * @pix: multi-plane format to adjust | |
722 | */ | |
723 | void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height, | |
724 | struct v4l2_pix_format_mplane *pix) | |
725 | { | |
726 | u32 bytesperline = 0; | |
727 | int i; | |
728 | ||
729 | pix->colorspace = V4L2_COLORSPACE_JPEG; | |
730 | pix->field = V4L2_FIELD_NONE; | |
731 | pix->num_planes = fmt->memplanes; | |
dafb9c70 | 732 | pix->pixelformat = fmt->fourcc; |
4db5e27e SN |
733 | pix->height = height; |
734 | pix->width = width; | |
735 | ||
736 | for (i = 0; i < pix->num_planes; ++i) { | |
d547ab66 SN |
737 | struct v4l2_plane_pix_format *plane_fmt = &pix->plane_fmt[i]; |
738 | u32 bpl = plane_fmt->bytesperline; | |
4db5e27e SN |
739 | |
740 | if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width)) | |
741 | bpl = pix->width; /* Planar */ | |
742 | ||
743 | if (fmt->colplanes == 1 && /* Packed */ | |
744 | (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width)) | |
745 | bpl = (pix->width * fmt->depth[0]) / 8; | |
fa8880be SN |
746 | /* |
747 | * Currently bytesperline for each plane is same, except | |
748 | * V4L2_PIX_FMT_YUV420M format. This calculation may need | |
749 | * to be changed when other multi-planar formats are added | |
750 | * to the fimc_formats[] array. | |
751 | */ | |
752 | if (i == 0) | |
4db5e27e | 753 | bytesperline = bpl; |
fa8880be SN |
754 | else if (i == 1 && fmt->memplanes == 3) |
755 | bytesperline /= 2; | |
4db5e27e | 756 | |
d547ab66 SN |
757 | plane_fmt->bytesperline = bytesperline; |
758 | plane_fmt->sizeimage = max((pix->width * pix->height * | |
759 | fmt->depth[i]) / 8, plane_fmt->sizeimage); | |
4db5e27e SN |
760 | } |
761 | } | |
762 | ||
cf52df8a SN |
763 | /** |
764 | * fimc_find_format - lookup fimc color format by fourcc or media bus format | |
765 | * @pixelformat: fourcc to match, ignored if null | |
766 | * @mbus_code: media bus code to match, ignored if null | |
767 | * @mask: the color flags to match | |
768 | * @index: offset in the fimc_formats array, ignored if negative | |
769 | */ | |
63746be5 | 770 | struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code, |
cf52df8a | 771 | unsigned int mask, int index) |
5fd8f738 | 772 | { |
cf52df8a | 773 | struct fimc_fmt *fmt, *def_fmt = NULL; |
5fd8f738 | 774 | unsigned int i; |
cf52df8a | 775 | int id = 0; |
5fd8f738 | 776 | |
63746be5 | 777 | if (index >= (int)ARRAY_SIZE(fimc_formats)) |
cf52df8a | 778 | return NULL; |
5f3cc447 SN |
779 | |
780 | for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) { | |
781 | fmt = &fimc_formats[i]; | |
cf52df8a SN |
782 | if (!(fmt->flags & mask)) |
783 | continue; | |
784 | if (pixelformat && fmt->fourcc == *pixelformat) | |
785 | return fmt; | |
786 | if (mbus_code && fmt->mbus_code == *mbus_code) | |
787 | return fmt; | |
788 | if (index == id) | |
789 | def_fmt = fmt; | |
790 | id++; | |
5f3cc447 | 791 | } |
cf52df8a | 792 | return def_fmt; |
5f3cc447 SN |
793 | } |
794 | ||
e9e21083 | 795 | static void fimc_clk_put(struct fimc_dev *fimc) |
5fd8f738 SN |
796 | { |
797 | int i; | |
6ec0163b | 798 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
b71b56b2 | 799 | if (IS_ERR(fimc->clock[i])) |
bd7d8888 SN |
800 | continue; |
801 | clk_unprepare(fimc->clock[i]); | |
802 | clk_put(fimc->clock[i]); | |
b71b56b2 | 803 | fimc->clock[i] = ERR_PTR(-EINVAL); |
5fd8f738 SN |
804 | } |
805 | } | |
806 | ||
807 | static int fimc_clk_get(struct fimc_dev *fimc) | |
808 | { | |
bd7d8888 SN |
809 | int i, ret; |
810 | ||
b71b56b2 SN |
811 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) |
812 | fimc->clock[i] = ERR_PTR(-EINVAL); | |
813 | ||
6ec0163b | 814 | for (i = 0; i < MAX_FIMC_CLOCKS; i++) { |
a25be18d | 815 | fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]); |
b71b56b2 SN |
816 | if (IS_ERR(fimc->clock[i])) { |
817 | ret = PTR_ERR(fimc->clock[i]); | |
bd7d8888 | 818 | goto err; |
b71b56b2 | 819 | } |
bd7d8888 SN |
820 | ret = clk_prepare(fimc->clock[i]); |
821 | if (ret < 0) { | |
822 | clk_put(fimc->clock[i]); | |
b71b56b2 | 823 | fimc->clock[i] = ERR_PTR(-EINVAL); |
bd7d8888 SN |
824 | goto err; |
825 | } | |
5fd8f738 | 826 | } |
e9e21083 | 827 | return 0; |
bd7d8888 SN |
828 | err: |
829 | fimc_clk_put(fimc); | |
830 | dev_err(&fimc->pdev->dev, "failed to get clock: %s\n", | |
831 | fimc_clocks[i]); | |
832 | return -ENXIO; | |
e9e21083 SN |
833 | } |
834 | ||
835 | static int fimc_m2m_suspend(struct fimc_dev *fimc) | |
836 | { | |
837 | unsigned long flags; | |
838 | int timeout; | |
839 | ||
840 | spin_lock_irqsave(&fimc->slock, flags); | |
841 | if (!fimc_m2m_pending(fimc)) { | |
842 | spin_unlock_irqrestore(&fimc->slock, flags); | |
843 | return 0; | |
844 | } | |
845 | clear_bit(ST_M2M_SUSPENDED, &fimc->state); | |
846 | set_bit(ST_M2M_SUSPENDING, &fimc->state); | |
847 | spin_unlock_irqrestore(&fimc->slock, flags); | |
848 | ||
849 | timeout = wait_event_timeout(fimc->irq_queue, | |
850 | test_bit(ST_M2M_SUSPENDED, &fimc->state), | |
851 | FIMC_SHUTDOWN_TIMEOUT); | |
852 | ||
853 | clear_bit(ST_M2M_SUSPENDING, &fimc->state); | |
854 | return timeout == 0 ? -EAGAIN : 0; | |
855 | } | |
856 | ||
857 | static int fimc_m2m_resume(struct fimc_dev *fimc) | |
858 | { | |
e34a89b3 | 859 | struct fimc_ctx *ctx; |
e9e21083 SN |
860 | unsigned long flags; |
861 | ||
862 | spin_lock_irqsave(&fimc->slock, flags); | |
863 | /* Clear for full H/W setup in first run after resume */ | |
e34a89b3 | 864 | ctx = fimc->m2m.ctx; |
e9e21083 SN |
865 | fimc->m2m.ctx = NULL; |
866 | spin_unlock_irqrestore(&fimc->slock, flags); | |
867 | ||
868 | if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state)) | |
e34a89b3 SAB |
869 | fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR); |
870 | ||
5fd8f738 SN |
871 | return 0; |
872 | } | |
873 | ||
e80cb1fa SN |
874 | static const struct of_device_id fimc_of_match[]; |
875 | ||
876 | static int fimc_parse_dt(struct fimc_dev *fimc, u32 *clk_freq) | |
877 | { | |
878 | struct device *dev = &fimc->pdev->dev; | |
879 | struct device_node *node = dev->of_node; | |
880 | const struct of_device_id *of_id; | |
881 | struct fimc_variant *v; | |
882 | struct fimc_pix_limit *lim; | |
883 | u32 args[FIMC_PIX_LIMITS_MAX]; | |
884 | int ret; | |
885 | ||
886 | if (of_property_read_bool(node, "samsung,lcd-wb")) | |
887 | return -ENODEV; | |
888 | ||
889 | v = devm_kzalloc(dev, sizeof(*v) + sizeof(*lim), GFP_KERNEL); | |
890 | if (!v) | |
891 | return -ENOMEM; | |
892 | ||
893 | of_id = of_match_node(fimc_of_match, node); | |
894 | if (!of_id) | |
895 | return -EINVAL; | |
896 | fimc->drv_data = of_id->data; | |
897 | ret = of_property_read_u32_array(node, "samsung,pix-limits", | |
898 | args, FIMC_PIX_LIMITS_MAX); | |
899 | if (ret < 0) | |
900 | return ret; | |
901 | ||
902 | lim = (struct fimc_pix_limit *)&v[1]; | |
903 | ||
904 | lim->scaler_en_w = args[0]; | |
905 | lim->scaler_dis_w = args[1]; | |
906 | lim->out_rot_en_w = args[2]; | |
907 | lim->out_rot_dis_w = args[3]; | |
908 | v->pix_limit = lim; | |
909 | ||
910 | ret = of_property_read_u32_array(node, "samsung,min-pix-sizes", | |
911 | args, 2); | |
912 | v->min_inp_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[0]; | |
913 | v->min_out_pixsize = ret ? FIMC_DEF_MIN_SIZE : args[1]; | |
914 | ret = of_property_read_u32_array(node, "samsung,min-pix-alignment", | |
915 | args, 2); | |
916 | v->min_vsize_align = ret ? FIMC_DEF_HEIGHT_ALIGN : args[0]; | |
917 | v->hor_offs_align = ret ? FIMC_DEF_HOR_OFFS_ALIGN : args[1]; | |
918 | ||
919 | ret = of_property_read_u32(node, "samsung,rotators", &args[1]); | |
920 | v->has_inp_rot = ret ? 1 : args[1] & 0x01; | |
921 | v->has_out_rot = ret ? 1 : args[1] & 0x10; | |
922 | v->has_mainscaler_ext = of_property_read_bool(node, | |
923 | "samsung,mainscaler-ext"); | |
924 | ||
925 | v->has_isp_wb = of_property_read_bool(node, "samsung,isp-wb"); | |
926 | v->has_cam_if = of_property_read_bool(node, "samsung,cam-if"); | |
927 | of_property_read_u32(node, "clock-frequency", clk_freq); | |
928 | fimc->id = of_alias_get_id(node, "fimc"); | |
929 | ||
930 | fimc->variant = v; | |
931 | return 0; | |
932 | } | |
933 | ||
5fd8f738 SN |
934 | static int fimc_probe(struct platform_device *pdev) |
935 | { | |
e80cb1fa SN |
936 | struct device *dev = &pdev->dev; |
937 | u32 lclk_freq = 0; | |
5fd8f738 SN |
938 | struct fimc_dev *fimc; |
939 | struct resource *res; | |
5fd8f738 SN |
940 | int ret = 0; |
941 | ||
e80cb1fa | 942 | fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL); |
5fd8f738 SN |
943 | if (!fimc) |
944 | return -ENOMEM; | |
945 | ||
5fd8f738 | 946 | fimc->pdev = pdev; |
e80cb1fa SN |
947 | |
948 | if (dev->of_node) { | |
949 | ret = fimc_parse_dt(fimc, &lclk_freq); | |
950 | if (ret < 0) | |
951 | return ret; | |
952 | } else { | |
953 | fimc->drv_data = fimc_get_drvdata(pdev); | |
954 | fimc->id = pdev->id; | |
955 | } | |
956 | if (!fimc->drv_data || fimc->id >= fimc->drv_data->num_entities || | |
957 | fimc->id < 0) { | |
38c602b8 SK |
958 | dev_err(dev, "Invalid driver data or device id (%d)\n", |
959 | fimc->id); | |
e80cb1fa SN |
960 | return -EINVAL; |
961 | } | |
962 | if (!dev->of_node) | |
963 | fimc->variant = fimc->drv_data->variant[fimc->id]; | |
e9e21083 | 964 | |
5f3cc447 | 965 | init_waitqueue_head(&fimc->irq_queue); |
5fd8f738 | 966 | spin_lock_init(&fimc->slock); |
5fd8f738 SN |
967 | mutex_init(&fimc->lock); |
968 | ||
b3d8b559 | 969 | fimc->sysreg = fimc_get_sysreg_regmap(dev->of_node); |
88fa8311 SN |
970 | if (IS_ERR(fimc->sysreg)) |
971 | return PTR_ERR(fimc->sysreg); | |
972 | ||
5fd8f738 | 973 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
e80cb1fa | 974 | fimc->regs = devm_ioremap_resource(dev, res); |
f23999ec TR |
975 | if (IS_ERR(fimc->regs)) |
976 | return PTR_ERR(fimc->regs); | |
5fd8f738 | 977 | |
5fd8f738 | 978 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
6d91a51a | 979 | if (res == NULL) { |
e80cb1fa | 980 | dev_err(dev, "Failed to get IRQ resource\n"); |
6d91a51a | 981 | return -ENXIO; |
5fd8f738 | 982 | } |
5fd8f738 | 983 | |
e9e21083 SN |
984 | ret = fimc_clk_get(fimc); |
985 | if (ret) | |
6d91a51a | 986 | return ret; |
b71b56b2 | 987 | |
e80cb1fa SN |
988 | if (lclk_freq == 0) |
989 | lclk_freq = fimc->drv_data->lclk_frequency; | |
990 | ||
991 | ret = clk_set_rate(fimc->clock[CLK_BUS], lclk_freq); | |
b71b56b2 SN |
992 | if (ret < 0) |
993 | return ret; | |
994 | ||
995 | ret = clk_enable(fimc->clock[CLK_BUS]); | |
996 | if (ret < 0) | |
997 | return ret; | |
e9e21083 | 998 | |
e80cb1fa SN |
999 | ret = devm_request_irq(dev, res->start, fimc_irq_handler, |
1000 | 0, dev_name(dev), fimc); | |
5fd8f738 | 1001 | if (ret) { |
e80cb1fa | 1002 | dev_err(dev, "failed to install irq (%d)\n", ret); |
5fd8f738 SN |
1003 | goto err_clk; |
1004 | } | |
1005 | ||
693f5c40 SN |
1006 | ret = fimc_initialize_capture_subdev(fimc); |
1007 | if (ret) | |
1008 | goto err_clk; | |
1009 | ||
1010 | platform_set_drvdata(pdev, fimc); | |
e80cb1fa SN |
1011 | pm_runtime_enable(dev); |
1012 | ret = pm_runtime_get_sync(dev); | |
e9e21083 | 1013 | if (ret < 0) |
693f5c40 | 1014 | goto err_sd; |
2dab38e2 | 1015 | /* Initialize contiguous memory allocator */ |
e80cb1fa | 1016 | fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev); |
2dab38e2 SN |
1017 | if (IS_ERR(fimc->alloc_ctx)) { |
1018 | ret = PTR_ERR(fimc->alloc_ctx); | |
e9e21083 | 1019 | goto err_pm; |
2dab38e2 SN |
1020 | } |
1021 | ||
e80cb1fa | 1022 | dev_dbg(dev, "FIMC.%d registered successfully\n", fimc->id); |
5fd8f738 | 1023 | |
e80cb1fa | 1024 | pm_runtime_put(dev); |
5fd8f738 | 1025 | return 0; |
e9e21083 | 1026 | err_pm: |
e80cb1fa | 1027 | pm_runtime_put(dev); |
693f5c40 SN |
1028 | err_sd: |
1029 | fimc_unregister_capture_subdev(fimc); | |
5fd8f738 | 1030 | err_clk: |
b71b56b2 | 1031 | clk_disable(fimc->clock[CLK_BUS]); |
e9e21083 | 1032 | fimc_clk_put(fimc); |
5fd8f738 SN |
1033 | return ret; |
1034 | } | |
1035 | ||
e9e21083 | 1036 | static int fimc_runtime_resume(struct device *dev) |
5fd8f738 | 1037 | { |
e9e21083 | 1038 | struct fimc_dev *fimc = dev_get_drvdata(dev); |
5fd8f738 | 1039 | |
e9e21083 SN |
1040 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); |
1041 | ||
1042 | /* Enable clocks and perform basic initalization */ | |
1043 | clk_enable(fimc->clock[CLK_GATE]); | |
5fd8f738 | 1044 | fimc_hw_reset(fimc); |
e9e21083 SN |
1045 | |
1046 | /* Resume the capture or mem-to-mem device */ | |
1047 | if (fimc_capture_busy(fimc)) | |
1048 | return fimc_capture_resume(fimc); | |
f664684a SN |
1049 | |
1050 | return fimc_m2m_resume(fimc); | |
e9e21083 SN |
1051 | } |
1052 | ||
1053 | static int fimc_runtime_suspend(struct device *dev) | |
1054 | { | |
1055 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1056 | int ret = 0; | |
1057 | ||
1058 | if (fimc_capture_busy(fimc)) | |
1059 | ret = fimc_capture_suspend(fimc); | |
1060 | else | |
1061 | ret = fimc_m2m_suspend(fimc); | |
1062 | if (!ret) | |
1063 | clk_disable(fimc->clock[CLK_GATE]); | |
1064 | ||
1065 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1066 | return ret; | |
1067 | } | |
1068 | ||
1069 | #ifdef CONFIG_PM_SLEEP | |
1070 | static int fimc_resume(struct device *dev) | |
1071 | { | |
1072 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1073 | unsigned long flags; | |
1074 | ||
1075 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1076 | ||
1077 | /* Do not resume if the device was idle before system suspend */ | |
1078 | spin_lock_irqsave(&fimc->slock, flags); | |
1079 | if (!test_and_clear_bit(ST_LPM, &fimc->state) || | |
1080 | (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) { | |
1081 | spin_unlock_irqrestore(&fimc->slock, flags); | |
1082 | return 0; | |
1083 | } | |
1084 | fimc_hw_reset(fimc); | |
e9e21083 SN |
1085 | spin_unlock_irqrestore(&fimc->slock, flags); |
1086 | ||
1087 | if (fimc_capture_busy(fimc)) | |
1088 | return fimc_capture_resume(fimc); | |
1089 | ||
1090 | return fimc_m2m_resume(fimc); | |
1091 | } | |
1092 | ||
1093 | static int fimc_suspend(struct device *dev) | |
1094 | { | |
1095 | struct fimc_dev *fimc = dev_get_drvdata(dev); | |
1096 | ||
1097 | dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state); | |
1098 | ||
1099 | if (test_and_set_bit(ST_LPM, &fimc->state)) | |
1100 | return 0; | |
1101 | if (fimc_capture_busy(fimc)) | |
1102 | return fimc_capture_suspend(fimc); | |
1103 | ||
1104 | return fimc_m2m_suspend(fimc); | |
1105 | } | |
1106 | #endif /* CONFIG_PM_SLEEP */ | |
1107 | ||
4c62e976 | 1108 | static int fimc_remove(struct platform_device *pdev) |
e9e21083 SN |
1109 | { |
1110 | struct fimc_dev *fimc = platform_get_drvdata(pdev); | |
1111 | ||
1112 | pm_runtime_disable(&pdev->dev); | |
e9e21083 | 1113 | pm_runtime_set_suspended(&pdev->dev); |
5fd8f738 | 1114 | |
693f5c40 | 1115 | fimc_unregister_capture_subdev(fimc); |
2dab38e2 SN |
1116 | vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx); |
1117 | ||
e9e21083 SN |
1118 | clk_disable(fimc->clock[CLK_BUS]); |
1119 | fimc_clk_put(fimc); | |
548aafcd | 1120 | |
e9e21083 | 1121 | dev_info(&pdev->dev, "driver unloaded\n"); |
5fd8f738 SN |
1122 | return 0; |
1123 | } | |
1124 | ||
a7d5bbcf | 1125 | /* Image pixel limits, similar across several FIMC HW revisions. */ |
405f230c | 1126 | static const struct fimc_pix_limit s5p_pix_limit[4] = { |
a7d5bbcf SN |
1127 | [0] = { |
1128 | .scaler_en_w = 3264, | |
1129 | .scaler_dis_w = 8192, | |
a7d5bbcf SN |
1130 | .out_rot_en_w = 1920, |
1131 | .out_rot_dis_w = 4224, | |
1132 | }, | |
1133 | [1] = { | |
1134 | .scaler_en_w = 4224, | |
1135 | .scaler_dis_w = 8192, | |
a7d5bbcf SN |
1136 | .out_rot_en_w = 1920, |
1137 | .out_rot_dis_w = 4224, | |
1138 | }, | |
1139 | [2] = { | |
1140 | .scaler_en_w = 1920, | |
1141 | .scaler_dis_w = 8192, | |
a7d5bbcf SN |
1142 | .out_rot_en_w = 1280, |
1143 | .out_rot_dis_w = 1920, | |
1144 | }, | |
1145 | }; | |
1146 | ||
405f230c | 1147 | static const struct fimc_variant fimc0_variant_s5p = { |
a7d5bbcf SN |
1148 | .has_inp_rot = 1, |
1149 | .has_out_rot = 1, | |
d3953223 | 1150 | .has_cam_if = 1, |
5fd8f738 SN |
1151 | .min_inp_pixsize = 16, |
1152 | .min_out_pixsize = 16, | |
a7d5bbcf | 1153 | .hor_offs_align = 8, |
9c63afcb | 1154 | .min_vsize_align = 16, |
a7d5bbcf | 1155 | .pix_limit = &s5p_pix_limit[0], |
5fd8f738 SN |
1156 | }; |
1157 | ||
405f230c | 1158 | static const struct fimc_variant fimc2_variant_s5p = { |
d3953223 | 1159 | .has_cam_if = 1, |
5fd8f738 SN |
1160 | .min_inp_pixsize = 16, |
1161 | .min_out_pixsize = 16, | |
a7d5bbcf | 1162 | .hor_offs_align = 8, |
9c63afcb | 1163 | .min_vsize_align = 16, |
bb7c276e | 1164 | .pix_limit = &s5p_pix_limit[1], |
5fd8f738 SN |
1165 | }; |
1166 | ||
405f230c | 1167 | static const struct fimc_variant fimc0_variant_s5pv210 = { |
a7d5bbcf SN |
1168 | .has_inp_rot = 1, |
1169 | .has_out_rot = 1, | |
d3953223 | 1170 | .has_cam_if = 1, |
5fd8f738 | 1171 | .min_inp_pixsize = 16, |
548aafcd | 1172 | .min_out_pixsize = 16, |
a7d5bbcf | 1173 | .hor_offs_align = 8, |
9c63afcb | 1174 | .min_vsize_align = 16, |
a7d5bbcf SN |
1175 | .pix_limit = &s5p_pix_limit[1], |
1176 | }; | |
5fd8f738 | 1177 | |
405f230c | 1178 | static const struct fimc_variant fimc1_variant_s5pv210 = { |
a7d5bbcf SN |
1179 | .has_inp_rot = 1, |
1180 | .has_out_rot = 1, | |
d3953223 | 1181 | .has_cam_if = 1, |
b241c6d6 | 1182 | .has_mainscaler_ext = 1, |
a7d5bbcf SN |
1183 | .min_inp_pixsize = 16, |
1184 | .min_out_pixsize = 16, | |
1185 | .hor_offs_align = 1, | |
9c63afcb | 1186 | .min_vsize_align = 1, |
a7d5bbcf | 1187 | .pix_limit = &s5p_pix_limit[2], |
5fd8f738 SN |
1188 | }; |
1189 | ||
405f230c | 1190 | static const struct fimc_variant fimc2_variant_s5pv210 = { |
d3953223 | 1191 | .has_cam_if = 1, |
5fd8f738 | 1192 | .min_inp_pixsize = 16, |
548aafcd | 1193 | .min_out_pixsize = 16, |
a7d5bbcf | 1194 | .hor_offs_align = 8, |
9c63afcb | 1195 | .min_vsize_align = 16, |
a7d5bbcf SN |
1196 | .pix_limit = &s5p_pix_limit[2], |
1197 | }; | |
5fd8f738 | 1198 | |
a7d5bbcf | 1199 | /* S5PC100 */ |
405f230c | 1200 | static const struct fimc_drvdata fimc_drvdata_s5p = { |
5fd8f738 | 1201 | .variant = { |
a7d5bbcf SN |
1202 | [0] = &fimc0_variant_s5p, |
1203 | [1] = &fimc0_variant_s5p, | |
5fd8f738 SN |
1204 | [2] = &fimc2_variant_s5p, |
1205 | }, | |
e80cb1fa | 1206 | .num_entities = 3, |
a7d5bbcf | 1207 | .lclk_frequency = 133000000UL, |
e80cb1fa | 1208 | .out_buf_count = 4, |
5fd8f738 SN |
1209 | }; |
1210 | ||
a7d5bbcf | 1211 | /* S5PV210, S5PC110 */ |
405f230c | 1212 | static const struct fimc_drvdata fimc_drvdata_s5pv210 = { |
5fd8f738 | 1213 | .variant = { |
a7d5bbcf SN |
1214 | [0] = &fimc0_variant_s5pv210, |
1215 | [1] = &fimc1_variant_s5pv210, | |
5fd8f738 SN |
1216 | [2] = &fimc2_variant_s5pv210, |
1217 | }, | |
e80cb1fa SN |
1218 | .num_entities = 3, |
1219 | .lclk_frequency = 166000000UL, | |
1220 | .out_buf_count = 4, | |
1221 | .dma_pix_hoff = 1, | |
a7d5bbcf SN |
1222 | }; |
1223 | ||
bb7c276e | 1224 | /* EXYNOS4210, S5PV310, S5PC210 */ |
405f230c | 1225 | static const struct fimc_drvdata fimc_drvdata_exynos4210 = { |
e80cb1fa | 1226 | .num_entities = 4, |
405f230c | 1227 | .lclk_frequency = 166000000UL, |
e80cb1fa SN |
1228 | .dma_pix_hoff = 1, |
1229 | .cistatus2 = 1, | |
1230 | .alpha_color = 1, | |
1231 | .out_buf_count = 32, | |
405f230c SN |
1232 | }; |
1233 | ||
1234 | /* EXYNOS4212, EXYNOS4412 */ | |
1235 | static const struct fimc_drvdata fimc_drvdata_exynos4x12 = { | |
e80cb1fa SN |
1236 | .num_entities = 4, |
1237 | .lclk_frequency = 166000000UL, | |
1238 | .dma_pix_hoff = 1, | |
1239 | .cistatus2 = 1, | |
1240 | .alpha_color = 1, | |
1241 | .out_buf_count = 32, | |
5fd8f738 SN |
1242 | }; |
1243 | ||
405f230c | 1244 | static const struct platform_device_id fimc_driver_ids[] = { |
5fd8f738 SN |
1245 | { |
1246 | .name = "s5p-fimc", | |
1247 | .driver_data = (unsigned long)&fimc_drvdata_s5p, | |
1248 | }, { | |
1249 | .name = "s5pv210-fimc", | |
1250 | .driver_data = (unsigned long)&fimc_drvdata_s5pv210, | |
a7d5bbcf | 1251 | }, { |
25b9875f | 1252 | .name = "exynos4-fimc", |
405f230c SN |
1253 | .driver_data = (unsigned long)&fimc_drvdata_exynos4210, |
1254 | }, { | |
1255 | .name = "exynos4x12-fimc", | |
1256 | .driver_data = (unsigned long)&fimc_drvdata_exynos4x12, | |
5fd8f738 | 1257 | }, |
e80cb1fa | 1258 | { }, |
5fd8f738 | 1259 | }; |
5fd8f738 | 1260 | |
e80cb1fa SN |
1261 | static const struct of_device_id fimc_of_match[] = { |
1262 | { | |
1263 | .compatible = "samsung,s5pv210-fimc", | |
1264 | .data = &fimc_drvdata_s5pv210, | |
1265 | }, { | |
1266 | .compatible = "samsung,exynos4210-fimc", | |
1267 | .data = &fimc_drvdata_exynos4210, | |
1268 | }, { | |
1269 | .compatible = "samsung,exynos4212-fimc", | |
1270 | .data = &fimc_drvdata_exynos4x12, | |
1271 | }, | |
1272 | { /* sentinel */ }, | |
1273 | }; | |
1274 | ||
e9e21083 SN |
1275 | static const struct dev_pm_ops fimc_pm_ops = { |
1276 | SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume) | |
1277 | SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL) | |
1278 | }; | |
1279 | ||
5fd8f738 SN |
1280 | static struct platform_driver fimc_driver = { |
1281 | .probe = fimc_probe, | |
4c62e976 | 1282 | .remove = fimc_remove, |
5fd8f738 SN |
1283 | .id_table = fimc_driver_ids, |
1284 | .driver = { | |
e80cb1fa SN |
1285 | .of_match_table = fimc_of_match, |
1286 | .name = FIMC_MODULE_NAME, | |
1287 | .owner = THIS_MODULE, | |
1288 | .pm = &fimc_pm_ops, | |
5fd8f738 SN |
1289 | } |
1290 | }; | |
1291 | ||
d3953223 | 1292 | int __init fimc_register_driver(void) |
5fd8f738 | 1293 | { |
ecd9acbf | 1294 | return platform_driver_register(&fimc_driver); |
5fd8f738 SN |
1295 | } |
1296 | ||
d3953223 | 1297 | void __exit fimc_unregister_driver(void) |
5fd8f738 SN |
1298 | { |
1299 | platform_driver_unregister(&fimc_driver); | |
1300 | } |