projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 9a761e43 SN |
1 | /* |
| 2 | * Samsung Exynos4x12 FIMC-IS (Imaging Subsystem) driver | |
| 3 | * | |
| 4 | * FIMC-IS command set definitions | |
| 5 | * | |
| 6 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
| 7 | * | |
| 8 | * Authors: Younghwan Joo <yhwan.joo@samsung.com> | |
| 9 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
| 10 | * | |
| 11 | * This program is free software; you can redistribute it and/or modify | |
| 12 | * it under the terms of the GNU General Public License version 2 as | |
| 13 | * published by the Free Software Foundation. | |
| 14 | */ | |
| 15 | ||
| 16 | #ifndef FIMC_IS_CMD_H_ | |
| 17 | #define FIMC_IS_CMD_H_ | |
| 18 | ||
| 19 | #define FIMC_IS_COMMAND_VER 110 /* FIMC-IS command set version 1.10 */ | |
| 20 | ||
| 21 | /* Enumeration of commands beetween the FIMC-IS and the host processor. */ | |
| 22 | ||
| 23 | /* HOST to FIMC-IS */ | |
| 24 | #define HIC_PREVIEW_STILL 0x0001 | |
| 25 | #define HIC_PREVIEW_VIDEO 0x0002 | |
| 26 | #define HIC_CAPTURE_STILL 0x0003 | |
| 27 | #define HIC_CAPTURE_VIDEO 0x0004 | |
| 28 | #define HIC_STREAM_ON 0x0005 | |
| 29 | #define HIC_STREAM_OFF 0x0006 | |
| 30 | #define HIC_SET_PARAMETER 0x0007 | |
| 31 | #define HIC_GET_PARAMETER 0x0008 | |
| 32 | #define HIC_SET_TUNE 0x0009 | |
| 33 | #define HIC_GET_STATUS 0x000b | |
| 34 | /* Sensor part */ | |
| 35 | #define HIC_OPEN_SENSOR 0x000c | |
| 36 | #define HIC_CLOSE_SENSOR 0x000d | |
| 37 | #define HIC_SIMMIAN_INIT 0x000e | |
| 38 | #define HIC_SIMMIAN_WRITE 0x000f | |
| 39 | #define HIC_SIMMIAN_READ 0x0010 | |
| 40 | #define HIC_POWER_DOWN 0x0011 | |
| 41 | #define HIC_GET_SET_FILE_ADDR 0x0012 | |
| 42 | #define HIC_LOAD_SET_FILE 0x0013 | |
| 43 | #define HIC_MSG_CONFIG 0x0014 | |
| 44 | #define HIC_MSG_TEST 0x0015 | |
| 45 | /* FIMC-IS to HOST */ | |
| 46 | #define IHC_GET_SENSOR_NUM 0x1000 | |
| 47 | #define IHC_SET_SHOT_MARK 0x1001 | |
| 48 | /* parameter1: frame number */ | |
| 49 | /* parameter2: confidence level (smile 0~100) */ | |
| 50 | /* parameter3: confidence level (blink 0~100) */ | |
| 51 | #define IHC_SET_FACE_MARK 0x1002 | |
| 52 | /* parameter1: coordinate count */ | |
| 53 | /* parameter2: coordinate buffer address */ | |
| 54 | #define IHC_FRAME_DONE 0x1003 | |
| 55 | /* parameter1: frame start number */ | |
| 56 | /* parameter2: frame count */ | |
| 57 | #define IHC_AA_DONE 0x1004 | |
| 58 | #define IHC_NOT_READY 0x1005 | |
| 59 | ||
| 60 | #define IH_REPLY_DONE 0x2000 | |
| 61 | #define IH_REPLY_NOT_DONE 0x2001 | |
| 62 | ||
| 63 | enum fimc_is_scenario { | |
| 64 | IS_SC_PREVIEW_STILL, | |
| 65 | IS_SC_PREVIEW_VIDEO, | |
| 66 | IS_SC_CAPTURE_STILL, | |
| 67 | IS_SC_CAPTURE_VIDEO, | |
| 68 | IS_SC_MAX | |
| 69 | }; | |
| 70 | ||
| 71 | enum fimc_is_sub_scenario { | |
| 72 | IS_SC_SUB_DEFAULT, | |
| 73 | IS_SC_SUB_PS_VTCALL, | |
| 74 | IS_SC_SUB_CS_VTCALL, | |
| 75 | IS_SC_SUB_PV_VTCALL, | |
| 76 | IS_SC_SUB_CV_VTCALL, | |
| 77 | }; | |
| 78 | ||
| 79 | struct is_common_regs { | |
| 80 | u32 hicmd; | |
| 81 | u32 hic_sensorid; | |
| 82 | u32 hic_param[4]; | |
| 83 | u32 reserved1[4]; | |
| 84 | ||
| 85 | u32 ihcmd; | |
| 86 | u32 ihc_sensorid; | |
| 87 | u32 ihc_param[4]; | |
| 88 | u32 reserved2[4]; | |
| 89 | ||
| 90 | u32 isp_sensor_id; | |
| 91 | u32 isp_param[2]; | |
| 92 | u32 reserved3[1]; | |
| 93 | ||
| 94 | u32 scc_sensor_id; | |
| 95 | u32 scc_param[2]; | |
| 96 | u32 reserved4[1]; | |
| 97 | ||
| 98 | u32 dnr_sensor_id; | |
| 99 | u32 dnr_param[2]; | |
| 100 | u32 reserved5[1]; | |
| 101 | ||
| 102 | u32 scp_sensor_id; | |
| 103 | u32 scp_param[2]; | |
| 104 | u32 reserved6[29]; | |
| 105 | } __packed; | |
| 106 | ||
| 107 | struct is_mcuctl_reg { | |
| 108 | u32 mcuctl; | |
| 109 | u32 bboar; | |
| 110 | ||
| 111 | u32 intgr0; | |
| 112 | u32 intcr0; | |
| 113 | u32 intmr0; | |
| 114 | u32 intsr0; | |
| 115 | u32 intmsr0; | |
| 116 | ||
| 117 | u32 intgr1; | |
| 118 | u32 intcr1; | |
| 119 | u32 intmr1; | |
| 120 | u32 intsr1; | |
| 121 | u32 intmsr1; | |
| 122 | ||
| 123 | u32 intcr2; | |
| 124 | u32 intmr2; | |
| 125 | u32 intsr2; | |
| 126 | u32 intmsr2; | |
| 127 | ||
| 128 | u32 gpoctrl; | |
| 129 | u32 cpoenctlr; | |
| 130 | u32 gpictlr; | |
| 131 | ||
| 132 | u32 reserved[0xd]; | |
| 133 | ||
| 134 | struct is_common_regs common; | |
| 135 | } __packed; | |
| 136 | ||
| 137 | #endif /* FIMC_IS_CMD_H_ */ |