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[media] exynos4-is: Make fimc-lite independent of struct fimc_sensor_info
[deliverable/linux.git] / drivers / media / platform / exynos4-is / fimc-is-param.c
CommitLineData
294781db
SN		 1/*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
7 * Sylwester Nawrocki <s.nawrocki@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
14
15#include <linux/bug.h>
16#include <linux/device.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/types.h>
21#include <linux/platform_device.h>
22#include <linux/slab.h>
23#include <linux/videodev2.h>
24
25#include <media/v4l2-device.h>
26#include <media/v4l2-ioctl.h>
27
28#include "fimc-is.h"
29#include "fimc-is-command.h"
30#include "fimc-is-errno.h"
31#include "fimc-is-param.h"
32#include "fimc-is-regs.h"
33#include "fimc-is-sensor.h"
34
35static void __hw_param_copy(void *dst, void *src)
36{
37 memcpy(dst, src, FIMC_IS_PARAM_MAX_SIZE);
38}
39
40void __fimc_is_hw_update_param_global_shotmode(struct fimc_is *is)
41{
42 struct param_global_shotmode *dst, *src;
43
44 dst = &is->is_p_region->parameter.global.shotmode;
45 src = &is->cfg_param[is->scenario_id].global.shotmode;
46 __hw_param_copy(dst, src);
47}
48
49void __fimc_is_hw_update_param_sensor_framerate(struct fimc_is *is)
50{
51 struct param_sensor_framerate *dst, *src;
52
53 dst = &is->is_p_region->parameter.sensor.frame_rate;
54 src = &is->cfg_param[is->scenario_id].sensor.frame_rate;
55 __hw_param_copy(dst, src);
56}
57
58int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset)
59{
60 struct is_param_region *par = &is->is_p_region->parameter;
61 struct is_config_param *cfg = &is->cfg_param[is->scenario_id];
62
63 switch (offset) {
64 case PARAM_ISP_CONTROL:
65 __hw_param_copy(&par->isp.control, &cfg->isp.control);
66 break;
67
68 case PARAM_ISP_OTF_INPUT:
69 __hw_param_copy(&par->isp.otf_input, &cfg->isp.otf_input);
70 break;
71
72 case PARAM_ISP_DMA1_INPUT:
73 __hw_param_copy(&par->isp.dma1_input, &cfg->isp.dma1_input);
74 break;
75
76 case PARAM_ISP_DMA2_INPUT:
77 __hw_param_copy(&par->isp.dma2_input, &cfg->isp.dma2_input);
78 break;
79
80 case PARAM_ISP_AA:
81 __hw_param_copy(&par->isp.aa, &cfg->isp.aa);
82 break;
83
84 case PARAM_ISP_FLASH:
85 __hw_param_copy(&par->isp.flash, &cfg->isp.flash);
86 break;
87
88 case PARAM_ISP_AWB:
89 __hw_param_copy(&par->isp.awb, &cfg->isp.awb);
90 break;
91
92 case PARAM_ISP_IMAGE_EFFECT:
93 __hw_param_copy(&par->isp.effect, &cfg->isp.effect);
94 break;
95
96 case PARAM_ISP_ISO:
97 __hw_param_copy(&par->isp.iso, &cfg->isp.iso);
98 break;
99
100 case PARAM_ISP_ADJUST:
101 __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust);
102 break;
103
104 case PARAM_ISP_METERING:
105 __hw_param_copy(&par->isp.metering, &cfg->isp.metering);
106 break;
107
108 case PARAM_ISP_AFC:
109 __hw_param_copy(&par->isp.afc, &cfg->isp.afc);
110 break;
111
112 case PARAM_ISP_OTF_OUTPUT:
113 __hw_param_copy(&par->isp.otf_output, &cfg->isp.otf_output);
114 break;
115
116 case PARAM_ISP_DMA1_OUTPUT:
117 __hw_param_copy(&par->isp.dma1_output, &cfg->isp.dma1_output);
118 break;
119
120 case PARAM_ISP_DMA2_OUTPUT:
121 __hw_param_copy(&par->isp.dma2_output, &cfg->isp.dma2_output);
122 break;
123
124 case PARAM_DRC_CONTROL:
125 __hw_param_copy(&par->drc.control, &cfg->drc.control);
126 break;
127
128 case PARAM_DRC_OTF_INPUT:
129 __hw_param_copy(&par->drc.otf_input, &cfg->drc.otf_input);
130 break;
131
132 case PARAM_DRC_DMA_INPUT:
133 __hw_param_copy(&par->drc.dma_input, &cfg->drc.dma_input);
134 break;
135
136 case PARAM_DRC_OTF_OUTPUT:
137 __hw_param_copy(&par->drc.otf_output, &cfg->drc.otf_output);
138 break;
139
140 case PARAM_FD_CONTROL:
141 __hw_param_copy(&par->fd.control, &cfg->fd.control);
142 break;
143
144 case PARAM_FD_OTF_INPUT:
145 __hw_param_copy(&par->fd.otf_input, &cfg->fd.otf_input);
146 break;
147
148 case PARAM_FD_DMA_INPUT:
149 __hw_param_copy(&par->fd.dma_input, &cfg->fd.dma_input);
150 break;
151
152 case PARAM_FD_CONFIG:
153 __hw_param_copy(&par->fd.config, &cfg->fd.config);
154 break;
155
156 default:
157 return -EINVAL;
158 }
159
160 return 0;
161}
162
163int __is_hw_update_params(struct fimc_is *is)
164{
165 unsigned long *p_index1, *p_index2;
166 int i, id, ret = 0;
167
168 id = is->scenario_id;
169 p_index1 = &is->cfg_param[id].p_region_index1;
170 p_index2 = &is->cfg_param[id].p_region_index2;
171
172 if (test_bit(PARAM_GLOBAL_SHOTMODE, p_index1))
173 __fimc_is_hw_update_param_global_shotmode(is);
174
175 if (test_bit(PARAM_SENSOR_FRAME_RATE, p_index1))
176 __fimc_is_hw_update_param_sensor_framerate(is);
177
178 for (i = PARAM_ISP_CONTROL; i < PARAM_DRC_CONTROL; i++) {
179 if (test_bit(i, p_index1))
180 ret = __fimc_is_hw_update_param(is, i);
181 }
182
183 for (i = PARAM_DRC_CONTROL; i < PARAM_SCALERC_CONTROL; i++) {
184 if (test_bit(i, p_index1))
185 ret = __fimc_is_hw_update_param(is, i);
186 }
187
188 for (i = PARAM_FD_CONTROL; i <= PARAM_FD_CONFIG; i++) {
189 if (test_bit((i - 32), p_index2))
190 ret = __fimc_is_hw_update_param(is, i);
191 }
192
193 return ret;
194}
195
196void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
197{
198 struct isp_param *isp;
199
200 isp = &is->cfg_param[is->scenario_id].isp;
201 mf->width = isp->otf_input.width;
202 mf->height = isp->otf_input.height;
203}
204
205void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
206{
207 struct isp_param *isp;
208 struct drc_param *drc;
209 struct fd_param *fd;
210 unsigned int mode;
211
212 mode = is->scenario_id;
213 isp = &is->cfg_param[mode].isp;
214 drc = &is->cfg_param[mode].drc;
215 fd = &is->cfg_param[mode].fd;
216
217 /* Update isp size info (OTF only) */
218 isp->otf_input.width = mf->width;
219 isp->otf_input.height = mf->height;
220 isp->otf_output.width = mf->width;
221 isp->otf_output.height = mf->height;
222 /* Update drc size info (OTF only) */
223 drc->otf_input.width = mf->width;
224 drc->otf_input.height = mf->height;
225 drc->otf_output.width = mf->width;
226 drc->otf_output.height = mf->height;
227 /* Update fd size info (OTF only) */
228 fd->otf_input.width = mf->width;
229 fd->otf_input.height = mf->height;
230
231 if (test_bit(PARAM_ISP_OTF_INPUT,
232 &is->cfg_param[mode].p_region_index1))
233 return;
234
235 /* Update field */
236 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
237 fimc_is_inc_param_num(is);
238 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
239 fimc_is_inc_param_num(is);
240 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
241 fimc_is_inc_param_num(is);
242 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
243 fimc_is_inc_param_num(is);
244 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
245 fimc_is_inc_param_num(is);
246}
247
248int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is)
249{
250 switch (is->sensor->drvdata->id) {
251 case FIMC_IS_SENSOR_ID_S5K6A3:
252 return 30;
253 default:
254 return 15;
255 }
256}
257
258void __is_set_sensor(struct fimc_is *is, int fps)
259{
260 struct sensor_param *sensor;
261 struct isp_param *isp;
262 unsigned long *p_index, mode;
263
264 mode = is->scenario_id;
265 p_index = &is->cfg_param[mode].p_region_index1;
266 sensor = &is->cfg_param[mode].sensor;
267 isp = &is->cfg_param[mode].isp;
268
269 if (fps == 0) {
270 sensor->frame_rate.frame_rate =
271 fimc_is_hw_get_sensor_max_framerate(is);
272 isp->otf_input.frametime_min = 0;
273 isp->otf_input.frametime_max = 66666;
274 } else {
275 sensor->frame_rate.frame_rate = fps;
276 isp->otf_input.frametime_min = 0;
277 isp->otf_input.frametime_max = (u32)1000000 / fps;
278 }
279
280 if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index)) {
281 fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE);
282 fimc_is_inc_param_num(is);
283 }
284 if (!test_bit(PARAM_ISP_OTF_INPUT, p_index)) {
285 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
286 fimc_is_inc_param_num(is);
287 }
288}
289
290void __is_set_init_isp_aa(struct fimc_is *is)
291{
292 struct isp_param *isp;
293
294 isp = &is->cfg_param[is->scenario_id].isp;
295
296 isp->aa.cmd = ISP_AA_COMMAND_START;
297 isp->aa.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
298 ISP_AA_TARGET_AWB;
299 isp->aa.mode = 0;
300 isp->aa.scene = 0;
301 isp->aa.sleep = 0;
302 isp->aa.face = 0;
303 isp->aa.touch_x = 0;
304 isp->aa.touch_y = 0;
305 isp->aa.manual_af_setting = 0;
306 isp->aa.err = ISP_AF_ERROR_NONE;
307
308 fimc_is_set_param_bit(is, PARAM_ISP_AA);
309 fimc_is_inc_param_num(is);
310}
311
312void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye)
313{
314 unsigned int mode = is->scenario_id;
315 struct is_config_param *cfg = &is->cfg_param[mode];
316 struct isp_param *isp = &cfg->isp;
317
318 isp->flash.cmd = cmd;
319 isp->flash.redeye = redeye;
320 isp->flash.err = ISP_FLASH_ERROR_NONE;
321
322 if (!test_bit(PARAM_ISP_FLASH, &cfg->p_region_index1)) {
323 fimc_is_set_param_bit(is, PARAM_ISP_FLASH);
324 fimc_is_inc_param_num(is);
325 }
326}
327
328void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val)
329{
330 unsigned int mode = is->scenario_id;
331 struct isp_param *isp;
332 unsigned long *p_index;
333
334 p_index = &is->cfg_param[mode].p_region_index1;
335 isp = &is->cfg_param[mode].isp;
336
337 isp->awb.cmd = cmd;
338 isp->awb.illumination = val;
339 isp->awb.err = ISP_AWB_ERROR_NONE;
340
341 if (!test_bit(PARAM_ISP_AWB, p_index)) {
342 fimc_is_set_param_bit(is, PARAM_ISP_AWB);
343 fimc_is_inc_param_num(is);
344 }
345}
346
347void __is_set_isp_effect(struct fimc_is *is, u32 cmd)
348{
349 unsigned int mode = is->scenario_id;
350 struct isp_param *isp;
351 unsigned long *p_index;
352
353 p_index = &is->cfg_param[mode].p_region_index1;
354 isp = &is->cfg_param[mode].isp;
355
356 isp->effect.cmd = cmd;
357 isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE;
358
359 if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index)) {
360 fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT);
361 fimc_is_inc_param_num(is);
362 }
363}
364
365void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val)
366{
367 unsigned int mode = is->scenario_id;
368 struct isp_param *isp;
369 unsigned long *p_index;
370
371 p_index = &is->cfg_param[mode].p_region_index1;
372 isp = &is->cfg_param[mode].isp;
373
374 isp->iso.cmd = cmd;
375 isp->iso.value = val;
376 isp->iso.err = ISP_ISO_ERROR_NONE;
377
378 if (!test_bit(PARAM_ISP_ISO, p_index)) {
379 fimc_is_set_param_bit(is, PARAM_ISP_ISO);
380 fimc_is_inc_param_num(is);
381 }
382}
383
384void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val)
385{
386 unsigned int mode = is->scenario_id;
387 unsigned long *p_index;
388 struct isp_param *isp;
389
390 p_index = &is->cfg_param[mode].p_region_index1;
391 isp = &is->cfg_param[mode].isp;
392
393 switch (cmd) {
394 case ISP_ADJUST_COMMAND_MANUAL_CONTRAST:
395 isp->adjust.contrast = val;
396 break;
397 case ISP_ADJUST_COMMAND_MANUAL_SATURATION:
398 isp->adjust.saturation = val;
399 break;
400 case ISP_ADJUST_COMMAND_MANUAL_SHARPNESS:
401 isp->adjust.sharpness = val;
402 break;
403 case ISP_ADJUST_COMMAND_MANUAL_EXPOSURE:
404 isp->adjust.exposure = val;
405 break;
406 case ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS:
407 isp->adjust.brightness = val;
408 break;
409 case ISP_ADJUST_COMMAND_MANUAL_HUE:
410 isp->adjust.hue = val;
411 break;
412 case ISP_ADJUST_COMMAND_AUTO:
413 isp->adjust.contrast = 0;
414 isp->adjust.saturation = 0;
415 isp->adjust.sharpness = 0;
416 isp->adjust.exposure = 0;
417 isp->adjust.brightness = 0;
418 isp->adjust.hue = 0;
419 break;
420 }
421
422 if (!test_bit(PARAM_ISP_ADJUST, p_index)) {
423 isp->adjust.cmd = cmd;
424 isp->adjust.err = ISP_ADJUST_ERROR_NONE;
425 fimc_is_set_param_bit(is, PARAM_ISP_ADJUST);
426 fimc_is_inc_param_num(is);
427 } else {
428 isp->adjust.cmd |= cmd;
429 }
430}
431
432void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val)
433{
434 struct isp_param *isp;
435 unsigned long *p_index, mode;
436
437 mode = is->scenario_id;
438 p_index = &is->cfg_param[mode].p_region_index1;
439 isp = &is->cfg_param[mode].isp;
440
441 switch (id) {
442 case IS_METERING_CONFIG_CMD:
443 isp->metering.cmd = val;
444 break;
445 case IS_METERING_CONFIG_WIN_POS_X:
446 isp->metering.win_pos_x = val;
447 break;
448 case IS_METERING_CONFIG_WIN_POS_Y:
449 isp->metering.win_pos_y = val;
450 break;
451 case IS_METERING_CONFIG_WIN_WIDTH:
452 isp->metering.win_width = val;
453 break;
454 case IS_METERING_CONFIG_WIN_HEIGHT:
455 isp->metering.win_height = val;
456 break;
457 default:
458 return;
459 }
460
461 if (!test_bit(PARAM_ISP_METERING, p_index)) {
462 isp->metering.err = ISP_METERING_ERROR_NONE;
463 fimc_is_set_param_bit(is, PARAM_ISP_METERING);
464 fimc_is_inc_param_num(is);
465 }
466}
467
468void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val)
469{
470 struct isp_param *isp;
471 unsigned long *p_index, mode;
472
473 mode = is->scenario_id;
474 p_index = &is->cfg_param[mode].p_region_index1;
475 isp = &is->cfg_param[mode].isp;
476
477 isp->afc.cmd = cmd;
478 isp->afc.manual = val;
479 isp->afc.err = ISP_AFC_ERROR_NONE;
480
481 if (!test_bit(PARAM_ISP_AFC, p_index)) {
482 fimc_is_set_param_bit(is, PARAM_ISP_AFC);
483 fimc_is_inc_param_num(is);
484 }
485}
486
487void __is_set_drc_control(struct fimc_is *is, u32 val)
488{
489 struct drc_param *drc;
490 unsigned long *p_index, mode;
491
492 mode = is->scenario_id;
493 p_index = &is->cfg_param[mode].p_region_index1;
494 drc = &is->cfg_param[mode].drc;
495
496 drc->control.bypass = val;
497
498 if (!test_bit(PARAM_DRC_CONTROL, p_index)) {
499 fimc_is_set_param_bit(is, PARAM_DRC_CONTROL);
500 fimc_is_inc_param_num(is);
501 }
502}
503
504void __is_set_fd_control(struct fimc_is *is, u32 val)
505{
506 struct fd_param *fd;
507 unsigned long *p_index, mode;
508
509 mode = is->scenario_id;
510 p_index = &is->cfg_param[mode].p_region_index2;
511 fd = &is->cfg_param[mode].fd;
512
513 fd->control.cmd = val;
514
515 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
516 fimc_is_set_param_bit(is, PARAM_FD_CONTROL);
517 fimc_is_inc_param_num(is);
518 }
519}
520
521void __is_set_fd_config_maxface(struct fimc_is *is, u32 val)
522{
523 struct fd_param *fd;
524 unsigned long *p_index, mode;
525
526 mode = is->scenario_id;
527 p_index = &is->cfg_param[mode].p_region_index2;
528 fd = &is->cfg_param[mode].fd;
529
530 fd->config.max_number = val;
531
532 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
533 fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
534 fd->config.err = ERROR_FD_NONE;
535 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
536 fimc_is_inc_param_num(is);
537 } else {
538 fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
539 }
540}
541
542void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val)
543{
544 struct fd_param *fd;
545 unsigned long *p_index, mode;
546
547 mode = is->scenario_id;
548 p_index = &is->cfg_param[mode].p_region_index2;
549 fd = &is->cfg_param[mode].fd;
550
551 fd->config.roll_angle = val;
552
553 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
554 fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE;
555 fd->config.err = ERROR_FD_NONE;
556 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
557 fimc_is_inc_param_num(is);
558 } else {
559 fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE;
560 }
561}
562
563void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val)
564{
565 struct fd_param *fd;
566 unsigned long *p_index, mode;
567
568 mode = is->scenario_id;
569 p_index = &is->cfg_param[mode].p_region_index2;
570 fd = &is->cfg_param[mode].fd;
571
572 fd->config.yaw_angle = val;
573
574 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
575 fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE;
576 fd->config.err = ERROR_FD_NONE;
577 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
578 fimc_is_inc_param_num(is);
579 } else {
580 fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE;
581 }
582}
583
584void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val)
585{
586 struct fd_param *fd;
587 unsigned long *p_index, mode;
588
589 mode = is->scenario_id;
590 p_index = &is->cfg_param[mode].p_region_index2;
591 fd = &is->cfg_param[mode].fd;
592
593 fd->config.smile_mode = val;
594
595 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
596 fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE;
597 fd->config.err = ERROR_FD_NONE;
598 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
599 fimc_is_inc_param_num(is);
600 } else {
601 fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE;
602 }
603}
604
605void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val)
606{
607 struct fd_param *fd;
608 unsigned long *p_index, mode;
609
610 mode = is->scenario_id;
611 p_index = &is->cfg_param[mode].p_region_index2;
612 fd = &is->cfg_param[mode].fd;
613
614 fd->config.blink_mode = val;
615
616 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
617 fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE;
618 fd->config.err = ERROR_FD_NONE;
619 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
620 fimc_is_inc_param_num(is);
621 } else {
622 fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE;
623 }
624}
625
626void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val)
627{
628 struct fd_param *fd;
629 unsigned long *p_index, mode;
630
631 mode = is->scenario_id;
632 p_index = &is->cfg_param[mode].p_region_index2;
633 fd = &is->cfg_param[mode].fd;
634
635 fd->config.eye_detect = val;
636
637 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
638 fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT;
639 fd->config.err = ERROR_FD_NONE;
640 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
641 fimc_is_inc_param_num(is);
642 } else {
643 fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT;
644 }
645}
646
647void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val)
648{
649 struct fd_param *fd;
650 unsigned long *p_index, mode;
651
652 mode = is->scenario_id;
653 p_index = &is->cfg_param[mode].p_region_index2;
654 fd = &is->cfg_param[mode].fd;
655
656 fd->config.mouth_detect = val;
657
658 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
659 fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT;
660 fd->config.err = ERROR_FD_NONE;
661 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
662 fimc_is_inc_param_num(is);
663 } else {
664 fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT;
665 }
666}
667
668void __is_set_fd_config_orientation(struct fimc_is *is, u32 val)
669{
670 struct fd_param *fd;
671 unsigned long *p_index, mode;
672
673 mode = is->scenario_id;
674 p_index = &is->cfg_param[mode].p_region_index2;
675 fd = &is->cfg_param[mode].fd;
676
677 fd->config.orientation = val;
678
679 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
680 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION;
681 fd->config.err = ERROR_FD_NONE;
682 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
683 fimc_is_inc_param_num(is);
684 } else {
685 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION;
686 }
687}
688
689void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val)
690{
691 struct fd_param *fd;
692 unsigned long *p_index, mode;
693
694 mode = is->scenario_id;
695 p_index = &is->cfg_param[mode].p_region_index2;
696 fd = &is->cfg_param[mode].fd;
697
698 fd->config.orientation_value = val;
699
700 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
701 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE;
702 fd->config.err = ERROR_FD_NONE;
703 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
704 fimc_is_inc_param_num(is);
705 } else {
706 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE;
707 }
708}
709
710void fimc_is_set_initial_params(struct fimc_is *is)
711{
712 struct global_param *global;
713 struct sensor_param *sensor;
714 struct isp_param *isp;
715 struct drc_param *drc;
716 struct fd_param *fd;
717 unsigned long *p_index1, *p_index2;
718 unsigned int mode;
719
720 mode = is->scenario_id;
721 global = &is->cfg_param[mode].global;
722 sensor = &is->cfg_param[mode].sensor;
723 isp = &is->cfg_param[mode].isp;
724 drc = &is->cfg_param[mode].drc;
725 fd = &is->cfg_param[mode].fd;
726 p_index1 = &is->cfg_param[mode].p_region_index1;
727 p_index2 = &is->cfg_param[mode].p_region_index2;
728
729 /* Global */
730 global->shotmode.cmd = 1;
731 fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE);
732 fimc_is_inc_param_num(is);
733
734 /* ISP */
735 isp->control.cmd = CONTROL_COMMAND_START;
736 isp->control.bypass = CONTROL_BYPASS_DISABLE;
737 isp->control.err = CONTROL_ERROR_NONE;
738 fimc_is_set_param_bit(is, PARAM_ISP_CONTROL);
739 fimc_is_inc_param_num(is);
740
741 isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
742 if (!test_bit(PARAM_ISP_OTF_INPUT, p_index1)) {
743 isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
744 isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
745 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
746 fimc_is_inc_param_num(is);
747 }
748 if (is->sensor->test_pattern)
749 isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER;
750 else
751 isp->otf_input.format = OTF_INPUT_FORMAT_BAYER;
752 isp->otf_input.bitwidth = 10;
753 isp->otf_input.order = OTF_INPUT_ORDER_BAYER_GR_BG;
754 isp->otf_input.crop_offset_x = 0;
755 isp->otf_input.crop_offset_y = 0;
756 isp->otf_input.err = OTF_INPUT_ERROR_NONE;
757
758 isp->dma1_input.cmd = DMA_INPUT_COMMAND_DISABLE;
759 isp->dma1_input.width = 0;
760 isp->dma1_input.height = 0;
761 isp->dma1_input.format = 0;
762 isp->dma1_input.bitwidth = 0;
763 isp->dma1_input.plane = 0;
764 isp->dma1_input.order = 0;
765 isp->dma1_input.buffer_number = 0;
766 isp->dma1_input.width = 0;
767 isp->dma1_input.err = DMA_INPUT_ERROR_NONE;
768 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT);
769 fimc_is_inc_param_num(is);
770
771 isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE;
772 isp->dma2_input.width = 0;
773 isp->dma2_input.height = 0;
774 isp->dma2_input.format = 0;
775 isp->dma2_input.bitwidth = 0;
776 isp->dma2_input.plane = 0;
777 isp->dma2_input.order = 0;
778 isp->dma2_input.buffer_number = 0;
779 isp->dma2_input.width = 0;
780 isp->dma2_input.err = DMA_INPUT_ERROR_NONE;
781 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT);
782 fimc_is_inc_param_num(is);
783
784 isp->aa.cmd = ISP_AA_COMMAND_START;
785 isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB;
786 fimc_is_set_param_bit(is, PARAM_ISP_AA);
787 fimc_is_inc_param_num(is);
788
789 if (!test_bit(PARAM_ISP_FLASH, p_index1))
790 __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE,
791 ISP_FLASH_REDEYE_DISABLE);
792
793 if (!test_bit(PARAM_ISP_AWB, p_index1))
794 __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
795
796 if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index1))
797 __is_set_isp_effect(is, ISP_IMAGE_EFFECT_DISABLE);
798
799 if (!test_bit(PARAM_ISP_ISO, p_index1))
800 __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
801
802 if (!test_bit(PARAM_ISP_ADJUST, p_index1)) {
803 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST, 0);
804 __is_set_isp_adjust(is,
805 ISP_ADJUST_COMMAND_MANUAL_SATURATION, 0);
806 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS, 0);
807 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE, 0);
808 __is_set_isp_adjust(is,
809 ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS, 0);
810 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE, 0);
811 }
812
813 if (!test_bit(PARAM_ISP_METERING, p_index1)) {
814 __is_set_isp_metering(is, 0, ISP_METERING_COMMAND_CENTER);
815 __is_set_isp_metering(is, 1, 0);
816 __is_set_isp_metering(is, 2, 0);
817 __is_set_isp_metering(is, 3, 0);
818 __is_set_isp_metering(is, 4, 0);
819 }
820
821 if (!test_bit(PARAM_ISP_AFC, p_index1))
822 __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
823
824 isp->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
825 if (!test_bit(PARAM_ISP_OTF_OUTPUT, p_index1)) {
826 isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
827 isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
828 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
829 fimc_is_inc_param_num(is);
830 }
831 isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
832 isp->otf_output.bitwidth = 12;
833 isp->otf_output.order = 0;
834 isp->otf_output.err = OTF_OUTPUT_ERROR_NONE;
835
836 if (!test_bit(PARAM_ISP_DMA1_OUTPUT, p_index1)) {
837 isp->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
838 isp->dma1_output.width = 0;
839 isp->dma1_output.height = 0;
840 isp->dma1_output.format = 0;
841 isp->dma1_output.bitwidth = 0;
842 isp->dma1_output.plane = 0;
843 isp->dma1_output.order = 0;
844 isp->dma1_output.buffer_number = 0;
845 isp->dma1_output.buffer_address = 0;
846 isp->dma1_output.notify_dma_done = 0;
847 isp->dma1_output.dma_out_mask = 0;
848 isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE;
849 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT);
850 fimc_is_inc_param_num(is);
851 }
852
853 if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index1)) {
854 isp->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
855 isp->dma2_output.width = 0;
856 isp->dma2_output.height = 0;
857 isp->dma2_output.format = 0;
858 isp->dma2_output.bitwidth = 0;
859 isp->dma2_output.plane = 0;
860 isp->dma2_output.order = 0;
861 isp->dma2_output.buffer_number = 0;
862 isp->dma2_output.buffer_address = 0;
863 isp->dma2_output.notify_dma_done = 0;
864 isp->dma2_output.dma_out_mask = 0;
865 isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE;
866 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT);
867 fimc_is_inc_param_num(is);
868 }
869
870 /* Sensor */
871 if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index1)) {
872 if (!mode)
873 __is_set_sensor(is, 0);
874 }
875
876 /* DRC */
877 drc->control.cmd = CONTROL_COMMAND_START;
878 __is_set_drc_control(is, CONTROL_BYPASS_ENABLE);
879
880 drc->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
881 if (!test_bit(PARAM_DRC_OTF_INPUT, p_index1)) {
882 drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
883 drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
884 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
885 fimc_is_inc_param_num(is);
886 }
887 drc->otf_input.format = OTF_INPUT_FORMAT_YUV444;
888 drc->otf_input.bitwidth = 12;
889 drc->otf_input.order = 0;
890 drc->otf_input.err = OTF_INPUT_ERROR_NONE;
891
892 drc->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
893 drc->dma_input.width = 0;
894 drc->dma_input.height = 0;
895 drc->dma_input.format = 0;
896 drc->dma_input.bitwidth = 0;
897 drc->dma_input.plane = 0;
898 drc->dma_input.order = 0;
899 drc->dma_input.buffer_number = 0;
900 drc->dma_input.width = 0;
901 drc->dma_input.err = DMA_INPUT_ERROR_NONE;
902 fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT);
903 fimc_is_inc_param_num(is);
904
905 drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
906 if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index1)) {
907 drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
908 drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
909 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
910 fimc_is_inc_param_num(is);
911 }
912 drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
913 drc->otf_output.bitwidth = 8;
914 drc->otf_output.order = 0;
915 drc->otf_output.err = OTF_OUTPUT_ERROR_NONE;
916
917 /* FD */
918 __is_set_fd_control(is, CONTROL_COMMAND_STOP);
919 fd->control.bypass = CONTROL_BYPASS_DISABLE;
920
921 fd->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
922 if (!test_bit((PARAM_FD_OTF_INPUT - 32), p_index2)) {
923 fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
924 fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
925 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
926 fimc_is_inc_param_num(is);
927 }
928 fd->otf_input.format = OTF_INPUT_FORMAT_YUV444;
929 fd->otf_input.bitwidth = 8;
930 fd->otf_input.order = 0;
931 fd->otf_input.err = OTF_INPUT_ERROR_NONE;
932
933 fd->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
934 fd->dma_input.width = 0;
935 fd->dma_input.height = 0;
936 fd->dma_input.format = 0;
937 fd->dma_input.bitwidth = 0;
938 fd->dma_input.plane = 0;
939 fd->dma_input.order = 0;
940 fd->dma_input.buffer_number = 0;
941 fd->dma_input.width = 0;
942 fd->dma_input.err = DMA_INPUT_ERROR_NONE;
943 fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT);
944 fimc_is_inc_param_num(is);
945
946 __is_set_fd_config_maxface(is, 5);
947 __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL);
948 __is_set_fd_config_yawangle(is, FD_CONFIG_YAW_ANGLE_45_90);
949 __is_set_fd_config_smilemode(is, FD_CONFIG_SMILE_MODE_DISABLE);
950 __is_set_fd_config_blinkmode(is, FD_CONFIG_BLINK_MODE_DISABLE);
951 __is_set_fd_config_eyedetect(is, FD_CONFIG_EYES_DETECT_ENABLE);
952 __is_set_fd_config_mouthdetect(is, FD_CONFIG_MOUTH_DETECT_DISABLE);
953 __is_set_fd_config_orientation(is, FD_CONFIG_ORIENTATION_DISABLE);
954 __is_set_fd_config_orientation_val(is, 0);
955}
Linux kernel - Deliverables
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