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[media] exynos4-is: Improve the ISP chain parameter count calculation
[deliverable/linux.git] / drivers / media / platform / exynos4-is / fimc-is-param.c
CommitLineData
294781db
SN		 1/*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Younghwan Joo <yhwan.joo@samsung.com>
7 * Sylwester Nawrocki <s.nawrocki@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
14
a6f5635e 15#include <linux/bitops.h>
294781db
SN		 16#include <linux/bug.h>
17#include <linux/device.h>
18#include <linux/errno.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
294781db
SN		 21#include <linux/platform_device.h>
22#include <linux/slab.h>
a6f5635e 23#include <linux/types.h>
294781db
SN		 24#include <linux/videodev2.h>
25
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28
29#include "fimc-is.h"
30#include "fimc-is-command.h"
31#include "fimc-is-errno.h"
32#include "fimc-is-param.h"
33#include "fimc-is-regs.h"
34#include "fimc-is-sensor.h"
35
36static void __hw_param_copy(void *dst, void *src)
37{
38 memcpy(dst, src, FIMC_IS_PARAM_MAX_SIZE);
39}
40
41void __fimc_is_hw_update_param_global_shotmode(struct fimc_is *is)
42{
43 struct param_global_shotmode *dst, *src;
44
45 dst = &is->is_p_region->parameter.global.shotmode;
46 src = &is->cfg_param[is->scenario_id].global.shotmode;
47 __hw_param_copy(dst, src);
48}
49
50void __fimc_is_hw_update_param_sensor_framerate(struct fimc_is *is)
51{
52 struct param_sensor_framerate *dst, *src;
53
54 dst = &is->is_p_region->parameter.sensor.frame_rate;
55 src = &is->cfg_param[is->scenario_id].sensor.frame_rate;
56 __hw_param_copy(dst, src);
57}
58
59int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset)
60{
61 struct is_param_region *par = &is->is_p_region->parameter;
62 struct is_config_param *cfg = &is->cfg_param[is->scenario_id];
63
64 switch (offset) {
65 case PARAM_ISP_CONTROL:
66 __hw_param_copy(&par->isp.control, &cfg->isp.control);
67 break;
68
69 case PARAM_ISP_OTF_INPUT:
70 __hw_param_copy(&par->isp.otf_input, &cfg->isp.otf_input);
71 break;
72
73 case PARAM_ISP_DMA1_INPUT:
74 __hw_param_copy(&par->isp.dma1_input, &cfg->isp.dma1_input);
75 break;
76
77 case PARAM_ISP_DMA2_INPUT:
78 __hw_param_copy(&par->isp.dma2_input, &cfg->isp.dma2_input);
79 break;
80
81 case PARAM_ISP_AA:
82 __hw_param_copy(&par->isp.aa, &cfg->isp.aa);
83 break;
84
85 case PARAM_ISP_FLASH:
86 __hw_param_copy(&par->isp.flash, &cfg->isp.flash);
87 break;
88
89 case PARAM_ISP_AWB:
90 __hw_param_copy(&par->isp.awb, &cfg->isp.awb);
91 break;
92
93 case PARAM_ISP_IMAGE_EFFECT:
94 __hw_param_copy(&par->isp.effect, &cfg->isp.effect);
95 break;
96
97 case PARAM_ISP_ISO:
98 __hw_param_copy(&par->isp.iso, &cfg->isp.iso);
99 break;
100
101 case PARAM_ISP_ADJUST:
102 __hw_param_copy(&par->isp.adjust, &cfg->isp.adjust);
103 break;
104
105 case PARAM_ISP_METERING:
106 __hw_param_copy(&par->isp.metering, &cfg->isp.metering);
107 break;
108
109 case PARAM_ISP_AFC:
110 __hw_param_copy(&par->isp.afc, &cfg->isp.afc);
111 break;
112
113 case PARAM_ISP_OTF_OUTPUT:
114 __hw_param_copy(&par->isp.otf_output, &cfg->isp.otf_output);
115 break;
116
117 case PARAM_ISP_DMA1_OUTPUT:
118 __hw_param_copy(&par->isp.dma1_output, &cfg->isp.dma1_output);
119 break;
120
121 case PARAM_ISP_DMA2_OUTPUT:
122 __hw_param_copy(&par->isp.dma2_output, &cfg->isp.dma2_output);
123 break;
124
125 case PARAM_DRC_CONTROL:
126 __hw_param_copy(&par->drc.control, &cfg->drc.control);
127 break;
128
129 case PARAM_DRC_OTF_INPUT:
130 __hw_param_copy(&par->drc.otf_input, &cfg->drc.otf_input);
131 break;
132
133 case PARAM_DRC_DMA_INPUT:
134 __hw_param_copy(&par->drc.dma_input, &cfg->drc.dma_input);
135 break;
136
137 case PARAM_DRC_OTF_OUTPUT:
138 __hw_param_copy(&par->drc.otf_output, &cfg->drc.otf_output);
139 break;
140
141 case PARAM_FD_CONTROL:
142 __hw_param_copy(&par->fd.control, &cfg->fd.control);
143 break;
144
145 case PARAM_FD_OTF_INPUT:
146 __hw_param_copy(&par->fd.otf_input, &cfg->fd.otf_input);
147 break;
148
149 case PARAM_FD_DMA_INPUT:
150 __hw_param_copy(&par->fd.dma_input, &cfg->fd.dma_input);
151 break;
152
153 case PARAM_FD_CONFIG:
154 __hw_param_copy(&par->fd.config, &cfg->fd.config);
155 break;
156
157 default:
158 return -EINVAL;
159 }
160
161 return 0;
162}
163
a6f5635e
SN		 164unsigned int __get_pending_param_count(struct fimc_is *is)
165{
166 struct is_config_param *config = &is->cfg_param[is->scenario_id];
167 unsigned long flags;
168 unsigned int count;
169
170 spin_lock_irqsave(&is->slock, flags);
171 count = hweight32(config->p_region_index1);
172 count += hweight32(config->p_region_index2);
173 spin_unlock_irqrestore(&is->slock, flags);
174
175 return count;
176}
177
294781db
SN		 178int __is_hw_update_params(struct fimc_is *is)
179{
180 unsigned long *p_index1, *p_index2;
181 int i, id, ret = 0;
182
183 id = is->scenario_id;
184 p_index1 = &is->cfg_param[id].p_region_index1;
185 p_index2 = &is->cfg_param[id].p_region_index2;
186
187 if (test_bit(PARAM_GLOBAL_SHOTMODE, p_index1))
188 __fimc_is_hw_update_param_global_shotmode(is);
189
190 if (test_bit(PARAM_SENSOR_FRAME_RATE, p_index1))
191 __fimc_is_hw_update_param_sensor_framerate(is);
192
193 for (i = PARAM_ISP_CONTROL; i < PARAM_DRC_CONTROL; i++) {
194 if (test_bit(i, p_index1))
195 ret = __fimc_is_hw_update_param(is, i);
196 }
197
198 for (i = PARAM_DRC_CONTROL; i < PARAM_SCALERC_CONTROL; i++) {
199 if (test_bit(i, p_index1))
200 ret = __fimc_is_hw_update_param(is, i);
201 }
202
203 for (i = PARAM_FD_CONTROL; i <= PARAM_FD_CONFIG; i++) {
204 if (test_bit((i - 32), p_index2))
205 ret = __fimc_is_hw_update_param(is, i);
206 }
207
208 return ret;
209}
210
211void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
212{
213 struct isp_param *isp;
214
215 isp = &is->cfg_param[is->scenario_id].isp;
216 mf->width = isp->otf_input.width;
217 mf->height = isp->otf_input.height;
218}
219
220void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf)
221{
222 struct isp_param *isp;
223 struct drc_param *drc;
224 struct fd_param *fd;
225 unsigned int mode;
226
227 mode = is->scenario_id;
228 isp = &is->cfg_param[mode].isp;
229 drc = &is->cfg_param[mode].drc;
230 fd = &is->cfg_param[mode].fd;
231
232 /* Update isp size info (OTF only) */
233 isp->otf_input.width = mf->width;
234 isp->otf_input.height = mf->height;
235 isp->otf_output.width = mf->width;
236 isp->otf_output.height = mf->height;
237 /* Update drc size info (OTF only) */
238 drc->otf_input.width = mf->width;
239 drc->otf_input.height = mf->height;
240 drc->otf_output.width = mf->width;
241 drc->otf_output.height = mf->height;
242 /* Update fd size info (OTF only) */
243 fd->otf_input.width = mf->width;
244 fd->otf_input.height = mf->height;
245
246 if (test_bit(PARAM_ISP_OTF_INPUT,
247 &is->cfg_param[mode].p_region_index1))
248 return;
249
250 /* Update field */
251 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
294781db 252 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
294781db 253 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
294781db 254 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
294781db 255 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
294781db
SN		 256}
257
258int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is)
259{
260 switch (is->sensor->drvdata->id) {
261 case FIMC_IS_SENSOR_ID_S5K6A3:
262 return 30;
263 default:
264 return 15;
265 }
266}
267
268void __is_set_sensor(struct fimc_is *is, int fps)
269{
270 struct sensor_param *sensor;
271 struct isp_param *isp;
272 unsigned long *p_index, mode;
273
274 mode = is->scenario_id;
275 p_index = &is->cfg_param[mode].p_region_index1;
276 sensor = &is->cfg_param[mode].sensor;
277 isp = &is->cfg_param[mode].isp;
278
279 if (fps == 0) {
280 sensor->frame_rate.frame_rate =
281 fimc_is_hw_get_sensor_max_framerate(is);
282 isp->otf_input.frametime_min = 0;
283 isp->otf_input.frametime_max = 66666;
284 } else {
285 sensor->frame_rate.frame_rate = fps;
286 isp->otf_input.frametime_min = 0;
287 isp->otf_input.frametime_max = (u32)1000000 / fps;
288 }
289
a6f5635e 290 if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index))
294781db 291 fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE);
a6f5635e
SN		 292
293 if (!test_bit(PARAM_ISP_OTF_INPUT, p_index))
294781db 294 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
294781db
SN		 295}
296
297void __is_set_init_isp_aa(struct fimc_is *is)
298{
299 struct isp_param *isp;
300
301 isp = &is->cfg_param[is->scenario_id].isp;
302
303 isp->aa.cmd = ISP_AA_COMMAND_START;
304 isp->aa.target = ISP_AA_TARGET_AF | ISP_AA_TARGET_AE |
305 ISP_AA_TARGET_AWB;
306 isp->aa.mode = 0;
307 isp->aa.scene = 0;
308 isp->aa.sleep = 0;
309 isp->aa.face = 0;
310 isp->aa.touch_x = 0;
311 isp->aa.touch_y = 0;
312 isp->aa.manual_af_setting = 0;
313 isp->aa.err = ISP_AF_ERROR_NONE;
314
315 fimc_is_set_param_bit(is, PARAM_ISP_AA);
294781db
SN		 316}
317
318void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye)
319{
320 unsigned int mode = is->scenario_id;
321 struct is_config_param *cfg = &is->cfg_param[mode];
322 struct isp_param *isp = &cfg->isp;
323
324 isp->flash.cmd = cmd;
325 isp->flash.redeye = redeye;
326 isp->flash.err = ISP_FLASH_ERROR_NONE;
327
a6f5635e 328 if (!test_bit(PARAM_ISP_FLASH, &cfg->p_region_index1))
294781db 329 fimc_is_set_param_bit(is, PARAM_ISP_FLASH);
294781db
SN		 330}
331
332void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val)
333{
334 unsigned int mode = is->scenario_id;
335 struct isp_param *isp;
336 unsigned long *p_index;
337
338 p_index = &is->cfg_param[mode].p_region_index1;
339 isp = &is->cfg_param[mode].isp;
340
341 isp->awb.cmd = cmd;
342 isp->awb.illumination = val;
343 isp->awb.err = ISP_AWB_ERROR_NONE;
344
a6f5635e 345 if (!test_bit(PARAM_ISP_AWB, p_index))
294781db 346 fimc_is_set_param_bit(is, PARAM_ISP_AWB);
294781db
SN		 347}
348
349void __is_set_isp_effect(struct fimc_is *is, u32 cmd)
350{
351 unsigned int mode = is->scenario_id;
352 struct isp_param *isp;
353 unsigned long *p_index;
354
355 p_index = &is->cfg_param[mode].p_region_index1;
356 isp = &is->cfg_param[mode].isp;
357
358 isp->effect.cmd = cmd;
359 isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE;
360
a6f5635e 361 if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index))
294781db 362 fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT);
294781db
SN		 363}
364
365void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val)
366{
367 unsigned int mode = is->scenario_id;
368 struct isp_param *isp;
369 unsigned long *p_index;
370
371 p_index = &is->cfg_param[mode].p_region_index1;
372 isp = &is->cfg_param[mode].isp;
373
374 isp->iso.cmd = cmd;
375 isp->iso.value = val;
376 isp->iso.err = ISP_ISO_ERROR_NONE;
377
a6f5635e 378 if (!test_bit(PARAM_ISP_ISO, p_index))
294781db 379 fimc_is_set_param_bit(is, PARAM_ISP_ISO);
294781db
SN		 380}
381
382void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val)
383{
384 unsigned int mode = is->scenario_id;
385 unsigned long *p_index;
386 struct isp_param *isp;
387
388 p_index = &is->cfg_param[mode].p_region_index1;
389 isp = &is->cfg_param[mode].isp;
390
391 switch (cmd) {
392 case ISP_ADJUST_COMMAND_MANUAL_CONTRAST:
393 isp->adjust.contrast = val;
394 break;
395 case ISP_ADJUST_COMMAND_MANUAL_SATURATION:
396 isp->adjust.saturation = val;
397 break;
398 case ISP_ADJUST_COMMAND_MANUAL_SHARPNESS:
399 isp->adjust.sharpness = val;
400 break;
401 case ISP_ADJUST_COMMAND_MANUAL_EXPOSURE:
402 isp->adjust.exposure = val;
403 break;
404 case ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS:
405 isp->adjust.brightness = val;
406 break;
407 case ISP_ADJUST_COMMAND_MANUAL_HUE:
408 isp->adjust.hue = val;
409 break;
410 case ISP_ADJUST_COMMAND_AUTO:
411 isp->adjust.contrast = 0;
412 isp->adjust.saturation = 0;
413 isp->adjust.sharpness = 0;
414 isp->adjust.exposure = 0;
415 isp->adjust.brightness = 0;
416 isp->adjust.hue = 0;
417 break;
418 }
419
420 if (!test_bit(PARAM_ISP_ADJUST, p_index)) {
421 isp->adjust.cmd = cmd;
422 isp->adjust.err = ISP_ADJUST_ERROR_NONE;
423 fimc_is_set_param_bit(is, PARAM_ISP_ADJUST);
294781db
SN		 424 } else {
425 isp->adjust.cmd |= cmd;
426 }
427}
428
429void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val)
430{
431 struct isp_param *isp;
432 unsigned long *p_index, mode;
433
434 mode = is->scenario_id;
435 p_index = &is->cfg_param[mode].p_region_index1;
436 isp = &is->cfg_param[mode].isp;
437
438 switch (id) {
439 case IS_METERING_CONFIG_CMD:
440 isp->metering.cmd = val;
441 break;
442 case IS_METERING_CONFIG_WIN_POS_X:
443 isp->metering.win_pos_x = val;
444 break;
445 case IS_METERING_CONFIG_WIN_POS_Y:
446 isp->metering.win_pos_y = val;
447 break;
448 case IS_METERING_CONFIG_WIN_WIDTH:
449 isp->metering.win_width = val;
450 break;
451 case IS_METERING_CONFIG_WIN_HEIGHT:
452 isp->metering.win_height = val;
453 break;
454 default:
455 return;
456 }
457
458 if (!test_bit(PARAM_ISP_METERING, p_index)) {
459 isp->metering.err = ISP_METERING_ERROR_NONE;
460 fimc_is_set_param_bit(is, PARAM_ISP_METERING);
294781db
SN		 461 }
462}
463
464void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val)
465{
466 struct isp_param *isp;
467 unsigned long *p_index, mode;
468
469 mode = is->scenario_id;
470 p_index = &is->cfg_param[mode].p_region_index1;
471 isp = &is->cfg_param[mode].isp;
472
473 isp->afc.cmd = cmd;
474 isp->afc.manual = val;
475 isp->afc.err = ISP_AFC_ERROR_NONE;
476
a6f5635e 477 if (!test_bit(PARAM_ISP_AFC, p_index))
294781db 478 fimc_is_set_param_bit(is, PARAM_ISP_AFC);
294781db
SN		 479}
480
481void __is_set_drc_control(struct fimc_is *is, u32 val)
482{
483 struct drc_param *drc;
484 unsigned long *p_index, mode;
485
486 mode = is->scenario_id;
487 p_index = &is->cfg_param[mode].p_region_index1;
488 drc = &is->cfg_param[mode].drc;
489
490 drc->control.bypass = val;
491
a6f5635e 492 if (!test_bit(PARAM_DRC_CONTROL, p_index))
294781db 493 fimc_is_set_param_bit(is, PARAM_DRC_CONTROL);
294781db
SN		 494}
495
496void __is_set_fd_control(struct fimc_is *is, u32 val)
497{
498 struct fd_param *fd;
499 unsigned long *p_index, mode;
500
501 mode = is->scenario_id;
502 p_index = &is->cfg_param[mode].p_region_index2;
503 fd = &is->cfg_param[mode].fd;
504
505 fd->control.cmd = val;
506
a6f5635e 507 if (!test_bit((PARAM_FD_CONFIG - 32), p_index))
294781db 508 fimc_is_set_param_bit(is, PARAM_FD_CONTROL);
294781db
SN		 509}
510
511void __is_set_fd_config_maxface(struct fimc_is *is, u32 val)
512{
513 struct fd_param *fd;
514 unsigned long *p_index, mode;
515
516 mode = is->scenario_id;
517 p_index = &is->cfg_param[mode].p_region_index2;
518 fd = &is->cfg_param[mode].fd;
519
520 fd->config.max_number = val;
521
522 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
523 fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
524 fd->config.err = ERROR_FD_NONE;
525 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 526 } else {
527 fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER;
528 }
529}
530
531void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val)
532{
533 struct fd_param *fd;
534 unsigned long *p_index, mode;
535
536 mode = is->scenario_id;
537 p_index = &is->cfg_param[mode].p_region_index2;
538 fd = &is->cfg_param[mode].fd;
539
540 fd->config.roll_angle = val;
541
542 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
543 fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE;
544 fd->config.err = ERROR_FD_NONE;
545 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 546 } else {
547 fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE;
548 }
549}
550
551void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val)
552{
553 struct fd_param *fd;
554 unsigned long *p_index, mode;
555
556 mode = is->scenario_id;
557 p_index = &is->cfg_param[mode].p_region_index2;
558 fd = &is->cfg_param[mode].fd;
559
560 fd->config.yaw_angle = val;
561
562 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
563 fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE;
564 fd->config.err = ERROR_FD_NONE;
565 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 566 } else {
567 fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE;
568 }
569}
570
571void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val)
572{
573 struct fd_param *fd;
574 unsigned long *p_index, mode;
575
576 mode = is->scenario_id;
577 p_index = &is->cfg_param[mode].p_region_index2;
578 fd = &is->cfg_param[mode].fd;
579
580 fd->config.smile_mode = val;
581
582 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
583 fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE;
584 fd->config.err = ERROR_FD_NONE;
585 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 586 } else {
587 fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE;
588 }
589}
590
591void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val)
592{
593 struct fd_param *fd;
594 unsigned long *p_index, mode;
595
596 mode = is->scenario_id;
597 p_index = &is->cfg_param[mode].p_region_index2;
598 fd = &is->cfg_param[mode].fd;
599
600 fd->config.blink_mode = val;
601
602 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
603 fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE;
604 fd->config.err = ERROR_FD_NONE;
605 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 606 } else {
607 fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE;
608 }
609}
610
611void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val)
612{
613 struct fd_param *fd;
614 unsigned long *p_index, mode;
615
616 mode = is->scenario_id;
617 p_index = &is->cfg_param[mode].p_region_index2;
618 fd = &is->cfg_param[mode].fd;
619
620 fd->config.eye_detect = val;
621
622 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
623 fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT;
624 fd->config.err = ERROR_FD_NONE;
625 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 626 } else {
627 fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT;
628 }
629}
630
631void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val)
632{
633 struct fd_param *fd;
634 unsigned long *p_index, mode;
635
636 mode = is->scenario_id;
637 p_index = &is->cfg_param[mode].p_region_index2;
638 fd = &is->cfg_param[mode].fd;
639
640 fd->config.mouth_detect = val;
641
642 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
643 fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT;
644 fd->config.err = ERROR_FD_NONE;
645 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 646 } else {
647 fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT;
648 }
649}
650
651void __is_set_fd_config_orientation(struct fimc_is *is, u32 val)
652{
653 struct fd_param *fd;
654 unsigned long *p_index, mode;
655
656 mode = is->scenario_id;
657 p_index = &is->cfg_param[mode].p_region_index2;
658 fd = &is->cfg_param[mode].fd;
659
660 fd->config.orientation = val;
661
662 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
663 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION;
664 fd->config.err = ERROR_FD_NONE;
665 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 666 } else {
667 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION;
668 }
669}
670
671void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val)
672{
673 struct fd_param *fd;
674 unsigned long *p_index, mode;
675
676 mode = is->scenario_id;
677 p_index = &is->cfg_param[mode].p_region_index2;
678 fd = &is->cfg_param[mode].fd;
679
680 fd->config.orientation_value = val;
681
682 if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) {
683 fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE;
684 fd->config.err = ERROR_FD_NONE;
685 fimc_is_set_param_bit(is, PARAM_FD_CONFIG);
294781db
SN		 686 } else {
687 fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE;
688 }
689}
690
691void fimc_is_set_initial_params(struct fimc_is *is)
692{
693 struct global_param *global;
694 struct sensor_param *sensor;
695 struct isp_param *isp;
696 struct drc_param *drc;
697 struct fd_param *fd;
698 unsigned long *p_index1, *p_index2;
699 unsigned int mode;
700
701 mode = is->scenario_id;
702 global = &is->cfg_param[mode].global;
703 sensor = &is->cfg_param[mode].sensor;
704 isp = &is->cfg_param[mode].isp;
705 drc = &is->cfg_param[mode].drc;
706 fd = &is->cfg_param[mode].fd;
707 p_index1 = &is->cfg_param[mode].p_region_index1;
708 p_index2 = &is->cfg_param[mode].p_region_index2;
709
710 /* Global */
711 global->shotmode.cmd = 1;
712 fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE);
294781db
SN		 713
714 /* ISP */
715 isp->control.cmd = CONTROL_COMMAND_START;
716 isp->control.bypass = CONTROL_BYPASS_DISABLE;
717 isp->control.err = CONTROL_ERROR_NONE;
718 fimc_is_set_param_bit(is, PARAM_ISP_CONTROL);
294781db
SN		 719
720 isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
721 if (!test_bit(PARAM_ISP_OTF_INPUT, p_index1)) {
722 isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
723 isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
724 fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT);
294781db
SN		 725 }
726 if (is->sensor->test_pattern)
727 isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER;
728 else
729 isp->otf_input.format = OTF_INPUT_FORMAT_BAYER;
730 isp->otf_input.bitwidth = 10;
731 isp->otf_input.order = OTF_INPUT_ORDER_BAYER_GR_BG;
732 isp->otf_input.crop_offset_x = 0;
733 isp->otf_input.crop_offset_y = 0;
734 isp->otf_input.err = OTF_INPUT_ERROR_NONE;
735
736 isp->dma1_input.cmd = DMA_INPUT_COMMAND_DISABLE;
737 isp->dma1_input.width = 0;
738 isp->dma1_input.height = 0;
739 isp->dma1_input.format = 0;
740 isp->dma1_input.bitwidth = 0;
741 isp->dma1_input.plane = 0;
742 isp->dma1_input.order = 0;
743 isp->dma1_input.buffer_number = 0;
744 isp->dma1_input.width = 0;
745 isp->dma1_input.err = DMA_INPUT_ERROR_NONE;
746 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT);
294781db
SN		 747
748 isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE;
749 isp->dma2_input.width = 0;
750 isp->dma2_input.height = 0;
751 isp->dma2_input.format = 0;
752 isp->dma2_input.bitwidth = 0;
753 isp->dma2_input.plane = 0;
754 isp->dma2_input.order = 0;
755 isp->dma2_input.buffer_number = 0;
756 isp->dma2_input.width = 0;
757 isp->dma2_input.err = DMA_INPUT_ERROR_NONE;
758 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT);
294781db
SN		 759
760 isp->aa.cmd = ISP_AA_COMMAND_START;
761 isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB;
762 fimc_is_set_param_bit(is, PARAM_ISP_AA);
294781db
SN		 763
764 if (!test_bit(PARAM_ISP_FLASH, p_index1))
765 __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE,
766 ISP_FLASH_REDEYE_DISABLE);
767
768 if (!test_bit(PARAM_ISP_AWB, p_index1))
769 __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0);
770
771 if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index1))
772 __is_set_isp_effect(is, ISP_IMAGE_EFFECT_DISABLE);
773
774 if (!test_bit(PARAM_ISP_ISO, p_index1))
775 __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0);
776
777 if (!test_bit(PARAM_ISP_ADJUST, p_index1)) {
778 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST, 0);
779 __is_set_isp_adjust(is,
780 ISP_ADJUST_COMMAND_MANUAL_SATURATION, 0);
781 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS, 0);
782 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE, 0);
783 __is_set_isp_adjust(is,
784 ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS, 0);
785 __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE, 0);
786 }
787
788 if (!test_bit(PARAM_ISP_METERING, p_index1)) {
789 __is_set_isp_metering(is, 0, ISP_METERING_COMMAND_CENTER);
790 __is_set_isp_metering(is, 1, 0);
791 __is_set_isp_metering(is, 2, 0);
792 __is_set_isp_metering(is, 3, 0);
793 __is_set_isp_metering(is, 4, 0);
794 }
795
796 if (!test_bit(PARAM_ISP_AFC, p_index1))
797 __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0);
798
799 isp->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
800 if (!test_bit(PARAM_ISP_OTF_OUTPUT, p_index1)) {
801 isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
802 isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
803 fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT);
294781db
SN		 804 }
805 isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
806 isp->otf_output.bitwidth = 12;
807 isp->otf_output.order = 0;
808 isp->otf_output.err = OTF_OUTPUT_ERROR_NONE;
809
810 if (!test_bit(PARAM_ISP_DMA1_OUTPUT, p_index1)) {
811 isp->dma1_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
812 isp->dma1_output.width = 0;
813 isp->dma1_output.height = 0;
814 isp->dma1_output.format = 0;
815 isp->dma1_output.bitwidth = 0;
816 isp->dma1_output.plane = 0;
817 isp->dma1_output.order = 0;
818 isp->dma1_output.buffer_number = 0;
819 isp->dma1_output.buffer_address = 0;
820 isp->dma1_output.notify_dma_done = 0;
821 isp->dma1_output.dma_out_mask = 0;
822 isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE;
823 fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT);
294781db
SN		 824 }
825
826 if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index1)) {
827 isp->dma2_output.cmd = DMA_OUTPUT_COMMAND_DISABLE;
828 isp->dma2_output.width = 0;
829 isp->dma2_output.height = 0;
830 isp->dma2_output.format = 0;
831 isp->dma2_output.bitwidth = 0;
832 isp->dma2_output.plane = 0;
833 isp->dma2_output.order = 0;
834 isp->dma2_output.buffer_number = 0;
835 isp->dma2_output.buffer_address = 0;
836 isp->dma2_output.notify_dma_done = 0;
837 isp->dma2_output.dma_out_mask = 0;
838 isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE;
839 fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT);
294781db
SN		 840 }
841
842 /* Sensor */
843 if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index1)) {
844 if (!mode)
845 __is_set_sensor(is, 0);
846 }
847
848 /* DRC */
849 drc->control.cmd = CONTROL_COMMAND_START;
850 __is_set_drc_control(is, CONTROL_BYPASS_ENABLE);
851
852 drc->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
853 if (!test_bit(PARAM_DRC_OTF_INPUT, p_index1)) {
854 drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
855 drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
856 fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT);
294781db
SN		 857 }
858 drc->otf_input.format = OTF_INPUT_FORMAT_YUV444;
859 drc->otf_input.bitwidth = 12;
860 drc->otf_input.order = 0;
861 drc->otf_input.err = OTF_INPUT_ERROR_NONE;
862
863 drc->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
864 drc->dma_input.width = 0;
865 drc->dma_input.height = 0;
866 drc->dma_input.format = 0;
867 drc->dma_input.bitwidth = 0;
868 drc->dma_input.plane = 0;
869 drc->dma_input.order = 0;
870 drc->dma_input.buffer_number = 0;
871 drc->dma_input.width = 0;
872 drc->dma_input.err = DMA_INPUT_ERROR_NONE;
873 fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT);
294781db
SN		 874
875 drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE;
876 if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index1)) {
877 drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH;
878 drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT;
879 fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT);
294781db
SN		 880 }
881 drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444;
882 drc->otf_output.bitwidth = 8;
883 drc->otf_output.order = 0;
884 drc->otf_output.err = OTF_OUTPUT_ERROR_NONE;
885
886 /* FD */
887 __is_set_fd_control(is, CONTROL_COMMAND_STOP);
888 fd->control.bypass = CONTROL_BYPASS_DISABLE;
889
890 fd->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE;
891 if (!test_bit((PARAM_FD_OTF_INPUT - 32), p_index2)) {
892 fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH;
893 fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT;
894 fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT);
294781db 895 }
a6f5635e 896
294781db
SN		 897 fd->otf_input.format = OTF_INPUT_FORMAT_YUV444;
898 fd->otf_input.bitwidth = 8;
899 fd->otf_input.order = 0;
900 fd->otf_input.err = OTF_INPUT_ERROR_NONE;
901
902 fd->dma_input.cmd = DMA_INPUT_COMMAND_DISABLE;
903 fd->dma_input.width = 0;
904 fd->dma_input.height = 0;
905 fd->dma_input.format = 0;
906 fd->dma_input.bitwidth = 0;
907 fd->dma_input.plane = 0;
908 fd->dma_input.order = 0;
909 fd->dma_input.buffer_number = 0;
910 fd->dma_input.width = 0;
911 fd->dma_input.err = DMA_INPUT_ERROR_NONE;
912 fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT);
294781db
SN		 913
914 __is_set_fd_config_maxface(is, 5);
915 __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL);
916 __is_set_fd_config_yawangle(is, FD_CONFIG_YAW_ANGLE_45_90);
917 __is_set_fd_config_smilemode(is, FD_CONFIG_SMILE_MODE_DISABLE);
918 __is_set_fd_config_blinkmode(is, FD_CONFIG_BLINK_MODE_DISABLE);
919 __is_set_fd_config_eyedetect(is, FD_CONFIG_EYES_DETECT_ENABLE);
920 __is_set_fd_config_mouthdetect(is, FD_CONFIG_MOUTH_DETECT_DISABLE);
921 __is_set_fd_config_orientation(is, FD_CONFIG_ORIENTATION_DISABLE);
922 __is_set_fd_config_orientation_val(is, 0);
923}
Linux kernel - Deliverables
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