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9a761e43 SN |
1 | /* |
2 | * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver | |
3 | * | |
4 | * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd. | |
5 | * | |
6 | * Authors: Younghwan Joo <yhwan.joo@samsung.com> | |
7 | * Sylwester Nawrocki <s.nawrocki@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #include <linux/delay.h> | |
14 | ||
15 | #include "fimc-is.h" | |
16 | #include "fimc-is-command.h" | |
17 | #include "fimc-is-regs.h" | |
18 | #include "fimc-is-sensor.h" | |
19 | ||
20 | void fimc_is_fw_clear_irq1(struct fimc_is *is, unsigned int nr) | |
21 | { | |
22 | mcuctl_write(1UL << nr, is, MCUCTL_REG_INTCR1); | |
23 | } | |
24 | ||
25 | void fimc_is_fw_clear_irq2(struct fimc_is *is) | |
26 | { | |
27 | u32 cfg = mcuctl_read(is, MCUCTL_REG_INTSR2); | |
28 | mcuctl_write(cfg, is, MCUCTL_REG_INTCR2); | |
29 | } | |
30 | ||
31 | void fimc_is_hw_set_intgr0_gd0(struct fimc_is *is) | |
32 | { | |
33 | mcuctl_write(INTGR0_INTGD(0), is, MCUCTL_REG_INTGR0); | |
34 | } | |
35 | ||
9a761e43 SN |
36 | int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is) |
37 | { | |
38 | unsigned int timeout = 2000; | |
39 | u32 cfg, status; | |
40 | ||
3f823e09 | 41 | do { |
9a761e43 SN |
42 | cfg = mcuctl_read(is, MCUCTL_REG_INTMSR0); |
43 | status = INTMSR0_GET_INTMSD(0, cfg); | |
3f823e09 SN |
44 | |
45 | if (--timeout == 0) { | |
9a761e43 SN |
46 | dev_warn(&is->pdev->dev, "%s timeout\n", |
47 | __func__); | |
3f823e09 | 48 | return -ETIMEDOUT; |
9a761e43 | 49 | } |
9a761e43 | 50 | udelay(1); |
3f823e09 SN |
51 | } while (status != 0); |
52 | ||
9a761e43 SN |
53 | return 0; |
54 | } | |
55 | ||
56 | int fimc_is_hw_set_param(struct fimc_is *is) | |
57 | { | |
3530ef0a | 58 | struct chain_config *config = &is->config[is->config_index]; |
a6f5635e | 59 | unsigned int param_count = __get_pending_param_count(is); |
9a761e43 SN |
60 | |
61 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
62 | ||
63 | mcuctl_write(HIC_SET_PARAMETER, is, MCUCTL_REG_ISSR(0)); | |
64 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
3530ef0a | 65 | mcuctl_write(is->config_index, is, MCUCTL_REG_ISSR(2)); |
9a761e43 | 66 | |
a6f5635e | 67 | mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3)); |
0e761b21 PC |
68 | mcuctl_write(config->p_region_index[0], is, MCUCTL_REG_ISSR(4)); |
69 | mcuctl_write(config->p_region_index[1], is, MCUCTL_REG_ISSR(5)); | |
9a761e43 SN |
70 | |
71 | fimc_is_hw_set_intgr0_gd0(is); | |
72 | return 0; | |
73 | } | |
74 | ||
3263f741 | 75 | static int __maybe_unused fimc_is_hw_set_tune(struct fimc_is *is) |
9a761e43 SN |
76 | { |
77 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
78 | ||
79 | mcuctl_write(HIC_SET_TUNE, is, MCUCTL_REG_ISSR(0)); | |
80 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
81 | mcuctl_write(is->h2i_cmd.entry_id, is, MCUCTL_REG_ISSR(2)); | |
82 | ||
83 | fimc_is_hw_set_intgr0_gd0(is); | |
84 | return 0; | |
85 | } | |
86 | ||
87 | #define FIMC_IS_MAX_PARAMS 4 | |
88 | ||
89 | int fimc_is_hw_get_params(struct fimc_is *is, unsigned int num_args) | |
90 | { | |
91 | int i; | |
92 | ||
93 | if (num_args > FIMC_IS_MAX_PARAMS) | |
94 | return -EINVAL; | |
95 | ||
96 | is->i2h_cmd.num_args = num_args; | |
97 | ||
98 | for (i = 0; i < FIMC_IS_MAX_PARAMS; i++) { | |
99 | if (i < num_args) | |
100 | is->i2h_cmd.args[i] = mcuctl_read(is, | |
101 | MCUCTL_REG_ISSR(12 + i)); | |
102 | else | |
103 | is->i2h_cmd.args[i] = 0; | |
104 | } | |
105 | return 0; | |
106 | } | |
107 | ||
108 | void fimc_is_hw_set_sensor_num(struct fimc_is *is) | |
109 | { | |
110 | pr_debug("setting sensor index to: %d\n", is->sensor_index); | |
111 | ||
112 | mcuctl_write(IH_REPLY_DONE, is, MCUCTL_REG_ISSR(0)); | |
113 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
114 | mcuctl_write(IHC_GET_SENSOR_NUM, is, MCUCTL_REG_ISSR(2)); | |
d265d9ac | 115 | mcuctl_write(FIMC_IS_SENSORS_NUM, is, MCUCTL_REG_ISSR(3)); |
9a761e43 SN |
116 | } |
117 | ||
118 | void fimc_is_hw_close_sensor(struct fimc_is *is, unsigned int index) | |
119 | { | |
120 | if (is->sensor_index != index) | |
121 | return; | |
122 | ||
123 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
124 | mcuctl_write(HIC_CLOSE_SENSOR, is, MCUCTL_REG_ISSR(0)); | |
125 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
126 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(2)); | |
127 | fimc_is_hw_set_intgr0_gd0(is); | |
128 | } | |
129 | ||
130 | void fimc_is_hw_get_setfile_addr(struct fimc_is *is) | |
131 | { | |
132 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
133 | mcuctl_write(HIC_GET_SET_FILE_ADDR, is, MCUCTL_REG_ISSR(0)); | |
134 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
135 | fimc_is_hw_set_intgr0_gd0(is); | |
136 | } | |
137 | ||
138 | void fimc_is_hw_load_setfile(struct fimc_is *is) | |
139 | { | |
140 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
141 | mcuctl_write(HIC_LOAD_SET_FILE, is, MCUCTL_REG_ISSR(0)); | |
142 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
143 | fimc_is_hw_set_intgr0_gd0(is); | |
144 | } | |
145 | ||
146 | int fimc_is_hw_change_mode(struct fimc_is *is) | |
147 | { | |
148 | const u8 cmd[] = { | |
149 | HIC_PREVIEW_STILL, HIC_PREVIEW_VIDEO, | |
150 | HIC_CAPTURE_STILL, HIC_CAPTURE_VIDEO, | |
151 | }; | |
152 | ||
7accedd2 | 153 | if (WARN_ON(is->config_index >= ARRAY_SIZE(cmd))) |
9a761e43 SN |
154 | return -EINVAL; |
155 | ||
3530ef0a | 156 | mcuctl_write(cmd[is->config_index], is, MCUCTL_REG_ISSR(0)); |
9a761e43 SN |
157 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
158 | mcuctl_write(is->setfile.sub_index, is, MCUCTL_REG_ISSR(2)); | |
159 | fimc_is_hw_set_intgr0_gd0(is); | |
160 | return 0; | |
161 | } | |
162 | ||
163 | void fimc_is_hw_stream_on(struct fimc_is *is) | |
164 | { | |
165 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
166 | mcuctl_write(HIC_STREAM_ON, is, MCUCTL_REG_ISSR(0)); | |
167 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
168 | mcuctl_write(0, is, MCUCTL_REG_ISSR(2)); | |
169 | fimc_is_hw_set_intgr0_gd0(is); | |
170 | } | |
171 | ||
172 | void fimc_is_hw_stream_off(struct fimc_is *is) | |
173 | { | |
174 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
175 | mcuctl_write(HIC_STREAM_OFF, is, MCUCTL_REG_ISSR(0)); | |
176 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
177 | fimc_is_hw_set_intgr0_gd0(is); | |
178 | } | |
179 | ||
180 | void fimc_is_hw_subip_power_off(struct fimc_is *is) | |
181 | { | |
182 | fimc_is_hw_wait_intmsr0_intmsd0(is); | |
183 | mcuctl_write(HIC_POWER_DOWN, is, MCUCTL_REG_ISSR(0)); | |
184 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | |
185 | fimc_is_hw_set_intgr0_gd0(is); | |
186 | } | |
187 | ||
188 | int fimc_is_itf_s_param(struct fimc_is *is, bool update) | |
189 | { | |
190 | int ret; | |
191 | ||
192 | if (update) | |
193 | __is_hw_update_params(is); | |
194 | ||
195 | fimc_is_mem_barrier(); | |
196 | ||
197 | clear_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); | |
198 | fimc_is_hw_set_param(is); | |
199 | ret = fimc_is_wait_event(is, IS_ST_BLOCK_CMD_CLEARED, 1, | |
200 | FIMC_IS_CONFIG_TIMEOUT); | |
201 | if (ret < 0) | |
202 | dev_err(&is->pdev->dev, "%s() timeout\n", __func__); | |
203 | ||
204 | return ret; | |
205 | } | |
206 | ||
207 | int fimc_is_itf_mode_change(struct fimc_is *is) | |
208 | { | |
209 | int ret; | |
210 | ||
211 | clear_bit(IS_ST_CHANGE_MODE, &is->state); | |
212 | fimc_is_hw_change_mode(is); | |
213 | ret = fimc_is_wait_event(is, IS_ST_CHANGE_MODE, 1, | |
214 | FIMC_IS_CONFIG_TIMEOUT); | |
915b034f | 215 | if (ret < 0) |
9a761e43 | 216 | dev_err(&is->pdev->dev, "%s(): mode change (%d) timeout\n", |
3530ef0a | 217 | __func__, is->config_index); |
9a761e43 SN |
218 | return ret; |
219 | } |