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Merge remote-tracking branch 'drm-tegra/drm/tegra/for-next'
[deliverable/linux.git] / drivers / media / platform / exynos4-is / fimc-is.c
CommitLineData
9a761e43
SN		 1/*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * Younghwan Joo <yhwan.joo@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
14
15#include <linux/device.h>
16#include <linux/debugfs.h>
17#include <linux/delay.h>
18#include <linux/dma-contiguous.h>
19#include <linux/errno.h>
20#include <linux/firmware.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
687b81d0 24#include <linux/i2c.h>
9a761e43
SN		 25#include <linux/of_irq.h>
26#include <linux/of_address.h>
fd9fdb78 27#include <linux/of_graph.h>
9a761e43
SN		 28#include <linux/of_platform.h>
29#include <linux/platform_device.h>
30#include <linux/pm_runtime.h>
31#include <linux/slab.h>
32#include <linux/types.h>
33#include <linux/videodev2.h>
9a761e43
SN		 34#include <media/videobuf2-dma-contig.h>
35
36#include "media-dev.h"
37#include "fimc-is.h"
38#include "fimc-is-command.h"
39#include "fimc-is-errno.h"
40#include "fimc-is-i2c.h"
41#include "fimc-is-param.h"
42#include "fimc-is-regs.h"
43
44
45static char *fimc_is_clocks[ISS_CLKS_MAX] = {
46 [ISS_CLK_PPMUISPX] = "ppmuispx",
47 [ISS_CLK_PPMUISPMX] = "ppmuispmx",
48 [ISS_CLK_LITE0] = "lite0",
49 [ISS_CLK_LITE1] = "lite1",
50 [ISS_CLK_MPLL] = "mpll",
9a761e43
SN		 51 [ISS_CLK_ISP] = "isp",
52 [ISS_CLK_DRC] = "drc",
53 [ISS_CLK_FD] = "fd",
54 [ISS_CLK_MCUISP] = "mcuisp",
55 [ISS_CLK_UART] = "uart",
56 [ISS_CLK_ISP_DIV0] = "ispdiv0",
57 [ISS_CLK_ISP_DIV1] = "ispdiv1",
58 [ISS_CLK_MCUISP_DIV0] = "mcuispdiv0",
59 [ISS_CLK_MCUISP_DIV1] = "mcuispdiv1",
60 [ISS_CLK_ACLK200] = "aclk200",
61 [ISS_CLK_ACLK200_DIV] = "div_aclk200",
62 [ISS_CLK_ACLK400MCUISP] = "aclk400mcuisp",
63 [ISS_CLK_ACLK400MCUISP_DIV] = "div_aclk400mcuisp",
64};
65
66static void fimc_is_put_clocks(struct fimc_is *is)
67{
68 int i;
69
70 for (i = 0; i < ISS_CLKS_MAX; i++) {
71 if (IS_ERR(is->clocks[i]))
72 continue;
9a761e43
SN		 73 clk_put(is->clocks[i]);
74 is->clocks[i] = ERR_PTR(-EINVAL);
75 }
76}
77
78static int fimc_is_get_clocks(struct fimc_is *is)
79{
80 int i, ret;
81
82 for (i = 0; i < ISS_CLKS_MAX; i++)
83 is->clocks[i] = ERR_PTR(-EINVAL);
84
85 for (i = 0; i < ISS_CLKS_MAX; i++) {
86 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
87 if (IS_ERR(is->clocks[i])) {
88 ret = PTR_ERR(is->clocks[i]);
89 goto err;
90 }
9a761e43
SN		 91 }
92
93 return 0;
94err:
95 fimc_is_put_clocks(is);
96 dev_err(&is->pdev->dev, "failed to get clock: %s\n",
97 fimc_is_clocks[i]);
b4155d7d 98 return ret;
9a761e43
SN		 99}
100
101static int fimc_is_setup_clocks(struct fimc_is *is)
102{
103 int ret;
104
105 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
106 is->clocks[ISS_CLK_ACLK200_DIV]);
107 if (ret < 0)
108 return ret;
109
110 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
111 is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
112 if (ret < 0)
113 return ret;
114
115 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
116 if (ret < 0)
117 return ret;
118
119 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
120 if (ret < 0)
121 return ret;
122
123 ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
124 ATCLK_MCUISP_FREQUENCY);
125 if (ret < 0)
126 return ret;
127
128 return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
129 ATCLK_MCUISP_FREQUENCY);
130}
131
e0e9f67a 132static int fimc_is_enable_clocks(struct fimc_is *is)
9a761e43
SN		 133{
134 int i, ret;
135
136 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
137 if (IS_ERR(is->clocks[i]))
138 continue;
b4155d7d 139 ret = clk_prepare_enable(is->clocks[i]);
9a761e43
SN		 140 if (ret < 0) {
141 dev_err(&is->pdev->dev, "clock %s enable failed\n",
142 fimc_is_clocks[i]);
143 for (--i; i >= 0; i--)
144 clk_disable(is->clocks[i]);
145 return ret;
146 }
147 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
148 }
149 return 0;
150}
151
e0e9f67a 152static void fimc_is_disable_clocks(struct fimc_is *is)
9a761e43
SN		 153{
154 int i;
155
156 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
157 if (!IS_ERR(is->clocks[i])) {
b4155d7d 158 clk_disable_unprepare(is->clocks[i]);
9a761e43
SN		 159 pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
160 }
161 }
162}
163
d265d9ac
SN		 164static int fimc_is_parse_sensor_config(struct fimc_is *is, unsigned int index,
165 struct device_node *node)
9a761e43 166{
d265d9ac 167 struct fimc_is_sensor *sensor = &is->sensor[index];
4f355cb5 168 struct device_node *ep, *port;
9a761e43
SN		 169 u32 tmp = 0;
170 int ret;
171
d265d9ac
SN		 172 sensor->drvdata = fimc_is_sensor_get_drvdata(node);
173 if (!sensor->drvdata) {
174 dev_err(&is->pdev->dev, "no driver data found for: %s\n",
175 node->full_name);
176 return -EINVAL;
177 }
178
4f355cb5
JMC		 179 ep = of_graph_get_next_endpoint(node, NULL);
180 if (!ep)
9a761e43 181 return -ENXIO;
d265d9ac 182
4f355cb5
JMC		 183 port = of_graph_get_remote_port(ep);
184 of_node_put(ep);
185 if (!port)
9a761e43
SN		 186 return -ENXIO;
187
188 /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
4f355cb5 189 ret = of_property_read_u32(port, "reg", &tmp);
d265d9ac
SN		 190 if (ret < 0) {
191 dev_err(&is->pdev->dev, "reg property not found at: %s\n",
4f355cb5
JMC		 192 port->full_name);
193 of_node_put(port);
d265d9ac
SN		 194 return ret;
195 }
9a761e43 196
4f355cb5 197 of_node_put(port);
d265d9ac
SN		 198 sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
199 return 0;
9a761e43
SN		 200}
201
202static int fimc_is_register_subdevs(struct fimc_is *is)
203{
d265d9ac
SN		 204 struct device_node *i2c_bus, *child;
205 int ret, index = 0;
9a761e43
SN		 206
207 ret = fimc_isp_subdev_create(&is->isp);
208 if (ret < 0)
209 return ret;
210
d265d9ac
SN		 211 for_each_compatible_node(i2c_bus, NULL, FIMC_IS_I2C_COMPATIBLE) {
212 for_each_available_child_of_node(i2c_bus, child) {
213 ret = fimc_is_parse_sensor_config(is, index, child);
9a761e43 214
d265d9ac
SN		 215 if (ret < 0 || index >= FIMC_IS_SENSORS_NUM) {
216 of_node_put(child);
217 return ret;
9a761e43 218 }
d265d9ac 219 index++;
9a761e43
SN		 220 }
221 }
222 return 0;
9a761e43
SN		 223}
224
225static int fimc_is_unregister_subdevs(struct fimc_is *is)
226{
227 fimc_isp_subdev_destroy(&is->isp);
9a761e43
SN		 228 return 0;
229}
230
231static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
232{
233 const struct firmware *fw;
234 void *buf;
235 int ret;
236
237 ret = request_firmware(&fw, file_name, &is->pdev->dev);
238 if (ret < 0) {
239 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
240 return ret;
241 }
242 buf = is->memory.vaddr + is->setfile.base;
243 memcpy(buf, fw->data, fw->size);
244 fimc_is_mem_barrier();
245 is->setfile.size = fw->size;
246
247 pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
248
249 memcpy(is->fw.setfile_info,
250 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
251 FIMC_IS_SETFILE_INFO_LEN - 1);
252
253 is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
254 is->setfile.state = 1;
255
256 pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
257 is->setfile.base, fw->size);
258
259 release_firmware(fw);
260 return ret;
261}
262
263int fimc_is_cpu_set_power(struct fimc_is *is, int on)
264{
265 unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
266
267 if (on) {
268 /* Disable watchdog */
269 mcuctl_write(0, is, REG_WDT_ISP);
270
271 /* Cortex-A5 start address setting */
272 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
273
274 /* Enable and start Cortex-A5 */
275 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
276 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
277 } else {
278 /* A5 power off */
279 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
280 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
281
282 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
283 if (timeout == 0)
284 return -ETIME;
285 timeout--;
286 udelay(1);
287 }
288 }
289
290 return 0;
291}
292
293/* Wait until @bit of @is->state is set to @state in the interrupt handler. */
294int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
295 unsigned int state, unsigned int timeout)
296{
297
298 int ret = wait_event_timeout(is->irq_queue,
299 !state ^ test_bit(bit, &is->state),
300 timeout);
301 if (ret == 0) {
302 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
303 return -ETIME;
304 }
305 return 0;
306}
307
308int fimc_is_start_firmware(struct fimc_is *is)
309{
310 struct device *dev = &is->pdev->dev;
311 int ret;
312
3cf138a6
SN		 313 if (is->fw.f_w == NULL) {
314 dev_err(dev, "firmware is not loaded\n");
315 return -EINVAL;
316 }
317
9a761e43
SN		 318 memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
319 wmb();
320
321 ret = fimc_is_cpu_set_power(is, 1);
322 if (ret < 0)
323 return ret;
324
325 ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
326 msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
327 if (ret < 0)
328 dev_err(dev, "FIMC-IS CPU power on failed\n");
329
330 return ret;
331}
332
333/* Allocate working memory for the FIMC-IS CPU. */
334static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
335{
336 struct device *dev = &is->pdev->dev;
337
338 is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
339 &is->memory.paddr, GFP_KERNEL);
340 if (is->memory.vaddr == NULL)
341 return -ENOMEM;
342
343 is->memory.size = FIMC_IS_CPU_MEM_SIZE;
344 memset(is->memory.vaddr, 0, is->memory.size);
345
346 dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
347
348 if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
349 dev_err(dev, "invalid firmware memory alignment: %#x\n",
350 (u32)is->memory.paddr);
351 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
352 is->memory.paddr);
353 return -EIO;
354 }
355
356 is->is_p_region = (struct is_region *)(is->memory.vaddr +
357 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
358
359 is->is_dma_p_region = is->memory.paddr +
360 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
361
362 is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
363 FIMC_IS_SHARED_REGION_OFFSET);
364 return 0;
365}
366
367static void fimc_is_free_cpu_memory(struct fimc_is *is)
368{
369 struct device *dev = &is->pdev->dev;
370
404a90ab
SN		 371 if (is->memory.vaddr == NULL)
372 return;
373
9a761e43
SN		 374 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
375 is->memory.paddr);
376}
377
378static void fimc_is_load_firmware(const struct firmware *fw, void *context)
379{
380 struct fimc_is *is = context;
381 struct device *dev = &is->pdev->dev;
382 void *buf;
383 int ret;
384
385 if (fw == NULL) {
386 dev_err(dev, "firmware request failed\n");
387 return;
388 }
389 mutex_lock(&is->lock);
390
391 if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
7d4020c3 392 dev_err(dev, "wrong firmware size: %zu\n", fw->size);
9a761e43
SN		 393 goto done;
394 }
395
396 is->fw.size = fw->size;
397
398 ret = fimc_is_alloc_cpu_memory(is);
399 if (ret < 0) {
400 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
401 goto done;
402 }
403
404 memcpy(is->memory.vaddr, fw->data, fw->size);
405 wmb();
406
407 /* Read firmware description. */
408 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
409 memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
410 is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
411
412 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
413 memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
414 is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
415
416 is->fw.state = 1;
417
418 dev_info(dev, "loaded firmware: %s, rev. %s\n",
419 is->fw.info, is->fw.version);
7d4020c3 420 dev_dbg(dev, "FW size: %zu, paddr: %pad\n", fw->size, &is->memory.paddr);
9a761e43
SN		 421
422 is->is_shared_region->chip_id = 0xe4412;
423 is->is_shared_region->chip_rev_no = 1;
424
425 fimc_is_mem_barrier();
426
427 /*
428 * FIXME: The firmware is not being released for now, as it is
429 * needed around for copying to the IS working memory every
430 * time before the Cortex-A5 is restarted.
431 */
332b295d 432 release_firmware(is->fw.f_w);
9a761e43
SN		 433 is->fw.f_w = fw;
434done:
435 mutex_unlock(&is->lock);
436}
437
438static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
439{
440 return request_firmware_nowait(THIS_MODULE,
441 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
442 GFP_KERNEL, is, fimc_is_load_firmware);
443}
444
445/* General IS interrupt handler */
446static void fimc_is_general_irq_handler(struct fimc_is *is)
447{
448 is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
449
450 switch (is->i2h_cmd.cmd) {
451 case IHC_GET_SENSOR_NUM:
452 fimc_is_hw_get_params(is, 1);
453 fimc_is_hw_wait_intmsr0_intmsd0(is);
454 fimc_is_hw_set_sensor_num(is);
455 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
456 break;
457 case IHC_SET_FACE_MARK:
458 case IHC_FRAME_DONE:
459 fimc_is_hw_get_params(is, 2);
460 break;
461 case IHC_SET_SHOT_MARK:
462 case IHC_AA_DONE:
463 case IH_REPLY_DONE:
464 fimc_is_hw_get_params(is, 3);
465 break;
466 case IH_REPLY_NOT_DONE:
467 fimc_is_hw_get_params(is, 4);
468 break;
469 case IHC_NOT_READY:
470 break;
471 default:
472 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
473 }
474
475 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
476
477 switch (is->i2h_cmd.cmd) {
478 case IHC_GET_SENSOR_NUM:
479 fimc_is_hw_set_intgr0_gd0(is);
480 set_bit(IS_ST_A5_PWR_ON, &is->state);
481 break;
482
483 case IHC_SET_SHOT_MARK:
484 break;
485
486 case IHC_SET_FACE_MARK:
487 is->fd_header.count = is->i2h_cmd.args[0];
488 is->fd_header.index = is->i2h_cmd.args[1];
489 is->fd_header.offset = 0;
490 break;
491
492 case IHC_FRAME_DONE:
493 break;
494
495 case IHC_AA_DONE:
496 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
497 is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
498 break;
499
500 case IH_REPLY_DONE:
501 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
502
503 switch (is->i2h_cmd.args[0]) {
504 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
505 /* Get CAC margin */
506 set_bit(IS_ST_CHANGE_MODE, &is->state);
507 is->isp.cac_margin_x = is->i2h_cmd.args[1];
508 is->isp.cac_margin_y = is->i2h_cmd.args[2];
509 pr_debug("CAC margin (x,y): (%d,%d)\n",
510 is->isp.cac_margin_x, is->isp.cac_margin_y);
511 break;
512
513 case HIC_STREAM_ON:
514 clear_bit(IS_ST_STREAM_OFF, &is->state);
515 set_bit(IS_ST_STREAM_ON, &is->state);
516 break;
517
518 case HIC_STREAM_OFF:
519 clear_bit(IS_ST_STREAM_ON, &is->state);
520 set_bit(IS_ST_STREAM_OFF, &is->state);
521 break;
522
523 case HIC_SET_PARAMETER:
0e761b21
PC		 524 is->config[is->config_index].p_region_index[0] = 0;
525 is->config[is->config_index].p_region_index[1] = 0;
9a761e43
SN		 526 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
527 pr_debug("HIC_SET_PARAMETER\n");
528 break;
529
530 case HIC_GET_PARAMETER:
531 break;
532
533 case HIC_SET_TUNE:
534 break;
535
536 case HIC_GET_STATUS:
537 break;
538
539 case HIC_OPEN_SENSOR:
540 set_bit(IS_ST_OPEN_SENSOR, &is->state);
541 pr_debug("data lanes: %d, settle line: %d\n",
542 is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
543 break;
544
545 case HIC_CLOSE_SENSOR:
546 clear_bit(IS_ST_OPEN_SENSOR, &is->state);
547 is->sensor_index = 0;
548 break;
549
550 case HIC_MSG_TEST:
551 pr_debug("config MSG level completed\n");
552 break;
553
554 case HIC_POWER_DOWN:
555 clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
556 break;
557
558 case HIC_GET_SET_FILE_ADDR:
559 is->setfile.base = is->i2h_cmd.args[1];
560 set_bit(IS_ST_SETFILE_LOADED, &is->state);
561 break;
562
563 case HIC_LOAD_SET_FILE:
564 set_bit(IS_ST_SETFILE_LOADED, &is->state);
565 break;
566 }
567 break;
568
569 case IH_REPLY_NOT_DONE:
570 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
571 is->i2h_cmd.args[1],
572 fimc_is_strerr(is->i2h_cmd.args[1]));
573
574 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
575 pr_err("IS_ERROR_TIME_OUT\n");
576
577 switch (is->i2h_cmd.args[1]) {
578 case IS_ERROR_SET_PARAMETER:
579 fimc_is_mem_barrier();
580 }
581
582 switch (is->i2h_cmd.args[0]) {
583 case HIC_SET_PARAMETER:
0e761b21
PC		 584 is->config[is->config_index].p_region_index[0] = 0;
585 is->config[is->config_index].p_region_index[1] = 0;
9a761e43
SN		 586 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
587 break;
588 }
589 break;
590
591 case IHC_NOT_READY:
592 pr_err("IS control sequence error: Not Ready\n");
593 break;
594 }
595
596 wake_up(&is->irq_queue);
597}
598
599static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
600{
601 struct fimc_is *is = priv;
602 unsigned long flags;
603 u32 status;
604
605 spin_lock_irqsave(&is->slock, flags);
606 status = mcuctl_read(is, MCUCTL_REG_INTSR1);
607
608 if (status & (1UL << FIMC_IS_INT_GENERAL))
609 fimc_is_general_irq_handler(is);
610
611 if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
612 fimc_isp_irq_handler(is);
613
614 spin_unlock_irqrestore(&is->slock, flags);
615 return IRQ_HANDLED;
616}
617
618static int fimc_is_hw_open_sensor(struct fimc_is *is,
619 struct fimc_is_sensor *sensor)
620{
621 struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
622
623 fimc_is_hw_wait_intmsr0_intmsd0(is);
624
625 soe->self_calibration_mode = 1;
626 soe->actuator_type = 0;
627 soe->mipi_lane_num = 0;
628 soe->mclk = 0;
629 soe->mipi_speed = 0;
630 soe->fast_open_sensor = 0;
631 soe->i2c_sclk = 88000000;
632
633 fimc_is_mem_barrier();
634
a13ddcae
JA		 635 /*
636 * Some user space use cases hang up here without this
637 * empirically chosen delay.
638 */
639 udelay(100);
640
9a761e43
SN		 641 mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
642 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
643 mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
644 mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
645 mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
646
647 fimc_is_hw_set_intgr0_gd0(is);
648
649 return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
d265d9ac 650 sensor->drvdata->open_timeout);
9a761e43
SN		 651}
652
653
654int fimc_is_hw_initialize(struct fimc_is *is)
655{
3530ef0a 656 const int config_ids[] = {
9a761e43
SN		 657 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
658 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
659 };
660 struct device *dev = &is->pdev->dev;
661 u32 prev_id;
662 int i, ret;
663
d265d9ac
SN		 664 /* Sensor initialization. Only one sensor is currently supported. */
665 ret = fimc_is_hw_open_sensor(is, &is->sensor[0]);
9a761e43
SN		 666 if (ret < 0)
667 return ret;
668
669 /* Get the setfile address. */
670 fimc_is_hw_get_setfile_addr(is);
671
672 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
673 FIMC_IS_CONFIG_TIMEOUT);
674 if (ret < 0) {
675 dev_err(dev, "get setfile address timed out\n");
676 return ret;
677 }
678 pr_debug("setfile.base: %#x\n", is->setfile.base);
679
680 /* Load the setfile. */
681 fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
682 clear_bit(IS_ST_SETFILE_LOADED, &is->state);
683 fimc_is_hw_load_setfile(is);
684 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
685 FIMC_IS_CONFIG_TIMEOUT);
686 if (ret < 0) {
687 dev_err(dev, "loading setfile timed out\n");
688 return ret;
689 }
690
691 pr_debug("setfile: base: %#x, size: %d\n",
692 is->setfile.base, is->setfile.size);
693 pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
694
695 /* Check magic number. */
696 if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
697 FIMC_IS_MAGIC_NUMBER) {
698 dev_err(dev, "magic number error!\n");
699 return -EIO;
700 }
701
7d4020c3
MCC		 702 pr_debug("shared region: %pad, parameter region: %pad\n",
703 &is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
704 &is->is_dma_p_region);
9a761e43
SN		 705
706 is->setfile.sub_index = 0;
707
708 /* Stream off. */
709 fimc_is_hw_stream_off(is);
710 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
711 FIMC_IS_CONFIG_TIMEOUT);
712 if (ret < 0) {
713 dev_err(dev, "stream off timeout\n");
714 return ret;
715 }
716
717 /* Preserve previous mode. */
3530ef0a 718 prev_id = is->config_index;
9a761e43
SN		 719
720 /* Set initial parameter values. */
3530ef0a
SN		 721 for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
722 is->config_index = config_ids[i];
9a761e43
SN		 723 fimc_is_set_initial_params(is);
724 ret = fimc_is_itf_s_param(is, true);
725 if (ret < 0) {
3530ef0a 726 is->config_index = prev_id;
9a761e43
SN		 727 return ret;
728 }
729 }
3530ef0a 730 is->config_index = prev_id;
9a761e43
SN		 731
732 set_bit(IS_ST_INIT_DONE, &is->state);
733 dev_info(dev, "initialization sequence completed (%d)\n",
3530ef0a 734 is->config_index);
9a761e43
SN		 735 return 0;
736}
737
738static int fimc_is_log_show(struct seq_file *s, void *data)
739{
740 struct fimc_is *is = s->private;
741 const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
742
743 if (is->memory.vaddr == NULL) {
744 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
745 return -EIO;
746 }
747
748 seq_printf(s, "%s\n", buf);
749 return 0;
750}
751
752static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
753{
754 return single_open(file, fimc_is_log_show, inode->i_private);
755}
756
757static const struct file_operations fimc_is_debugfs_fops = {
758 .open = fimc_is_debugfs_open,
759 .read = seq_read,
760 .llseek = seq_lseek,
761 .release = single_release,
762};
763
764static void fimc_is_debugfs_remove(struct fimc_is *is)
765{
450f5f54 766 debugfs_remove_recursive(is->debugfs_entry);
9a761e43
SN		 767 is->debugfs_entry = NULL;
768}
769
770static int fimc_is_debugfs_create(struct fimc_is *is)
771{
772 struct dentry *dentry;
773
774 is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
775
776 dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
777 is, &fimc_is_debugfs_fops);
778 if (!dentry)
779 fimc_is_debugfs_remove(is);
780
781 return is->debugfs_entry == NULL ? -EIO : 0;
782}
783
283bf33b
SN		 784static int fimc_is_runtime_resume(struct device *dev);
785static int fimc_is_runtime_suspend(struct device *dev);
786
9a761e43
SN		 787static int fimc_is_probe(struct platform_device *pdev)
788{
789 struct device *dev = &pdev->dev;
790 struct fimc_is *is;
791 struct resource res;
792 struct device_node *node;
793 int ret;
794
795 is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
796 if (!is)
797 return -ENOMEM;
798
799 is->pdev = pdev;
800 is->isp.pdev = pdev;
801
802 init_waitqueue_head(&is->irq_queue);
803 spin_lock_init(&is->slock);
804 mutex_init(&is->lock);
805
806 ret = of_address_to_resource(dev->of_node, 0, &res);
807 if (ret < 0)
808 return ret;
809
810 is->regs = devm_ioremap_resource(dev, &res);
811 if (IS_ERR(is->regs))
812 return PTR_ERR(is->regs);
813
814 node = of_get_child_by_name(dev->of_node, "pmu");
815 if (!node)
816 return -ENODEV;
817
818 is->pmu_regs = of_iomap(node, 0);
819 if (!is->pmu_regs)
820 return -ENOMEM;
821
822 is->irq = irq_of_parse_and_map(dev->of_node, 0);
9a7a848d 823 if (!is->irq) {
9a761e43 824 dev_err(dev, "no irq found\n");
9a7a848d 825 return -EINVAL;
9a761e43
SN		 826 }
827
828 ret = fimc_is_get_clocks(is);
829 if (ret < 0)
830 return ret;
831
832 platform_set_drvdata(pdev, is);
833
834 ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
835 if (ret < 0) {
836 dev_err(dev, "irq request failed\n");
837 goto err_clk;
838 }
839 pm_runtime_enable(dev);
b34f51fa 840
283bf33b
SN		 841 if (!pm_runtime_enabled(dev)) {
842 ret = fimc_is_runtime_resume(dev);
843 if (ret < 0)
844 goto err_irq;
845 }
846
722a860e 847 ret = pm_runtime_get_sync(dev);
9a761e43 848 if (ret < 0)
283bf33b 849 goto err_pm;
9a761e43 850
712b617e 851 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
9a761e43
SN		 852 /*
853 * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
854 * will be created within the subdev's registered() callback.
855 */
856 ret = fimc_is_register_subdevs(is);
857 if (ret < 0)
2548fee6 858 goto err_pm;
9a761e43
SN		 859
860 ret = fimc_is_debugfs_create(is);
861 if (ret < 0)
862 goto err_sd;
863
864 ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
865 if (ret < 0)
866 goto err_dfs;
867
722a860e
SN		 868 pm_runtime_put_sync(dev);
869
9a761e43
SN		 870 dev_dbg(dev, "FIMC-IS registered successfully\n");
871 return 0;
872
873err_dfs:
874 fimc_is_debugfs_remove(is);
9a761e43
SN		 875err_sd:
876 fimc_is_unregister_subdevs(is);
283bf33b
SN		 877err_pm:
878 if (!pm_runtime_enabled(dev))
879 fimc_is_runtime_suspend(dev);
9a761e43
SN		 880err_irq:
881 free_irq(is->irq, is);
9a761e43
SN		 882err_clk:
883 fimc_is_put_clocks(is);
884 return ret;
885}
886
887static int fimc_is_runtime_resume(struct device *dev)
888{
889 struct fimc_is *is = dev_get_drvdata(dev);
722a860e 890 int ret;
9a761e43 891
722a860e
SN		 892 ret = fimc_is_setup_clocks(is);
893 if (ret)
894 return ret;
9a761e43
SN		 895
896 return fimc_is_enable_clocks(is);
897}
898
899static int fimc_is_runtime_suspend(struct device *dev)
900{
901 struct fimc_is *is = dev_get_drvdata(dev);
902
722a860e 903 fimc_is_disable_clocks(is);
9a761e43
SN		 904 return 0;
905}
906
907#ifdef CONFIG_PM_SLEEP
908static int fimc_is_resume(struct device *dev)
909{
910 /* TODO: */
911 return 0;
912}
913
914static int fimc_is_suspend(struct device *dev)
915{
916 struct fimc_is *is = dev_get_drvdata(dev);
917
918 /* TODO: */
919 if (test_bit(IS_ST_A5_PWR_ON, &is->state))
920 return -EBUSY;
921
922 return 0;
923}
924#endif /* CONFIG_PM_SLEEP */
925
926static int fimc_is_remove(struct platform_device *pdev)
927{
283bf33b
SN		 928 struct device *dev = &pdev->dev;
929 struct fimc_is *is = dev_get_drvdata(dev);
9a761e43 930
283bf33b
SN		 931 pm_runtime_disable(dev);
932 pm_runtime_set_suspended(dev);
933 if (!pm_runtime_status_suspended(dev))
934 fimc_is_runtime_suspend(dev);
9a761e43
SN		 935 free_irq(is->irq, is);
936 fimc_is_unregister_subdevs(is);
712b617e 937 vb2_dma_contig_clear_max_seg_size(dev);
9a761e43
SN		 938 fimc_is_put_clocks(is);
939 fimc_is_debugfs_remove(is);
332b295d 940 release_firmware(is->fw.f_w);
9a761e43
SN		 941 fimc_is_free_cpu_memory(is);
942
943 return 0;
944}
945
946static const struct of_device_id fimc_is_of_match[] = {
947 { .compatible = "samsung,exynos4212-fimc-is" },
948 { /* sentinel */ },
949};
950MODULE_DEVICE_TABLE(of, fimc_is_of_match);
951
952static const struct dev_pm_ops fimc_is_pm_ops = {
953 SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
954 SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
955 NULL)
956};
957
958static struct platform_driver fimc_is_driver = {
959 .probe = fimc_is_probe,
960 .remove = fimc_is_remove,
961 .driver = {
962 .of_match_table = fimc_is_of_match,
963 .name = FIMC_IS_DRV_NAME,
9a761e43
SN		 964 .pm = &fimc_is_pm_ops,
965 }
966};
967
968static int fimc_is_module_init(void)
969{
970 int ret;
971
9a761e43
SN		 972 ret = fimc_is_register_i2c_driver();
973 if (ret < 0)
d265d9ac 974 return ret;
9a761e43
SN		 975
976 ret = platform_driver_register(&fimc_is_driver);
9a761e43 977
d265d9ac
SN		 978 if (ret < 0)
979 fimc_is_unregister_i2c_driver();
980
9a761e43
SN		 981 return ret;
982}
983
984static void fimc_is_module_exit(void)
985{
0e30c7e1
SN		 986 fimc_is_unregister_i2c_driver();
987 platform_driver_unregister(&fimc_is_driver);
9a761e43
SN		 988}
989
990module_init(fimc_is_module_init);
991module_exit(fimc_is_module_exit);
992
993MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
994MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
995MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
fdb49827 996MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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