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[media] exynos4-is: Prevent NULL pointer dereference when firmware isn't loaded
[deliverable/linux.git] / drivers / media / platform / exynos4-is / fimc-is.c
CommitLineData
9a761e43
SN		 1/*
2 * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
3 *
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 *
6 * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com>
7 * Younghwan Joo <yhwan.joo@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
14
15#include <linux/device.h>
16#include <linux/debugfs.h>
17#include <linux/delay.h>
18#include <linux/dma-contiguous.h>
19#include <linux/errno.h>
20#include <linux/firmware.h>
21#include <linux/interrupt.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of_i2c.h>
25#include <linux/of_irq.h>
26#include <linux/of_address.h>
27#include <linux/of_platform.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32#include <linux/videodev2.h>
33#include <media/v4l2-of.h>
34#include <media/videobuf2-dma-contig.h>
35
36#include "media-dev.h"
37#include "fimc-is.h"
38#include "fimc-is-command.h"
39#include "fimc-is-errno.h"
40#include "fimc-is-i2c.h"
41#include "fimc-is-param.h"
42#include "fimc-is-regs.h"
43
44
45static char *fimc_is_clocks[ISS_CLKS_MAX] = {
46 [ISS_CLK_PPMUISPX] = "ppmuispx",
47 [ISS_CLK_PPMUISPMX] = "ppmuispmx",
48 [ISS_CLK_LITE0] = "lite0",
49 [ISS_CLK_LITE1] = "lite1",
50 [ISS_CLK_MPLL] = "mpll",
51 [ISS_CLK_SYSREG] = "sysreg",
52 [ISS_CLK_ISP] = "isp",
53 [ISS_CLK_DRC] = "drc",
54 [ISS_CLK_FD] = "fd",
55 [ISS_CLK_MCUISP] = "mcuisp",
56 [ISS_CLK_UART] = "uart",
57 [ISS_CLK_ISP_DIV0] = "ispdiv0",
58 [ISS_CLK_ISP_DIV1] = "ispdiv1",
59 [ISS_CLK_MCUISP_DIV0] = "mcuispdiv0",
60 [ISS_CLK_MCUISP_DIV1] = "mcuispdiv1",
61 [ISS_CLK_ACLK200] = "aclk200",
62 [ISS_CLK_ACLK200_DIV] = "div_aclk200",
63 [ISS_CLK_ACLK400MCUISP] = "aclk400mcuisp",
64 [ISS_CLK_ACLK400MCUISP_DIV] = "div_aclk400mcuisp",
65};
66
67static void fimc_is_put_clocks(struct fimc_is *is)
68{
69 int i;
70
71 for (i = 0; i < ISS_CLKS_MAX; i++) {
72 if (IS_ERR(is->clocks[i]))
73 continue;
74 clk_unprepare(is->clocks[i]);
75 clk_put(is->clocks[i]);
76 is->clocks[i] = ERR_PTR(-EINVAL);
77 }
78}
79
80static int fimc_is_get_clocks(struct fimc_is *is)
81{
82 int i, ret;
83
84 for (i = 0; i < ISS_CLKS_MAX; i++)
85 is->clocks[i] = ERR_PTR(-EINVAL);
86
87 for (i = 0; i < ISS_CLKS_MAX; i++) {
88 is->clocks[i] = clk_get(&is->pdev->dev, fimc_is_clocks[i]);
89 if (IS_ERR(is->clocks[i])) {
90 ret = PTR_ERR(is->clocks[i]);
91 goto err;
92 }
93 ret = clk_prepare(is->clocks[i]);
94 if (ret < 0) {
95 clk_put(is->clocks[i]);
96 is->clocks[i] = ERR_PTR(-EINVAL);
97 goto err;
98 }
99 }
100
101 return 0;
102err:
103 fimc_is_put_clocks(is);
104 dev_err(&is->pdev->dev, "failed to get clock: %s\n",
105 fimc_is_clocks[i]);
106 return -ENXIO;
107}
108
109static int fimc_is_setup_clocks(struct fimc_is *is)
110{
111 int ret;
112
113 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK200],
114 is->clocks[ISS_CLK_ACLK200_DIV]);
115 if (ret < 0)
116 return ret;
117
118 ret = clk_set_parent(is->clocks[ISS_CLK_ACLK400MCUISP],
119 is->clocks[ISS_CLK_ACLK400MCUISP_DIV]);
120 if (ret < 0)
121 return ret;
122
123 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV0], ACLK_AXI_FREQUENCY);
124 if (ret < 0)
125 return ret;
126
127 ret = clk_set_rate(is->clocks[ISS_CLK_ISP_DIV1], ACLK_AXI_FREQUENCY);
128 if (ret < 0)
129 return ret;
130
131 ret = clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV0],
132 ATCLK_MCUISP_FREQUENCY);
133 if (ret < 0)
134 return ret;
135
136 return clk_set_rate(is->clocks[ISS_CLK_MCUISP_DIV1],
137 ATCLK_MCUISP_FREQUENCY);
138}
139
140int fimc_is_enable_clocks(struct fimc_is *is)
141{
142 int i, ret;
143
144 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
145 if (IS_ERR(is->clocks[i]))
146 continue;
147 ret = clk_enable(is->clocks[i]);
148 if (ret < 0) {
149 dev_err(&is->pdev->dev, "clock %s enable failed\n",
150 fimc_is_clocks[i]);
151 for (--i; i >= 0; i--)
152 clk_disable(is->clocks[i]);
153 return ret;
154 }
155 pr_debug("enabled clock: %s\n", fimc_is_clocks[i]);
156 }
157 return 0;
158}
159
160void fimc_is_disable_clocks(struct fimc_is *is)
161{
162 int i;
163
164 for (i = 0; i < ISS_GATE_CLKS_MAX; i++) {
165 if (!IS_ERR(is->clocks[i])) {
166 clk_disable(is->clocks[i]);
167 pr_debug("disabled clock: %s\n", fimc_is_clocks[i]);
168 }
169 }
170}
171
172static int fimc_is_parse_sensor_config(struct fimc_is_sensor *sensor,
173 struct device_node *np)
174{
175 u32 tmp = 0;
176 int ret;
177
178 np = v4l2_of_get_next_endpoint(np, NULL);
179 if (!np)
180 return -ENXIO;
181 np = v4l2_of_get_remote_port(np);
182 if (!np)
183 return -ENXIO;
184
185 /* Use MIPI-CSIS channel id to determine the ISP I2C bus index. */
186 ret = of_property_read_u32(np, "reg", &tmp);
187 sensor->i2c_bus = tmp - FIMC_INPUT_MIPI_CSI2_0;
188
189 return ret;
190}
191
192static int fimc_is_register_subdevs(struct fimc_is *is)
193{
194 struct device_node *adapter, *child;
195 int ret;
196
197 ret = fimc_isp_subdev_create(&is->isp);
198 if (ret < 0)
199 return ret;
200
201 for_each_compatible_node(adapter, NULL, FIMC_IS_I2C_COMPATIBLE) {
202 if (!of_find_device_by_node(adapter)) {
203 of_node_put(adapter);
204 return -EPROBE_DEFER;
205 }
206
207 for_each_available_child_of_node(adapter, child) {
208 struct i2c_client *client;
209 struct v4l2_subdev *sd;
210
211 client = of_find_i2c_device_by_node(child);
212 if (!client)
213 goto e_retry;
214
215 sd = i2c_get_clientdata(client);
216 if (!sd)
217 goto e_retry;
218
219 /* FIXME: Add support for multiple sensors. */
220 if (WARN_ON(is->sensor))
221 continue;
222
1bc515ac 223 is->sensor = sd_to_fimc_is_sensor(sd);
9a761e43
SN		 224
225 if (fimc_is_parse_sensor_config(is->sensor, child)) {
226 dev_warn(&is->pdev->dev, "DT parse error: %s\n",
227 child->full_name);
228 }
229 pr_debug("%s(): registered subdev: %p\n",
230 __func__, sd->name);
231 }
232 }
233 return 0;
234
235e_retry:
236 of_node_put(child);
237 return -EPROBE_DEFER;
238}
239
240static int fimc_is_unregister_subdevs(struct fimc_is *is)
241{
242 fimc_isp_subdev_destroy(&is->isp);
243 is->sensor = NULL;
244 return 0;
245}
246
247static int fimc_is_load_setfile(struct fimc_is *is, char *file_name)
248{
249 const struct firmware *fw;
250 void *buf;
251 int ret;
252
253 ret = request_firmware(&fw, file_name, &is->pdev->dev);
254 if (ret < 0) {
255 dev_err(&is->pdev->dev, "firmware request failed (%d)\n", ret);
256 return ret;
257 }
258 buf = is->memory.vaddr + is->setfile.base;
259 memcpy(buf, fw->data, fw->size);
260 fimc_is_mem_barrier();
261 is->setfile.size = fw->size;
262
263 pr_debug("mem vaddr: %p, setfile buf: %p\n", is->memory.vaddr, buf);
264
265 memcpy(is->fw.setfile_info,
266 fw->data + fw->size - FIMC_IS_SETFILE_INFO_LEN,
267 FIMC_IS_SETFILE_INFO_LEN - 1);
268
269 is->fw.setfile_info[FIMC_IS_SETFILE_INFO_LEN - 1] = '\0';
270 is->setfile.state = 1;
271
272 pr_debug("FIMC-IS setfile loaded: base: %#x, size: %zu B\n",
273 is->setfile.base, fw->size);
274
275 release_firmware(fw);
276 return ret;
277}
278
279int fimc_is_cpu_set_power(struct fimc_is *is, int on)
280{
281 unsigned int timeout = FIMC_IS_POWER_ON_TIMEOUT;
282
283 if (on) {
284 /* Disable watchdog */
285 mcuctl_write(0, is, REG_WDT_ISP);
286
287 /* Cortex-A5 start address setting */
288 mcuctl_write(is->memory.paddr, is, MCUCTL_REG_BBOAR);
289
290 /* Enable and start Cortex-A5 */
291 pmuisp_write(0x18000, is, REG_PMU_ISP_ARM_OPTION);
292 pmuisp_write(0x1, is, REG_PMU_ISP_ARM_CONFIGURATION);
293 } else {
294 /* A5 power off */
295 pmuisp_write(0x10000, is, REG_PMU_ISP_ARM_OPTION);
296 pmuisp_write(0x0, is, REG_PMU_ISP_ARM_CONFIGURATION);
297
298 while (pmuisp_read(is, REG_PMU_ISP_ARM_STATUS) & 1) {
299 if (timeout == 0)
300 return -ETIME;
301 timeout--;
302 udelay(1);
303 }
304 }
305
306 return 0;
307}
308
309/* Wait until @bit of @is->state is set to @state in the interrupt handler. */
310int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
311 unsigned int state, unsigned int timeout)
312{
313
314 int ret = wait_event_timeout(is->irq_queue,
315 !state ^ test_bit(bit, &is->state),
316 timeout);
317 if (ret == 0) {
318 dev_WARN(&is->pdev->dev, "%s() timed out\n", __func__);
319 return -ETIME;
320 }
321 return 0;
322}
323
324int fimc_is_start_firmware(struct fimc_is *is)
325{
326 struct device *dev = &is->pdev->dev;
327 int ret;
328
3cf138a6
SN		 329 if (is->fw.f_w == NULL) {
330 dev_err(dev, "firmware is not loaded\n");
331 return -EINVAL;
332 }
333
9a761e43
SN		 334 memcpy(is->memory.vaddr, is->fw.f_w->data, is->fw.f_w->size);
335 wmb();
336
337 ret = fimc_is_cpu_set_power(is, 1);
338 if (ret < 0)
339 return ret;
340
341 ret = fimc_is_wait_event(is, IS_ST_A5_PWR_ON, 1,
342 msecs_to_jiffies(FIMC_IS_FW_LOAD_TIMEOUT));
343 if (ret < 0)
344 dev_err(dev, "FIMC-IS CPU power on failed\n");
345
346 return ret;
347}
348
349/* Allocate working memory for the FIMC-IS CPU. */
350static int fimc_is_alloc_cpu_memory(struct fimc_is *is)
351{
352 struct device *dev = &is->pdev->dev;
353
354 is->memory.vaddr = dma_alloc_coherent(dev, FIMC_IS_CPU_MEM_SIZE,
355 &is->memory.paddr, GFP_KERNEL);
356 if (is->memory.vaddr == NULL)
357 return -ENOMEM;
358
359 is->memory.size = FIMC_IS_CPU_MEM_SIZE;
360 memset(is->memory.vaddr, 0, is->memory.size);
361
362 dev_info(dev, "FIMC-IS CPU memory base: %#x\n", (u32)is->memory.paddr);
363
364 if (((u32)is->memory.paddr) & FIMC_IS_FW_ADDR_MASK) {
365 dev_err(dev, "invalid firmware memory alignment: %#x\n",
366 (u32)is->memory.paddr);
367 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
368 is->memory.paddr);
369 return -EIO;
370 }
371
372 is->is_p_region = (struct is_region *)(is->memory.vaddr +
373 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE);
374
375 is->is_dma_p_region = is->memory.paddr +
376 FIMC_IS_CPU_MEM_SIZE - FIMC_IS_REGION_SIZE;
377
378 is->is_shared_region = (struct is_share_region *)(is->memory.vaddr +
379 FIMC_IS_SHARED_REGION_OFFSET);
380 return 0;
381}
382
383static void fimc_is_free_cpu_memory(struct fimc_is *is)
384{
385 struct device *dev = &is->pdev->dev;
386
387 dma_free_coherent(dev, is->memory.size, is->memory.vaddr,
388 is->memory.paddr);
389}
390
391static void fimc_is_load_firmware(const struct firmware *fw, void *context)
392{
393 struct fimc_is *is = context;
394 struct device *dev = &is->pdev->dev;
395 void *buf;
396 int ret;
397
398 if (fw == NULL) {
399 dev_err(dev, "firmware request failed\n");
400 return;
401 }
402 mutex_lock(&is->lock);
403
404 if (fw->size < FIMC_IS_FW_SIZE_MIN || fw->size > FIMC_IS_FW_SIZE_MAX) {
405 dev_err(dev, "wrong firmware size: %d\n", fw->size);
406 goto done;
407 }
408
409 is->fw.size = fw->size;
410
411 ret = fimc_is_alloc_cpu_memory(is);
412 if (ret < 0) {
413 dev_err(dev, "failed to allocate FIMC-IS CPU memory\n");
414 goto done;
415 }
416
417 memcpy(is->memory.vaddr, fw->data, fw->size);
418 wmb();
419
420 /* Read firmware description. */
421 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_DESC_LEN);
422 memcpy(&is->fw.info, buf, FIMC_IS_FW_INFO_LEN);
423 is->fw.info[FIMC_IS_FW_INFO_LEN] = 0;
424
425 buf = (void *)(is->memory.vaddr + fw->size - FIMC_IS_FW_VER_LEN);
426 memcpy(&is->fw.version, buf, FIMC_IS_FW_VER_LEN);
427 is->fw.version[FIMC_IS_FW_VER_LEN - 1] = 0;
428
429 is->fw.state = 1;
430
431 dev_info(dev, "loaded firmware: %s, rev. %s\n",
432 is->fw.info, is->fw.version);
433 dev_dbg(dev, "FW size: %d, paddr: %#x\n", fw->size, is->memory.paddr);
434
435 is->is_shared_region->chip_id = 0xe4412;
436 is->is_shared_region->chip_rev_no = 1;
437
438 fimc_is_mem_barrier();
439
440 /*
441 * FIXME: The firmware is not being released for now, as it is
442 * needed around for copying to the IS working memory every
443 * time before the Cortex-A5 is restarted.
444 */
445 if (is->fw.f_w)
446 release_firmware(is->fw.f_w);
447 is->fw.f_w = fw;
448done:
449 mutex_unlock(&is->lock);
450}
451
452static int fimc_is_request_firmware(struct fimc_is *is, const char *fw_name)
453{
454 return request_firmware_nowait(THIS_MODULE,
455 FW_ACTION_HOTPLUG, fw_name, &is->pdev->dev,
456 GFP_KERNEL, is, fimc_is_load_firmware);
457}
458
459/* General IS interrupt handler */
460static void fimc_is_general_irq_handler(struct fimc_is *is)
461{
462 is->i2h_cmd.cmd = mcuctl_read(is, MCUCTL_REG_ISSR(10));
463
464 switch (is->i2h_cmd.cmd) {
465 case IHC_GET_SENSOR_NUM:
466 fimc_is_hw_get_params(is, 1);
467 fimc_is_hw_wait_intmsr0_intmsd0(is);
468 fimc_is_hw_set_sensor_num(is);
469 pr_debug("ISP FW version: %#x\n", is->i2h_cmd.args[0]);
470 break;
471 case IHC_SET_FACE_MARK:
472 case IHC_FRAME_DONE:
473 fimc_is_hw_get_params(is, 2);
474 break;
475 case IHC_SET_SHOT_MARK:
476 case IHC_AA_DONE:
477 case IH_REPLY_DONE:
478 fimc_is_hw_get_params(is, 3);
479 break;
480 case IH_REPLY_NOT_DONE:
481 fimc_is_hw_get_params(is, 4);
482 break;
483 case IHC_NOT_READY:
484 break;
485 default:
486 pr_info("unknown command: %#x\n", is->i2h_cmd.cmd);
487 }
488
489 fimc_is_fw_clear_irq1(is, FIMC_IS_INT_GENERAL);
490
491 switch (is->i2h_cmd.cmd) {
492 case IHC_GET_SENSOR_NUM:
493 fimc_is_hw_set_intgr0_gd0(is);
494 set_bit(IS_ST_A5_PWR_ON, &is->state);
495 break;
496
497 case IHC_SET_SHOT_MARK:
498 break;
499
500 case IHC_SET_FACE_MARK:
501 is->fd_header.count = is->i2h_cmd.args[0];
502 is->fd_header.index = is->i2h_cmd.args[1];
503 is->fd_header.offset = 0;
504 break;
505
506 case IHC_FRAME_DONE:
507 break;
508
509 case IHC_AA_DONE:
510 pr_debug("AA_DONE - %d, %d, %d\n", is->i2h_cmd.args[0],
511 is->i2h_cmd.args[1], is->i2h_cmd.args[2]);
512 break;
513
514 case IH_REPLY_DONE:
515 pr_debug("ISR_DONE: args[0]: %#x\n", is->i2h_cmd.args[0]);
516
517 switch (is->i2h_cmd.args[0]) {
518 case HIC_PREVIEW_STILL...HIC_CAPTURE_VIDEO:
519 /* Get CAC margin */
520 set_bit(IS_ST_CHANGE_MODE, &is->state);
521 is->isp.cac_margin_x = is->i2h_cmd.args[1];
522 is->isp.cac_margin_y = is->i2h_cmd.args[2];
523 pr_debug("CAC margin (x,y): (%d,%d)\n",
524 is->isp.cac_margin_x, is->isp.cac_margin_y);
525 break;
526
527 case HIC_STREAM_ON:
528 clear_bit(IS_ST_STREAM_OFF, &is->state);
529 set_bit(IS_ST_STREAM_ON, &is->state);
530 break;
531
532 case HIC_STREAM_OFF:
533 clear_bit(IS_ST_STREAM_ON, &is->state);
534 set_bit(IS_ST_STREAM_OFF, &is->state);
535 break;
536
537 case HIC_SET_PARAMETER:
3530ef0a
SN		 538 is->config[is->config_index].p_region_index1 = 0;
539 is->config[is->config_index].p_region_index2 = 0;
9a761e43
SN		 540 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
541 pr_debug("HIC_SET_PARAMETER\n");
542 break;
543
544 case HIC_GET_PARAMETER:
545 break;
546
547 case HIC_SET_TUNE:
548 break;
549
550 case HIC_GET_STATUS:
551 break;
552
553 case HIC_OPEN_SENSOR:
554 set_bit(IS_ST_OPEN_SENSOR, &is->state);
555 pr_debug("data lanes: %d, settle line: %d\n",
556 is->i2h_cmd.args[2], is->i2h_cmd.args[1]);
557 break;
558
559 case HIC_CLOSE_SENSOR:
560 clear_bit(IS_ST_OPEN_SENSOR, &is->state);
561 is->sensor_index = 0;
562 break;
563
564 case HIC_MSG_TEST:
565 pr_debug("config MSG level completed\n");
566 break;
567
568 case HIC_POWER_DOWN:
569 clear_bit(IS_ST_PWR_SUBIP_ON, &is->state);
570 break;
571
572 case HIC_GET_SET_FILE_ADDR:
573 is->setfile.base = is->i2h_cmd.args[1];
574 set_bit(IS_ST_SETFILE_LOADED, &is->state);
575 break;
576
577 case HIC_LOAD_SET_FILE:
578 set_bit(IS_ST_SETFILE_LOADED, &is->state);
579 break;
580 }
581 break;
582
583 case IH_REPLY_NOT_DONE:
584 pr_err("ISR_NDONE: %d: %#x, %s\n", is->i2h_cmd.args[0],
585 is->i2h_cmd.args[1],
586 fimc_is_strerr(is->i2h_cmd.args[1]));
587
588 if (is->i2h_cmd.args[1] & IS_ERROR_TIME_OUT_FLAG)
589 pr_err("IS_ERROR_TIME_OUT\n");
590
591 switch (is->i2h_cmd.args[1]) {
592 case IS_ERROR_SET_PARAMETER:
593 fimc_is_mem_barrier();
594 }
595
596 switch (is->i2h_cmd.args[0]) {
597 case HIC_SET_PARAMETER:
3530ef0a
SN		 598 is->config[is->config_index].p_region_index1 = 0;
599 is->config[is->config_index].p_region_index2 = 0;
9a761e43
SN		 600 set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state);
601 break;
602 }
603 break;
604
605 case IHC_NOT_READY:
606 pr_err("IS control sequence error: Not Ready\n");
607 break;
608 }
609
610 wake_up(&is->irq_queue);
611}
612
613static irqreturn_t fimc_is_irq_handler(int irq, void *priv)
614{
615 struct fimc_is *is = priv;
616 unsigned long flags;
617 u32 status;
618
619 spin_lock_irqsave(&is->slock, flags);
620 status = mcuctl_read(is, MCUCTL_REG_INTSR1);
621
622 if (status & (1UL << FIMC_IS_INT_GENERAL))
623 fimc_is_general_irq_handler(is);
624
625 if (status & (1UL << FIMC_IS_INT_FRAME_DONE_ISP))
626 fimc_isp_irq_handler(is);
627
628 spin_unlock_irqrestore(&is->slock, flags);
629 return IRQ_HANDLED;
630}
631
632static int fimc_is_hw_open_sensor(struct fimc_is *is,
633 struct fimc_is_sensor *sensor)
634{
635 struct sensor_open_extended *soe = (void *)&is->is_p_region->shared;
636
637 fimc_is_hw_wait_intmsr0_intmsd0(is);
638
639 soe->self_calibration_mode = 1;
640 soe->actuator_type = 0;
641 soe->mipi_lane_num = 0;
642 soe->mclk = 0;
643 soe->mipi_speed = 0;
644 soe->fast_open_sensor = 0;
645 soe->i2c_sclk = 88000000;
646
647 fimc_is_mem_barrier();
648
649 mcuctl_write(HIC_OPEN_SENSOR, is, MCUCTL_REG_ISSR(0));
650 mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1));
651 mcuctl_write(sensor->drvdata->id, is, MCUCTL_REG_ISSR(2));
652 mcuctl_write(sensor->i2c_bus, is, MCUCTL_REG_ISSR(3));
653 mcuctl_write(is->is_dma_p_region, is, MCUCTL_REG_ISSR(4));
654
655 fimc_is_hw_set_intgr0_gd0(is);
656
657 return fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 1,
658 FIMC_IS_SENSOR_OPEN_TIMEOUT);
659}
660
661
662int fimc_is_hw_initialize(struct fimc_is *is)
663{
3530ef0a 664 const int config_ids[] = {
9a761e43
SN		 665 IS_SC_PREVIEW_STILL, IS_SC_PREVIEW_VIDEO,
666 IS_SC_CAPTURE_STILL, IS_SC_CAPTURE_VIDEO
667 };
668 struct device *dev = &is->pdev->dev;
669 u32 prev_id;
670 int i, ret;
671
672 /* Sensor initialization. */
673 ret = fimc_is_hw_open_sensor(is, is->sensor);
674 if (ret < 0)
675 return ret;
676
677 /* Get the setfile address. */
678 fimc_is_hw_get_setfile_addr(is);
679
680 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
681 FIMC_IS_CONFIG_TIMEOUT);
682 if (ret < 0) {
683 dev_err(dev, "get setfile address timed out\n");
684 return ret;
685 }
686 pr_debug("setfile.base: %#x\n", is->setfile.base);
687
688 /* Load the setfile. */
689 fimc_is_load_setfile(is, FIMC_IS_SETFILE_6A3);
690 clear_bit(IS_ST_SETFILE_LOADED, &is->state);
691 fimc_is_hw_load_setfile(is);
692 ret = fimc_is_wait_event(is, IS_ST_SETFILE_LOADED, 1,
693 FIMC_IS_CONFIG_TIMEOUT);
694 if (ret < 0) {
695 dev_err(dev, "loading setfile timed out\n");
696 return ret;
697 }
698
699 pr_debug("setfile: base: %#x, size: %d\n",
700 is->setfile.base, is->setfile.size);
701 pr_info("FIMC-IS Setfile info: %s\n", is->fw.setfile_info);
702
703 /* Check magic number. */
704 if (is->is_p_region->shared[MAX_SHARED_COUNT - 1] !=
705 FIMC_IS_MAGIC_NUMBER) {
706 dev_err(dev, "magic number error!\n");
707 return -EIO;
708 }
709
710 pr_debug("shared region: %#x, parameter region: %#x\n",
711 is->memory.paddr + FIMC_IS_SHARED_REGION_OFFSET,
712 is->is_dma_p_region);
713
714 is->setfile.sub_index = 0;
715
716 /* Stream off. */
717 fimc_is_hw_stream_off(is);
718 ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1,
719 FIMC_IS_CONFIG_TIMEOUT);
720 if (ret < 0) {
721 dev_err(dev, "stream off timeout\n");
722 return ret;
723 }
724
725 /* Preserve previous mode. */
3530ef0a 726 prev_id = is->config_index;
9a761e43
SN		 727
728 /* Set initial parameter values. */
3530ef0a
SN		 729 for (i = 0; i < ARRAY_SIZE(config_ids); i++) {
730 is->config_index = config_ids[i];
9a761e43
SN		 731 fimc_is_set_initial_params(is);
732 ret = fimc_is_itf_s_param(is, true);
733 if (ret < 0) {
3530ef0a 734 is->config_index = prev_id;
9a761e43
SN		 735 return ret;
736 }
737 }
3530ef0a 738 is->config_index = prev_id;
9a761e43
SN		 739
740 set_bit(IS_ST_INIT_DONE, &is->state);
741 dev_info(dev, "initialization sequence completed (%d)\n",
3530ef0a 742 is->config_index);
9a761e43
SN		 743 return 0;
744}
745
746static int fimc_is_log_show(struct seq_file *s, void *data)
747{
748 struct fimc_is *is = s->private;
749 const u8 *buf = is->memory.vaddr + FIMC_IS_DEBUG_REGION_OFFSET;
750
751 if (is->memory.vaddr == NULL) {
752 dev_err(&is->pdev->dev, "firmware memory is not initialized\n");
753 return -EIO;
754 }
755
756 seq_printf(s, "%s\n", buf);
757 return 0;
758}
759
760static int fimc_is_debugfs_open(struct inode *inode, struct file *file)
761{
762 return single_open(file, fimc_is_log_show, inode->i_private);
763}
764
765static const struct file_operations fimc_is_debugfs_fops = {
766 .open = fimc_is_debugfs_open,
767 .read = seq_read,
768 .llseek = seq_lseek,
769 .release = single_release,
770};
771
772static void fimc_is_debugfs_remove(struct fimc_is *is)
773{
450f5f54 774 debugfs_remove_recursive(is->debugfs_entry);
9a761e43
SN		 775 is->debugfs_entry = NULL;
776}
777
778static int fimc_is_debugfs_create(struct fimc_is *is)
779{
780 struct dentry *dentry;
781
782 is->debugfs_entry = debugfs_create_dir("fimc_is", NULL);
783
784 dentry = debugfs_create_file("fw_log", S_IRUGO, is->debugfs_entry,
785 is, &fimc_is_debugfs_fops);
786 if (!dentry)
787 fimc_is_debugfs_remove(is);
788
789 return is->debugfs_entry == NULL ? -EIO : 0;
790}
791
792static int fimc_is_probe(struct platform_device *pdev)
793{
794 struct device *dev = &pdev->dev;
795 struct fimc_is *is;
796 struct resource res;
797 struct device_node *node;
798 int ret;
799
800 is = devm_kzalloc(&pdev->dev, sizeof(*is), GFP_KERNEL);
801 if (!is)
802 return -ENOMEM;
803
804 is->pdev = pdev;
805 is->isp.pdev = pdev;
806
807 init_waitqueue_head(&is->irq_queue);
808 spin_lock_init(&is->slock);
809 mutex_init(&is->lock);
810
811 ret = of_address_to_resource(dev->of_node, 0, &res);
812 if (ret < 0)
813 return ret;
814
815 is->regs = devm_ioremap_resource(dev, &res);
816 if (IS_ERR(is->regs))
817 return PTR_ERR(is->regs);
818
819 node = of_get_child_by_name(dev->of_node, "pmu");
820 if (!node)
821 return -ENODEV;
822
823 is->pmu_regs = of_iomap(node, 0);
824 if (!is->pmu_regs)
825 return -ENOMEM;
826
827 is->irq = irq_of_parse_and_map(dev->of_node, 0);
828 if (is->irq < 0) {
829 dev_err(dev, "no irq found\n");
830 return is->irq;
831 }
832
833 ret = fimc_is_get_clocks(is);
834 if (ret < 0)
835 return ret;
836
837 platform_set_drvdata(pdev, is);
838
839 ret = request_irq(is->irq, fimc_is_irq_handler, 0, dev_name(dev), is);
840 if (ret < 0) {
841 dev_err(dev, "irq request failed\n");
842 goto err_clk;
843 }
844 pm_runtime_enable(dev);
845 /*
846 * Enable only the ISP power domain, keep FIMC-IS clocks off until
847 * the whole clock tree is configured. The ISP power domain needs
848 * be active in order to acces any CMU_ISP clock registers.
849 */
850 ret = pm_runtime_get_sync(dev);
851 if (ret < 0)
852 goto err_irq;
853
854 ret = fimc_is_setup_clocks(is);
b34f51fa
SN		 855 pm_runtime_put_sync(dev);
856
9a761e43
SN		 857 if (ret < 0)
858 goto err_irq;
859
9a761e43
SN		 860 is->clk_init = true;
861
862 is->alloc_ctx = vb2_dma_contig_init_ctx(dev);
863 if (IS_ERR(is->alloc_ctx)) {
864 ret = PTR_ERR(is->alloc_ctx);
b34f51fa 865 goto err_irq;
9a761e43
SN		 866 }
867 /*
868 * Register FIMC-IS V4L2 subdevs to this driver. The video nodes
869 * will be created within the subdev's registered() callback.
870 */
871 ret = fimc_is_register_subdevs(is);
872 if (ret < 0)
873 goto err_vb;
874
875 ret = fimc_is_debugfs_create(is);
876 if (ret < 0)
877 goto err_sd;
878
879 ret = fimc_is_request_firmware(is, FIMC_IS_FW_FILENAME);
880 if (ret < 0)
881 goto err_dfs;
882
883 dev_dbg(dev, "FIMC-IS registered successfully\n");
884 return 0;
885
886err_dfs:
887 fimc_is_debugfs_remove(is);
888err_vb:
889 vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
890err_sd:
891 fimc_is_unregister_subdevs(is);
892err_irq:
893 free_irq(is->irq, is);
9a761e43
SN		 894err_clk:
895 fimc_is_put_clocks(is);
896 return ret;
897}
898
899static int fimc_is_runtime_resume(struct device *dev)
900{
901 struct fimc_is *is = dev_get_drvdata(dev);
902
903 if (!is->clk_init)
904 return 0;
905
906 return fimc_is_enable_clocks(is);
907}
908
909static int fimc_is_runtime_suspend(struct device *dev)
910{
911 struct fimc_is *is = dev_get_drvdata(dev);
912
913 if (is->clk_init)
914 fimc_is_disable_clocks(is);
915
916 return 0;
917}
918
919#ifdef CONFIG_PM_SLEEP
920static int fimc_is_resume(struct device *dev)
921{
922 /* TODO: */
923 return 0;
924}
925
926static int fimc_is_suspend(struct device *dev)
927{
928 struct fimc_is *is = dev_get_drvdata(dev);
929
930 /* TODO: */
931 if (test_bit(IS_ST_A5_PWR_ON, &is->state))
932 return -EBUSY;
933
934 return 0;
935}
936#endif /* CONFIG_PM_SLEEP */
937
938static int fimc_is_remove(struct platform_device *pdev)
939{
940 struct fimc_is *is = platform_get_drvdata(pdev);
941
942 pm_runtime_disable(&pdev->dev);
943 pm_runtime_set_suspended(&pdev->dev);
944 free_irq(is->irq, is);
945 fimc_is_unregister_subdevs(is);
946 vb2_dma_contig_cleanup_ctx(is->alloc_ctx);
947 fimc_is_put_clocks(is);
948 fimc_is_debugfs_remove(is);
3cf138a6
SN		 949 if (is->fw.f_w)
950 release_firmware(is->fw.f_w);
9a761e43
SN		 951 fimc_is_free_cpu_memory(is);
952
953 return 0;
954}
955
956static const struct of_device_id fimc_is_of_match[] = {
957 { .compatible = "samsung,exynos4212-fimc-is" },
958 { /* sentinel */ },
959};
960MODULE_DEVICE_TABLE(of, fimc_is_of_match);
961
962static const struct dev_pm_ops fimc_is_pm_ops = {
963 SET_SYSTEM_SLEEP_PM_OPS(fimc_is_suspend, fimc_is_resume)
964 SET_RUNTIME_PM_OPS(fimc_is_runtime_suspend, fimc_is_runtime_resume,
965 NULL)
966};
967
968static struct platform_driver fimc_is_driver = {
969 .probe = fimc_is_probe,
970 .remove = fimc_is_remove,
971 .driver = {
972 .of_match_table = fimc_is_of_match,
973 .name = FIMC_IS_DRV_NAME,
974 .owner = THIS_MODULE,
975 .pm = &fimc_is_pm_ops,
976 }
977};
978
979static int fimc_is_module_init(void)
980{
981 int ret;
982
983 ret = fimc_is_register_sensor_driver();
984 if (ret < 0)
985 return ret;
986
987 ret = fimc_is_register_i2c_driver();
988 if (ret < 0)
989 goto err_sens;
990
991 ret = platform_driver_register(&fimc_is_driver);
992 if (!ret)
993 return ret;
994
995 fimc_is_unregister_i2c_driver();
996err_sens:
997 fimc_is_unregister_sensor_driver();
998 return ret;
999}
1000
1001static void fimc_is_module_exit(void)
1002{
9a761e43 1003 fimc_is_unregister_sensor_driver();
0e30c7e1
SN		 1004 fimc_is_unregister_i2c_driver();
1005 platform_driver_unregister(&fimc_is_driver);
9a761e43
SN		 1006}
1007
1008module_init(fimc_is_module_init);
1009module_exit(fimc_is_module_exit);
1010
1011MODULE_ALIAS("platform:" FIMC_IS_DRV_NAME);
1012MODULE_AUTHOR("Younghwan Joo <yhwan.joo@samsung.com>");
1013MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
Linux kernel - Deliverables
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