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9a761e43 SN |
1 | /* |
2 | * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver | |
3 | * | |
4 | * Copyright (C) 2013 Samsung Electronics Co., Ltd. | |
5 | * | |
6 | * Authors: Sylwester Nawrocki <s.nawrocki@samsung.com> | |
7 | * Younghwan Joo <yhwan.joo@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__ | |
14 | ||
15 | #include <linux/device.h> | |
16 | #include <linux/errno.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/list.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/printk.h> | |
22 | #include <linux/pm_runtime.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/types.h> | |
25 | #include <media/v4l2-device.h> | |
26 | ||
27 | #include "media-dev.h" | |
28 | #include "fimc-is-command.h" | |
29 | #include "fimc-is-param.h" | |
30 | #include "fimc-is-regs.h" | |
31 | #include "fimc-is.h" | |
32 | ||
b54373c5 | 33 | static int debug; |
9a761e43 SN |
34 | module_param_named(debug_isp, debug, int, S_IRUGO | S_IWUSR); |
35 | ||
36 | static const struct fimc_fmt fimc_isp_formats[FIMC_ISP_NUM_FORMATS] = { | |
37 | { | |
38 | .name = "RAW8 (GRBG)", | |
39 | .fourcc = V4L2_PIX_FMT_SGRBG8, | |
40 | .depth = { 8 }, | |
41 | .color = FIMC_FMT_RAW8, | |
42 | .memplanes = 1, | |
43 | .mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8, | |
44 | }, { | |
45 | .name = "RAW10 (GRBG)", | |
46 | .fourcc = V4L2_PIX_FMT_SGRBG10, | |
47 | .depth = { 10 }, | |
48 | .color = FIMC_FMT_RAW10, | |
49 | .memplanes = 1, | |
50 | .mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10, | |
51 | }, { | |
52 | .name = "RAW12 (GRBG)", | |
53 | .fourcc = V4L2_PIX_FMT_SGRBG12, | |
54 | .depth = { 12 }, | |
55 | .color = FIMC_FMT_RAW12, | |
56 | .memplanes = 1, | |
57 | .mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12, | |
58 | }, | |
59 | }; | |
60 | ||
61 | /** | |
62 | * fimc_isp_find_format - lookup color format by fourcc or media bus code | |
63 | * @pixelformat: fourcc to match, ignored if null | |
64 | * @mbus_code: media bus code to match, ignored if null | |
65 | * @index: index to the fimc_isp_formats array, ignored if negative | |
66 | */ | |
67 | const struct fimc_fmt *fimc_isp_find_format(const u32 *pixelformat, | |
68 | const u32 *mbus_code, int index) | |
69 | { | |
70 | const struct fimc_fmt *fmt, *def_fmt = NULL; | |
71 | unsigned int i; | |
72 | int id = 0; | |
73 | ||
74 | if (index >= (int)ARRAY_SIZE(fimc_isp_formats)) | |
75 | return NULL; | |
76 | ||
77 | for (i = 0; i < ARRAY_SIZE(fimc_isp_formats); ++i) { | |
78 | fmt = &fimc_isp_formats[i]; | |
79 | if (pixelformat && fmt->fourcc == *pixelformat) | |
80 | return fmt; | |
81 | if (mbus_code && fmt->mbus_code == *mbus_code) | |
82 | return fmt; | |
83 | if (index == id) | |
84 | def_fmt = fmt; | |
85 | id++; | |
86 | } | |
87 | return def_fmt; | |
88 | } | |
89 | ||
90 | void fimc_isp_irq_handler(struct fimc_is *is) | |
91 | { | |
92 | is->i2h_cmd.args[0] = mcuctl_read(is, MCUCTL_REG_ISSR(20)); | |
93 | is->i2h_cmd.args[1] = mcuctl_read(is, MCUCTL_REG_ISSR(21)); | |
94 | ||
95 | fimc_is_fw_clear_irq1(is, FIMC_IS_INT_FRAME_DONE_ISP); | |
96 | ||
97 | /* TODO: Complete ISP DMA interrupt handler */ | |
98 | wake_up(&is->irq_queue); | |
99 | } | |
100 | ||
101 | /* Capture subdev media entity operations */ | |
102 | static int fimc_is_link_setup(struct media_entity *entity, | |
103 | const struct media_pad *local, | |
104 | const struct media_pad *remote, u32 flags) | |
105 | { | |
106 | return 0; | |
107 | } | |
108 | ||
109 | static const struct media_entity_operations fimc_is_subdev_media_ops = { | |
110 | .link_setup = fimc_is_link_setup, | |
111 | }; | |
112 | ||
113 | static int fimc_is_subdev_enum_mbus_code(struct v4l2_subdev *sd, | |
114 | struct v4l2_subdev_fh *fh, | |
115 | struct v4l2_subdev_mbus_code_enum *code) | |
116 | { | |
117 | const struct fimc_fmt *fmt; | |
118 | ||
119 | fmt = fimc_isp_find_format(NULL, NULL, code->index); | |
120 | if (!fmt) | |
121 | return -EINVAL; | |
122 | code->code = fmt->mbus_code; | |
123 | return 0; | |
124 | } | |
125 | ||
126 | static int fimc_isp_subdev_get_fmt(struct v4l2_subdev *sd, | |
127 | struct v4l2_subdev_fh *fh, | |
128 | struct v4l2_subdev_format *fmt) | |
129 | { | |
130 | struct fimc_isp *isp = v4l2_get_subdevdata(sd); | |
131 | struct fimc_is *is = fimc_isp_to_is(isp); | |
132 | struct v4l2_mbus_framefmt *mf = &fmt->format; | |
133 | struct v4l2_mbus_framefmt cur_fmt; | |
134 | ||
135 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
136 | mf = v4l2_subdev_get_try_format(fh, fmt->pad); | |
137 | fmt->format = *mf; | |
138 | return 0; | |
139 | } | |
140 | ||
141 | mf->colorspace = V4L2_COLORSPACE_JPEG; | |
142 | ||
143 | mutex_lock(&isp->subdev_lock); | |
144 | __is_get_frame_size(is, &cur_fmt); | |
145 | ||
146 | if (fmt->pad == FIMC_ISP_SD_PAD_SINK) { | |
147 | /* full camera input frame size */ | |
148 | mf->width = cur_fmt.width + FIMC_ISP_CAC_MARGIN_WIDTH; | |
149 | mf->height = cur_fmt.height + FIMC_ISP_CAC_MARGIN_HEIGHT; | |
150 | mf->code = V4L2_MBUS_FMT_SGRBG10_1X10; | |
151 | } else { | |
152 | /* crop size */ | |
153 | mf->width = cur_fmt.width; | |
154 | mf->height = cur_fmt.height; | |
155 | mf->code = V4L2_MBUS_FMT_YUV10_1X30; | |
156 | } | |
157 | ||
158 | mutex_unlock(&isp->subdev_lock); | |
159 | ||
160 | v4l2_dbg(1, debug, sd, "%s: pad%d: fmt: 0x%x, %dx%d\n", | |
161 | __func__, fmt->pad, mf->code, mf->width, mf->height); | |
162 | ||
163 | return 0; | |
164 | } | |
165 | ||
166 | static void __isp_subdev_try_format(struct fimc_isp *isp, | |
167 | struct v4l2_subdev_format *fmt) | |
168 | { | |
169 | struct v4l2_mbus_framefmt *mf = &fmt->format; | |
170 | ||
171 | if (fmt->pad == FIMC_ISP_SD_PAD_SINK) { | |
172 | v4l_bound_align_image(&mf->width, FIMC_ISP_SINK_WIDTH_MIN, | |
173 | FIMC_ISP_SINK_WIDTH_MAX, 0, | |
174 | &mf->height, FIMC_ISP_SINK_HEIGHT_MIN, | |
175 | FIMC_ISP_SINK_HEIGHT_MAX, 0, 0); | |
176 | isp->subdev_fmt = *mf; | |
177 | } else { | |
178 | /* Allow changing format only on sink pad */ | |
179 | mf->width = isp->subdev_fmt.width - FIMC_ISP_CAC_MARGIN_WIDTH; | |
180 | mf->height = isp->subdev_fmt.height - FIMC_ISP_CAC_MARGIN_HEIGHT; | |
181 | mf->code = isp->subdev_fmt.code; | |
182 | } | |
183 | } | |
184 | ||
185 | static int fimc_isp_subdev_set_fmt(struct v4l2_subdev *sd, | |
186 | struct v4l2_subdev_fh *fh, | |
187 | struct v4l2_subdev_format *fmt) | |
188 | { | |
189 | struct fimc_isp *isp = v4l2_get_subdevdata(sd); | |
190 | struct fimc_is *is = fimc_isp_to_is(isp); | |
191 | struct v4l2_mbus_framefmt *mf = &fmt->format; | |
192 | int ret = 0; | |
193 | ||
194 | v4l2_dbg(1, debug, sd, "%s: pad%d: code: 0x%x, %dx%d\n", | |
195 | __func__, fmt->pad, mf->code, mf->width, mf->height); | |
196 | ||
197 | mf->colorspace = V4L2_COLORSPACE_JPEG; | |
198 | ||
199 | mutex_lock(&isp->subdev_lock); | |
200 | __isp_subdev_try_format(isp, fmt); | |
201 | ||
202 | if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) { | |
203 | mf = v4l2_subdev_get_try_format(fh, fmt->pad); | |
204 | *mf = fmt->format; | |
205 | mutex_unlock(&isp->subdev_lock); | |
206 | return 0; | |
207 | } | |
208 | ||
209 | if (sd->entity.stream_count == 0) | |
210 | __is_set_frame_size(is, mf); | |
211 | else | |
212 | ret = -EBUSY; | |
213 | mutex_unlock(&isp->subdev_lock); | |
214 | ||
215 | return ret; | |
216 | } | |
217 | ||
218 | static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on) | |
219 | { | |
220 | struct fimc_isp *isp = v4l2_get_subdevdata(sd); | |
221 | struct fimc_is *is = fimc_isp_to_is(isp); | |
222 | int ret; | |
223 | ||
224 | v4l2_dbg(1, debug, sd, "%s: on: %d\n", __func__, on); | |
225 | ||
226 | if (!test_bit(IS_ST_INIT_DONE, &is->state)) | |
227 | return -EBUSY; | |
228 | ||
229 | fimc_is_mem_barrier(); | |
230 | ||
231 | if (on) { | |
a6f5635e | 232 | if (__get_pending_param_count(is)) { |
9a761e43 | 233 | ret = fimc_is_itf_s_param(is, true); |
a6f5635e SN |
234 | if (ret < 0) |
235 | return ret; | |
236 | } | |
9a761e43 SN |
237 | |
238 | v4l2_dbg(1, debug, sd, "changing mode to %d\n", | |
3530ef0a | 239 | is->config_index); |
9a761e43 SN |
240 | ret = fimc_is_itf_mode_change(is); |
241 | if (ret) | |
242 | return -EINVAL; | |
243 | ||
244 | clear_bit(IS_ST_STREAM_ON, &is->state); | |
245 | fimc_is_hw_stream_on(is); | |
246 | ret = fimc_is_wait_event(is, IS_ST_STREAM_ON, 1, | |
247 | FIMC_IS_CONFIG_TIMEOUT); | |
248 | if (ret < 0) { | |
249 | v4l2_err(sd, "stream on timeout\n"); | |
250 | return ret; | |
251 | } | |
252 | } else { | |
253 | clear_bit(IS_ST_STREAM_OFF, &is->state); | |
254 | fimc_is_hw_stream_off(is); | |
255 | ret = fimc_is_wait_event(is, IS_ST_STREAM_OFF, 1, | |
256 | FIMC_IS_CONFIG_TIMEOUT); | |
257 | if (ret < 0) { | |
258 | v4l2_err(sd, "stream off timeout\n"); | |
259 | return ret; | |
260 | } | |
261 | is->setfile.sub_index = 0; | |
262 | } | |
263 | ||
264 | return 0; | |
265 | } | |
266 | ||
267 | static int fimc_isp_subdev_s_power(struct v4l2_subdev *sd, int on) | |
268 | { | |
269 | struct fimc_isp *isp = v4l2_get_subdevdata(sd); | |
270 | struct fimc_is *is = fimc_isp_to_is(isp); | |
271 | int ret = 0; | |
272 | ||
273 | pr_debug("on: %d\n", on); | |
274 | ||
275 | if (on) { | |
276 | ret = pm_runtime_get_sync(&is->pdev->dev); | |
277 | if (ret < 0) | |
278 | return ret; | |
279 | set_bit(IS_ST_PWR_ON, &is->state); | |
280 | ||
281 | ret = fimc_is_start_firmware(is); | |
282 | if (ret < 0) { | |
283 | v4l2_err(sd, "firmware booting failed\n"); | |
284 | pm_runtime_put(&is->pdev->dev); | |
285 | return ret; | |
286 | } | |
287 | set_bit(IS_ST_PWR_SUBIP_ON, &is->state); | |
288 | ||
289 | ret = fimc_is_hw_initialize(is); | |
290 | } else { | |
291 | /* Close sensor */ | |
292 | if (!test_bit(IS_ST_PWR_ON, &is->state)) { | |
293 | fimc_is_hw_close_sensor(is, 0); | |
294 | ||
295 | ret = fimc_is_wait_event(is, IS_ST_OPEN_SENSOR, 0, | |
296 | FIMC_IS_CONFIG_TIMEOUT); | |
297 | if (ret < 0) { | |
298 | v4l2_err(sd, "sensor close timeout\n"); | |
299 | return ret; | |
300 | } | |
301 | } | |
302 | ||
303 | /* SUB IP power off */ | |
304 | if (test_bit(IS_ST_PWR_SUBIP_ON, &is->state)) { | |
305 | fimc_is_hw_subip_power_off(is); | |
306 | ret = fimc_is_wait_event(is, IS_ST_PWR_SUBIP_ON, 0, | |
307 | FIMC_IS_CONFIG_TIMEOUT); | |
308 | if (ret < 0) { | |
309 | v4l2_err(sd, "sub-IP power off timeout\n"); | |
310 | return ret; | |
311 | } | |
312 | } | |
313 | ||
314 | fimc_is_cpu_set_power(is, 0); | |
315 | pm_runtime_put_sync(&is->pdev->dev); | |
316 | ||
317 | clear_bit(IS_ST_PWR_ON, &is->state); | |
318 | clear_bit(IS_ST_INIT_DONE, &is->state); | |
319 | is->state = 0; | |
0e761b21 PC |
320 | is->config[is->config_index].p_region_index[0] = 0; |
321 | is->config[is->config_index].p_region_index[1] = 0; | |
9a761e43 SN |
322 | set_bit(IS_ST_IDLE, &is->state); |
323 | wmb(); | |
324 | } | |
325 | ||
326 | return ret; | |
327 | } | |
328 | ||
329 | static int fimc_isp_subdev_open(struct v4l2_subdev *sd, | |
330 | struct v4l2_subdev_fh *fh) | |
331 | { | |
332 | struct v4l2_mbus_framefmt fmt; | |
333 | struct v4l2_mbus_framefmt *format; | |
334 | ||
335 | format = v4l2_subdev_get_try_format(fh, FIMC_ISP_SD_PAD_SINK); | |
336 | ||
337 | fmt.colorspace = V4L2_COLORSPACE_SRGB; | |
338 | fmt.code = fimc_isp_formats[0].mbus_code; | |
339 | fmt.width = DEFAULT_PREVIEW_STILL_WIDTH + FIMC_ISP_CAC_MARGIN_WIDTH; | |
340 | fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT + FIMC_ISP_CAC_MARGIN_HEIGHT; | |
341 | fmt.field = V4L2_FIELD_NONE; | |
342 | *format = fmt; | |
343 | ||
344 | format = v4l2_subdev_get_try_format(fh, FIMC_ISP_SD_PAD_SRC_FIFO); | |
345 | fmt.width = DEFAULT_PREVIEW_STILL_WIDTH; | |
346 | fmt.height = DEFAULT_PREVIEW_STILL_HEIGHT; | |
347 | *format = fmt; | |
348 | ||
349 | format = v4l2_subdev_get_try_format(fh, FIMC_ISP_SD_PAD_SRC_DMA); | |
350 | *format = fmt; | |
351 | ||
352 | return 0; | |
353 | } | |
354 | ||
355 | static const struct v4l2_subdev_internal_ops fimc_is_subdev_internal_ops = { | |
356 | .open = fimc_isp_subdev_open, | |
357 | }; | |
358 | ||
359 | static const struct v4l2_subdev_pad_ops fimc_is_subdev_pad_ops = { | |
360 | .enum_mbus_code = fimc_is_subdev_enum_mbus_code, | |
361 | .get_fmt = fimc_isp_subdev_get_fmt, | |
362 | .set_fmt = fimc_isp_subdev_set_fmt, | |
363 | }; | |
364 | ||
365 | static const struct v4l2_subdev_video_ops fimc_is_subdev_video_ops = { | |
366 | .s_stream = fimc_isp_subdev_s_stream, | |
367 | }; | |
368 | ||
369 | static const struct v4l2_subdev_core_ops fimc_is_core_ops = { | |
370 | .s_power = fimc_isp_subdev_s_power, | |
371 | }; | |
372 | ||
373 | static struct v4l2_subdev_ops fimc_is_subdev_ops = { | |
374 | .core = &fimc_is_core_ops, | |
375 | .video = &fimc_is_subdev_video_ops, | |
376 | .pad = &fimc_is_subdev_pad_ops, | |
377 | }; | |
378 | ||
379 | static int __ctrl_set_white_balance(struct fimc_is *is, int value) | |
380 | { | |
381 | switch (value) { | |
382 | case V4L2_WHITE_BALANCE_AUTO: | |
383 | __is_set_isp_awb(is, ISP_AWB_COMMAND_AUTO, 0); | |
384 | break; | |
385 | case V4L2_WHITE_BALANCE_DAYLIGHT: | |
386 | __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION, | |
387 | ISP_AWB_ILLUMINATION_DAYLIGHT); | |
388 | break; | |
389 | case V4L2_WHITE_BALANCE_CLOUDY: | |
390 | __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION, | |
391 | ISP_AWB_ILLUMINATION_CLOUDY); | |
392 | break; | |
393 | case V4L2_WHITE_BALANCE_INCANDESCENT: | |
394 | __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION, | |
395 | ISP_AWB_ILLUMINATION_TUNGSTEN); | |
396 | break; | |
397 | case V4L2_WHITE_BALANCE_FLUORESCENT: | |
398 | __is_set_isp_awb(is, ISP_AWB_COMMAND_ILLUMINATION, | |
399 | ISP_AWB_ILLUMINATION_FLUORESCENT); | |
400 | break; | |
401 | default: | |
402 | return -EINVAL; | |
403 | } | |
404 | ||
405 | return 0; | |
406 | } | |
407 | ||
408 | static int __ctrl_set_aewb_lock(struct fimc_is *is, | |
409 | struct v4l2_ctrl *ctrl) | |
410 | { | |
411 | bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE; | |
412 | bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE; | |
413 | struct isp_param *isp = &is->is_p_region->parameter.isp; | |
414 | int cmd, ret; | |
415 | ||
416 | cmd = ae_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START; | |
417 | isp->aa.cmd = cmd; | |
418 | isp->aa.target = ISP_AA_TARGET_AE; | |
419 | fimc_is_set_param_bit(is, PARAM_ISP_AA); | |
9a761e43 SN |
420 | is->af.ae_lock_state = ae_lock; |
421 | wmb(); | |
422 | ||
423 | ret = fimc_is_itf_s_param(is, false); | |
424 | if (ret < 0) | |
425 | return ret; | |
426 | ||
427 | cmd = awb_lock ? ISP_AA_COMMAND_STOP : ISP_AA_COMMAND_START; | |
428 | isp->aa.cmd = cmd; | |
429 | isp->aa.target = ISP_AA_TARGET_AE; | |
430 | fimc_is_set_param_bit(is, PARAM_ISP_AA); | |
9a761e43 SN |
431 | is->af.awb_lock_state = awb_lock; |
432 | wmb(); | |
433 | ||
434 | return fimc_is_itf_s_param(is, false); | |
435 | } | |
436 | ||
437 | /* Supported manual ISO values */ | |
438 | static const s64 iso_qmenu[] = { | |
439 | 50, 100, 200, 400, 800, | |
440 | }; | |
441 | ||
442 | static int __ctrl_set_iso(struct fimc_is *is, int value) | |
443 | { | |
444 | unsigned int idx, iso; | |
445 | ||
446 | if (value == V4L2_ISO_SENSITIVITY_AUTO) { | |
447 | __is_set_isp_iso(is, ISP_ISO_COMMAND_AUTO, 0); | |
448 | return 0; | |
449 | } | |
450 | idx = is->isp.ctrls.iso->val; | |
451 | if (idx >= ARRAY_SIZE(iso_qmenu)) | |
452 | return -EINVAL; | |
453 | ||
454 | iso = iso_qmenu[idx]; | |
455 | __is_set_isp_iso(is, ISP_ISO_COMMAND_MANUAL, iso); | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static int __ctrl_set_metering(struct fimc_is *is, unsigned int value) | |
460 | { | |
461 | unsigned int val; | |
462 | ||
463 | switch (value) { | |
464 | case V4L2_EXPOSURE_METERING_AVERAGE: | |
465 | val = ISP_METERING_COMMAND_AVERAGE; | |
466 | break; | |
467 | case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED: | |
468 | val = ISP_METERING_COMMAND_CENTER; | |
469 | break; | |
470 | case V4L2_EXPOSURE_METERING_SPOT: | |
471 | val = ISP_METERING_COMMAND_SPOT; | |
472 | break; | |
473 | case V4L2_EXPOSURE_METERING_MATRIX: | |
474 | val = ISP_METERING_COMMAND_MATRIX; | |
475 | break; | |
476 | default: | |
477 | return -EINVAL; | |
478 | }; | |
479 | ||
480 | __is_set_isp_metering(is, IS_METERING_CONFIG_CMD, val); | |
481 | return 0; | |
482 | } | |
483 | ||
484 | static int __ctrl_set_afc(struct fimc_is *is, int value) | |
485 | { | |
486 | switch (value) { | |
487 | case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED: | |
488 | __is_set_isp_afc(is, ISP_AFC_COMMAND_DISABLE, 0); | |
489 | break; | |
490 | case V4L2_CID_POWER_LINE_FREQUENCY_50HZ: | |
491 | __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 50); | |
492 | break; | |
493 | case V4L2_CID_POWER_LINE_FREQUENCY_60HZ: | |
494 | __is_set_isp_afc(is, ISP_AFC_COMMAND_MANUAL, 60); | |
495 | break; | |
496 | case V4L2_CID_POWER_LINE_FREQUENCY_AUTO: | |
497 | __is_set_isp_afc(is, ISP_AFC_COMMAND_AUTO, 0); | |
498 | break; | |
499 | default: | |
500 | return -EINVAL; | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static int __ctrl_set_image_effect(struct fimc_is *is, int value) | |
507 | { | |
508 | static const u8 effects[][2] = { | |
509 | { V4L2_COLORFX_NONE, ISP_IMAGE_EFFECT_DISABLE }, | |
510 | { V4L2_COLORFX_BW, ISP_IMAGE_EFFECT_MONOCHROME }, | |
511 | { V4L2_COLORFX_SEPIA, ISP_IMAGE_EFFECT_SEPIA }, | |
512 | { V4L2_COLORFX_NEGATIVE, ISP_IMAGE_EFFECT_NEGATIVE_MONO }, | |
513 | { 16 /* TODO */, ISP_IMAGE_EFFECT_NEGATIVE_COLOR }, | |
514 | }; | |
515 | int i; | |
516 | ||
517 | for (i = 0; i < ARRAY_SIZE(effects); i++) { | |
518 | if (effects[i][0] != value) | |
519 | continue; | |
520 | ||
521 | __is_set_isp_effect(is, effects[i][1]); | |
522 | return 0; | |
523 | } | |
524 | ||
525 | return -EINVAL; | |
526 | } | |
527 | ||
528 | static int fimc_is_s_ctrl(struct v4l2_ctrl *ctrl) | |
529 | { | |
530 | struct fimc_isp *isp = ctrl_to_fimc_isp(ctrl); | |
531 | struct fimc_is *is = fimc_isp_to_is(isp); | |
532 | bool set_param = true; | |
533 | int ret = 0; | |
534 | ||
535 | switch (ctrl->id) { | |
536 | case V4L2_CID_CONTRAST: | |
537 | __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_CONTRAST, | |
538 | ctrl->val); | |
539 | break; | |
540 | ||
541 | case V4L2_CID_SATURATION: | |
542 | __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SATURATION, | |
543 | ctrl->val); | |
544 | break; | |
545 | ||
546 | case V4L2_CID_SHARPNESS: | |
547 | __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_SHARPNESS, | |
548 | ctrl->val); | |
549 | break; | |
550 | ||
551 | case V4L2_CID_EXPOSURE_ABSOLUTE: | |
552 | __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_EXPOSURE, | |
553 | ctrl->val); | |
554 | break; | |
555 | ||
556 | case V4L2_CID_BRIGHTNESS: | |
557 | __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_BRIGHTNESS, | |
558 | ctrl->val); | |
559 | break; | |
560 | ||
561 | case V4L2_CID_HUE: | |
562 | __is_set_isp_adjust(is, ISP_ADJUST_COMMAND_MANUAL_HUE, | |
563 | ctrl->val); | |
564 | break; | |
565 | ||
566 | case V4L2_CID_EXPOSURE_METERING: | |
567 | ret = __ctrl_set_metering(is, ctrl->val); | |
568 | break; | |
569 | ||
570 | case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: | |
571 | ret = __ctrl_set_white_balance(is, ctrl->val); | |
572 | break; | |
573 | ||
574 | case V4L2_CID_3A_LOCK: | |
575 | ret = __ctrl_set_aewb_lock(is, ctrl); | |
576 | set_param = false; | |
577 | break; | |
578 | ||
579 | case V4L2_CID_ISO_SENSITIVITY_AUTO: | |
580 | ret = __ctrl_set_iso(is, ctrl->val); | |
581 | break; | |
582 | ||
583 | case V4L2_CID_POWER_LINE_FREQUENCY: | |
584 | ret = __ctrl_set_afc(is, ctrl->val); | |
585 | break; | |
586 | ||
587 | case V4L2_CID_COLORFX: | |
588 | __ctrl_set_image_effect(is, ctrl->val); | |
589 | break; | |
590 | ||
591 | default: | |
592 | ret = -EINVAL; | |
593 | break; | |
594 | } | |
595 | ||
596 | if (ret < 0) { | |
597 | v4l2_err(&isp->subdev, "Failed to set control: %s (%d)\n", | |
598 | ctrl->name, ctrl->val); | |
599 | return ret; | |
600 | } | |
601 | ||
602 | if (set_param && test_bit(IS_ST_STREAM_ON, &is->state)) | |
603 | return fimc_is_itf_s_param(is, true); | |
604 | ||
605 | return 0; | |
606 | } | |
607 | ||
608 | static const struct v4l2_ctrl_ops fimc_isp_ctrl_ops = { | |
609 | .s_ctrl = fimc_is_s_ctrl, | |
610 | }; | |
611 | ||
612 | int fimc_isp_subdev_create(struct fimc_isp *isp) | |
613 | { | |
614 | const struct v4l2_ctrl_ops *ops = &fimc_isp_ctrl_ops; | |
615 | struct v4l2_ctrl_handler *handler = &isp->ctrls.handler; | |
616 | struct v4l2_subdev *sd = &isp->subdev; | |
617 | struct fimc_isp_ctrls *ctrls = &isp->ctrls; | |
618 | int ret; | |
619 | ||
620 | mutex_init(&isp->subdev_lock); | |
621 | ||
622 | v4l2_subdev_init(sd, &fimc_is_subdev_ops); | |
623 | sd->grp_id = GRP_ID_FIMC_IS; | |
5a66561f | 624 | sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; |
9a761e43 SN |
625 | snprintf(sd->name, sizeof(sd->name), "FIMC-IS-ISP"); |
626 | ||
627 | isp->subdev_pads[FIMC_ISP_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK; | |
628 | isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_FIFO].flags = MEDIA_PAD_FL_SOURCE; | |
629 | isp->subdev_pads[FIMC_ISP_SD_PAD_SRC_DMA].flags = MEDIA_PAD_FL_SOURCE; | |
630 | ret = media_entity_init(&sd->entity, FIMC_ISP_SD_PADS_NUM, | |
631 | isp->subdev_pads, 0); | |
632 | if (ret) | |
633 | return ret; | |
634 | ||
635 | v4l2_ctrl_handler_init(handler, 20); | |
636 | ||
637 | ctrls->saturation = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SATURATION, | |
638 | -2, 2, 1, 0); | |
639 | ctrls->brightness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_BRIGHTNESS, | |
640 | -4, 4, 1, 0); | |
641 | ctrls->contrast = v4l2_ctrl_new_std(handler, ops, V4L2_CID_CONTRAST, | |
642 | -2, 2, 1, 0); | |
643 | ctrls->sharpness = v4l2_ctrl_new_std(handler, ops, V4L2_CID_SHARPNESS, | |
644 | -2, 2, 1, 0); | |
645 | ctrls->hue = v4l2_ctrl_new_std(handler, ops, V4L2_CID_HUE, | |
646 | -2, 2, 1, 0); | |
647 | ||
648 | ctrls->auto_wb = v4l2_ctrl_new_std_menu(handler, ops, | |
649 | V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, | |
650 | 8, ~0x14e, V4L2_WHITE_BALANCE_AUTO); | |
651 | ||
652 | ctrls->exposure = v4l2_ctrl_new_std(handler, ops, | |
653 | V4L2_CID_EXPOSURE_ABSOLUTE, | |
654 | -4, 4, 1, 0); | |
655 | ||
656 | ctrls->exp_metering = v4l2_ctrl_new_std_menu(handler, ops, | |
657 | V4L2_CID_EXPOSURE_METERING, 3, | |
658 | ~0xf, V4L2_EXPOSURE_METERING_AVERAGE); | |
659 | ||
660 | v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_POWER_LINE_FREQUENCY, | |
661 | V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0, | |
662 | V4L2_CID_POWER_LINE_FREQUENCY_AUTO); | |
663 | /* ISO sensitivity */ | |
664 | ctrls->auto_iso = v4l2_ctrl_new_std_menu(handler, ops, | |
665 | V4L2_CID_ISO_SENSITIVITY_AUTO, 1, 0, | |
666 | V4L2_ISO_SENSITIVITY_AUTO); | |
667 | ||
668 | ctrls->iso = v4l2_ctrl_new_int_menu(handler, ops, | |
669 | V4L2_CID_ISO_SENSITIVITY, ARRAY_SIZE(iso_qmenu) - 1, | |
670 | ARRAY_SIZE(iso_qmenu)/2 - 1, iso_qmenu); | |
671 | ||
672 | ctrls->aewb_lock = v4l2_ctrl_new_std(handler, ops, | |
673 | V4L2_CID_3A_LOCK, 0, 0x3, 0, 0); | |
674 | ||
675 | /* TODO: Add support for NEGATIVE_COLOR option */ | |
676 | ctrls->colorfx = v4l2_ctrl_new_std_menu(handler, ops, V4L2_CID_COLORFX, | |
677 | V4L2_COLORFX_SET_CBCR + 1, ~0x1000f, V4L2_COLORFX_NONE); | |
678 | ||
679 | if (handler->error) { | |
680 | media_entity_cleanup(&sd->entity); | |
681 | return handler->error; | |
682 | } | |
683 | ||
684 | v4l2_ctrl_auto_cluster(2, &ctrls->auto_iso, | |
685 | V4L2_ISO_SENSITIVITY_MANUAL, false); | |
686 | ||
687 | sd->ctrl_handler = handler; | |
688 | sd->internal_ops = &fimc_is_subdev_internal_ops; | |
689 | sd->entity.ops = &fimc_is_subdev_media_ops; | |
690 | v4l2_set_subdevdata(sd, isp); | |
691 | ||
692 | return 0; | |
693 | } | |
694 | ||
695 | void fimc_isp_subdev_destroy(struct fimc_isp *isp) | |
696 | { | |
697 | struct v4l2_subdev *sd = &isp->subdev; | |
698 | ||
699 | v4l2_device_unregister_subdev(sd); | |
700 | media_entity_cleanup(&sd->entity); | |
701 | v4l2_ctrl_handler_free(&isp->ctrls.handler); | |
702 | v4l2_set_subdevdata(sd, NULL); | |
703 | } |